sys/dev/qlnx/qlnxe/ecore_cxt.c

   1 /*
   2  * Copyright (c) 2017-2018 Cavium, Inc.
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 /*
  29  * File : ecore_cxt.c
  30  */
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include "bcm_osal.h"
  35 #include "reg_addr.h"
  36 #include "common_hsi.h"
  37 #include "ecore_hsi_common.h"
  38 #include "ecore_hsi_eth.h"
  39 #include "tcp_common.h"
  40 #include "ecore_hsi_iscsi.h"
  41 #include "ecore_hsi_fcoe.h"
  42 #include "ecore_hsi_roce.h"
  43 #include "ecore_hsi_iwarp.h"
  44 #include "ecore_rt_defs.h"
  45 #include "ecore_status.h"
  46 #include "ecore.h"
  47 #include "ecore_init_ops.h"
  48 #include "ecore_init_fw_funcs.h"
  49 #include "ecore_cxt.h"
  50 #include "ecore_hw.h"
  51 #include "ecore_dev_api.h"
  52 #include "ecore_sriov.h"
  53 #include "ecore_roce.h"
  54 #include "ecore_mcp.h"
  55
  56 /* Max number of connection types in HW (DQ/CDU etc.) */
  57 #define MAX_CONN_TYPES          PROTOCOLID_COMMON
  58 #define NUM_TASK_TYPES          2
  59 #define NUM_TASK_PF_SEGMENTS    4
  60 #define NUM_TASK_VF_SEGMENTS    1
  61
  62 /* Doorbell-Queue constants */
  63 #define DQ_RANGE_SHIFT  4
  64 #define DQ_RANGE_ALIGN  (1 << DQ_RANGE_SHIFT)
  65
  66 /* Searcher constants */
  67 #define SRC_MIN_NUM_ELEMS 256
  68
  69 /* Timers constants */
  70 #define TM_SHIFT        7
  71 #define TM_ALIGN        (1 << TM_SHIFT)
  72 #define TM_ELEM_SIZE    4
  73
  74 /* ILT constants */
  75 /* If for some reason, HW P size is modified to be less than 32K,
  76  * special handling needs to be made for CDU initialization
  77  */
  78 #ifdef CONFIG_ECORE_ROCE
  79 /* For RoCE we configure to 64K to cover for RoCE max tasks 256K purpose. Can be
  80  * optimized with resource management scheme
  81  */
  82 #define ILT_DEFAULT_HW_P_SIZE   4
  83 #else
  84 #define ILT_DEFAULT_HW_P_SIZE   3
  85 #endif
  86
  87 #define ILT_PAGE_IN_BYTES(hw_p_size)    (1U << ((hw_p_size) + 12))
  88 #define ILT_CFG_REG(cli, reg)           PSWRQ2_REG_##cli##_##reg##_RT_OFFSET
  89
  90 /* ILT entry structure */
  91 #define ILT_ENTRY_PHY_ADDR_MASK         0x000FFFFFFFFFFFULL
  92 #define ILT_ENTRY_PHY_ADDR_SHIFT        0
  93 #define ILT_ENTRY_VALID_MASK            0x1ULL
  94 #define ILT_ENTRY_VALID_SHIFT           52
  95 #define ILT_ENTRY_IN_REGS               2
  96 #define ILT_REG_SIZE_IN_BYTES           4
  97
  98 /* connection context union */
  99 union conn_context {
 100         struct core_conn_context  core_ctx;
 101         struct eth_conn_context   eth_ctx;
 102         struct iscsi_conn_context iscsi_ctx;
 103         struct fcoe_conn_context  fcoe_ctx;
 104         struct roce_conn_context  roce_ctx;
 105 };
 106
 107 /* TYPE-0 task context - iSCSI, FCOE */
 108 union type0_task_context {
 109         struct iscsi_task_context iscsi_ctx;
 110         struct fcoe_task_context  fcoe_ctx;
 111 };
 112
 113 /* TYPE-1 task context - ROCE */
 114 union type1_task_context {
 115         struct rdma_task_context roce_ctx;
 116 };
 117
 118 struct src_ent {
 119         u8  opaque[56];
 120         u64 next;
 121 };
 122
 123 #define CDUT_SEG_ALIGNMET 3 /* in 4k chunks */
 124 #define CDUT_SEG_ALIGNMET_IN_BYTES (1 << (CDUT_SEG_ALIGNMET + 12))
 125
 126 #define CONN_CXT_SIZE(p_hwfn) \
 127         ALIGNED_TYPE_SIZE(union conn_context, p_hwfn)
 128
 129 #define SRQ_CXT_SIZE (sizeof(struct rdma_srq_context))
 130
 131 #define TYPE0_TASK_CXT_SIZE(p_hwfn) \
 132         ALIGNED_TYPE_SIZE(union type0_task_context, p_hwfn)
 133
 134 /* Alignment is inherent to the type1_task_context structure */
 135 #define TYPE1_TASK_CXT_SIZE(p_hwfn) sizeof(union type1_task_context)
 136
 137 /* PF per protocl configuration object */
 138 #define TASK_SEGMENTS   (NUM_TASK_PF_SEGMENTS + NUM_TASK_VF_SEGMENTS)
 139 #define TASK_SEGMENT_VF (NUM_TASK_PF_SEGMENTS)
 140
 141 struct ecore_tid_seg {
 142         u32     count;
 143         u8      type;
 144         bool    has_fl_mem;
 145 };
 146
 147 struct ecore_conn_type_cfg {
 148         u32                     cid_count;
 149         u32                     cids_per_vf;
 150         struct ecore_tid_seg    tid_seg[TASK_SEGMENTS];
 151 };
 152
 153 /* ILT Client configuration,
 154  * Per connection type (protocol) resources (cids, tis, vf cids etc.)
 155  * 1 - for connection context (CDUC) and for each task context we need two
 156  * values, for regular task context and for force load memory
 157  */
 158 #define ILT_CLI_PF_BLOCKS       (1 + NUM_TASK_PF_SEGMENTS * 2)
 159 #define ILT_CLI_VF_BLOCKS       (1 + NUM_TASK_VF_SEGMENTS * 2)
 160 #define CDUC_BLK                (0)
 161 #define SRQ_BLK                 (0)
 162 #define CDUT_SEG_BLK(n)         (1 + (u8)(n))
 163 #define CDUT_FL_SEG_BLK(n, X)   (1 + (n) + NUM_TASK_##X##_SEGMENTS)
 164
 165 enum ilt_clients {
 166         ILT_CLI_CDUC,
 167         ILT_CLI_CDUT,
 168         ILT_CLI_QM,
 169         ILT_CLI_TM,
 170         ILT_CLI_SRC,
 171         ILT_CLI_TSDM,
 172         ILT_CLI_MAX
 173 };
 174
 175 struct ilt_cfg_pair {
 176         u32 reg;
 177         u32 val;
 178 };
 179
 180 struct ecore_ilt_cli_blk {
 181         u32 total_size; /* 0 means not active */
 182         u32 real_size_in_page;
 183         u32 start_line;
 184         u32 dynamic_line_cnt;
 185 };
 186
 187 struct ecore_ilt_client_cfg {
 188         bool                            active;
 189
 190         /* ILT boundaries */
 191         struct ilt_cfg_pair             first;
 192         struct ilt_cfg_pair             last;
 193         struct ilt_cfg_pair             p_size;
 194
 195         /* ILT client blocks for PF */
 196         struct ecore_ilt_cli_blk        pf_blks[ILT_CLI_PF_BLOCKS];
 197         u32                             pf_total_lines;
 198
 199         /* ILT client blocks for VFs */
 200         struct ecore_ilt_cli_blk        vf_blks[ILT_CLI_VF_BLOCKS];
 201         u32                             vf_total_lines;
 202 };
 203
 204 /* Per Path -
 205  *      ILT shadow table
 206  *      Protocol acquired CID lists
 207  *      PF start line in ILT
 208  */
 209 struct ecore_dma_mem {
 210         dma_addr_t      p_phys;
 211         void            *p_virt;
 212         osal_size_t     size;
 213 };
 214
 215 #define MAP_WORD_SIZE           sizeof(unsigned long)
 216 #define BITS_PER_MAP_WORD       (MAP_WORD_SIZE * 8)
 217
 218 struct ecore_cid_acquired_map {
 219         u32             start_cid;
 220         u32             max_count;
 221         unsigned long   *cid_map;
 222 };
 223
 224 struct ecore_cxt_mngr {
 225         /* Per protocl configuration */
 226         struct ecore_conn_type_cfg      conn_cfg[MAX_CONN_TYPES];
 227
 228         /* computed ILT structure */
 229         struct ecore_ilt_client_cfg     clients[ILT_CLI_MAX];
 230
 231         /* Task type sizes */
 232         u32                             task_type_size[NUM_TASK_TYPES];
 233
 234         /* total number of VFs for this hwfn -
 235          * ALL VFs are symmetric in terms of HW resources
 236          */
 237         u32                             vf_count;
 238
 239         /* Acquired CIDs */
 240         struct ecore_cid_acquired_map acquired[MAX_CONN_TYPES];
 241         /* TBD - do we want this allocated to reserve space? */
 242         struct ecore_cid_acquired_map acquired_vf[MAX_CONN_TYPES][COMMON_MAX_NUM_VFS];
 243
 244         /* ILT shadow table */
 245         struct ecore_dma_mem            *ilt_shadow;
 246         u32                             pf_start_line;
 247
 248         /* Mutex for a dynamic ILT allocation */
 249         osal_mutex_t                    mutex;
 250
 251         /* SRC T2 */
 252         struct ecore_dma_mem            *t2;
 253         u32                             t2_num_pages;
 254         u64                             first_free;
 255         u64                             last_free;
 256
 257         /* The infrastructure originally was very generic and context/task
 258          * oriented - per connection-type we would set how many of those
 259          * are needed, and later when determining how much memory we're
 260          * needing for a given block we'd iterate over all the relevant
 261          * connection-types.
 262          * But since then we've had some additional resources, some of which
 263          * require memory which is indepent of the general context/task
 264          * scheme. We add those here explicitly per-feature.
 265          */
 266
 267         /* total number of SRQ's for this hwfn */
 268         u32                             srq_count;
 269
 270         /* Maximal number of L2 steering filters */
 271         u32                             arfs_count;
 272
 273         /* TODO - VF arfs filters ? */
 274 };
 275
 276 /* check if resources/configuration is required according to protocol type */
 277 static bool src_proto(struct ecore_hwfn *p_hwfn,
 278                       enum protocol_type type)
 279 {
 280         return  type == PROTOCOLID_ISCSI        ||
 281                 type == PROTOCOLID_FCOE         ||
 282                 type == PROTOCOLID_TOE          ||
 283                 type == PROTOCOLID_IWARP;
 284 }
 285
 286 static bool tm_cid_proto(enum protocol_type type)
 287 {
 288         return type == PROTOCOLID_ISCSI ||
 289                type == PROTOCOLID_FCOE  ||
 290                type == PROTOCOLID_ROCE  ||
 291                type == PROTOCOLID_IWARP;
 292 }
 293
 294 static bool tm_tid_proto(enum protocol_type type)
 295 {
 296         return type == PROTOCOLID_FCOE;
 297 }
 298
 299 /* counts the iids for the CDU/CDUC ILT client configuration */
 300 struct ecore_cdu_iids {
 301         u32 pf_cids;
 302         u32 per_vf_cids;
 303 };
 304
 305 static void ecore_cxt_cdu_iids(struct ecore_cxt_mngr   *p_mngr,
 306                                struct ecore_cdu_iids    *iids)
 307 {
 308         u32 type;
 309
 310         for (type = 0; type < MAX_CONN_TYPES; type++) {
 311                 iids->pf_cids += p_mngr->conn_cfg[type].cid_count;
 312                 iids->per_vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 313         }
 314 }
 315
 316 /* counts the iids for the Searcher block configuration */
 317 struct ecore_src_iids {
 318         u32                     pf_cids;
 319         u32                     per_vf_cids;
 320 };
 321
 322 static void ecore_cxt_src_iids(struct ecore_hwfn *p_hwfn,
 323                                struct ecore_cxt_mngr *p_mngr,
 324                                struct ecore_src_iids *iids)
 325 {
 326         u32 i;
 327
 328         for (i = 0; i < MAX_CONN_TYPES; i++) {
 329                 if (!src_proto(p_hwfn, i))
 330                         continue;
 331
 332                 iids->pf_cids += p_mngr->conn_cfg[i].cid_count;
 333                 iids->per_vf_cids += p_mngr->conn_cfg[i].cids_per_vf;
 334         }
 335
 336         /* Add L2 filtering filters in addition */
 337         iids->pf_cids += p_mngr->arfs_count;
 338 }
 339
 340 /* counts the iids for the Timers block configuration */
 341 struct ecore_tm_iids {
 342         u32 pf_cids;
 343         u32 pf_tids[NUM_TASK_PF_SEGMENTS]; /* per segment */
 344         u32 pf_tids_total;
 345         u32 per_vf_cids;
 346         u32 per_vf_tids;
 347 };
 348
 349 static void ecore_cxt_tm_iids(struct ecore_hwfn *p_hwfn,
 350                               struct ecore_cxt_mngr *p_mngr,
 351                               struct ecore_tm_iids *iids)
 352 {
 353         bool tm_vf_required = false;
 354         bool tm_required = false;
 355         int i, j;
 356
 357         /* Timers is a special case -> we don't count how many cids require
 358          * timers but what's the max cid that will be used by the timer block.
 359          * therefore we traverse in reverse order, and once we hit a protocol
 360          * that requires the timers memory, we'll sum all the protocols up
 361          * to that one.
 362          */
 363         for (i = MAX_CONN_TYPES - 1; i >= 0; i--) {
 364                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[i];
 365
 366                 if (tm_cid_proto(i) || tm_required) {
 367                         if (p_cfg->cid_count)
 368                                 tm_required = true;
 369
 370                         iids->pf_cids += p_cfg->cid_count;
 371                 }
 372
 373                 if (tm_cid_proto(i) || tm_vf_required) {
 374                         if (p_cfg->cids_per_vf)
 375                                 tm_vf_required = true;
 376
 377                         iids->per_vf_cids += p_cfg->cids_per_vf;
 378                 }
 379
 380                 if (tm_tid_proto(i)) {
 381                         struct ecore_tid_seg *segs = p_cfg->tid_seg;
 382
 383                         /* for each segment there is at most one
 384                          * protocol for which count is not 0.
 385                          */
 386                         for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 387                                 iids->pf_tids[j] += segs[j].count;
 388
 389                         /* The last array elelment is for the VFs. As for PF
 390                          * segments there can be only one protocol for
 391                          * which this value is not 0.
 392                          */
 393                         iids->per_vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 394                 }
 395         }
 396
 397         iids->pf_cids = ROUNDUP(iids->pf_cids, TM_ALIGN);
 398         iids->per_vf_cids = ROUNDUP(iids->per_vf_cids, TM_ALIGN);
 399         iids->per_vf_tids = ROUNDUP(iids->per_vf_tids, TM_ALIGN);
 400
 401         for (iids->pf_tids_total = 0, j = 0; j < NUM_TASK_PF_SEGMENTS; j++) {
 402                 iids->pf_tids[j] = ROUNDUP(iids->pf_tids[j], TM_ALIGN);
 403                 iids->pf_tids_total += iids->pf_tids[j];
 404         }
 405 }
 406
 407 static void ecore_cxt_qm_iids(struct ecore_hwfn *p_hwfn,
 408                               struct ecore_qm_iids *iids)
 409 {
 410         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 411         struct ecore_tid_seg *segs;
 412         u32 vf_cids = 0, type, j;
 413         u32 vf_tids = 0;
 414
 415         for (type = 0; type < MAX_CONN_TYPES; type++) {
 416                 iids->cids += p_mngr->conn_cfg[type].cid_count;
 417                 vf_cids += p_mngr->conn_cfg[type].cids_per_vf;
 418
 419                 segs = p_mngr->conn_cfg[type].tid_seg;
 420                 /* for each segment there is at most one
 421                  * protocol for which count is not 0.
 422                  */
 423                 for (j = 0; j < NUM_TASK_PF_SEGMENTS; j++)
 424                         iids->tids += segs[j].count;
 425
 426                 /* The last array elelment is for the VFs. As for PF
 427                  * segments there can be only one protocol for
 428                  * which this value is not 0.
 429                  */
 430                 vf_tids += segs[NUM_TASK_PF_SEGMENTS].count;
 431         }
 432
 433         iids->vf_cids += vf_cids * p_mngr->vf_count;
 434         iids->tids += vf_tids * p_mngr->vf_count;
 435
 436         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 437                    "iids: CIDS %08x vf_cids %08x tids %08x vf_tids %08x\n",
 438                    iids->cids, iids->vf_cids, iids->tids, vf_tids);
 439 }
 440
 441 static struct ecore_tid_seg *ecore_cxt_tid_seg_info(struct ecore_hwfn   *p_hwfn,
 442                                                     u32                 seg)
 443 {
 444         struct ecore_cxt_mngr *p_cfg = p_hwfn->p_cxt_mngr;
 445         u32 i;
 446
 447         /* Find the protocol with tid count > 0 for this segment.
 448            Note: there can only be one and this is already validated.
 449          */
 450         for (i = 0; i < MAX_CONN_TYPES; i++) {
 451                 if (p_cfg->conn_cfg[i].tid_seg[seg].count)
 452                         return &p_cfg->conn_cfg[i].tid_seg[seg];
 453         }
 454         return OSAL_NULL;
 455 }
 456
 457 /* set the iids (cid/tid) count per protocol */
 458 static void ecore_cxt_set_proto_cid_count(struct ecore_hwfn *p_hwfn,
 459                                           enum protocol_type type,
 460                                           u32 cid_count, u32 vf_cid_cnt)
 461 {
 462         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
 463         struct ecore_conn_type_cfg *p_conn = &p_mgr->conn_cfg[type];
 464
 465         p_conn->cid_count = ROUNDUP(cid_count, DQ_RANGE_ALIGN);
 466         p_conn->cids_per_vf = ROUNDUP(vf_cid_cnt, DQ_RANGE_ALIGN);
 467
 468         if (type == PROTOCOLID_ROCE) {
 469                 u32 page_sz = p_mgr->clients[ILT_CLI_CDUC].p_size.val;
 470                 u32 cxt_size = CONN_CXT_SIZE(p_hwfn);
 471                 u32 elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
 472                 u32 align = elems_per_page * DQ_RANGE_ALIGN;
 473
 474                 p_conn->cid_count = ROUNDUP(p_conn->cid_count, align);
 475         }
 476 }
 477
 478 u32 ecore_cxt_get_proto_cid_count(struct ecore_hwfn     *p_hwfn,
 479                                   enum protocol_type    type,
 480                                   u32                   *vf_cid)
 481 {
 482         if (vf_cid)
 483                 *vf_cid = p_hwfn->p_cxt_mngr->conn_cfg[type].cids_per_vf;
 484
 485         return p_hwfn->p_cxt_mngr->conn_cfg[type].cid_count;
 486 }
 487
 488 u32 ecore_cxt_get_proto_cid_start(struct ecore_hwfn     *p_hwfn,
 489                                   enum protocol_type    type)
 490 {
 491         return p_hwfn->p_cxt_mngr->acquired[type].start_cid;
 492 }
 493
 494 u32 ecore_cxt_get_proto_tid_count(struct ecore_hwfn *p_hwfn,
 495                                   enum protocol_type type)
 496 {
 497         u32 cnt = 0;
 498         int i;
 499
 500         for (i = 0; i < TASK_SEGMENTS; i++)
 501                 cnt += p_hwfn->p_cxt_mngr->conn_cfg[type].tid_seg[i].count;
 502
 503         return cnt;
 504 }
 505
 506 static void ecore_cxt_set_proto_tid_count(struct ecore_hwfn *p_hwfn,
 507                                           enum protocol_type proto,
 508                                           u8 seg,
 509                                           u8 seg_type,
 510                                           u32 count,
 511                                           bool has_fl)
 512 {
 513         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 514         struct ecore_tid_seg *p_seg = &p_mngr->conn_cfg[proto].tid_seg[seg];
 515
 516         p_seg->count = count;
 517         p_seg->has_fl_mem = has_fl;
 518         p_seg->type = seg_type;
 519 }
 520
 521 /* the *p_line parameter must be either 0 for the first invocation or the
 522    value returned in the previous invocation.
 523  */
 524 static void ecore_ilt_cli_blk_fill(struct ecore_ilt_client_cfg  *p_cli,
 525                                    struct ecore_ilt_cli_blk     *p_blk,
 526                                    u32                          start_line,
 527                                    u32                          total_size,
 528                                    u32                          elem_size)
 529 {
 530         u32 ilt_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 531
 532         /* verify that it's called once for each block */
 533         if (p_blk->total_size)
 534                 return;
 535
 536         p_blk->total_size = total_size;
 537         p_blk->real_size_in_page = 0;
 538         if (elem_size)
 539                 p_blk->real_size_in_page = (ilt_size / elem_size) * elem_size;
 540         p_blk->start_line = start_line;
 541 }
 542
 543 static void ecore_ilt_cli_adv_line(struct ecore_hwfn            *p_hwfn,
 544                                     struct ecore_ilt_client_cfg *p_cli,
 545                                     struct ecore_ilt_cli_blk    *p_blk,
 546                                     u32                         *p_line,
 547                                     enum ilt_clients            client_id)
 548 {
 549         if (!p_blk->total_size)
 550                 return;
 551
 552         if (!p_cli->active)
 553                 p_cli->first.val = *p_line;
 554
 555         p_cli->active = true;
 556         *p_line += DIV_ROUND_UP(p_blk->total_size, p_blk->real_size_in_page);
 557         p_cli->last.val = *p_line-1;
 558
 559         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 560                    "ILT[Client %d] - Lines: [%08x - %08x]. Block - Size %08x [Real %08x] Start line %d\n",
 561                    client_id, p_cli->first.val, p_cli->last.val,
 562                    p_blk->total_size, p_blk->real_size_in_page,
 563                    p_blk->start_line);
 564 }
 565
 566 static u32 ecore_ilt_get_dynamic_line_cnt(struct ecore_hwfn *p_hwfn,
 567                                           enum ilt_clients ilt_client)
 568 {
 569         u32 cid_count = p_hwfn->p_cxt_mngr->conn_cfg[PROTOCOLID_ROCE].cid_count;
 570         struct ecore_ilt_client_cfg *p_cli;
 571         u32 lines_to_skip = 0;
 572         u32 cxts_per_p;
 573
 574         /* TBD MK: ILT code should be simplified once PROTO enum is changed */
 575
 576         if (ilt_client == ILT_CLI_CDUC) {
 577                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
 578
 579                 cxts_per_p = ILT_PAGE_IN_BYTES(p_cli->p_size.val) /
 580                              (u32)CONN_CXT_SIZE(p_hwfn);
 581
 582                 lines_to_skip = cid_count / cxts_per_p;
 583         }
 584
 585         return lines_to_skip;
 586 }
 587
 588 static struct ecore_ilt_client_cfg *
 589 ecore_cxt_set_cli(struct ecore_ilt_client_cfg *p_cli)
 590 {
 591         p_cli->active = false;
 592         p_cli->first.val = 0;
 593         p_cli->last.val = 0;
 594         return p_cli;
 595 }
 596
 597 static struct ecore_ilt_cli_blk *
 598 ecore_cxt_set_blk(struct ecore_ilt_cli_blk *p_blk)
 599 {
 600         p_blk->total_size = 0;
 601         return p_blk;
 602 }
 603
 604 enum _ecore_status_t ecore_cxt_cfg_ilt_compute(struct ecore_hwfn *p_hwfn,
 605                                                u32 *line_count)
 606 {
 607         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 608         u32 curr_line, total, i, task_size, line;
 609         struct ecore_ilt_client_cfg *p_cli;
 610         struct ecore_ilt_cli_blk *p_blk;
 611         struct ecore_cdu_iids cdu_iids;
 612         struct ecore_src_iids src_iids;
 613         struct ecore_qm_iids qm_iids;
 614         struct ecore_tm_iids tm_iids;
 615         struct ecore_tid_seg *p_seg;
 616
 617         OSAL_MEM_ZERO(&qm_iids, sizeof(qm_iids));
 618         OSAL_MEM_ZERO(&cdu_iids, sizeof(cdu_iids));
 619         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 620         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
 621
 622         p_mngr->pf_start_line = RESC_START(p_hwfn, ECORE_ILT);
 623
 624         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 625                    "hwfn [%d] - Set context manager starting line to be 0x%08x\n",
 626                    p_hwfn->my_id, p_hwfn->p_cxt_mngr->pf_start_line);
 627
 628         /* CDUC */
 629         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUC]);
 630
 631         curr_line = p_mngr->pf_start_line;
 632
 633         /* CDUC PF */
 634         p_cli->pf_total_lines = 0;
 635
 636         /* get the counters for the CDUC,CDUC and QM clients  */
 637         ecore_cxt_cdu_iids(p_mngr, &cdu_iids);
 638
 639         p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUC_BLK]);
 640
 641         total = cdu_iids.pf_cids * CONN_CXT_SIZE(p_hwfn);
 642
 643         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 644                                total, CONN_CXT_SIZE(p_hwfn));
 645
 646         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 647         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 648
 649         p_blk->dynamic_line_cnt = ecore_ilt_get_dynamic_line_cnt(p_hwfn,
 650                                                                  ILT_CLI_CDUC);
 651
 652         /* CDUC VF */
 653         p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUC_BLK]);
 654         total = cdu_iids.per_vf_cids * CONN_CXT_SIZE(p_hwfn);
 655
 656         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 657                                total, CONN_CXT_SIZE(p_hwfn));
 658
 659         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_CDUC);
 660         p_cli->vf_total_lines = curr_line - p_blk->start_line;
 661
 662         for (i = 1; i < p_mngr->vf_count; i++)
 663                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 664                                        ILT_CLI_CDUC);
 665
 666         /* CDUT PF */
 667         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_CDUT]);
 668         p_cli->first.val = curr_line;
 669
 670         /* first the 'working' task memory */
 671         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 672                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 673                 if (!p_seg || p_seg->count == 0)
 674                         continue;
 675
 676                 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[CDUT_SEG_BLK(i)]);
 677                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 678                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total,
 679                                        p_mngr->task_type_size[p_seg->type]);
 680
 681                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 682                                        ILT_CLI_CDUT);
 683         }
 684
 685         /* next the 'init' task memory (forced load memory) */
 686         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 687                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 688                 if (!p_seg || p_seg->count == 0)
 689                         continue;
 690
 691                 p_blk = ecore_cxt_set_blk(
 692                                 &p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)]);
 693
 694                 if (!p_seg->has_fl_mem) {
 695                         /* The segment is active (total size pf 'working'
 696                          * memory is > 0) but has no FL (forced-load, Init)
 697                          * memory. Thus:
 698                          *
 699                          * 1.   The total-size in the corrsponding FL block of
 700                          *      the ILT client is set to 0 - No ILT line are
 701                          *      provisioned and no ILT memory allocated.
 702                          *
 703                          * 2.   The start-line of said block is set to the
 704                          *      start line of the matching working memory
 705                          *      block in the ILT client. This is later used to
 706                          *      configure the CDU segment offset registers and
 707                          *      results in an FL command for TIDs of this
 708                          *      segement behaves as regular load commands
 709                          *      (loading TIDs from the working memory).
 710                          */
 711                         line = p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line;
 712
 713                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 714                         continue;
 715                 }
 716                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 717
 718                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 719                                        curr_line, total,
 720                                        p_mngr->task_type_size[p_seg->type]);
 721
 722                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 723                                        ILT_CLI_CDUT);
 724         }
 725         p_cli->pf_total_lines = curr_line - p_cli->pf_blks[0].start_line;
 726
 727         /* CDUT VF */
 728         p_seg = ecore_cxt_tid_seg_info(p_hwfn, TASK_SEGMENT_VF);
 729         if (p_seg && p_seg->count) {
 730                 /* Stricly speaking we need to iterate over all VF
 731                  * task segment types, but a VF has only 1 segment
 732                  */
 733
 734                 /* 'working' memory */
 735                 total = p_seg->count * p_mngr->task_type_size[p_seg->type];
 736
 737                 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[CDUT_SEG_BLK(0)]);
 738                 ecore_ilt_cli_blk_fill(p_cli, p_blk,
 739                                        curr_line, total,
 740                                        p_mngr->task_type_size[p_seg->type]);
 741
 742                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 743                                        ILT_CLI_CDUT);
 744
 745                 /* 'init' memory */
 746                 p_blk = ecore_cxt_set_blk(
 747                                 &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)]);
 748                 if (!p_seg->has_fl_mem) {
 749                         /* see comment above */
 750                         line = p_cli->vf_blks[CDUT_SEG_BLK(0)].start_line;
 751                         ecore_ilt_cli_blk_fill(p_cli, p_blk, line, 0, 0);
 752                 } else {
 753                         task_size = p_mngr->task_type_size[p_seg->type];
 754                         ecore_ilt_cli_blk_fill(p_cli, p_blk,
 755                                                curr_line, total,
 756                                                task_size);
 757                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 758                                                ILT_CLI_CDUT);
 759                 }
 760                 p_cli->vf_total_lines = curr_line -
 761                                         p_cli->vf_blks[0].start_line;
 762
 763                 /* Now for the rest of the VFs */
 764                 for (i = 1; i < p_mngr->vf_count; i++) {
 765                         /* don't set p_blk i.e. don't clear total_size */
 766                         p_blk = &p_cli->vf_blks[CDUT_SEG_BLK(0)];
 767                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 768                                                ILT_CLI_CDUT);
 769
 770                         /* don't set p_blk i.e. don't clear total_size */
 771                         p_blk = &p_cli->vf_blks[CDUT_FL_SEG_BLK(0, VF)];
 772                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 773                                                ILT_CLI_CDUT);
 774                 }
 775         }
 776
 777         /* QM */
 778         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_QM]);
 779         p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
 780
 781         ecore_cxt_qm_iids(p_hwfn, &qm_iids);
 782         total = ecore_qm_pf_mem_size(p_hwfn->rel_pf_id, qm_iids.cids,
 783                                      qm_iids.vf_cids, qm_iids.tids,
 784                                      p_hwfn->qm_info.num_pqs,
 785                                      p_hwfn->qm_info.num_vf_pqs);
 786
 787         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
 788                    "QM ILT Info, (cids=%d, vf_cids=%d, tids=%d, num_pqs=%d, num_vf_pqs=%d, memory_size=%d)\n",
 789                    qm_iids.cids, qm_iids.vf_cids, qm_iids.tids,
 790                    p_hwfn->qm_info.num_pqs, p_hwfn->qm_info.num_vf_pqs, total);
 791
 792         ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line, total * 0x1000,
 793                                QM_PQ_ELEMENT_SIZE);
 794
 795         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line, ILT_CLI_QM);
 796         p_cli->pf_total_lines = curr_line - p_blk->start_line;
 797
 798         /* SRC */
 799         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_SRC]);
 800         ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
 801
 802         /* Both the PF and VFs searcher connections are stored in the per PF
 803          * database. Thus sum the PF searcher cids and all the VFs searcher
 804          * cids.
 805          */
 806         total = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 807         if (total) {
 808                 u32 local_max = OSAL_MAX_T(u32, total,
 809                                            SRC_MIN_NUM_ELEMS);
 810
 811                 total = OSAL_ROUNDUP_POW_OF_TWO(local_max);
 812
 813                 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
 814                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 815                                        total * sizeof(struct src_ent),
 816                                        sizeof(struct src_ent));
 817
 818                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 819                                        ILT_CLI_SRC);
 820                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 821         }
 822
 823         /* TM PF */
 824         p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TM]);
 825         ecore_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
 826         total = tm_iids.pf_cids + tm_iids.pf_tids_total;
 827         if (total) {
 828                 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[0]);
 829                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 830                                        total * TM_ELEM_SIZE,
 831                                        TM_ELEM_SIZE);
 832
 833                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 834                                        ILT_CLI_TM);
 835                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 836         }
 837
 838         /* TM VF */
 839         total = tm_iids.per_vf_cids + tm_iids.per_vf_tids;
 840         if (total) {
 841                 p_blk = ecore_cxt_set_blk(&p_cli->vf_blks[0]);
 842                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 843                                        total * TM_ELEM_SIZE,
 844                                        TM_ELEM_SIZE);
 845
 846                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 847                                        ILT_CLI_TM);
 848
 849                 p_cli->vf_total_lines = curr_line - p_blk->start_line;
 850                 for (i = 1; i < p_mngr->vf_count; i++) {
 851                         ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 852                                                ILT_CLI_TM);
 853                 }
 854         }
 855
 856         /* TSDM (SRQ CONTEXT) */
 857         total = ecore_cxt_get_srq_count(p_hwfn);
 858
 859         if (total) {
 860                 p_cli = ecore_cxt_set_cli(&p_mngr->clients[ILT_CLI_TSDM]);
 861                 p_blk = ecore_cxt_set_blk(&p_cli->pf_blks[SRQ_BLK]);
 862                 ecore_ilt_cli_blk_fill(p_cli, p_blk, curr_line,
 863                                        total * SRQ_CXT_SIZE, SRQ_CXT_SIZE);
 864
 865                 ecore_ilt_cli_adv_line(p_hwfn, p_cli, p_blk, &curr_line,
 866                                        ILT_CLI_TSDM);
 867                 p_cli->pf_total_lines = curr_line - p_blk->start_line;
 868         }
 869
 870         *line_count = curr_line - p_hwfn->p_cxt_mngr->pf_start_line;
 871
 872         if (curr_line - p_hwfn->p_cxt_mngr->pf_start_line >
 873             RESC_NUM(p_hwfn, ECORE_ILT)) {
 874                 return ECORE_INVAL;
 875         }
 876
 877         return ECORE_SUCCESS;
 878 }
 879
 880 u32 ecore_cxt_cfg_ilt_compute_excess(struct ecore_hwfn *p_hwfn, u32 used_lines)
 881 {
 882         struct ecore_ilt_client_cfg *p_cli;
 883         u32 excess_lines, available_lines;
 884         struct ecore_cxt_mngr *p_mngr;
 885         u32 ilt_page_size, elem_size;
 886         struct ecore_tid_seg *p_seg;
 887         int i;
 888
 889         available_lines = RESC_NUM(p_hwfn, ECORE_ILT);
 890         excess_lines = used_lines - available_lines;
 891
 892         if (!excess_lines)
 893                 return 0;
 894
 895         if (!ECORE_IS_RDMA_PERSONALITY(p_hwfn))
 896                 return 0;
 897
 898         p_mngr = p_hwfn->p_cxt_mngr;
 899         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
 900         ilt_page_size = ILT_PAGE_IN_BYTES(p_cli->p_size.val);
 901
 902         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
 903                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
 904                 if (!p_seg || p_seg->count == 0)
 905                         continue;
 906
 907                 elem_size = p_mngr->task_type_size[p_seg->type];
 908                 if (!elem_size)
 909                         continue;
 910
 911                 return (ilt_page_size / elem_size) * excess_lines;
 912         }
 913
 914         DP_ERR(p_hwfn, "failed computing excess ILT lines\n");
 915         return 0;
 916 }
 917
 918 static void ecore_cxt_src_t2_free(struct ecore_hwfn *p_hwfn)
 919 {
 920         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
 921         u32 i;
 922
 923         if (!p_mngr->t2)
 924                 return;
 925
 926         for (i = 0; i < p_mngr->t2_num_pages; i++)
 927                 if (p_mngr->t2[i].p_virt)
 928                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
 929                                                p_mngr->t2[i].p_virt,
 930                                                p_mngr->t2[i].p_phys,
 931                                                p_mngr->t2[i].size);
 932
 933         OSAL_FREE(p_hwfn->p_dev, p_mngr->t2);
 934         p_mngr->t2 = OSAL_NULL;
 935 }
 936
 937 static enum _ecore_status_t ecore_cxt_src_t2_alloc(struct ecore_hwfn *p_hwfn)
 938 {
 939         struct ecore_cxt_mngr *p_mngr  = p_hwfn->p_cxt_mngr;
 940         u32 conn_num, total_size, ent_per_page, psz, i;
 941         struct ecore_ilt_client_cfg *p_src;
 942         struct ecore_src_iids src_iids;
 943         struct ecore_dma_mem *p_t2;
 944         enum _ecore_status_t rc;
 945
 946         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
 947
 948         /* if the SRC ILT client is inactive - there are no connection
 949          * requiring the searcer, leave.
 950          */
 951         p_src = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_SRC];
 952         if (!p_src->active)
 953                 return ECORE_SUCCESS;
 954
 955         ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
 956         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
 957         total_size = conn_num * sizeof(struct src_ent);
 958
 959         /* use the same page size as the SRC ILT client */
 960         psz = ILT_PAGE_IN_BYTES(p_src->p_size.val);
 961         p_mngr->t2_num_pages = DIV_ROUND_UP(total_size, psz);
 962
 963         /* allocate t2 */
 964         p_mngr->t2 = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
 965                                  p_mngr->t2_num_pages *
 966                                  sizeof(struct ecore_dma_mem));
 967         if (!p_mngr->t2) {
 968                 DP_NOTICE(p_hwfn, true, "Failed to allocate t2 table\n");
 969                 rc = ECORE_NOMEM;
 970                 goto t2_fail;
 971         }
 972
 973         /* allocate t2 pages */
 974         for (i = 0; i < p_mngr->t2_num_pages; i++) {
 975                 u32 size = OSAL_MIN_T(u32, total_size, psz);
 976                 void **p_virt = &p_mngr->t2[i].p_virt;
 977
 978                 *p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
 979                                                   &p_mngr->t2[i].p_phys,
 980                                                   size);
 981                 if (!p_mngr->t2[i].p_virt) {
 982                         rc = ECORE_NOMEM;
 983                         goto t2_fail;
 984                 }
 985                 OSAL_MEM_ZERO(*p_virt, size);
 986                 p_mngr->t2[i].size = size;
 987                 total_size -= size;
 988         }
 989
 990         /* Set the t2 pointers */
 991
 992         /* entries per page - must be a power of two */
 993         ent_per_page = psz / sizeof(struct src_ent);
 994
 995         p_mngr->first_free = (u64)p_mngr->t2[0].p_phys;
 996
 997         p_t2 = &p_mngr->t2[(conn_num - 1) / ent_per_page];
 998         p_mngr->last_free = (u64)p_t2->p_phys +
 999                                  ((conn_num - 1) & (ent_per_page - 1)) *
1000                                  sizeof(struct src_ent);
1001
1002         for (i = 0; i < p_mngr->t2_num_pages; i++) {
1003                 u32 ent_num = OSAL_MIN_T(u32, ent_per_page, conn_num);
1004                 struct src_ent *entries = p_mngr->t2[i].p_virt;
1005                 u64 p_ent_phys = (u64)p_mngr->t2[i].p_phys, val;
1006                 u32 j;
1007
1008                 for (j = 0; j < ent_num - 1; j++) {
1009                         val = p_ent_phys +
1010                               (j + 1) * sizeof(struct src_ent);
1011                         entries[j].next = OSAL_CPU_TO_BE64(val);
1012                 }
1013
1014                 if (i < p_mngr->t2_num_pages - 1)
1015                         val = (u64)p_mngr->t2[i + 1].p_phys;
1016                 else
1017                         val = 0;
1018                 entries[j].next = OSAL_CPU_TO_BE64(val);
1019
1020                 conn_num -= ent_num;
1021         }
1022
1023         return ECORE_SUCCESS;
1024
1025 t2_fail:
1026         ecore_cxt_src_t2_free(p_hwfn);
1027         return rc;
1028 }
1029
1030 #define for_each_ilt_valid_client(pos, clients) \
1031         for (pos = 0; pos < ILT_CLI_MAX; pos++) \
1032                 if (!clients[pos].active) {     \
1033                         continue;               \
1034                 } else                          \
1035
1036
1037 /* Total number of ILT lines used by this PF */
1038 static u32 ecore_cxt_ilt_shadow_size(struct ecore_ilt_client_cfg *ilt_clients)
1039 {
1040         u32 size = 0;
1041         u32 i;
1042
1043         for_each_ilt_valid_client(i, ilt_clients)
1044                 size += (ilt_clients[i].last.val -
1045                          ilt_clients[i].first.val + 1);
1046
1047         return size;
1048 }
1049
1050 static void ecore_ilt_shadow_free(struct ecore_hwfn *p_hwfn)
1051 {
1052         struct ecore_ilt_client_cfg *p_cli = p_hwfn->p_cxt_mngr->clients;
1053         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1054         u32 ilt_size, i;
1055
1056         ilt_size = ecore_cxt_ilt_shadow_size(p_cli);
1057
1058         for (i = 0; p_mngr->ilt_shadow && i < ilt_size; i++) {
1059                 struct ecore_dma_mem *p_dma = &p_mngr->ilt_shadow[i];
1060
1061                 if (p_dma->p_virt)
1062                         OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
1063                                                p_dma->p_virt,
1064                                                p_dma->p_phys,
1065                                                p_dma->size);
1066                 p_dma->p_virt = OSAL_NULL;
1067         }
1068         OSAL_FREE(p_hwfn->p_dev, p_mngr->ilt_shadow);
1069 }
1070
1071 static enum _ecore_status_t ecore_ilt_blk_alloc(struct ecore_hwfn *p_hwfn,
1072                                                 struct ecore_ilt_cli_blk *p_blk,
1073                                                 enum ilt_clients ilt_client,
1074                                                 u32 start_line_offset)
1075 {
1076         struct ecore_dma_mem *ilt_shadow = p_hwfn->p_cxt_mngr->ilt_shadow;
1077         u32 lines, line, sz_left, lines_to_skip = 0;
1078
1079         /* Special handling for RoCE that supports dynamic allocation */
1080         if (ECORE_IS_RDMA_PERSONALITY(p_hwfn) &&
1081             ((ilt_client == ILT_CLI_CDUT) || ilt_client == ILT_CLI_TSDM))
1082                 return ECORE_SUCCESS;
1083
1084         lines_to_skip = p_blk->dynamic_line_cnt;
1085
1086         if (!p_blk->total_size)
1087                 return ECORE_SUCCESS;
1088
1089         sz_left = p_blk->total_size;
1090         lines = DIV_ROUND_UP(sz_left, p_blk->real_size_in_page) -
1091                 lines_to_skip;
1092         line = p_blk->start_line + start_line_offset -
1093                p_hwfn->p_cxt_mngr->pf_start_line + lines_to_skip;
1094
1095         for (; lines; lines--) {
1096                 dma_addr_t p_phys;
1097                 void *p_virt;
1098                 u32 size;
1099
1100                 size = OSAL_MIN_T(u32, sz_left, p_blk->real_size_in_page);
1101                 p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
1102                                                  &p_phys, size);
1103                 if (!p_virt)
1104                         return ECORE_NOMEM;
1105                 OSAL_MEM_ZERO(p_virt, size);
1106
1107                 ilt_shadow[line].p_phys = p_phys;
1108                 ilt_shadow[line].p_virt = p_virt;
1109                 ilt_shadow[line].size = size;
1110
1111                 DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1112                            "ILT shadow: Line [%d] Physical 0x%llx Virtual %p Size %d\n",
1113                            line, (unsigned long long)p_phys, p_virt, size);
1114
1115                 sz_left -= size;
1116                 line++;
1117         }
1118
1119         return ECORE_SUCCESS;
1120 }
1121
1122 static enum _ecore_status_t ecore_ilt_shadow_alloc(struct ecore_hwfn *p_hwfn)
1123 {
1124         struct ecore_cxt_mngr *p_mngr  = p_hwfn->p_cxt_mngr;
1125         struct ecore_ilt_client_cfg *clients = p_mngr->clients;
1126         struct ecore_ilt_cli_blk *p_blk;
1127         u32 size, i, j, k;
1128         enum _ecore_status_t rc;
1129
1130         size = ecore_cxt_ilt_shadow_size(clients);
1131         p_mngr->ilt_shadow = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL,
1132                                          size * sizeof(struct ecore_dma_mem));
1133
1134         if (!p_mngr->ilt_shadow) {
1135                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt shadow table\n");
1136                 rc = ECORE_NOMEM;
1137                 goto ilt_shadow_fail;
1138         }
1139
1140         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1141                    "Allocated 0x%x bytes for ilt shadow\n",
1142                    (u32)(size * sizeof(struct ecore_dma_mem)));
1143
1144         for_each_ilt_valid_client(i, clients) {
1145                 for (j = 0; j < ILT_CLI_PF_BLOCKS; j++) {
1146                         p_blk = &clients[i].pf_blks[j];
1147                         rc = ecore_ilt_blk_alloc(p_hwfn, p_blk, i, 0);
1148                         if (rc != ECORE_SUCCESS)
1149                                 goto ilt_shadow_fail;
1150                 }
1151                 for (k = 0; k < p_mngr->vf_count; k++) {
1152                         for (j = 0; j < ILT_CLI_VF_BLOCKS; j++) {
1153                                 u32 lines = clients[i].vf_total_lines * k;
1154
1155                                 p_blk = &clients[i].vf_blks[j];
1156                                 rc = ecore_ilt_blk_alloc(p_hwfn, p_blk,
1157                                                          i, lines);
1158                                 if (rc != ECORE_SUCCESS)
1159                                         goto ilt_shadow_fail;
1160                         }
1161                 }
1162         }
1163
1164         return ECORE_SUCCESS;
1165
1166 ilt_shadow_fail:
1167         ecore_ilt_shadow_free(p_hwfn);
1168         return rc;
1169 }
1170
1171 static void ecore_cid_map_free(struct ecore_hwfn *p_hwfn)
1172 {
1173         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1174         u32 type, vf;
1175
1176         for (type = 0; type < MAX_CONN_TYPES; type++) {
1177                 OSAL_FREE(p_hwfn->p_dev, p_mngr->acquired[type].cid_map);
1178                 p_mngr->acquired[type].max_count = 0;
1179                 p_mngr->acquired[type].start_cid = 0;
1180
1181                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1182                         OSAL_FREE(p_hwfn->p_dev,
1183                                   p_mngr->acquired_vf[type][vf].cid_map);
1184                         p_mngr->acquired_vf[type][vf].max_count = 0;
1185                         p_mngr->acquired_vf[type][vf].start_cid = 0;
1186                 }
1187         }
1188 }
1189
1190 static enum _ecore_status_t
1191 ecore_cid_map_alloc_single(struct ecore_hwfn *p_hwfn, u32 type,
1192                            u32 cid_start, u32 cid_count,
1193                            struct ecore_cid_acquired_map *p_map)
1194 {
1195         u32 size;
1196
1197         if (!cid_count)
1198                 return ECORE_SUCCESS;
1199
1200         size = MAP_WORD_SIZE * DIV_ROUND_UP(cid_count, BITS_PER_MAP_WORD);
1201         p_map->cid_map = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, size);
1202         if (p_map->cid_map == OSAL_NULL)
1203                 return ECORE_NOMEM;
1204
1205         p_map->max_count = cid_count;
1206         p_map->start_cid = cid_start;
1207
1208         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1209                    "Type %08x start: %08x count %08x\n",
1210                    type, p_map->start_cid, p_map->max_count);
1211
1212         return ECORE_SUCCESS;
1213 }
1214
1215 static enum _ecore_status_t ecore_cid_map_alloc(struct ecore_hwfn *p_hwfn)
1216 {
1217         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1218         u32 start_cid = 0, vf_start_cid = 0;
1219         u32 type, vf;
1220
1221         for (type = 0; type < MAX_CONN_TYPES; type++) {
1222                 struct ecore_conn_type_cfg *p_cfg = &p_mngr->conn_cfg[type];
1223                 struct ecore_cid_acquired_map *p_map;
1224
1225                 /* Handle PF maps */
1226                 p_map = &p_mngr->acquired[type];
1227                 if (ecore_cid_map_alloc_single(p_hwfn, type, start_cid,
1228                                                p_cfg->cid_count, p_map))
1229                         goto cid_map_fail;
1230
1231                 /* Handle VF maps */
1232                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1233                         p_map = &p_mngr->acquired_vf[type][vf];
1234                         if (ecore_cid_map_alloc_single(p_hwfn, type,
1235                                                        vf_start_cid,
1236                                                        p_cfg->cids_per_vf,
1237                                                        p_map))
1238                                 goto cid_map_fail;
1239                 }
1240
1241                 start_cid += p_cfg->cid_count;
1242                 vf_start_cid += p_cfg->cids_per_vf;
1243         }
1244
1245         return ECORE_SUCCESS;
1246
1247 cid_map_fail:
1248         ecore_cid_map_free(p_hwfn);
1249         return ECORE_NOMEM;
1250 }
1251
1252 enum _ecore_status_t ecore_cxt_mngr_alloc(struct ecore_hwfn *p_hwfn)
1253 {
1254         struct ecore_ilt_client_cfg *clients;
1255         struct ecore_cxt_mngr *p_mngr;
1256         u32 i;
1257
1258         p_mngr = OSAL_ZALLOC(p_hwfn->p_dev, GFP_KERNEL, sizeof(*p_mngr));
1259         if (!p_mngr) {
1260                 DP_NOTICE(p_hwfn, true, "Failed to allocate `struct ecore_cxt_mngr'\n");
1261                 return ECORE_NOMEM;
1262         }
1263
1264         /* Initialize ILT client registers */
1265         clients = p_mngr->clients;
1266         clients[ILT_CLI_CDUC].first.reg = ILT_CFG_REG(CDUC, FIRST_ILT);
1267         clients[ILT_CLI_CDUC].last.reg  = ILT_CFG_REG(CDUC, LAST_ILT);
1268         clients[ILT_CLI_CDUC].p_size.reg = ILT_CFG_REG(CDUC, P_SIZE);
1269
1270         clients[ILT_CLI_QM].first.reg   = ILT_CFG_REG(QM, FIRST_ILT);
1271         clients[ILT_CLI_QM].last.reg    = ILT_CFG_REG(QM, LAST_ILT);
1272         clients[ILT_CLI_QM].p_size.reg  = ILT_CFG_REG(QM, P_SIZE);
1273
1274         clients[ILT_CLI_TM].first.reg   = ILT_CFG_REG(TM, FIRST_ILT);
1275         clients[ILT_CLI_TM].last.reg    = ILT_CFG_REG(TM, LAST_ILT);
1276         clients[ILT_CLI_TM].p_size.reg  = ILT_CFG_REG(TM, P_SIZE);
1277
1278         clients[ILT_CLI_SRC].first.reg  = ILT_CFG_REG(SRC, FIRST_ILT);
1279         clients[ILT_CLI_SRC].last.reg   = ILT_CFG_REG(SRC, LAST_ILT);
1280         clients[ILT_CLI_SRC].p_size.reg = ILT_CFG_REG(SRC, P_SIZE);
1281
1282         clients[ILT_CLI_CDUT].first.reg = ILT_CFG_REG(CDUT, FIRST_ILT);
1283         clients[ILT_CLI_CDUT].last.reg  = ILT_CFG_REG(CDUT, LAST_ILT);
1284         clients[ILT_CLI_CDUT].p_size.reg = ILT_CFG_REG(CDUT, P_SIZE);
1285
1286         clients[ILT_CLI_TSDM].first.reg = ILT_CFG_REG(TSDM, FIRST_ILT);
1287         clients[ILT_CLI_TSDM].last.reg  = ILT_CFG_REG(TSDM, LAST_ILT);
1288         clients[ILT_CLI_TSDM].p_size.reg = ILT_CFG_REG(TSDM, P_SIZE);
1289
1290         /* default ILT page size for all clients is 32K */
1291         for (i = 0; i < ILT_CLI_MAX; i++)
1292                 p_mngr->clients[i].p_size.val = ILT_DEFAULT_HW_P_SIZE;
1293
1294         /* Initialize task sizes */
1295         p_mngr->task_type_size[0] = TYPE0_TASK_CXT_SIZE(p_hwfn);
1296         p_mngr->task_type_size[1] = TYPE1_TASK_CXT_SIZE(p_hwfn);
1297
1298         if (p_hwfn->p_dev->p_iov_info)
1299                 p_mngr->vf_count = p_hwfn->p_dev->p_iov_info->total_vfs;
1300
1301         /* Initialize the dynamic ILT allocation mutex */
1302         OSAL_MUTEX_ALLOC(p_hwfn, &p_mngr->mutex);
1303         OSAL_MUTEX_INIT(&p_mngr->mutex);
1304
1305         /* Set the cxt mangr pointer priori to further allocations */
1306         p_hwfn->p_cxt_mngr = p_mngr;
1307
1308         return ECORE_SUCCESS;
1309 }
1310
1311 enum _ecore_status_t ecore_cxt_tables_alloc(struct ecore_hwfn *p_hwfn)
1312 {
1313         enum _ecore_status_t    rc;
1314
1315         /* Allocate the ILT shadow table */
1316         rc = ecore_ilt_shadow_alloc(p_hwfn);
1317         if (rc) {
1318                 DP_NOTICE(p_hwfn, true, "Failed to allocate ilt memory\n");
1319                 goto tables_alloc_fail;
1320         }
1321
1322         /* Allocate the T2  table */
1323         rc = ecore_cxt_src_t2_alloc(p_hwfn);
1324         if (rc) {
1325                 DP_NOTICE(p_hwfn, true, "Failed to allocate T2 memory\n");
1326                 goto tables_alloc_fail;
1327         }
1328
1329         /* Allocate and initialize the acquired cids bitmaps */
1330         rc = ecore_cid_map_alloc(p_hwfn);
1331         if (rc) {
1332                 DP_NOTICE(p_hwfn, true, "Failed to allocate cid maps\n");
1333                 goto tables_alloc_fail;
1334         }
1335
1336         return ECORE_SUCCESS;
1337
1338 tables_alloc_fail:
1339         ecore_cxt_mngr_free(p_hwfn);
1340         return rc;
1341 }
1342 void ecore_cxt_mngr_free(struct ecore_hwfn *p_hwfn)
1343 {
1344         if (!p_hwfn->p_cxt_mngr)
1345                 return;
1346
1347         ecore_cid_map_free(p_hwfn);
1348         ecore_cxt_src_t2_free(p_hwfn);
1349         ecore_ilt_shadow_free(p_hwfn);
1350         OSAL_MUTEX_DEALLOC(&p_hwfn->p_cxt_mngr->mutex);
1351         OSAL_FREE(p_hwfn->p_dev, p_hwfn->p_cxt_mngr);
1352
1353         p_hwfn->p_cxt_mngr = OSAL_NULL;
1354 }
1355
1356 void ecore_cxt_mngr_setup(struct ecore_hwfn *p_hwfn)
1357 {
1358         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1359         struct ecore_cid_acquired_map *p_map;
1360         struct ecore_conn_type_cfg *p_cfg;
1361         int type;
1362         u32 len;
1363
1364         /* Reset acquired cids */
1365         for (type = 0; type < MAX_CONN_TYPES; type++) {
1366                 u32 vf;
1367
1368                 p_cfg = &p_mngr->conn_cfg[type];
1369                 if (p_cfg->cid_count) {
1370                         p_map = &p_mngr->acquired[type];
1371                         len = DIV_ROUND_UP(p_map->max_count,
1372                                            BITS_PER_MAP_WORD) *
1373                               MAP_WORD_SIZE;
1374                         OSAL_MEM_ZERO(p_map->cid_map, len);
1375                 }
1376
1377                 if (!p_cfg->cids_per_vf)
1378                         continue;
1379
1380                 for (vf = 0; vf < COMMON_MAX_NUM_VFS; vf++) {
1381                         p_map = &p_mngr->acquired_vf[type][vf];
1382                         len = DIV_ROUND_UP(p_map->max_count,
1383                                            BITS_PER_MAP_WORD) *
1384                               MAP_WORD_SIZE;
1385                         OSAL_MEM_ZERO(p_map->cid_map, len);
1386                 }
1387         }
1388 }
1389
1390 /* HW initialization helper (per Block, per phase) */
1391
1392 /* CDU Common */
1393 #define CDUC_CXT_SIZE_SHIFT                                             \
1394         CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE_SHIFT
1395
1396 #define CDUC_CXT_SIZE_MASK                                              \
1397         (CDU_REG_CID_ADDR_PARAMS_CONTEXT_SIZE >> CDUC_CXT_SIZE_SHIFT)
1398
1399 #define CDUC_BLOCK_WASTE_SHIFT                                          \
1400         CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE_SHIFT
1401
1402 #define CDUC_BLOCK_WASTE_MASK                                           \
1403         (CDU_REG_CID_ADDR_PARAMS_BLOCK_WASTE >> CDUC_BLOCK_WASTE_SHIFT)
1404
1405 #define CDUC_NCIB_SHIFT                                                 \
1406         CDU_REG_CID_ADDR_PARAMS_NCIB_SHIFT
1407
1408 #define CDUC_NCIB_MASK                                                  \
1409         (CDU_REG_CID_ADDR_PARAMS_NCIB >> CDUC_NCIB_SHIFT)
1410
1411 #define CDUT_TYPE0_CXT_SIZE_SHIFT                                       \
1412         CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE_SHIFT
1413
1414 #define CDUT_TYPE0_CXT_SIZE_MASK                                        \
1415         (CDU_REG_SEGMENT0_PARAMS_T0_TID_SIZE >>                         \
1416         CDUT_TYPE0_CXT_SIZE_SHIFT)
1417
1418 #define CDUT_TYPE0_BLOCK_WASTE_SHIFT                                    \
1419         CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE_SHIFT
1420
1421 #define CDUT_TYPE0_BLOCK_WASTE_MASK                                     \
1422         (CDU_REG_SEGMENT0_PARAMS_T0_TID_BLOCK_WASTE >>                  \
1423         CDUT_TYPE0_BLOCK_WASTE_SHIFT)
1424
1425 #define CDUT_TYPE0_NCIB_SHIFT                                           \
1426         CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK_SHIFT
1427
1428 #define CDUT_TYPE0_NCIB_MASK                                            \
1429         (CDU_REG_SEGMENT0_PARAMS_T0_NUM_TIDS_IN_BLOCK >>                \
1430         CDUT_TYPE0_NCIB_SHIFT)
1431
1432 #define CDUT_TYPE1_CXT_SIZE_SHIFT                                       \
1433         CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE_SHIFT
1434
1435 #define CDUT_TYPE1_CXT_SIZE_MASK                                        \
1436         (CDU_REG_SEGMENT1_PARAMS_T1_TID_SIZE >>                         \
1437         CDUT_TYPE1_CXT_SIZE_SHIFT)
1438
1439 #define CDUT_TYPE1_BLOCK_WASTE_SHIFT                                    \
1440         CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE_SHIFT
1441
1442 #define CDUT_TYPE1_BLOCK_WASTE_MASK                                     \
1443         (CDU_REG_SEGMENT1_PARAMS_T1_TID_BLOCK_WASTE >>                  \
1444         CDUT_TYPE1_BLOCK_WASTE_SHIFT)
1445
1446 #define CDUT_TYPE1_NCIB_SHIFT                                           \
1447         CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK_SHIFT
1448
1449 #define CDUT_TYPE1_NCIB_MASK                                            \
1450         (CDU_REG_SEGMENT1_PARAMS_T1_NUM_TIDS_IN_BLOCK >>                \
1451         CDUT_TYPE1_NCIB_SHIFT)
1452
1453 static void ecore_cdu_init_common(struct ecore_hwfn *p_hwfn)
1454 {
1455         u32 page_sz, elems_per_page, block_waste,  cxt_size, cdu_params = 0;
1456
1457         /* CDUC - connection configuration */
1458         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
1459         cxt_size = CONN_CXT_SIZE(p_hwfn);
1460         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1461         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1462
1463         SET_FIELD(cdu_params, CDUC_CXT_SIZE, cxt_size);
1464         SET_FIELD(cdu_params, CDUC_BLOCK_WASTE, block_waste);
1465         SET_FIELD(cdu_params, (u32)CDUC_NCIB, elems_per_page);
1466         STORE_RT_REG(p_hwfn, CDU_REG_CID_ADDR_PARAMS_RT_OFFSET, cdu_params);
1467
1468         /* CDUT - type-0 tasks configuration */
1469         page_sz = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT].p_size.val;
1470         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[0];
1471         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1472         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1473
1474         /* cxt size and block-waste are multipes of 8 */
1475         cdu_params = 0;
1476         SET_FIELD(cdu_params, (u32)CDUT_TYPE0_CXT_SIZE, (cxt_size >> 3));
1477         SET_FIELD(cdu_params, CDUT_TYPE0_BLOCK_WASTE, (block_waste >> 3));
1478         SET_FIELD(cdu_params, CDUT_TYPE0_NCIB, elems_per_page);
1479         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT0_PARAMS_RT_OFFSET, cdu_params);
1480
1481         /* CDUT - type-1 tasks configuration */
1482         cxt_size = p_hwfn->p_cxt_mngr->task_type_size[1];
1483         elems_per_page = ILT_PAGE_IN_BYTES(page_sz) / cxt_size;
1484         block_waste = ILT_PAGE_IN_BYTES(page_sz) - elems_per_page * cxt_size;
1485
1486         /* cxt size and block-waste are multipes of 8 */
1487         cdu_params = 0;
1488         SET_FIELD(cdu_params, (u32)CDUT_TYPE1_CXT_SIZE, (cxt_size >> 3));
1489         SET_FIELD(cdu_params, CDUT_TYPE1_BLOCK_WASTE, (block_waste >> 3));
1490         SET_FIELD(cdu_params, CDUT_TYPE1_NCIB, elems_per_page);
1491         STORE_RT_REG(p_hwfn, CDU_REG_SEGMENT1_PARAMS_RT_OFFSET, cdu_params);
1492 }
1493
1494 /* CDU PF */
1495 #define CDU_SEG_REG_TYPE_SHIFT          CDU_SEG_TYPE_OFFSET_REG_TYPE_SHIFT
1496 #define CDU_SEG_REG_TYPE_MASK           0x1
1497 #define CDU_SEG_REG_OFFSET_SHIFT        0
1498 #define CDU_SEG_REG_OFFSET_MASK         CDU_SEG_TYPE_OFFSET_REG_OFFSET_MASK
1499
1500 static void ecore_cdu_init_pf(struct ecore_hwfn *p_hwfn)
1501 {
1502         struct ecore_ilt_client_cfg *p_cli;
1503         struct ecore_tid_seg *p_seg;
1504         u32 cdu_seg_params, offset;
1505         int i;
1506
1507         static const u32 rt_type_offset_arr[] = {
1508                 CDU_REG_PF_SEG0_TYPE_OFFSET_RT_OFFSET,
1509                 CDU_REG_PF_SEG1_TYPE_OFFSET_RT_OFFSET,
1510                 CDU_REG_PF_SEG2_TYPE_OFFSET_RT_OFFSET,
1511                 CDU_REG_PF_SEG3_TYPE_OFFSET_RT_OFFSET
1512         };
1513
1514         static const u32 rt_type_offset_fl_arr[] = {
1515                 CDU_REG_PF_FL_SEG0_TYPE_OFFSET_RT_OFFSET,
1516                 CDU_REG_PF_FL_SEG1_TYPE_OFFSET_RT_OFFSET,
1517                 CDU_REG_PF_FL_SEG2_TYPE_OFFSET_RT_OFFSET,
1518                 CDU_REG_PF_FL_SEG3_TYPE_OFFSET_RT_OFFSET
1519         };
1520
1521         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1522
1523         /* There are initializations only for CDUT during pf Phase */
1524         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1525                 /* Segment 0*/
1526                 p_seg = ecore_cxt_tid_seg_info(p_hwfn, i);
1527                 if (!p_seg)
1528                         continue;
1529
1530                 /* Note: start_line is already adjusted for the CDU
1531                  * segment register granularity, so we just need to
1532                  * divide. Adjustment is implicit as we assume ILT
1533                  * Page size is larger than 32K!
1534                  */
1535                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1536                          (p_cli->pf_blks[CDUT_SEG_BLK(i)].start_line -
1537                           p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1538
1539                 cdu_seg_params = 0;
1540                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1541                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1542                 STORE_RT_REG(p_hwfn, rt_type_offset_arr[i],
1543                              cdu_seg_params);
1544
1545                 offset = (ILT_PAGE_IN_BYTES(p_cli->p_size.val) *
1546                          (p_cli->pf_blks[CDUT_FL_SEG_BLK(i, PF)].start_line -
1547                           p_cli->first.val)) / CDUT_SEG_ALIGNMET_IN_BYTES;
1548
1549                 cdu_seg_params = 0;
1550                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_TYPE, p_seg->type);
1551                 SET_FIELD(cdu_seg_params, CDU_SEG_REG_OFFSET, offset);
1552                 STORE_RT_REG(p_hwfn, rt_type_offset_fl_arr[i],
1553                              cdu_seg_params);
1554
1555         }
1556 }
1557
1558 void ecore_qm_init_pf(struct ecore_hwfn *p_hwfn)
1559 {
1560         struct ecore_qm_info *qm_info = &p_hwfn->qm_info;
1561         struct ecore_qm_iids iids;
1562
1563         OSAL_MEM_ZERO(&iids, sizeof(iids));
1564         ecore_cxt_qm_iids(p_hwfn, &iids);
1565
1566         ecore_qm_pf_rt_init(p_hwfn, p_hwfn->p_main_ptt, p_hwfn->port_id,
1567                             p_hwfn->rel_pf_id, qm_info->max_phys_tcs_per_port,
1568                             p_hwfn->first_on_engine,
1569                             iids.cids, iids.vf_cids, iids.tids,
1570                             qm_info->start_pq,
1571                             qm_info->num_pqs - qm_info->num_vf_pqs,
1572                             qm_info->num_vf_pqs,
1573                             qm_info->start_vport,
1574                             qm_info->num_vports, qm_info->pf_wfq, qm_info->pf_rl,
1575                             p_hwfn->qm_info.qm_pq_params,
1576                             p_hwfn->qm_info.qm_vport_params);
1577 }
1578
1579 /* CM PF */
1580 static void ecore_cm_init_pf(struct ecore_hwfn *p_hwfn)
1581 {
1582         STORE_RT_REG(p_hwfn, XCM_REG_CON_PHY_Q3_RT_OFFSET, ecore_get_cm_pq_idx(p_hwfn, PQ_FLAGS_LB));
1583 }
1584
1585 /* DQ PF */
1586 static void ecore_dq_init_pf(struct ecore_hwfn *p_hwfn)
1587 {
1588         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1589         u32 dq_pf_max_cid = 0, dq_vf_max_cid = 0;
1590
1591         dq_pf_max_cid += (p_mngr->conn_cfg[0].cid_count >> DQ_RANGE_SHIFT);
1592         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_0_RT_OFFSET, dq_pf_max_cid);
1593
1594         dq_vf_max_cid += (p_mngr->conn_cfg[0].cids_per_vf >> DQ_RANGE_SHIFT);
1595         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_0_RT_OFFSET, dq_vf_max_cid);
1596
1597         dq_pf_max_cid += (p_mngr->conn_cfg[1].cid_count >> DQ_RANGE_SHIFT);
1598         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_1_RT_OFFSET, dq_pf_max_cid);
1599
1600         dq_vf_max_cid += (p_mngr->conn_cfg[1].cids_per_vf >> DQ_RANGE_SHIFT);
1601         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_1_RT_OFFSET, dq_vf_max_cid);
1602
1603         dq_pf_max_cid += (p_mngr->conn_cfg[2].cid_count >> DQ_RANGE_SHIFT);
1604         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_2_RT_OFFSET, dq_pf_max_cid);
1605
1606         dq_vf_max_cid += (p_mngr->conn_cfg[2].cids_per_vf >> DQ_RANGE_SHIFT);
1607         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_2_RT_OFFSET, dq_vf_max_cid);
1608
1609         dq_pf_max_cid += (p_mngr->conn_cfg[3].cid_count >> DQ_RANGE_SHIFT);
1610         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_3_RT_OFFSET, dq_pf_max_cid);
1611
1612         dq_vf_max_cid += (p_mngr->conn_cfg[3].cids_per_vf >> DQ_RANGE_SHIFT);
1613         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_3_RT_OFFSET, dq_vf_max_cid);
1614
1615         dq_pf_max_cid += (p_mngr->conn_cfg[4].cid_count >> DQ_RANGE_SHIFT);
1616         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_4_RT_OFFSET, dq_pf_max_cid);
1617
1618         dq_vf_max_cid += (p_mngr->conn_cfg[4].cids_per_vf >> DQ_RANGE_SHIFT);
1619         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_4_RT_OFFSET, dq_vf_max_cid);
1620
1621         dq_pf_max_cid += (p_mngr->conn_cfg[5].cid_count >> DQ_RANGE_SHIFT);
1622         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_5_RT_OFFSET, dq_pf_max_cid);
1623
1624         dq_vf_max_cid += (p_mngr->conn_cfg[5].cids_per_vf >> DQ_RANGE_SHIFT);
1625         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_5_RT_OFFSET, dq_vf_max_cid);
1626
1627         /* Connection types 6 & 7 are not in use, yet they must be configured
1628          * as the highest possible connection. Not configuring them means the
1629          * defaults will be  used, and with a large number of cids a bug may
1630          * occur, if the defaults will be smaller than dq_pf_max_cid /
1631          * dq_vf_max_cid.
1632          */
1633         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_6_RT_OFFSET, dq_pf_max_cid);
1634         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_6_RT_OFFSET, dq_vf_max_cid);
1635
1636         STORE_RT_REG(p_hwfn, DORQ_REG_PF_MAX_ICID_7_RT_OFFSET, dq_pf_max_cid);
1637         STORE_RT_REG(p_hwfn, DORQ_REG_VF_MAX_ICID_7_RT_OFFSET, dq_vf_max_cid);
1638 }
1639
1640 static void ecore_ilt_bounds_init(struct ecore_hwfn *p_hwfn)
1641 {
1642         struct ecore_ilt_client_cfg *ilt_clients;
1643         int i;
1644
1645         ilt_clients = p_hwfn->p_cxt_mngr->clients;
1646         for_each_ilt_valid_client(i, ilt_clients) {
1647                 STORE_RT_REG(p_hwfn,
1648                              ilt_clients[i].first.reg,
1649                              ilt_clients[i].first.val);
1650                 STORE_RT_REG(p_hwfn,
1651                              ilt_clients[i].last.reg,
1652                              ilt_clients[i].last.val);
1653                 STORE_RT_REG(p_hwfn,
1654                              ilt_clients[i].p_size.reg,
1655                              ilt_clients[i].p_size.val);
1656         }
1657 }
1658
1659 static void ecore_ilt_vf_bounds_init(struct ecore_hwfn *p_hwfn)
1660 {
1661         struct ecore_ilt_client_cfg *p_cli;
1662         u32 blk_factor;
1663
1664         /* For simplicty  we set the 'block' to be an ILT page */
1665         if (p_hwfn->p_dev->p_iov_info) {
1666                 struct ecore_hw_sriov_info *p_iov = p_hwfn->p_dev->p_iov_info;
1667
1668                 STORE_RT_REG(p_hwfn,
1669                              PSWRQ2_REG_VF_BASE_RT_OFFSET,
1670                              p_iov->first_vf_in_pf);
1671                 STORE_RT_REG(p_hwfn,
1672                              PSWRQ2_REG_VF_LAST_ILT_RT_OFFSET,
1673                              p_iov->first_vf_in_pf + p_iov->total_vfs);
1674         }
1675
1676         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
1677         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1678         if (p_cli->active) {
1679                 STORE_RT_REG(p_hwfn,
1680                              PSWRQ2_REG_CDUC_BLOCKS_FACTOR_RT_OFFSET,
1681                              blk_factor);
1682                 STORE_RT_REG(p_hwfn,
1683                              PSWRQ2_REG_CDUC_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1684                              p_cli->pf_total_lines);
1685                 STORE_RT_REG(p_hwfn,
1686                              PSWRQ2_REG_CDUC_VF_BLOCKS_RT_OFFSET,
1687                              p_cli->vf_total_lines);
1688         }
1689
1690         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
1691         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1692         if (p_cli->active) {
1693                 STORE_RT_REG(p_hwfn,
1694                              PSWRQ2_REG_CDUT_BLOCKS_FACTOR_RT_OFFSET,
1695                              blk_factor);
1696                 STORE_RT_REG(p_hwfn,
1697                              PSWRQ2_REG_CDUT_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1698                              p_cli->pf_total_lines);
1699                 STORE_RT_REG(p_hwfn,
1700                              PSWRQ2_REG_CDUT_VF_BLOCKS_RT_OFFSET,
1701                              p_cli->vf_total_lines);
1702         }
1703
1704         p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TM];
1705         blk_factor = OSAL_LOG2(ILT_PAGE_IN_BYTES(p_cli->p_size.val) >> 10);
1706         if (p_cli->active) {
1707                 STORE_RT_REG(p_hwfn,
1708                              PSWRQ2_REG_TM_BLOCKS_FACTOR_RT_OFFSET,
1709                              blk_factor);
1710                 STORE_RT_REG(p_hwfn,
1711                              PSWRQ2_REG_TM_NUMBER_OF_PF_BLOCKS_RT_OFFSET,
1712                              p_cli->pf_total_lines);
1713                 STORE_RT_REG(p_hwfn,
1714                              PSWRQ2_REG_TM_VF_BLOCKS_RT_OFFSET,
1715                              p_cli->vf_total_lines);
1716         }
1717 }
1718
1719 /* ILT (PSWRQ2) PF */
1720 static void ecore_ilt_init_pf(struct ecore_hwfn *p_hwfn)
1721 {
1722         struct ecore_ilt_client_cfg *clients;
1723         struct ecore_cxt_mngr *p_mngr;
1724         struct ecore_dma_mem *p_shdw;
1725         u32 line, rt_offst, i;
1726
1727         ecore_ilt_bounds_init(p_hwfn);
1728         ecore_ilt_vf_bounds_init(p_hwfn);
1729
1730         p_mngr  = p_hwfn->p_cxt_mngr;
1731         p_shdw  = p_mngr->ilt_shadow;
1732         clients = p_hwfn->p_cxt_mngr->clients;
1733
1734         for_each_ilt_valid_client(i, clients) {
1735                 /* Client's 1st val and RT array are absolute, ILT shadows'
1736                  * lines are relative.
1737                  */
1738                 line = clients[i].first.val - p_mngr->pf_start_line;
1739                 rt_offst = PSWRQ2_REG_ILT_MEMORY_RT_OFFSET +
1740                            clients[i].first.val * ILT_ENTRY_IN_REGS;
1741
1742                 for (; line <= clients[i].last.val - p_mngr->pf_start_line;
1743                      line++, rt_offst += ILT_ENTRY_IN_REGS) {
1744                         u64 ilt_hw_entry = 0;
1745
1746                         /** p_virt could be OSAL_NULL incase of dynamic
1747                          *  allocation
1748                          */
1749                         if (p_shdw[line].p_virt != OSAL_NULL) {
1750                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
1751                                 SET_FIELD(ilt_hw_entry, ILT_ENTRY_PHY_ADDR,
1752                                           (p_shdw[line].p_phys >> 12));
1753
1754                                 DP_VERBOSE(
1755                                         p_hwfn, ECORE_MSG_ILT,
1756                                         "Setting RT[0x%08x] from ILT[0x%08x] [Client is %d] to Physical addr: 0x%llx\n",
1757                                         rt_offst, line, i,
1758                                         (unsigned long long)(p_shdw[line].p_phys >> 12));
1759                         }
1760
1761                         STORE_RT_REG_AGG(p_hwfn, rt_offst, ilt_hw_entry);
1762                 }
1763         }
1764 }
1765
1766 /* SRC (Searcher) PF */
1767 static void ecore_src_init_pf(struct ecore_hwfn *p_hwfn)
1768 {
1769         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1770         u32 rounded_conn_num, conn_num, conn_max;
1771         struct ecore_src_iids src_iids;
1772
1773         OSAL_MEM_ZERO(&src_iids, sizeof(src_iids));
1774         ecore_cxt_src_iids(p_hwfn, p_mngr, &src_iids);
1775         conn_num = src_iids.pf_cids + src_iids.per_vf_cids * p_mngr->vf_count;
1776         if (!conn_num)
1777                 return;
1778
1779         conn_max = OSAL_MAX_T(u32, conn_num, SRC_MIN_NUM_ELEMS);
1780         rounded_conn_num = OSAL_ROUNDUP_POW_OF_TWO(conn_max);
1781
1782         STORE_RT_REG(p_hwfn, SRC_REG_COUNTFREE_RT_OFFSET, conn_num);
1783         STORE_RT_REG(p_hwfn, SRC_REG_NUMBER_HASH_BITS_RT_OFFSET,
1784                      OSAL_LOG2(rounded_conn_num));
1785
1786         STORE_RT_REG_AGG(p_hwfn, SRC_REG_FIRSTFREE_RT_OFFSET,
1787                          p_hwfn->p_cxt_mngr->first_free);
1788         STORE_RT_REG_AGG(p_hwfn, SRC_REG_LASTFREE_RT_OFFSET,
1789                          p_hwfn->p_cxt_mngr->last_free);
1790         DP_VERBOSE(p_hwfn, ECORE_MSG_ILT,
1791                    "Configured SEARCHER for 0x%08x connections\n",
1792                    conn_num);
1793 }
1794
1795 /* Timers PF */
1796 #define TM_CFG_NUM_IDS_SHIFT            0
1797 #define TM_CFG_NUM_IDS_MASK             0xFFFFULL
1798 #define TM_CFG_PRE_SCAN_OFFSET_SHIFT    16
1799 #define TM_CFG_PRE_SCAN_OFFSET_MASK     0x1FFULL
1800 #define TM_CFG_PARENT_PF_SHIFT          25
1801 #define TM_CFG_PARENT_PF_MASK           0x7ULL
1802
1803 #define TM_CFG_CID_PRE_SCAN_ROWS_SHIFT  30
1804 #define TM_CFG_CID_PRE_SCAN_ROWS_MASK   0x1FFULL
1805
1806 #define TM_CFG_TID_OFFSET_SHIFT         30
1807 #define TM_CFG_TID_OFFSET_MASK          0x7FFFFULL
1808 #define TM_CFG_TID_PRE_SCAN_ROWS_SHIFT  49
1809 #define TM_CFG_TID_PRE_SCAN_ROWS_MASK   0x1FFULL
1810
1811 static void ecore_tm_init_pf(struct ecore_hwfn *p_hwfn)
1812 {
1813         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1814         u32 active_seg_mask = 0, tm_offset, rt_reg;
1815         struct ecore_tm_iids tm_iids;
1816         u64 cfg_word;
1817         u8 i;
1818
1819         OSAL_MEM_ZERO(&tm_iids, sizeof(tm_iids));
1820         ecore_cxt_tm_iids(p_hwfn, p_mngr, &tm_iids);
1821
1822         /* @@@TBD No pre-scan for now */
1823
1824         /* Note: We assume consecutive VFs for a PF */
1825         for (i = 0; i < p_mngr->vf_count; i++) {
1826                 cfg_word = 0;
1827                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_cids);
1828                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1829                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1830                 SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all */
1831
1832                 rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1833                          (sizeof(cfg_word) / sizeof(u32)) *
1834                          (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1835                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1836         }
1837
1838         cfg_word = 0;
1839         SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_cids);
1840         SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1841         SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);         /* n/a for PF */
1842         SET_FIELD(cfg_word, TM_CFG_CID_PRE_SCAN_ROWS, 0); /* scan all   */
1843
1844         rt_reg = TM_REG_CONFIG_CONN_MEM_RT_OFFSET +
1845                  (sizeof(cfg_word) / sizeof(u32)) *
1846                  (NUM_OF_VFS(p_hwfn->p_dev) + p_hwfn->rel_pf_id);
1847         STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1848
1849         /* enale scan */
1850         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_CONN_RT_OFFSET,
1851                      tm_iids.pf_cids  ? 0x1 : 0x0);
1852
1853         /* @@@TBD how to enable the scan for the VFs */
1854
1855         tm_offset = tm_iids.per_vf_cids;
1856
1857         /* Note: We assume consecutive VFs for a PF */
1858         for (i = 0; i < p_mngr->vf_count; i++) {
1859                 cfg_word = 0;
1860                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.per_vf_tids);
1861                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1862                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, p_hwfn->rel_pf_id);
1863                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1864                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1865
1866                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1867                          (sizeof(cfg_word) / sizeof(u32)) *
1868                          (p_hwfn->p_dev->p_iov_info->first_vf_in_pf + i);
1869
1870                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1871         }
1872
1873         tm_offset = tm_iids.pf_cids;
1874         for (i = 0; i < NUM_TASK_PF_SEGMENTS; i++) {
1875                 cfg_word = 0;
1876                 SET_FIELD(cfg_word, TM_CFG_NUM_IDS, tm_iids.pf_tids[i]);
1877                 SET_FIELD(cfg_word, TM_CFG_PRE_SCAN_OFFSET, 0);
1878                 SET_FIELD(cfg_word, TM_CFG_PARENT_PF, 0);
1879                 SET_FIELD(cfg_word, TM_CFG_TID_OFFSET, tm_offset);
1880                 SET_FIELD(cfg_word, TM_CFG_TID_PRE_SCAN_ROWS, (u64)0);
1881
1882                 rt_reg = TM_REG_CONFIG_TASK_MEM_RT_OFFSET +
1883                          (sizeof(cfg_word) / sizeof(u32)) *
1884                          (NUM_OF_VFS(p_hwfn->p_dev) +
1885                          p_hwfn->rel_pf_id * NUM_TASK_PF_SEGMENTS + i);
1886
1887                 STORE_RT_REG_AGG(p_hwfn, rt_reg, cfg_word);
1888                 active_seg_mask |= (tm_iids.pf_tids[i] ? (1 << i) : 0);
1889
1890                 tm_offset += tm_iids.pf_tids[i];
1891         }
1892
1893         if (ECORE_IS_RDMA_PERSONALITY(p_hwfn))
1894                 active_seg_mask = 0;
1895
1896         STORE_RT_REG(p_hwfn, TM_REG_PF_ENABLE_TASK_RT_OFFSET, active_seg_mask);
1897
1898         /* @@@TBD how to enable the scan for the VFs */
1899 }
1900
1901 static void ecore_prs_init_common(struct ecore_hwfn *p_hwfn)
1902 {
1903         if ((p_hwfn->hw_info.personality == ECORE_PCI_FCOE) &&
1904             p_hwfn->pf_params.fcoe_pf_params.is_target)
1905                 STORE_RT_REG(p_hwfn, PRS_REG_SEARCH_RESP_INITIATOR_TYPE_RT_OFFSET, 0);
1906 }
1907
1908 static void ecore_prs_init_pf(struct ecore_hwfn *p_hwfn)
1909 {
1910         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1911         struct ecore_conn_type_cfg *p_fcoe = &p_mngr->conn_cfg[PROTOCOLID_FCOE];
1912         struct ecore_tid_seg *p_tid;
1913
1914         /* If FCoE is active set the MAX OX_ID (tid) in the Parser */
1915         if (!p_fcoe->cid_count)
1916                 return;
1917
1918         p_tid = &p_fcoe->tid_seg[ECORE_CXT_FCOE_TID_SEG];
1919         if (p_hwfn->pf_params.fcoe_pf_params.is_target) {
1920                 STORE_RT_REG_AGG(p_hwfn,
1921                                  PRS_REG_TASK_ID_MAX_TARGET_PF_RT_OFFSET,
1922                                  p_tid->count);
1923         } else {
1924                 STORE_RT_REG_AGG(p_hwfn,
1925                                 PRS_REG_TASK_ID_MAX_INITIATOR_PF_RT_OFFSET,
1926                                 p_tid->count);
1927         }
1928 }
1929
1930 void ecore_cxt_hw_init_common(struct ecore_hwfn *p_hwfn)
1931 {
1932         /* CDU configuration */
1933         ecore_cdu_init_common(p_hwfn);
1934         ecore_prs_init_common(p_hwfn);
1935 }
1936
1937 void ecore_cxt_hw_init_pf(struct ecore_hwfn *p_hwfn)
1938 {
1939         ecore_qm_init_pf(p_hwfn);
1940         ecore_cm_init_pf(p_hwfn);
1941         ecore_dq_init_pf(p_hwfn);
1942         ecore_cdu_init_pf(p_hwfn);
1943         ecore_ilt_init_pf(p_hwfn);
1944         ecore_src_init_pf(p_hwfn);
1945         ecore_tm_init_pf(p_hwfn);
1946         ecore_prs_init_pf(p_hwfn);
1947 }
1948
1949 enum _ecore_status_t _ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1950                                             enum protocol_type type,
1951                                             u32 *p_cid, u8 vfid)
1952 {
1953         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
1954         struct ecore_cid_acquired_map *p_map;
1955         u32 rel_cid;
1956
1957         if (type >= MAX_CONN_TYPES) {
1958                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1959                 return ECORE_INVAL;
1960         }
1961
1962         if (vfid >= COMMON_MAX_NUM_VFS && vfid != ECORE_CXT_PF_CID) {
1963                 DP_NOTICE(p_hwfn, true, "VF [%02x] is out of range\n", vfid);
1964                 return ECORE_INVAL;
1965         }
1966
1967         /* Determine the right map to take this CID from */
1968         if (vfid == ECORE_CXT_PF_CID)
1969                 p_map = &p_mngr->acquired[type];
1970         else
1971                 p_map = &p_mngr->acquired_vf[type][vfid];
1972
1973         if (p_map->cid_map == OSAL_NULL) {
1974                 DP_NOTICE(p_hwfn, true, "Invalid protocol type %d", type);
1975                 return ECORE_INVAL;
1976         }
1977
1978         rel_cid = OSAL_FIND_FIRST_ZERO_BIT(p_map->cid_map,
1979                                            p_map->max_count);
1980
1981         if (rel_cid >= p_map->max_count) {
1982                 DP_NOTICE(p_hwfn, false, "no CID available for protocol %d\n",
1983                           type);
1984                 return ECORE_NORESOURCES;
1985         }
1986
1987         OSAL_SET_BIT(rel_cid, p_map->cid_map);
1988
1989         *p_cid = rel_cid + p_map->start_cid;
1990
1991         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
1992                    "Acquired cid 0x%08x [rel. %08x] vfid %02x type %d\n",
1993                    *p_cid, rel_cid, vfid, type);
1994
1995         return ECORE_SUCCESS;
1996 }
1997
1998 enum _ecore_status_t ecore_cxt_acquire_cid(struct ecore_hwfn *p_hwfn,
1999                                            enum protocol_type type,
2000                                            u32 *p_cid)
2001 {
2002         return _ecore_cxt_acquire_cid(p_hwfn, type, p_cid, ECORE_CXT_PF_CID);
2003 }
2004
2005 static bool ecore_cxt_test_cid_acquired(struct ecore_hwfn *p_hwfn,
2006                                         u32 cid, u8 vfid,
2007                                         enum protocol_type *p_type,
2008                                         struct ecore_cid_acquired_map **pp_map)
2009 {
2010         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2011         u32 rel_cid;
2012
2013         /* Iterate over protocols and find matching cid range */
2014         for (*p_type = 0; *p_type < MAX_CONN_TYPES; (*p_type)++) {
2015                 if (vfid == ECORE_CXT_PF_CID)
2016                         *pp_map = &p_mngr->acquired[*p_type];
2017                 else
2018                         *pp_map = &p_mngr->acquired_vf[*p_type][vfid];
2019
2020                 if (!((*pp_map)->cid_map))
2021                         continue;
2022                 if (cid >= (*pp_map)->start_cid &&
2023                     cid < (*pp_map)->start_cid + (*pp_map)->max_count) {
2024                         break;
2025                 }
2026         }
2027
2028         if (*p_type == MAX_CONN_TYPES) {
2029                 DP_NOTICE(p_hwfn, true, "Invalid CID %d vfid %02x", cid, vfid);
2030                 goto fail;
2031         }
2032
2033         rel_cid = cid - (*pp_map)->start_cid;
2034         if (!OSAL_TEST_BIT(rel_cid, (*pp_map)->cid_map)) {
2035                 DP_NOTICE(p_hwfn, true,
2036                           "CID %d [vifd %02x] not acquired", cid, vfid);
2037                 goto fail;
2038         }
2039
2040         return true;
2041 fail:
2042         *p_type = MAX_CONN_TYPES;
2043         *pp_map = OSAL_NULL;
2044         return false;
2045 }
2046
2047 void _ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid, u8 vfid)
2048 {
2049         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
2050         enum protocol_type type;
2051         bool b_acquired;
2052         u32 rel_cid;
2053
2054         if (vfid != ECORE_CXT_PF_CID && vfid > COMMON_MAX_NUM_VFS) {
2055                 DP_NOTICE(p_hwfn, true,
2056                           "Trying to return incorrect CID belonging to VF %02x\n",
2057                           vfid);
2058                 return;
2059         }
2060
2061         /* Test acquired and find matching per-protocol map */
2062         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, cid, vfid,
2063                                                  &type, &p_map);
2064
2065         if (!b_acquired)
2066                 return;
2067
2068         rel_cid = cid - p_map->start_cid;
2069         OSAL_CLEAR_BIT(rel_cid, p_map->cid_map);
2070
2071         DP_VERBOSE(p_hwfn, ECORE_MSG_CXT,
2072                    "Released CID 0x%08x [rel. %08x] vfid %02x type %d\n",
2073                    cid, rel_cid, vfid, type);
2074 }
2075
2076 void ecore_cxt_release_cid(struct ecore_hwfn *p_hwfn, u32 cid)
2077 {
2078         _ecore_cxt_release_cid(p_hwfn, cid, ECORE_CXT_PF_CID);
2079 }
2080
2081 enum _ecore_status_t ecore_cxt_get_cid_info(struct ecore_hwfn *p_hwfn,
2082                                             struct ecore_cxt_info *p_info)
2083 {
2084         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2085         struct ecore_cid_acquired_map *p_map = OSAL_NULL;
2086         u32 conn_cxt_size, hw_p_size, cxts_per_p, line;
2087         enum protocol_type type;
2088         bool b_acquired;
2089
2090         /* Test acquired and find matching per-protocol map */
2091         b_acquired = ecore_cxt_test_cid_acquired(p_hwfn, p_info->iid,
2092                                                  ECORE_CXT_PF_CID,
2093                                                  &type, &p_map);
2094
2095         if (!b_acquired)
2096                 return ECORE_INVAL;
2097
2098         /* set the protocl type */
2099         p_info->type = type;
2100
2101         /* compute context virtual pointer */
2102         hw_p_size = p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC].p_size.val;
2103
2104         conn_cxt_size = CONN_CXT_SIZE(p_hwfn);
2105         cxts_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / conn_cxt_size;
2106         line = p_info->iid / cxts_per_p;
2107
2108         /* Make sure context is allocated (dynamic allocation) */
2109         if (!p_mngr->ilt_shadow[line].p_virt)
2110                 return ECORE_INVAL;
2111
2112         p_info->p_cxt = (u8 *)p_mngr->ilt_shadow[line].p_virt +
2113                               p_info->iid % cxts_per_p * conn_cxt_size;
2114
2115         DP_VERBOSE(p_hwfn, (ECORE_MSG_ILT | ECORE_MSG_CXT),
2116                    "Accessing ILT shadow[%d]: CXT pointer is at %p (for iid %d)\n",
2117                    (p_info->iid / cxts_per_p), p_info->p_cxt, p_info->iid);
2118
2119         return ECORE_SUCCESS;
2120 }
2121
2122 static void ecore_cxt_set_srq_count(struct ecore_hwfn *p_hwfn, u32 num_srqs)
2123 {
2124         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
2125
2126         p_mgr->srq_count = num_srqs;
2127 }
2128
2129 u32 ecore_cxt_get_srq_count(struct ecore_hwfn *p_hwfn)
2130 {
2131         struct ecore_cxt_mngr *p_mgr = p_hwfn->p_cxt_mngr;
2132
2133         return p_mgr->srq_count;
2134 }
2135
2136 static void ecore_rdma_set_pf_params(struct ecore_hwfn *p_hwfn,
2137                                      struct ecore_rdma_pf_params *p_params,
2138                                      u32 num_tasks)
2139 {
2140         u32 num_cons, num_qps, num_srqs;
2141         enum protocol_type proto;
2142
2143         /* Override personality with rdma flavor */
2144         num_srqs = OSAL_MIN_T(u32, ECORE_RDMA_MAX_SRQS, p_params->num_srqs);
2145
2146         /* The only case RDMA personality can be overridden is if NVRAM is
2147          * configured with ETH_RDMA or if no rdma protocol was requested
2148          */
2149         switch (p_params->rdma_protocol) {
2150         case ECORE_RDMA_PROTOCOL_DEFAULT:
2151                 if (p_hwfn->mcp_info->func_info.protocol ==
2152                     ECORE_PCI_ETH_RDMA) {
2153                         DP_NOTICE(p_hwfn, false,
2154                                   "Current day drivers don't support RoCE & iWARP. Default to RoCE-only\n");
2155                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2156                 }
2157                 break;
2158         case ECORE_RDMA_PROTOCOL_NONE:
2159                 p_hwfn->hw_info.personality = ECORE_PCI_ETH;
2160                 return; /* intentional... nothing left to do... */
2161         case ECORE_RDMA_PROTOCOL_ROCE:
2162                 if (p_hwfn->mcp_info->func_info.protocol == ECORE_PCI_ETH_RDMA)
2163                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_ROCE;
2164                 break;
2165         case ECORE_RDMA_PROTOCOL_IWARP:
2166                 if (p_hwfn->mcp_info->func_info.protocol == ECORE_PCI_ETH_RDMA)
2167                         p_hwfn->hw_info.personality = ECORE_PCI_ETH_IWARP;
2168                 break;
2169         }
2170
2171         switch (p_hwfn->hw_info.personality) {
2172         case ECORE_PCI_ETH_IWARP:
2173                 num_qps = OSAL_MIN_T(u32, IWARP_MAX_QPS, p_params->num_qps);
2174                 num_cons = num_qps;
2175                 proto = PROTOCOLID_IWARP;
2176                 p_params->roce_edpm_mode = false;
2177                 break;
2178         case ECORE_PCI_ETH_ROCE:
2179                 num_qps = OSAL_MIN_T(u32, ROCE_MAX_QPS, p_params->num_qps);
2180                 num_cons = num_qps * 2; /* each QP requires two connections */
2181                 proto = PROTOCOLID_ROCE;
2182                 break;
2183         default:
2184                 return;
2185         }
2186
2187         if (num_cons && num_tasks) {
2188                 ecore_cxt_set_proto_cid_count(p_hwfn, proto,
2189                                               num_cons, 0);
2190
2191                 /* Deliberatly passing ROCE for tasks id. This is because
2192                  * iWARP / RoCE share the task id.
2193                  */
2194                 ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ROCE,
2195                                               ECORE_CXT_ROCE_TID_SEG,
2196                                               1, /* RoCE segment type */
2197                                               num_tasks,
2198                                               false); /* !force load */
2199                 ecore_cxt_set_srq_count(p_hwfn, num_srqs);
2200
2201         } else {
2202                 DP_INFO(p_hwfn->p_dev,
2203                         "RDMA personality used without setting params!\n");
2204         }
2205 }
2206
2207 enum _ecore_status_t ecore_cxt_set_pf_params(struct ecore_hwfn *p_hwfn,
2208                                              u32 rdma_tasks)
2209 {
2210         /* Set the number of required CORE connections */
2211         u32 core_cids = 1; /* SPQ */
2212
2213         if (p_hwfn->using_ll2)
2214                 core_cids += 4; /* @@@TBD Use the proper #define */
2215
2216         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_CORE, core_cids, 0);
2217
2218         switch (p_hwfn->hw_info.personality) {
2219         case ECORE_PCI_ETH_RDMA:
2220         case ECORE_PCI_ETH_IWARP:
2221         case ECORE_PCI_ETH_ROCE:
2222         {
2223                 ecore_rdma_set_pf_params(p_hwfn,
2224                                          &p_hwfn->pf_params.rdma_pf_params,
2225                                          rdma_tasks);
2226
2227                 /* no need for break since RoCE coexist with Ethernet */
2228         }
2229         case ECORE_PCI_ETH:
2230         {
2231                 struct ecore_eth_pf_params *p_params =
2232                                         &p_hwfn->pf_params.eth_pf_params;
2233
2234                 if (!p_params->num_vf_cons)
2235                         p_params->num_vf_cons = ETH_PF_PARAMS_VF_CONS_DEFAULT;
2236                 ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ETH,
2237                                               p_params->num_cons,
2238                                               p_params->num_vf_cons);
2239                 p_hwfn->p_cxt_mngr->arfs_count = p_params->num_arfs_filters;
2240
2241                 break;
2242         }
2243         case ECORE_PCI_FCOE:
2244         {
2245                 struct ecore_fcoe_pf_params *p_params;
2246
2247                 p_params = &p_hwfn->pf_params.fcoe_pf_params;
2248
2249                 if (p_params->num_cons && p_params->num_tasks) {
2250                         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_FCOE,
2251                                                       p_params->num_cons, 0);
2252
2253                         ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_FCOE,
2254                                                       ECORE_CXT_FCOE_TID_SEG,
2255                                                       0, /* segment type */
2256                                                       p_params->num_tasks,
2257                                                       true);
2258                 } else {
2259                         DP_INFO(p_hwfn->p_dev,
2260                                 "Fcoe personality used without setting params!\n");
2261                 }
2262                 break;
2263         }
2264         case ECORE_PCI_ISCSI:
2265         {
2266                 struct ecore_iscsi_pf_params *p_params;
2267
2268                 p_params = &p_hwfn->pf_params.iscsi_pf_params;
2269
2270                 if (p_params->num_cons && p_params->num_tasks) {
2271                         ecore_cxt_set_proto_cid_count(p_hwfn, PROTOCOLID_ISCSI,
2272                                                       p_params->num_cons, 0);
2273
2274                         ecore_cxt_set_proto_tid_count(p_hwfn, PROTOCOLID_ISCSI,
2275                                                       ECORE_CXT_ISCSI_TID_SEG,
2276                                                       0, /* segment type */
2277                                                       p_params->num_tasks,
2278                                                       true);
2279                 } else {
2280                         DP_INFO(p_hwfn->p_dev,
2281                                 "Iscsi personality used without setting params!\n");
2282                 }
2283                 break;
2284         }
2285         default:
2286                 return ECORE_INVAL;
2287         }
2288
2289         return ECORE_SUCCESS;
2290 }
2291
2292 enum _ecore_status_t ecore_cxt_get_tid_mem_info(struct ecore_hwfn *p_hwfn,
2293                                                 struct ecore_tid_mem *p_info)
2294 {
2295         struct ecore_cxt_mngr *p_mngr = p_hwfn->p_cxt_mngr;
2296         u32 proto, seg, total_lines, i, shadow_line;
2297         struct ecore_ilt_client_cfg *p_cli;
2298         struct ecore_ilt_cli_blk *p_fl_seg;
2299         struct ecore_tid_seg *p_seg_info;
2300
2301         /* Verify the personality */
2302         switch (p_hwfn->hw_info.personality) {
2303         case ECORE_PCI_FCOE:
2304                 proto = PROTOCOLID_FCOE;
2305                 seg = ECORE_CXT_FCOE_TID_SEG;
2306                 break;
2307         case ECORE_PCI_ISCSI:
2308                 proto = PROTOCOLID_ISCSI;
2309                 seg = ECORE_CXT_ISCSI_TID_SEG;
2310                 break;
2311         default:
2312                 return ECORE_INVAL;
2313         }
2314
2315         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2316         if (!p_cli->active) {
2317                 return ECORE_INVAL;
2318         }
2319
2320         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2321         if (!p_seg_info->has_fl_mem)
2322                 return ECORE_INVAL;
2323
2324         p_fl_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2325         total_lines = DIV_ROUND_UP(p_fl_seg->total_size,
2326                                    p_fl_seg->real_size_in_page);
2327
2328         for (i = 0; i < total_lines; i++) {
2329                 shadow_line = i + p_fl_seg->start_line -
2330                               p_hwfn->p_cxt_mngr->pf_start_line;
2331                 p_info->blocks[i] = p_mngr->ilt_shadow[shadow_line].p_virt;
2332         }
2333         p_info->waste = ILT_PAGE_IN_BYTES(p_cli->p_size.val) -
2334                         p_fl_seg->real_size_in_page;
2335         p_info->tid_size = p_mngr->task_type_size[p_seg_info->type];
2336         p_info->num_tids_per_block = p_fl_seg->real_size_in_page /
2337                                      p_info->tid_size;
2338
2339         return ECORE_SUCCESS;
2340 }
2341
2342 /* This function is very RoCE oriented, if another protocol in the future
2343  * will want this feature we'll need to modify the function to be more generic
2344  */
2345 enum _ecore_status_t
2346 ecore_cxt_dynamic_ilt_alloc(struct ecore_hwfn *p_hwfn,
2347                             enum ecore_cxt_elem_type elem_type,
2348                             u32 iid)
2349 {
2350         u32 reg_offset, shadow_line, elem_size, hw_p_size, elems_per_p, line;
2351         struct ecore_ilt_client_cfg *p_cli;
2352         struct ecore_ilt_cli_blk *p_blk;
2353         struct ecore_ptt *p_ptt;
2354         dma_addr_t p_phys;
2355         u64 ilt_hw_entry;
2356         void *p_virt;
2357         enum _ecore_status_t rc = ECORE_SUCCESS;
2358
2359         switch (elem_type) {
2360         case ECORE_ELEM_CXT:
2361                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2362                 elem_size = CONN_CXT_SIZE(p_hwfn);
2363                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2364                 break;
2365         case ECORE_ELEM_SRQ:
2366                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2367                 elem_size = SRQ_CXT_SIZE;
2368                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2369                 break;
2370         case ECORE_ELEM_TASK:
2371                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2372                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2373                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2374                 break;
2375         default:
2376                 DP_NOTICE(p_hwfn, false,
2377                           "ECORE_INVALID elem type = %d", elem_type);
2378                 return ECORE_INVAL;
2379         }
2380
2381         /* Calculate line in ilt */
2382         hw_p_size = p_cli->p_size.val;
2383         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2384         line = p_blk->start_line + (iid / elems_per_p);
2385         shadow_line = line - p_hwfn->p_cxt_mngr->pf_start_line;
2386
2387         /* If line is already allocated, do nothing, otherwise allocate it and
2388          * write it to the PSWRQ2 registers.
2389          * This section can be run in parallel from different contexts and thus
2390          * a mutex protection is needed.
2391          */
2392
2393         OSAL_MUTEX_ACQUIRE(&p_hwfn->p_cxt_mngr->mutex);
2394
2395         if (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt)
2396                 goto out0;
2397
2398         p_ptt = ecore_ptt_acquire(p_hwfn);
2399         if (!p_ptt) {
2400                 DP_NOTICE(p_hwfn, false,
2401                           "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2402                 rc = ECORE_TIMEOUT;
2403                 goto out0;
2404         }
2405
2406         p_virt = OSAL_DMA_ALLOC_COHERENT(p_hwfn->p_dev,
2407                                          &p_phys,
2408                                          p_blk->real_size_in_page);
2409         if (!p_virt) {
2410                 rc = ECORE_NOMEM;
2411                 goto out1;
2412         }
2413         OSAL_MEM_ZERO(p_virt, p_blk->real_size_in_page);
2414
2415         /* configuration of refTagMask to 0xF is required for RoCE DIF MR only,
2416          * to compensate for a HW bug, but it is configured even if DIF is not
2417          * enabled. This is harmless and allows us to avoid a dedicated API. We
2418          * configure the field for all of the contexts on the newly allocated
2419          * page.
2420          */
2421         if (elem_type == ECORE_ELEM_TASK) {
2422                 u32 elem_i;
2423                 u8 *elem_start = (u8 *)p_virt;
2424                 union type1_task_context *elem;
2425
2426                 for (elem_i = 0; elem_i < elems_per_p; elem_i++) {
2427                         elem = (union type1_task_context *)elem_start;
2428                         SET_FIELD(elem->roce_ctx.tdif_context.flags1,
2429                                   TDIF_TASK_CONTEXT_REFTAGMASK , 0xf);
2430                         elem_start += TYPE1_TASK_CXT_SIZE(p_hwfn);
2431                 }
2432         }
2433
2434         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_virt = p_virt;
2435         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys = p_phys;
2436         p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].size =
2437                 p_blk->real_size_in_page;
2438
2439         /* compute absolute offset */
2440         reg_offset = PSWRQ2_REG_ILT_MEMORY +
2441                      (line * ILT_REG_SIZE_IN_BYTES * ILT_ENTRY_IN_REGS);
2442
2443         ilt_hw_entry = 0;
2444         SET_FIELD(ilt_hw_entry, ILT_ENTRY_VALID, 1ULL);
2445         SET_FIELD(ilt_hw_entry,
2446                   ILT_ENTRY_PHY_ADDR,
2447                   (p_hwfn->p_cxt_mngr->ilt_shadow[shadow_line].p_phys >> 12));
2448
2449         /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a wide-bus */
2450         ecore_dmae_host2grc(p_hwfn, p_ptt, (u64)(osal_uintptr_t)&ilt_hw_entry,
2451                             reg_offset, sizeof(ilt_hw_entry) / sizeof(u32),
2452                             0 /* no flags */);
2453
2454         if (elem_type == ECORE_ELEM_CXT) {
2455                 u32 last_cid_allocated = (1 + (iid / elems_per_p)) *
2456                                          elems_per_p;
2457
2458                 /* Update the relevant register in the parser */
2459                 ecore_wr(p_hwfn, p_ptt, PRS_REG_ROCE_DEST_QP_MAX_PF,
2460                          last_cid_allocated - 1);
2461
2462                 /* RoCE w/a -> we don't write to the prs search reg until first
2463                  * cid is allocated. This is because the prs checks
2464                  * last_cid-1 >=0 making 0 a valid value... this will cause
2465                  * the a context load to occur on a RoCE packet received with
2466                  * cid=0 even before context was initialized, can happen with a
2467                  * stray packet from switch or a packet with crc-error
2468                  */
2469
2470                 if (!p_hwfn->b_rdma_enabled_in_prs) {
2471                         /* Enable Rdma search */
2472                         ecore_wr(p_hwfn, p_ptt, p_hwfn->rdma_prs_search_reg, 1);
2473                         p_hwfn->b_rdma_enabled_in_prs = true;
2474                 }
2475         }
2476
2477 out1:
2478         ecore_ptt_release(p_hwfn, p_ptt);
2479 out0:
2480         OSAL_MUTEX_RELEASE(&p_hwfn->p_cxt_mngr->mutex);
2481
2482         return rc;
2483 }
2484
2485 /* This function is very RoCE oriented, if another protocol in the future
2486  * will want this feature we'll need to modify the function to be more generic
2487  */
2488 enum _ecore_status_t
2489 ecore_cxt_free_ilt_range(struct ecore_hwfn *p_hwfn,
2490                          enum ecore_cxt_elem_type elem_type,
2491                          u32 start_iid, u32 count)
2492 {
2493         u32 start_line, end_line, shadow_start_line, shadow_end_line;
2494         u32 reg_offset, elem_size, hw_p_size, elems_per_p;
2495         struct ecore_ilt_client_cfg *p_cli;
2496         struct ecore_ilt_cli_blk *p_blk;
2497         u32 end_iid = start_iid + count;
2498         struct ecore_ptt *p_ptt;
2499         u64 ilt_hw_entry = 0;
2500         u32 i;
2501
2502         switch (elem_type) {
2503         case ECORE_ELEM_CXT:
2504                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUC];
2505                 elem_size = CONN_CXT_SIZE(p_hwfn);
2506                 p_blk = &p_cli->pf_blks[CDUC_BLK];
2507                 break;
2508         case ECORE_ELEM_SRQ:
2509                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_TSDM];
2510                 elem_size = SRQ_CXT_SIZE;
2511                 p_blk = &p_cli->pf_blks[SRQ_BLK];
2512                 break;
2513         case ECORE_ELEM_TASK:
2514                 p_cli = &p_hwfn->p_cxt_mngr->clients[ILT_CLI_CDUT];
2515                 elem_size = TYPE1_TASK_CXT_SIZE(p_hwfn);
2516                 p_blk = &p_cli->pf_blks[CDUT_SEG_BLK(ECORE_CXT_ROCE_TID_SEG)];
2517                 break;
2518         default:
2519                 DP_NOTICE(p_hwfn, false,
2520                           "ECORE_INVALID elem type = %d", elem_type);
2521                 return ECORE_INVAL;
2522         }
2523
2524         /* Calculate line in ilt */
2525         hw_p_size = p_cli->p_size.val;
2526         elems_per_p = ILT_PAGE_IN_BYTES(hw_p_size) / elem_size;
2527         start_line = p_blk->start_line + (start_iid / elems_per_p);
2528         end_line = p_blk->start_line + (end_iid / elems_per_p);
2529         if (((end_iid + 1) / elems_per_p) != (end_iid / elems_per_p))
2530                 end_line--;
2531
2532         shadow_start_line = start_line - p_hwfn->p_cxt_mngr->pf_start_line;
2533         shadow_end_line = end_line - p_hwfn->p_cxt_mngr->pf_start_line;
2534
2535         p_ptt = ecore_ptt_acquire(p_hwfn);
2536         if (!p_ptt) {
2537                 DP_NOTICE(p_hwfn, false, "ECORE_TIME_OUT on ptt acquire - dynamic allocation");
2538                 return ECORE_TIMEOUT;
2539         }
2540
2541         for (i = shadow_start_line; i < shadow_end_line; i++) {
2542                 if (!p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt)
2543                         continue;
2544
2545                 OSAL_DMA_FREE_COHERENT(p_hwfn->p_dev,
2546                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt,
2547                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys,
2548                                        p_hwfn->p_cxt_mngr->ilt_shadow[i].size);
2549
2550                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_virt = OSAL_NULL;
2551                 p_hwfn->p_cxt_mngr->ilt_shadow[i].p_phys = 0;
2552                 p_hwfn->p_cxt_mngr->ilt_shadow[i].size = 0;
2553
2554                 /* compute absolute offset */
2555                 reg_offset = PSWRQ2_REG_ILT_MEMORY +
2556                              ((start_line++) * ILT_REG_SIZE_IN_BYTES *
2557                               ILT_ENTRY_IN_REGS);
2558
2559                 /* Write via DMAE since the PSWRQ2_REG_ILT_MEMORY line is a
2560                  * wide-bus.
2561                  */
2562                 ecore_dmae_host2grc(p_hwfn, p_ptt,
2563                                     (u64)(osal_uintptr_t)&ilt_hw_entry,
2564                                     reg_offset,
2565                                     sizeof(ilt_hw_entry) / sizeof(u32),
2566                                     0 /* no flags */);
2567         }
2568
2569         ecore_ptt_release(p_hwfn, p_ptt);
2570
2571         return ECORE_SUCCESS;
2572 }
2573
2574 enum _ecore_status_t ecore_cxt_get_task_ctx(struct ecore_hwfn *p_hwfn,
2575                                             u32 tid,
2576                                             u8 ctx_type,
2577                                             void **pp_task_ctx)
2578 {
2579         struct ecore_cxt_mngr           *p_mngr = p_hwfn->p_cxt_mngr;
2580         struct ecore_ilt_client_cfg     *p_cli;
2581         struct ecore_ilt_cli_blk        *p_seg;
2582         struct ecore_tid_seg            *p_seg_info;
2583         u32                             proto, seg;
2584         u32                             total_lines;
2585         u32                             tid_size, ilt_idx;
2586         u32                             num_tids_per_block;
2587
2588         /* Verify the personality */
2589         switch (p_hwfn->hw_info.personality) {
2590         case ECORE_PCI_FCOE:
2591                 proto = PROTOCOLID_FCOE;
2592                 seg = ECORE_CXT_FCOE_TID_SEG;
2593                 break;
2594         case ECORE_PCI_ISCSI:
2595                 proto = PROTOCOLID_ISCSI;
2596                 seg = ECORE_CXT_ISCSI_TID_SEG;
2597                 break;
2598         default:
2599                 return ECORE_INVAL;
2600         }
2601
2602         p_cli = &p_mngr->clients[ILT_CLI_CDUT];
2603         if (!p_cli->active) {
2604                 return ECORE_INVAL;
2605         }
2606
2607         p_seg_info = &p_mngr->conn_cfg[proto].tid_seg[seg];
2608
2609         if (ctx_type == ECORE_CTX_WORKING_MEM) {
2610                 p_seg = &p_cli->pf_blks[CDUT_SEG_BLK(seg)];
2611         } else if (ctx_type == ECORE_CTX_FL_MEM) {
2612                 if (!p_seg_info->has_fl_mem) {
2613                         return ECORE_INVAL;
2614                 }
2615                 p_seg = &p_cli->pf_blks[CDUT_FL_SEG_BLK(seg, PF)];
2616         } else {
2617                 return ECORE_INVAL;
2618         }
2619         total_lines = DIV_ROUND_UP(p_seg->total_size,
2620                                    p_seg->real_size_in_page);
2621         tid_size = p_mngr->task_type_size[p_seg_info->type];
2622         num_tids_per_block = p_seg->real_size_in_page / tid_size;
2623
2624         if (total_lines < tid/num_tids_per_block)
2625                 return ECORE_INVAL;
2626
2627         ilt_idx = tid / num_tids_per_block + p_seg->start_line -
2628                   p_mngr->pf_start_line;
2629         *pp_task_ctx = (u8 *)p_mngr->ilt_shadow[ilt_idx].p_virt +
2630                              (tid % num_tids_per_block) * tid_size;
2631
2632         return ECORE_SUCCESS;
2633 }