2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __ECORE_HSI_INIT_TOOL__
33 #define __ECORE_HSI_INIT_TOOL__
34 /**************************************/
35 /* Init Tool HSI constants and macros */
36 /**************************************/
38 /* Width of GRC address in bits (addresses are specified in dwords) */
39 #define GRC_ADDR_BITS 23
40 #define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1)
42 /* indicates an init that should be applied to any phase ID */
43 #define ANY_PHASE_ID 0xffff
45 /* Max size in dwords of a zipped array */
46 #define MAX_ZIPPED_SIZE 8192
58 struct fw_asserts_ram_section
60 __le16 section_ram_line_offset /* The offset of the section in the RAM in RAM lines (64-bit units) */;
61 __le16 section_ram_line_size /* The size of the section in RAM lines (64-bit units) */;
62 u8 list_dword_offset /* The offset of the asserts list within the section in dwords */;
63 u8 list_element_dword_size /* The size of an assert list element in dwords */;
64 u8 list_num_elements /* The number of elements in the asserts list */;
65 u8 list_next_index_dword_offset /* The offset of the next list index field within the section in dwords */;
71 u8 major /* Firmware major version number */;
72 u8 minor /* Firmware minor version number */;
73 u8 rev /* Firmware revision version number */;
74 u8 eng /* Firmware engineering version number (for bootleg versions) */;
79 __le16 tools_ver /* Tools version number */;
80 u8 image_id /* FW image ID (e.g. main, l2b, kuku) */;
82 struct fw_ver_num num /* FW version number */;
83 __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */;
89 struct fw_ver_info ver /* FW version information */;
90 struct fw_asserts_ram_section fw_asserts_section /* Info regarding the FW asserts section in the Storm RAM */;
94 struct fw_info_location
96 __le32 grc_addr /* GRC address where the fw_info struct is located. */;
97 __le32 size /* Size of the fw_info structure (thats located at the grc_addr). */;
105 MODE_BB_A0_DEPRECATED,
116 MODE_PORTS_PER_ENG_1,
117 MODE_PORTS_PER_ENG_2,
118 MODE_PORTS_PER_ENG_4,
136 enum init_split_types
148 * Binary buffer header
150 struct bin_buffer_hdr
152 __le32 offset /* buffer offset in bytes from the beginning of the binary file */;
153 __le32 length /* buffer length in bytes */;
158 * binary init buffer types
160 enum bin_init_buffer_type
162 BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */,
163 BIN_BUF_INIT_CMD /* init commands */,
164 BIN_BUF_INIT_VAL /* init data */,
165 BIN_BUF_INIT_MODE_TREE /* init modes tree */,
166 BIN_BUF_INIT_IRO /* internal RAM offsets */,
167 MAX_BIN_INIT_BUFFER_TYPE
172 * init array header: raw
174 struct init_array_raw_hdr
177 #define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */
178 #define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0
179 #define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */
180 #define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4
184 * init array header: standard
186 struct init_array_standard_hdr
189 #define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */
190 #define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0
191 #define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */
192 #define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4
196 * init array header: zipped
198 struct init_array_zipped_hdr
201 #define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */
202 #define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0
203 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */
204 #define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4
208 * init array header: pattern
210 struct init_array_pattern_hdr
213 #define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */
214 #define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0
215 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */
216 #define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4
217 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */
218 #define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8
222 * init array header union
226 struct init_array_raw_hdr raw /* raw init array header */;
227 struct init_array_standard_hdr standard /* standard init array header */;
228 struct init_array_zipped_hdr zipped /* zipped init array header */;
229 struct init_array_pattern_hdr pattern /* pattern init array header */;
239 enum init_array_types
241 INIT_ARR_STANDARD /* standard init array */,
242 INIT_ARR_ZIPPED /* zipped init array */,
243 INIT_ARR_PATTERN /* a repeated pattern */,
250 * init operation: callback
252 struct init_callback_op
255 #define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
256 #define INIT_CALLBACK_OP_OP_SHIFT 0
257 #define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF
258 #define INIT_CALLBACK_OP_RESERVED_SHIFT 4
259 __le16 callback_id /* Callback ID */;
260 __le16 block_id /* Blocks ID */;
265 * init operation: delay
270 #define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
271 #define INIT_DELAY_OP_OP_SHIFT 0
272 #define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF
273 #define INIT_DELAY_OP_RESERVED_SHIFT 4
274 __le32 delay /* delay in us */;
279 * init operation: if_mode
281 struct init_if_mode_op
284 #define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
285 #define INIT_IF_MODE_OP_OP_SHIFT 0
286 #define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF
287 #define INIT_IF_MODE_OP_RESERVED1_SHIFT 4
288 #define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */
289 #define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16
291 __le16 modes_buf_offset /* offset (in bytes) in modes expression buffer */;
296 * init operation: if_phase
298 struct init_if_phase_op
301 #define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
302 #define INIT_IF_PHASE_OP_OP_SHIFT 0
303 #define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */
304 #define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4
305 #define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF
306 #define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5
307 #define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */
308 #define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16
310 #define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */
311 #define INIT_IF_PHASE_OP_PHASE_SHIFT 0
312 #define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF
313 #define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8
314 #define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */
315 #define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16
320 * init mode operators
324 INIT_MODE_OP_NOT /* init mode not operator */,
325 INIT_MODE_OP_OR /* init mode or operator */,
326 INIT_MODE_OP_AND /* init mode and operator */,
332 * init operation: raw
337 #define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */
338 #define INIT_RAW_OP_OP_SHIFT 0
339 #define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */
340 #define INIT_RAW_OP_PARAM1_SHIFT 4
341 __le32 param2 /* Init param 2 */;
347 struct init_op_array_params
349 __le16 size /* array size in dwords */;
350 __le16 offset /* array start offset in dwords */;
354 * Write init operation arguments
356 union init_write_args
358 __le32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */;
359 __le32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */;
360 __le32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */;
361 struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */;
365 * init operation: write
370 #define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */
371 #define INIT_WRITE_OP_OP_SHIFT 0
372 #define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */
373 #define INIT_WRITE_OP_SOURCE_SHIFT 4
374 #define INIT_WRITE_OP_RESERVED_MASK 0x1
375 #define INIT_WRITE_OP_RESERVED_SHIFT 7
376 #define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */
377 #define INIT_WRITE_OP_WIDE_BUS_SHIFT 8
378 #define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */
379 #define INIT_WRITE_OP_ADDRESS_SHIFT 9
380 union init_write_args args /* Write init operation arguments */;
384 * init operation: read
389 #define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */
390 #define INIT_READ_OP_OP_SHIFT 0
391 #define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */
392 #define INIT_READ_OP_POLL_TYPE_SHIFT 4
393 #define INIT_READ_OP_RESERVED_MASK 0x1
394 #define INIT_READ_OP_RESERVED_SHIFT 8
395 #define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */
396 #define INIT_READ_OP_ADDRESS_SHIFT 9
397 __le32 expected_val /* expected polling value, used only when polling is done */;
401 * Init operations union
405 struct init_raw_op raw /* raw init operation */;
406 struct init_write_op write /* write init operation */;
407 struct init_read_op read /* read init operation */;
408 struct init_if_mode_op if_mode /* if_mode init operation */;
409 struct init_if_phase_op if_phase /* if_phase init operation */;
410 struct init_callback_op callback /* callback init operation */;
411 struct init_delay_op delay /* delay init operation */;
417 * Init command operation types
421 INIT_OP_READ /* GRC read init command */,
422 INIT_OP_WRITE /* GRC write init command */,
423 INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */,
424 INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */,
425 INIT_OP_DELAY /* delay init command */,
426 INIT_OP_CALLBACK /* callback init command */,
436 INIT_POLL_NONE /* No polling */,
437 INIT_POLL_EQ /* init value is included in the init command */,
438 INIT_POLL_OR /* init value is all zeros */,
439 INIT_POLL_AND /* init value is an array of values */,
449 enum init_source_types
451 INIT_SRC_INLINE /* init value is included in the init command */,
452 INIT_SRC_ZEROS /* init value is all zeros */,
453 INIT_SRC_ARRAY /* init value is an array of values */,
454 INIT_SRC_RUNTIME /* init value is provided during runtime */,
455 MAX_INIT_SOURCE_TYPES
462 * Internal RAM Offsets macro data
466 __le32 base /* RAM field offset */;
467 __le16 m1 /* multiplier 1 */;
468 __le16 m2 /* multiplier 2 */;
469 __le16 m3 /* multiplier 3 */;
470 __le16 size /* RAM field size */;
473 #endif /* __ECORE_HSI_INIT_TOOL__ */