sys/dev/qlnx/qlnxe/ecore_int_api.h

   1 /*
   2  * Copyright (c) 2017-2018 Cavium, Inc.
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  *
  29  */
  30
  31
  32 #ifndef __ECORE_INT_API_H__
  33 #define __ECORE_INT_API_H__
  34
  35 #define ECORE_SB_IDX            0x0002
  36
  37 #define RX_PI           0
  38 #define TX_PI(tc)       (RX_PI + 1 + tc)
  39
  40 #ifndef ECORE_INT_MODE
  41 #define ECORE_INT_MODE
  42 enum ecore_int_mode {
  43         ECORE_INT_MODE_INTA,
  44         ECORE_INT_MODE_MSIX,
  45         ECORE_INT_MODE_MSI,
  46         ECORE_INT_MODE_POLL,
  47 };
  48 #endif
  49
  50 struct ecore_sb_info {
  51         struct status_block *sb_virt;
  52         dma_addr_t sb_phys;
  53         u32 sb_ack; /* Last given ack */
  54         u16 igu_sb_id;
  55         void OSAL_IOMEM *igu_addr;
  56         u8 flags;
  57 #define ECORE_SB_INFO_INIT      0x1
  58 #define ECORE_SB_INFO_SETUP     0x2
  59
  60 #ifdef ECORE_CONFIG_DIRECT_HWFN
  61         struct ecore_hwfn *p_hwfn;
  62 #endif
  63         struct ecore_dev *p_dev;
  64 };
  65
  66 struct ecore_sb_info_dbg {
  67         u32 igu_prod;
  68         u32 igu_cons;
  69         u16 pi[PIS_PER_SB];
  70 };
  71
  72 struct ecore_sb_cnt_info {
  73         /* Original, current, and free SBs for PF */
  74         int orig;
  75         int cnt;
  76         int free_cnt;
  77
  78         /* Original, current and free SBS for child VFs */
  79         int iov_orig;
  80         int iov_cnt;
  81         int free_cnt_iov;
  82 };
  83
  84 static OSAL_INLINE u16 ecore_sb_update_sb_idx(struct ecore_sb_info *sb_info)
  85 {
  86         u32 prod = 0;
  87         u16 rc   = 0;
  88
  89         // barrier(); /* status block is written to by the chip */
  90         // FIXME: need some sort of barrier.
  91         prod = OSAL_LE32_TO_CPU(sb_info->sb_virt->prod_index) &
  92                STATUS_BLOCK_PROD_INDEX_MASK;
  93         if (sb_info->sb_ack != prod) {
  94                 sb_info->sb_ack = prod;
  95                 rc |= ECORE_SB_IDX;
  96         }
  97
  98         OSAL_MMIOWB(sb_info->p_dev);
  99         return rc;
 100 }
 101
 102 /**
 103  * @brief This function creates an update command for interrupts that is
 104  *        written to the IGU.
 105  *
 106  * @param sb_info       - This is the structure allocated and
 107  *                 initialized per status block. Assumption is
 108  *                 that it was initialized using ecore_sb_init
 109  * @param int_cmd       - Enable/Disable/Nop
 110  * @param upd_flg       - whether igu consumer should be
 111  *                 updated.
 112  *
 113  * @return OSAL_INLINE void
 114  */
 115 static OSAL_INLINE void ecore_sb_ack(struct ecore_sb_info *sb_info,
 116                                      enum igu_int_cmd int_cmd, u8 upd_flg)
 117 {
 118         struct igu_prod_cons_update igu_ack = { 0 };
 119
 120         igu_ack.sb_id_and_flags =
 121                 ((sb_info->sb_ack << IGU_PROD_CONS_UPDATE_SB_INDEX_SHIFT) |
 122                  (upd_flg << IGU_PROD_CONS_UPDATE_UPDATE_FLAG_SHIFT) |
 123                  (int_cmd << IGU_PROD_CONS_UPDATE_ENABLE_INT_SHIFT) |
 124                  (IGU_SEG_ACCESS_REG <<
 125                   IGU_PROD_CONS_UPDATE_SEGMENT_ACCESS_SHIFT));
 126
 127 #ifdef ECORE_CONFIG_DIRECT_HWFN
 128         DIRECT_REG_WR(sb_info->p_hwfn, sb_info->igu_addr,
 129                       igu_ack.sb_id_and_flags);
 130 #else
 131         DIRECT_REG_WR(OSAL_NULL, sb_info->igu_addr, igu_ack.sb_id_and_flags);
 132 #endif
 133         /* Both segments (interrupts & acks) are written to same place address;
 134          * Need to guarantee all commands will be received (in-order) by HW.
 135          */
 136         OSAL_MMIOWB(sb_info->p_dev);
 137         OSAL_BARRIER(sb_info->p_dev);
 138 }
 139
 140 #ifdef ECORE_CONFIG_DIRECT_HWFN
 141 static OSAL_INLINE void __internal_ram_wr(struct ecore_hwfn *p_hwfn,
 142                                           void OSAL_IOMEM *addr,
 143                                           int size, u32 *data)
 144 #else
 145 static OSAL_INLINE void __internal_ram_wr(void *p_hwfn,
 146                                           void OSAL_IOMEM *addr,
 147                                           int size, u32 *data)
 148
 149 #endif
 150 {
 151         unsigned int i;
 152
 153         for (i = 0; i < size / sizeof(*data); i++)
 154                 DIRECT_REG_WR(p_hwfn, &((u32 OSAL_IOMEM *)addr)[i], data[i]);
 155 }
 156
 157 #ifdef ECORE_CONFIG_DIRECT_HWFN
 158 static OSAL_INLINE void internal_ram_wr(struct ecore_hwfn *p_hwfn,
 159                                         void OSAL_IOMEM *addr,
 160                                         int size, u32 *data)
 161 {
 162         __internal_ram_wr(p_hwfn, addr, size, data);
 163 }
 164 #else
 165 static OSAL_INLINE void internal_ram_wr(void OSAL_IOMEM *addr,
 166                                         int size, u32 *data)
 167 {
 168         __internal_ram_wr(OSAL_NULL, addr, size, data);
 169 }
 170 #endif
 171
 172 struct ecore_hwfn;
 173 struct ecore_ptt;
 174
 175 enum ecore_coalescing_fsm {
 176         ECORE_COAL_RX_STATE_MACHINE,
 177         ECORE_COAL_TX_STATE_MACHINE
 178 };
 179
 180 /**
 181  * @brief ecore_int_cau_conf_pi - configure cau for a given
 182  *        status block
 183  *
 184  * @param p_hwfn
 185  * @param p_ptt
 186  * @param p_sb
 187  * @param pi_index
 188  * @param state
 189  * @param timeset
 190  */
 191 void ecore_int_cau_conf_pi(struct ecore_hwfn            *p_hwfn,
 192                            struct ecore_ptt             *p_ptt,
 193                            struct ecore_sb_info         *p_sb,
 194                            u32                          pi_index,
 195                            enum ecore_coalescing_fsm    coalescing_fsm,
 196                            u8                           timeset);
 197
 198 /**
 199  * @brief ecore_int_igu_enable_int - enable device interrupts
 200  *
 201  * @param p_hwfn
 202  * @param p_ptt
 203  * @param int_mode - interrupt mode to use
 204  */
 205 void ecore_int_igu_enable_int(struct ecore_hwfn *p_hwfn,
 206                               struct ecore_ptt *p_ptt,
 207                               enum ecore_int_mode int_mode);
 208
 209 /**
 210  * @brief ecore_int_igu_disable_int - disable device interrupts
 211  *
 212  * @param p_hwfn
 213  * @param p_ptt
 214  */
 215 void ecore_int_igu_disable_int(struct ecore_hwfn *p_hwfn,
 216                                struct ecore_ptt *p_ptt);
 217
 218 /**
 219  * @brief ecore_int_igu_read_sisr_reg - Reads the single isr multiple dpc
 220  *        register from igu.
 221  *
 222  * @param p_hwfn
 223  *
 224  * @return u64
 225  */
 226 u64 ecore_int_igu_read_sisr_reg(struct ecore_hwfn *p_hwfn);
 227
 228 #define ECORE_SP_SB_ID 0xffff
 229
 230 /**
 231  * @brief ecore_int_sb_init - Initializes the sb_info structure.
 232  *
 233  * once the structure is initialized it can be passed to sb related functions.
 234  *
 235  * @param p_hwfn
 236  * @param p_ptt
 237  * @param sb_info       points to an uninitialized (but
 238  *                      allocated) sb_info structure
 239  * @param sb_virt_addr
 240  * @param sb_phy_addr
 241  * @param sb_id         the sb_id to be used (zero based in driver)
 242  *                      should use ECORE_SP_SB_ID for SP Status block
 243  *
 244  * @return enum _ecore_status_t
 245  */
 246 enum _ecore_status_t ecore_int_sb_init(struct ecore_hwfn        *p_hwfn,
 247                                        struct ecore_ptt         *p_ptt,
 248                                        struct ecore_sb_info     *sb_info,
 249                                        void                     *sb_virt_addr,
 250                                        dma_addr_t               sb_phy_addr,
 251                                        u16                      sb_id);
 252 /**
 253  * @brief ecore_int_sb_setup - Setup the sb.
 254  *
 255  * @param p_hwfn
 256  * @param p_ptt
 257  * @param sb_info       initialized sb_info structure
 258  */
 259 void ecore_int_sb_setup(
 260                 struct ecore_hwfn       *p_hwfn,
 261                 struct ecore_ptt                *p_ptt,
 262                 struct ecore_sb_info    *sb_info);
 263
 264 /**
 265  * @brief ecore_int_sb_release - releases the sb_info structure.
 266  *
 267  * once the structure is released, it's memory can be freed
 268  *
 269  * @param p_hwfn
 270  * @param sb_info       points to an allocated sb_info structure
 271  * @param sb_id         the sb_id to be used (zero based in driver)
 272  *                      should never be equal to ECORE_SP_SB_ID
 273  *                      (SP Status block)
 274  *
 275  * @return enum _ecore_status_t
 276  */
 277 enum _ecore_status_t ecore_int_sb_release(struct ecore_hwfn     *p_hwfn,
 278                                           struct ecore_sb_info  *sb_info,
 279                                           u16                   sb_id);
 280
 281 /**
 282  * @brief ecore_int_sp_dpc - To be called when an interrupt is received on the
 283  *        default status block.
 284  *
 285  * @param p_hwfn - pointer to hwfn
 286  *
 287  */
 288 void ecore_int_sp_dpc(osal_int_ptr_t hwfn_cookie);
 289
 290 /**
 291  * @brief ecore_int_get_num_sbs - get the number of status
 292  *        blocks configured for this funciton in the igu.
 293  *
 294  * @param p_hwfn
 295  * @param p_sb_cnt_info
 296  *
 297  * @return
 298  */
 299 void ecore_int_get_num_sbs(struct ecore_hwfn        *p_hwfn,
 300                            struct ecore_sb_cnt_info *p_sb_cnt_info);
 301
 302 /**
 303  * @brief ecore_int_disable_post_isr_release - performs the cleanup post ISR
 304  *        release. The API need to be called after releasing all slowpath IRQs
 305  *        of the device.
 306  *
 307  * @param p_dev
 308  *
 309  */
 310 void ecore_int_disable_post_isr_release(struct ecore_dev *p_dev);
 311
 312 /**
 313  * @brief ecore_int_attn_clr_enable - sets whether the general behavior is
 314  *        preventing attentions from being reasserted, or following the
 315  *        attributes of the specific attention.
 316  *
 317  * @param p_dev
 318  * @param clr_enable
 319  *
 320  */
 321 void ecore_int_attn_clr_enable(struct ecore_dev *p_dev, bool clr_enable);
 322
 323 /**
 324  * @brief Read debug information regarding a given SB.
 325  *
 326  * @param p_hwfn
 327  * @param p_ptt
 328  * @param p_sb - point to Status block for which we want to get info.
 329  * @param p_info - pointer to struct to fill with information regarding SB.
 330  *
 331  * @return ECORE_SUCCESS if pointer is filled; failure otherwise.
 332  */
 333 enum _ecore_status_t ecore_int_get_sb_dbg(struct ecore_hwfn *p_hwfn,
 334                                           struct ecore_ptt *p_ptt,
 335                                           struct ecore_sb_info *p_sb,
 336                                           struct ecore_sb_info_dbg *p_info);
 337
 338 /**
 339  * @brief - Move a free Status block between PF and child VF
 340  *
 341  * @param p_hwfn
 342  * @param p_ptt
 343  * @param sb_id - The PF fastpath vector to be moved [re-assigned if claiming
 344  *                from VF, given-up if moving to VF]
 345  * @param b_to_vf - PF->VF == true, VF->PF == false
 346  *
 347  * @return ECORE_SUCCESS if SB successfully moved.
 348  */
 349 enum _ecore_status_t
 350 ecore_int_igu_relocate_sb(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt,
 351                           u16 sb_id, bool b_to_vf);
 352 #endif