2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
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13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __ECORE_RDMA_H__
33 #define __ECORE_RDMA_H__
35 #include "ecore_status.h"
37 #include "ecore_hsi_common.h"
38 #include "ecore_proto_if.h"
39 #include "ecore_roce_api.h"
40 #include "ecore_dev_api.h"
44 /* HW/FW RoCE Limitations (internal. For external see ecore_rdma_api.h) */
45 #define ECORE_RDMA_MAX_FMR (RDMA_MAX_TIDS) /* 2^17 - 1 */
46 #define ECORE_RDMA_MAX_P_KEY (1)
47 #define ECORE_RDMA_MAX_WQE (0x7FFF) /* 2^15 -1 */
48 #define ECORE_RDMA_MAX_SRQ_WQE_ELEM (0x7FFF) /* 2^15 -1 */
49 #define ECORE_RDMA_PAGE_SIZE_CAPS (0xFFFFF000) /* TODO: > 4k?! */
50 #define ECORE_RDMA_ACK_DELAY (15) /* 131 milliseconds */
51 #define ECORE_RDMA_MAX_MR_SIZE (0x10000000000ULL) /* 2^40 */
52 #define ECORE_RDMA_MAX_CQS (RDMA_MAX_CQS) /* 64k */
53 #define ECORE_RDMA_MAX_MRS (RDMA_MAX_TIDS) /* 2^17 - 1 */
54 /* Add 1 for header element */
55 #define ECORE_RDMA_MAX_SRQ_ELEM_PER_WQE (RDMA_MAX_SGE_PER_RQ_WQE + 1)
56 #define ECORE_RDMA_MAX_SGE_PER_SRQ_WQE (RDMA_MAX_SGE_PER_RQ_WQE)
57 #define ECORE_RDMA_SRQ_WQE_ELEM_SIZE (16)
58 #define ECORE_RDMA_MAX_SRQS (32 * 1024) /* 32k */
61 /* Max CQE is derived from u16/32 size, halved and decremented by 1 to handle
62 * wrap properly and then decremented by 1 again. The latter decrement comes
63 * from a requirement to create a chain that is bigger than what the user
65 * The CQE size is 32 bytes but the FW writes in chunks of 64
66 * bytes, for performance purposes. Allocating an extra entry and telling the
67 * FW we have less prevents overwriting the first entry in case of a wrap i.e.
68 * when the FW writes the last entry and the application hasn't read the first
71 #define ECORE_RDMA_MAX_CQE_32_BIT (0x7FFFFFFF - 1)
72 #define ECORE_RDMA_MAX_CQE_16_BIT (0x7FFF - 1)
74 enum ecore_rdma_toggle_bit {
75 ECORE_RDMA_TOGGLE_BIT_CLEAR = 0,
76 ECORE_RDMA_TOGGLE_BIT_SET = 1
79 /* @@@TBD Currently we support only affilited events
80 * enum ecore_rdma_unaffiliated_event_code {
81 * ECORE_RDMA_PORT_ACTIVE, // Link Up
82 * ECORE_RDMA_PORT_CHANGED, // SGID table has changed
83 * ECORE_RDMA_LOCAL_CATASTROPHIC_ERR, // Fatal device error
84 * ECORE_RDMA_PORT_ERR, // Link down
88 #define QEDR_MAX_BMAP_NAME (10)
91 unsigned long *bitmap;
92 char name[QEDR_MAX_BMAP_NAME];
95 /* functions for enabling/disabling edpm in rdma PFs according to existence of
96 * qps during DCBx update or bar size
98 void ecore_roce_dpm_dcbx(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
99 void ecore_rdma_dpm_bar(struct ecore_hwfn *p_hwfn, struct ecore_ptt *p_ptt);
101 #ifdef CONFIG_ECORE_IWARP
103 #define ECORE_IWARP_LL2_SYN_TX_SIZE (128)
104 #define ECORE_IWARP_LL2_SYN_RX_SIZE (256)
106 #define ECORE_IWARP_LL2_OOO_DEF_TX_SIZE (256)
107 #define ECORE_IWARP_LL2_OOO_DEF_RX_SIZE (4096)
109 #define ECORE_IWARP_MAX_SYN_PKT_SIZE (128)
110 #define ECORE_IWARP_HANDLE_INVAL (0xff)
112 struct ecore_iwarp_ll2_buff {
113 struct ecore_iwarp_ll2_buff *piggy_buf;
115 dma_addr_t data_phys_addr;
119 struct ecore_iwarp_ll2_mpa_buf {
120 osal_list_entry_t list_entry;
121 struct ecore_iwarp_ll2_buff *ll2_buf;
122 struct unaligned_opaque_data data;
127 /* In some cases a fpdu will arrive with only one byte of the header, in this
128 * case the fpdu_length will be partial ( contain only higher byte and
129 * incomplete bytes will contain the invalid value */
130 #define ECORE_IWARP_INVALID_INCOMPLETE_BYTES 0xffff
132 struct ecore_iwarp_fpdu {
133 struct ecore_iwarp_ll2_buff *mpa_buf;
140 u16 incomplete_bytes;
143 struct ecore_iwarp_info {
144 osal_list_t listen_list; /* ecore_iwarp_listener */
145 osal_list_t ep_list; /* ecore_iwarp_ep */
146 osal_list_t ep_free_list;/* pre-allocated ep's */
147 osal_list_t mpa_buf_list;/* list of mpa_bufs */
148 osal_list_t mpa_buf_pending_list;
149 osal_spinlock_t iw_lock;
150 osal_spinlock_t qp_lock; /* for teardown races */
151 struct iwarp_rxmit_stats_drv stats;
155 u8 mac_addr[ETH_ALEN];
163 enum mpa_negotiation_mode mpa_rev;
164 enum mpa_rtr_type rtr_type;
165 struct ecore_iwarp_fpdu *partial_fpdus;
166 struct ecore_iwarp_ll2_mpa_buf *mpa_bufs;
167 u8 *mpa_intermediate_buf;
168 u16 max_num_partial_fpdus;
175 #define IS_ECORE_DCQCN(p_hwfn) \
176 (!!(p_hwfn->pf_params.rdma_pf_params.enable_dcqcn))
178 struct ecore_roce_info {
179 struct roce_events_stats event_stats;
182 u8 dcqcn_reaction_point;
185 struct ecore_rdma_info {
186 osal_spinlock_t lock;
188 struct ecore_bmap cq_map;
189 struct ecore_bmap pd_map;
190 struct ecore_bmap tid_map;
191 struct ecore_bmap srq_map;
192 struct ecore_bmap cid_map;
193 struct ecore_bmap tcp_cid_map;
194 struct ecore_bmap real_cid_map;
195 struct ecore_bmap dpi_map;
196 struct ecore_bmap toggle_bits;
197 struct ecore_rdma_events events;
198 struct ecore_rdma_device *dev;
199 struct ecore_rdma_port *port;
202 struct rdma_sent_stats rdma_sent_pstats;
203 struct rdma_rcv_stats rdma_rcv_tstats;
209 enum protocol_type proto;
210 struct ecore_roce_info roce;
211 #ifdef CONFIG_ECORE_IWARP
212 struct ecore_iwarp_info iwarp;
216 #ifdef CONFIG_ECORE_IWARP
217 enum ecore_iwarp_qp_state {
218 ECORE_IWARP_QP_STATE_IDLE,
219 ECORE_IWARP_QP_STATE_RTS,
220 ECORE_IWARP_QP_STATE_TERMINATE,
221 ECORE_IWARP_QP_STATE_CLOSING,
222 ECORE_IWARP_QP_STATE_ERROR,
226 struct ecore_rdma_qp {
227 struct regpair qp_handle;
228 struct regpair qp_handle_async;
229 u32 qpid; /* iwarp: may differ from icid */
231 enum ecore_roce_qp_state cur_state;
232 #ifdef CONFIG_ECORE_IWARP
233 enum ecore_iwarp_qp_state iwarp_state;
237 bool fmr_and_reserved_lkey;
239 bool incoming_rdma_read_en;
240 bool incoming_rdma_write_en;
241 bool incoming_atomic_en;
242 bool e2e_flow_control_en;
244 u16 pd; /* Protection domain */
245 u16 pkey; /* Primary P_key index */
249 u8 traffic_class_tos; /* IPv6/GRH traffic class; IPv4 TOS */
250 u8 hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
252 u32 flow_label; /* ignored in IPv4 */
257 u8 min_rnr_nak_timer;
259 union ecore_gid sgid; /* GRH SGID; IPv4/6 Source IP */
260 union ecore_gid dgid; /* GRH DGID; IPv4/6 Destination IP */
261 enum roce_mode roce_mode;
262 u16 udp_src_port; /* RoCEv2 only */
266 u8 max_rd_atomic_req;
268 u16 sq_cq_id; /* The cq to be associated with the send queue*/
270 dma_addr_t sq_pbl_ptr;
272 dma_addr_t orq_phys_addr;
277 u8 max_rd_atomic_resp;
279 u16 rq_cq_id; /* The cq to be associated with the receive queue */
281 dma_addr_t rq_pbl_ptr;
283 dma_addr_t irq_phys_addr;
288 u8 remote_mac_addr[6];
289 u8 local_mac_addr[6];
292 dma_addr_t shared_queue_phys_addr;
293 #ifdef CONFIG_ECORE_IWARP
294 struct ecore_iwarp_ep *ep;
298 #ifdef CONFIG_ECORE_IWARP
300 enum ecore_iwarp_ep_state {
302 ECORE_IWARP_EP_MPA_REQ_RCVD,
303 ECORE_IWARP_EP_ESTABLISHED,
304 ECORE_IWARP_EP_CLOSED
308 struct iwarp_eqe_data_mpa_async_completion mpa_response;
309 struct iwarp_eqe_data_tcp_async_completion mpa_request;
312 /* Endpoint structure represents a TCP connection. This connection can be
313 * associated with a QP or not (in which case QP==NULL)
315 struct ecore_iwarp_ep {
316 osal_list_entry_t list_entry;
318 struct ecore_rdma_qp *qp;
319 enum ecore_iwarp_ep_state state;
321 /* This contains entire buffer required for ep memories. This is the
322 * only one actually allocated and freed. The rest are pointers into
325 void *ep_buffer_virt;
326 dma_addr_t ep_buffer_phys;
328 /* Asynce EQE events contain only the ep pointer on the completion. The
329 * rest of the data is written to an output buffer pre-allocated by
330 * the driver. This buffer points to a location in the ep_buffer.
332 union async_output *async_output_virt;
333 dma_addr_t async_output_phys;
335 struct ecore_iwarp_cm_info cm_info;
336 enum tcp_connect_mode connect_mode;
337 enum mpa_rtr_type rtr_type;
338 enum mpa_negotiation_mode mpa_rev;
341 u8 remote_mac_addr[6];
342 u8 local_mac_addr[6];
344 bool mpa_reply_processed;
346 /* The event_cb function is called for asynchrounous events associated
347 * with the ep. It is initialized at different entry points depending
348 * on whether the ep is the tcp connection active side or passive side
349 * The cb_context is passed to the event_cb function.
351 iwarp_event_handler event_cb;
354 /* For Passive side - syn packet related data */
355 struct ecore_iwarp_ll2_buff *syn;
356 u16 syn_ip_payload_length;
357 dma_addr_t syn_phy_addr;
360 struct ecore_iwarp_listener {
361 osal_list_entry_t list_entry;
363 /* The event_cb function is called for connection requests.
364 * The cb_context is passed to the event_cb function.
366 iwarp_event_handler event_cb;
376 void ecore_iwarp_async_event(struct ecore_hwfn *p_hwfn,
378 struct regpair *fw_handle,
381 #endif /* CONFIG_ECORE_IWARP */
383 void ecore_roce_async_event(struct ecore_hwfn *p_hwfn,
385 union rdma_eqe_data *rdma_data);
387 #endif /*__ECORE_RDMA_H__*/