2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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25 * POSSIBILITY OF SUCH DAMAGE.
31 #ifndef __ECORE_RDMA_API_H__
32 #define __ECORE_RDMA_API_H__
37 enum ecore_roce_ll2_tx_dest
39 ECORE_ROCE_LL2_TX_DEST_NW /* Light L2 TX Destination to the Network */,
40 ECORE_ROCE_LL2_TX_DEST_LB /* Light L2 TX Destination to the Loopback */,
41 ECORE_ROCE_LL2_TX_DEST_MAX
44 /* HW/FW RoCE Limitations (external. For internal see ecore_roce.h) */
45 /* CNQ size Limitation
46 * The CNQ size should be set as twice the amount of CQs, since for each CQ one
47 * element may be inserted into the CNQ and another element is used per CQ to
48 * accommodate for a possible race in the arm mechanism.
49 * The FW supports a CNQ of 64k-1 and this apparently causes an issue - notice
50 * that the number of QPs can reach 32k giving 64k CQs and 128k CNQ elements.
51 * Luckily the FW can buffer CNQ elements avoiding an overflow, on the expense
54 #define ECORE_RDMA_MAX_CNQ_SIZE (0xFFFF) /* 2^16 - 1 */
57 enum ecore_rdma_tid_type
59 ECORE_RDMA_TID_REGISTERED_MR,
61 ECORE_RDMA_TID_MW_TYPE1,
62 ECORE_RDMA_TID_MW_TYPE2A
65 enum ecore_roce_qp_state {
66 ECORE_ROCE_QP_STATE_RESET, /* Reset */
67 ECORE_ROCE_QP_STATE_INIT, /* Initialized */
68 ECORE_ROCE_QP_STATE_RTR, /* Ready to Receive */
69 ECORE_ROCE_QP_STATE_RTS, /* Ready to Send */
70 ECORE_ROCE_QP_STATE_SQD, /* Send Queue Draining */
71 ECORE_ROCE_QP_STATE_ERR, /* Error */
72 ECORE_ROCE_QP_STATE_SQE /* Send Queue Error */
76 void (*affiliated_event_t)(void *context,
81 void (*unaffiliated_event_t)(void *context,
84 struct ecore_rdma_events {
86 affiliated_event_t affiliated_event;
87 unaffiliated_event_t unaffiliated_event;
90 struct ecore_rdma_device {
91 /* Vendor specific information */
97 u64 node_guid; /* node GUID */
98 u64 sys_image_guid; /* System image GUID */
101 u8 max_sge; /* The maximum number of scatter/gather entries
102 * per Work Request supported
104 u8 max_srq_sge; /* The maximum number of scatter/gather entries
105 * per Work Request supported for SRQ
108 u32 max_wqe; /* The maximum number of outstanding work
109 * requests on any Work Queue supported
111 u32 max_srq_wqe; /* The maximum number of outstanding work
112 * requests on any Work Queue supported for SRQ
114 u8 max_qp_resp_rd_atomic_resc; /* The maximum number of RDMA Reads
115 * & atomic operation that can be
119 u8 max_qp_req_rd_atomic_resc; /* The maximum depth per QP for
120 * initiation of RDMA Read
121 * & atomic operations
123 u64 max_dev_resp_rd_atomic_resc;
126 u32 max_srq; /* Maximum number of SRQs */
127 u32 max_mr; /* Maximum number of MRs supported by this device */
128 u64 max_mr_size; /* Size (in bytes) of the largest contiguous memory
129 * block that can be registered by this device
132 u32 max_mw; /* The maximum number of memory windows supported */
134 u32 max_mr_mw_fmr_pbl;
135 u64 max_mr_mw_fmr_size;
136 u32 max_pd; /* The maximum number of protection domains supported */
139 u16 max_srq_wr; /* Maximum number of WRs per SRQ */
140 u8 max_stats_queues; /* Maximum number of statistics queues */
143 /* Abilty to support RNR-NAK generation */
145 #define ECORE_RDMA_DEV_CAP_RNR_NAK_MASK 0x1
146 #define ECORE_RDMA_DEV_CAP_RNR_NAK_SHIFT 0
147 /* Abilty to support shutdown port */
148 #define ECORE_RDMA_DEV_CAP_SHUTDOWN_PORT_MASK 0x1
149 #define ECORE_RDMA_DEV_CAP_SHUTDOWN_PORT_SHIFT 1
150 /* Abilty to support port active event */
151 #define ECORE_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_MASK 0x1
152 #define ECORE_RDMA_DEV_CAP_PORT_ACTIVE_EVENT_SHIFT 2
153 /* Abilty to support port change event */
154 #define ECORE_RDMA_DEV_CAP_PORT_CHANGE_EVENT_MASK 0x1
155 #define ECORE_RDMA_DEV_CAP_PORT_CHANGE_EVENT_SHIFT 3
156 /* Abilty to support system image GUID */
157 #define ECORE_RDMA_DEV_CAP_SYS_IMAGE_MASK 0x1
158 #define ECORE_RDMA_DEV_CAP_SYS_IMAGE_SHIFT 4
159 /* Abilty to support bad P_Key counter support */
160 #define ECORE_RDMA_DEV_CAP_BAD_PKEY_CNT_MASK 0x1
161 #define ECORE_RDMA_DEV_CAP_BAD_PKEY_CNT_SHIFT 5
162 /* Abilty to support atomic operations */
163 #define ECORE_RDMA_DEV_CAP_ATOMIC_OP_MASK 0x1
164 #define ECORE_RDMA_DEV_CAP_ATOMIC_OP_SHIFT 6
165 #define ECORE_RDMA_DEV_CAP_RESIZE_CQ_MASK 0x1
166 #define ECORE_RDMA_DEV_CAP_RESIZE_CQ_SHIFT 7
167 /* Abilty to support modifying the maximum number of
168 * outstanding work requests per QP
170 #define ECORE_RDMA_DEV_CAP_RESIZE_MAX_WR_MASK 0x1
171 #define ECORE_RDMA_DEV_CAP_RESIZE_MAX_WR_SHIFT 8
172 /* Abilty to support automatic path migration */
173 #define ECORE_RDMA_DEV_CAP_AUTO_PATH_MIG_MASK 0x1
174 #define ECORE_RDMA_DEV_CAP_AUTO_PATH_MIG_SHIFT 9
175 /* Abilty to support the base memory management extensions */
176 #define ECORE_RDMA_DEV_CAP_BASE_MEMORY_EXT_MASK 0x1
177 #define ECORE_RDMA_DEV_CAP_BASE_MEMORY_EXT_SHIFT 10
178 #define ECORE_RDMA_DEV_CAP_BASE_QUEUE_EXT_MASK 0x1
179 #define ECORE_RDMA_DEV_CAP_BASE_QUEUE_EXT_SHIFT 11
180 /* Abilty to support multipile page sizes per memory region */
181 #define ECORE_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_MASK 0x1
182 #define ECORE_RDMA_DEV_CAP_MULTI_PAGE_PER_MR_EXT_SHIFT 12
183 /* Abilty to support block list physical buffer list */
184 #define ECORE_RDMA_DEV_CAP_BLOCK_MODE_MASK 0x1
185 #define ECORE_RDMA_DEV_CAP_BLOCK_MODE_SHIFT 13
186 /* Abilty to support zero based virtual addresses */
187 #define ECORE_RDMA_DEV_CAP_ZBVA_MASK 0x1
188 #define ECORE_RDMA_DEV_CAP_ZBVA_SHIFT 14
189 /* Abilty to support local invalidate fencing */
190 #define ECORE_RDMA_DEV_CAP_LOCAL_INV_FENCE_MASK 0x1
191 #define ECORE_RDMA_DEV_CAP_LOCAL_INV_FENCE_SHIFT 15
192 /* Abilty to support Loopback on QP */
193 #define ECORE_RDMA_DEV_CAP_LB_INDICATOR_MASK 0x1
194 #define ECORE_RDMA_DEV_CAP_LB_INDICATOR_SHIFT 16
197 u32 reserved_lkey; /* Value of reserved L_key */
198 u32 bad_pkey_counter; /* Bad P_key counter support indicator */
199 struct ecore_rdma_events events;
202 enum ecore_port_state {
204 ECORE_RDMA_PORT_DOWN,
207 enum ecore_roce_capability {
208 ECORE_ROCE_V1 = 1 << 0,
209 ECORE_ROCE_V2 = 1 << 1,
212 struct ecore_rdma_port {
213 enum ecore_port_state port_state;
216 u8 source_gid_table_len;
217 void *source_gid_table_ptr;
219 void *pkey_table_ptr;
220 u32 pkey_bad_counter;
221 enum ecore_roce_capability capability;
224 struct ecore_rdma_cnq_params
226 u8 num_pbl_pages; /* Number of pages in the PBL allocated
229 u64 pbl_ptr; /* Address to the first entry of the queue PBL */
232 /* The CQ Mode affects the CQ doorbell transaction size.
233 * 64/32 bit machines should configure to 32/16 bits respectively.
235 enum ecore_rdma_cq_mode {
236 ECORE_RDMA_CQ_MODE_16_BITS,
237 ECORE_RDMA_CQ_MODE_32_BITS,
240 struct ecore_roce_dcqcn_params {
241 u8 notification_point;
244 /* fields for notification point */
245 u32 cnp_send_timeout;
247 /* fields for reaction point */
248 u32 rl_bc_rate; /* Byte Counter Limit. */
249 u16 rl_max_rate; /* Maximum rate in 1.6 Mbps resolution */
250 u16 rl_r_ai; /* Active increase rate */
251 u16 rl_r_hai; /* Hyper active increase rate */
252 u16 dcqcn_g; /* Alpha update gain in 1/64K resolution */
253 u32 dcqcn_k_us; /* Alpha update interval */
254 u32 dcqcn_timeout_us;
257 #ifdef CONFIG_ECORE_IWARP
259 #define ECORE_MPA_RTR_TYPE_NONE 0 /* No RTR type */
260 #define ECORE_MPA_RTR_TYPE_ZERO_SEND (1 << 0)
261 #define ECORE_MPA_RTR_TYPE_ZERO_WRITE (1 << 1)
262 #define ECORE_MPA_RTR_TYPE_ZERO_READ (1 << 2)
269 struct ecore_iwarp_params {
272 #define ECORE_IWARP_TS_EN (1 << 0)
273 #define ECORE_IWARP_DA_EN (1 << 1)
276 enum ecore_mpa_rev mpa_rev;
283 struct ecore_roce_params {
284 enum ecore_rdma_cq_mode cq_mode;
285 struct ecore_roce_dcqcn_params dcqcn_params;
286 u8 ll2_handle; /* required for UD QPs */
289 struct ecore_rdma_start_in_params {
290 struct ecore_rdma_events *events;
291 struct ecore_rdma_cnq_params cnq_pbl_list[128];
294 u8 mac_addr[ETH_ALEN];
295 #ifdef CONFIG_ECORE_IWARP
296 struct ecore_iwarp_params iwarp;
298 struct ecore_roce_params roce;
301 struct ecore_rdma_add_user_out_params {
302 /* output variables (given to miniport) */
310 /*Returns the CQ CID or zero in case of failure */
311 struct ecore_rdma_create_cq_in_params {
312 /* input variables (given by miniport) */
313 u32 cq_handle_lo; /* CQ handle to be written in CNQ */
320 u8 pbl_page_size_log; /* for the pages that contain the
321 * pointers to the CQ pages
328 struct ecore_rdma_resize_cq_in_params {
329 /* input variables (given by miniport) */
336 u8 pbl_page_size_log; /* for the pages that contain the
337 * pointers to the CQ pages
350 struct ecore_rdma_create_qp_in_params {
351 /* input variables (given by miniport) */
352 u32 qp_handle_lo; /* QP handle to be written in CQE */
354 u32 qp_handle_async_lo; /* QP handle to be written in async event */
355 u32 qp_handle_async_hi;
358 bool fmr_and_reserved_lkey;
363 u64 sq_pbl_ptr; /* Not relevant for iWARP */
367 u64 rq_pbl_ptr; /* Not relevant for iWARP */
372 struct ecore_rdma_create_qp_out_params {
373 /* output variables (given to miniport) */
377 dma_addr_t rq_pbl_phys;
379 dma_addr_t sq_pbl_phys;
382 struct ecore_rdma_destroy_cq_in_params {
383 /* input variables (given by miniport) */
387 struct ecore_rdma_destroy_cq_out_params {
388 /* output variables, provided to the upper layer */
390 /* Sequence number of completion notification sent for the CQ on
396 /* ECORE GID can be used as IPv4/6 address in RoCE v2 */
405 struct ecore_rdma_modify_qp_in_params {
406 /* input variables (given by miniport) */
408 #define ECORE_RDMA_MODIFY_QP_VALID_NEW_STATE_MASK 0x1
409 #define ECORE_RDMA_MODIFY_QP_VALID_NEW_STATE_SHIFT 0
410 #define ECORE_ROCE_MODIFY_QP_VALID_PKEY_MASK 0x1
411 #define ECORE_ROCE_MODIFY_QP_VALID_PKEY_SHIFT 1
412 #define ECORE_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_MASK 0x1
413 #define ECORE_RDMA_MODIFY_QP_VALID_RDMA_OPS_EN_SHIFT 2
414 #define ECORE_ROCE_MODIFY_QP_VALID_DEST_QP_MASK 0x1
415 #define ECORE_ROCE_MODIFY_QP_VALID_DEST_QP_SHIFT 3
416 #define ECORE_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_MASK 0x1
417 #define ECORE_ROCE_MODIFY_QP_VALID_ADDRESS_VECTOR_SHIFT 4
418 #define ECORE_ROCE_MODIFY_QP_VALID_RQ_PSN_MASK 0x1
419 #define ECORE_ROCE_MODIFY_QP_VALID_RQ_PSN_SHIFT 5
420 #define ECORE_ROCE_MODIFY_QP_VALID_SQ_PSN_MASK 0x1
421 #define ECORE_ROCE_MODIFY_QP_VALID_SQ_PSN_SHIFT 6
422 #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_MASK 0x1
423 #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_REQ_SHIFT 7
424 #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_MASK 0x1
425 #define ECORE_RDMA_MODIFY_QP_VALID_MAX_RD_ATOMIC_RESP_SHIFT 8
426 #define ECORE_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_MASK 0x1
427 #define ECORE_ROCE_MODIFY_QP_VALID_ACK_TIMEOUT_SHIFT 9
428 #define ECORE_ROCE_MODIFY_QP_VALID_RETRY_CNT_MASK 0x1
429 #define ECORE_ROCE_MODIFY_QP_VALID_RETRY_CNT_SHIFT 10
430 #define ECORE_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_MASK 0x1
431 #define ECORE_ROCE_MODIFY_QP_VALID_RNR_RETRY_CNT_SHIFT 11
432 #define ECORE_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_MASK 0x1
433 #define ECORE_ROCE_MODIFY_QP_VALID_MIN_RNR_NAK_TIMER_SHIFT 12
434 #define ECORE_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_MASK 0x1
435 #define ECORE_ROCE_MODIFY_QP_VALID_E2E_FLOW_CONTROL_EN_SHIFT 13
436 #define ECORE_ROCE_MODIFY_QP_VALID_ROCE_MODE_MASK 0x1
437 #define ECORE_ROCE_MODIFY_QP_VALID_ROCE_MODE_SHIFT 14
439 enum ecore_roce_qp_state new_state;
441 bool incoming_rdma_read_en;
442 bool incoming_rdma_write_en;
443 bool incoming_atomic_en;
444 bool e2e_flow_control_en;
447 u8 traffic_class_tos; /* IPv6/GRH tc; IPv4 TOS */
448 u8 hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
449 u32 flow_label; /* ignored in IPv4 */
450 union ecore_gid sgid; /* GRH SGID; IPv4/6 Source IP */
451 union ecore_gid dgid; /* GRH DGID; IPv4/6 Destination IP */
452 u16 udp_src_port; /* RoCEv2 only */
458 u8 max_rd_atomic_resp;
459 u8 max_rd_atomic_req;
463 u8 min_rnr_nak_timer;
465 u8 remote_mac_addr[6];
466 u8 local_mac_addr[6];
468 enum roce_mode roce_mode;
471 struct ecore_rdma_query_qp_out_params {
472 /* output variables (given to miniport) */
473 enum ecore_roce_qp_state state;
474 u32 rq_psn; /* responder */
475 u32 sq_psn; /* requester */
476 bool draining; /* send queue is draining */
479 bool incoming_rdma_read_en;
480 bool incoming_rdma_write_en;
481 bool incoming_atomic_en;
482 bool e2e_flow_control_en;
483 union ecore_gid sgid; /* GRH SGID; IPv4/6 Source IP */
484 union ecore_gid dgid; /* GRH DGID; IPv4/6 Destination IP */
485 u32 flow_label; /* ignored in IPv4 */
486 u8 hop_limit_ttl; /* IPv6/GRH hop limit; IPv4 TTL */
487 u8 traffic_class_tos; /* IPv6/GRH tc; IPv4 TOS */
491 u8 min_rnr_nak_timer;
494 u8 max_dest_rd_atomic;
498 struct ecore_rdma_register_tid_in_params {
499 /* input variables (given by miniport) */
500 u32 itid; /* index only, 18 bit long, lkey = itid << 8 | key */
501 enum ecore_rdma_tid_type tid_type;
512 u8 pbl_page_size_log; /* for the pages that contain the pointers
515 u8 page_size_log; /* for the MR pages */
517 u64 length; /* only lower 40 bits are valid */
523 /* DIF related fields */
529 struct ecore_rdma_create_srq_in_params {
537 struct ecore_rdma_create_srq_out_params {
541 struct ecore_rdma_destroy_srq_in_params {
545 struct ecore_rdma_modify_srq_in_params {
550 struct ecore_rdma_resize_cq_out_params {
551 /* output variables, provided to the upper layer */
552 u32 prod; /* CQ producer value on old PBL */
553 u32 cons; /* CQ consumer value on old PBL */
556 struct ecore_rdma_resize_cnq_in_params {
557 /* input variables (given by miniport) */
559 u32 pbl_page_size_log; /* for the pages that contain the
560 * pointers to the cnq pages
565 struct ecore_rdma_stats_out_params {
572 u64 icrc_errors; /* wraps at 32 bits */
573 u64 retransmit_events; /* wraps at 32 bits */
574 u64 silent_drops; /* wraps at 16 bits */
575 u64 rnr_nacks_sent; /* wraps at 16 bits */
578 u64 iwarp_tx_fast_rxmit_cnt;
579 u64 iwarp_tx_slow_start_cnt;
583 struct ecore_rdma_counters_out_params {
597 ecore_rdma_add_user(void *rdma_cxt,
598 struct ecore_rdma_add_user_out_params *out_params);
601 ecore_rdma_alloc_pd(void *rdma_cxt,
605 ecore_rdma_alloc_tid(void *rdma_cxt,
609 ecore_rdma_create_cq(void *rdma_cxt,
610 struct ecore_rdma_create_cq_in_params *params,
613 /* Returns a pointer to the responders' CID, which is also a pointer to the
614 * ecore_qp_params struct. Returns NULL in case of failure.
616 struct ecore_rdma_qp*
617 ecore_rdma_create_qp(void *rdma_cxt,
618 struct ecore_rdma_create_qp_in_params *in_params,
619 struct ecore_rdma_create_qp_out_params *out_params);
622 ecore_roce_create_ud_qp(void *rdma_cxt,
623 struct ecore_rdma_create_qp_out_params *out_params);
626 ecore_rdma_deregister_tid(void *rdma_cxt,
630 ecore_rdma_destroy_cq(void *rdma_cxt,
631 struct ecore_rdma_destroy_cq_in_params *in_params,
632 struct ecore_rdma_destroy_cq_out_params *out_params);
635 ecore_rdma_destroy_qp(void *rdma_cxt,
636 struct ecore_rdma_qp *qp);
639 ecore_roce_destroy_ud_qp(void *rdma_cxt, u16 cid);
642 ecore_rdma_free_pd(void *rdma_cxt,
646 ecore_rdma_free_tid(void *rdma_cxt,
650 ecore_rdma_modify_qp(void *rdma_cxt,
651 struct ecore_rdma_qp *qp,
652 struct ecore_rdma_modify_qp_in_params *params);
654 struct ecore_rdma_device*
655 ecore_rdma_query_device(void *rdma_cxt);
657 struct ecore_rdma_port*
658 ecore_rdma_query_port(void *rdma_cxt);
661 ecore_rdma_query_qp(void *rdma_cxt,
662 struct ecore_rdma_qp *qp,
663 struct ecore_rdma_query_qp_out_params *out_params);
666 ecore_rdma_register_tid(void *rdma_cxt,
667 struct ecore_rdma_register_tid_in_params *params);
669 void ecore_rdma_remove_user(void *rdma_cxt,
673 ecore_rdma_resize_cnq(void *rdma_cxt,
674 struct ecore_rdma_resize_cnq_in_params *in_params);
676 /*Returns the CQ CID or zero in case of failure */
678 ecore_rdma_resize_cq(void *rdma_cxt,
679 struct ecore_rdma_resize_cq_in_params *in_params,
680 struct ecore_rdma_resize_cq_out_params *out_params);
682 /* Before calling rdma_start upper layer (VBD/qed) should fill the
683 * page-size and mtu in hwfn context
686 ecore_rdma_start(void *p_hwfn,
687 struct ecore_rdma_start_in_params *params);
690 ecore_rdma_stop(void *rdma_cxt);
693 ecore_rdma_query_stats(void *rdma_cxt, u8 stats_queue,
694 struct ecore_rdma_stats_out_params *out_parms);
697 ecore_rdma_query_counters(void *rdma_cxt,
698 struct ecore_rdma_counters_out_params *out_parms);
700 u32 ecore_rdma_get_sb_id(void *p_hwfn, u32 rel_sb_id);
702 u32 ecore_rdma_query_cau_timer_res(void *p_hwfn);
704 void ecore_rdma_cnq_prod_update(void *rdma_cxt, u8 cnq_index, u16 prod);
706 void ecore_rdma_resc_free(struct ecore_hwfn *p_hwfn);
708 #ifdef CONFIG_ECORE_IWARP
713 enum ecore_iwarp_event_type {
714 ECORE_IWARP_EVENT_MPA_REQUEST, /* Passive side request received */
715 ECORE_IWARP_EVENT_PASSIVE_COMPLETE, /* Passive side established
716 * ( ack on mpa response )
718 ECORE_IWARP_EVENT_ACTIVE_COMPLETE, /* Active side reply received */
719 ECORE_IWARP_EVENT_DISCONNECT,
720 ECORE_IWARP_EVENT_CLOSE,
721 ECORE_IWARP_EVENT_IRQ_FULL,
722 ECORE_IWARP_EVENT_RQ_EMPTY,
723 ECORE_IWARP_EVENT_LLP_TIMEOUT,
724 ECORE_IWARP_EVENT_REMOTE_PROTECTION_ERROR,
725 ECORE_IWARP_EVENT_CQ_OVERFLOW,
726 ECORE_IWARP_EVENT_QP_CATASTROPHIC,
727 ECORE_IWARP_EVENT_ACTIVE_MPA_REPLY,
728 ECORE_IWARP_EVENT_LOCAL_ACCESS_ERROR,
729 ECORE_IWARP_EVENT_REMOTE_OPERATION_ERROR,
730 ECORE_IWARP_EVENT_TERMINATE_RECEIVED
733 enum ecore_tcp_ip_version
739 struct ecore_iwarp_cm_info {
740 enum ecore_tcp_ip_version ip_version;
746 const void *private_data;
747 u16 private_data_len;
752 struct ecore_iwarp_cm_event_params {
753 enum ecore_iwarp_event_type event;
754 const struct ecore_iwarp_cm_info *cm_info;
755 void *ep_context; /* To be passed to accept call */
759 typedef int (*iwarp_event_handler)(void *context,
760 struct ecore_iwarp_cm_event_params *event);
762 /* Active Side Connect Flow:
763 * upper layer driver calls ecore_iwarp_connect
764 * Function is blocking: i.e. returns after tcp connection is established
765 * After MPA connection is established ECORE_IWARP_EVENT_ACTIVE_COMPLETE event
766 * will be passed to upperlayer driver using the event_cb passed in
767 * ecore_iwarp_connect_in. Information of the established connection will be
768 * initialized in event data.
770 struct ecore_iwarp_connect_in {
771 iwarp_event_handler event_cb;
773 struct ecore_rdma_qp *qp;
774 struct ecore_iwarp_cm_info cm_info;
776 u8 remote_mac_addr[6];
777 u8 local_mac_addr[6];
780 struct ecore_iwarp_connect_out {
784 /* Passive side connect flow:
785 * upper layer driver calls ecore_iwarp_create_listen
786 * once Syn packet that matches a ip/port that is listened on arrives, ecore
787 * will offload the tcp connection. After MPA Request is received on the
788 * offload connection, the event ECORE_IWARP_EVENT_MPA_REQUEST will be sent
789 * to upper layer driver using the event_cb passed below. The event data
790 * will be placed in event parameter. After upper layer driver processes the
791 * event, ecore_iwarp_accept or ecore_iwarp_reject should be called to continue
792 * MPA negotiation. Once negotiation is complete the event
793 * ECORE_IWARP_EVENT_PASSIVE_COMPLETE will be passed to the event_cb passed
794 * originally in ecore_iwarp_listen_in structure.
796 struct ecore_iwarp_listen_in {
797 iwarp_event_handler event_cb; /* Callback func for delivering events */
798 void *cb_context; /* passed to event_cb */
799 u32 max_backlog; /* Max num of pending incoming connection requests */
800 enum ecore_tcp_ip_version ip_version;
806 struct ecore_iwarp_listen_out {
807 void *handle; /* to be sent to destroy */
810 struct ecore_iwarp_accept_in {
811 void *ep_context; /* From event data of ECORE_IWARP_EVENT_MPA_REQUEST */
812 void *cb_context; /* context to be passed to event_cb */
813 struct ecore_rdma_qp *qp;
814 const void *private_data;
815 u16 private_data_len;
820 struct ecore_iwarp_reject_in {
821 void *ep_context; /* From event data of ECORE_IWARP_EVENT_MPA_REQUEST */
822 void *cb_context; /* context to be passed to event_cb */
823 const void *private_data;
824 u16 private_data_len;
827 struct ecore_iwarp_send_rtr_in {
831 struct ecore_iwarp_tcp_abort_in {
837 ecore_iwarp_connect(void *rdma_cxt,
838 struct ecore_iwarp_connect_in *iparams,
839 struct ecore_iwarp_connect_out *oparams);
842 ecore_iwarp_create_listen(void *rdma_cxt,
843 struct ecore_iwarp_listen_in *iparams,
844 struct ecore_iwarp_listen_out *oparams);
847 ecore_iwarp_accept(void *rdma_cxt,
848 struct ecore_iwarp_accept_in *iparams);
851 ecore_iwarp_reject(void *rdma_cxt,
852 struct ecore_iwarp_reject_in *iparams);
855 ecore_iwarp_destroy_listen(void *rdma_cxt, void *handle);
858 ecore_iwarp_send_rtr(void *rdma_cxt, struct ecore_iwarp_send_rtr_in *iparams);
861 ecore_iwarp_tcp_abort(void *rdma_cxt, struct ecore_iwarp_tcp_abort_in *iparams);
863 #endif /* CONFIG_ECORE_IWARP */