2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
31 /****************************************************************************
35 * Description: MCP private data. Located in HSI only to provide debug access
38 ****************************************************************************/
43 #if (!defined MFW_SIM) && (!defined RECOVERY)
48 #include "mcp_public.h"
50 typedef enum active_mf_mode {
53 MF_MODE_MF_SWITCH_INDEPENDENT,
68 struct dci_info_global {
69 enum ov_current_cfg current_cfg;
74 /* Resource allocation information of one resource */
75 struct resource_info_private {
76 u16 size; /* number of allocated resources */
77 u16 offset; /* Offset of the 1st resource */
81 /* Cache for resource allocation of one PF */
82 struct res_alloc_cache {
84 struct resource_info_private res[RESOURCE_MAX_NUM];
94 /**************************************/
96 /* P R I V A T E G L O B A L */
98 /**************************************/
99 struct private_global {
100 active_mf_mode_t mf_mode; /* TBD - require initialization */
101 u32 exp_rom_nvm_addr;
103 /* The pmm_config structure holds all active phy/link configuration */
106 struct pmm_config eth_cfg;
108 struct ah_eth eth_cfg;
114 u32 avs_init_timestamp;
116 u32 seconds_since_mcp_reset;
118 u32 last_malloc_dir_used_timestamp;
119 #define MAX_USED_DIR_ALLOWED_TIME (3) /* Seconds */
123 #define DRV_NVM_STATE_IN_PROGRESS_MASK (0x0000ffff)
124 #define DRV_NVM_STATE_IN_PROGRESS_OFFSET (0)
129 struct dci_info_global dci_global;
131 /* Resource allocation cached data */
132 struct res_alloc_cache res_alloc;
133 #define G_RES_ALLOC_P (&g_spad.private_data.global.res_alloc)
134 u32 resource_max_values[RESOURCE_MAX_NUM];
137 /**************************************/
139 /* P R I V A T E P A T H */
141 /**************************************/
142 struct private_path {
143 u32 recovery_countdown; /* Counting down 2 seconds, using TMR3 */
144 #define RECOVERY_MAX_COUNTDOWN_SECONDS 2
146 u32 drv_load_vars; /* When the seconds_since_mcp_reset gets here */
147 #define DRV_LOAD_TIMEOUT_MASK 0x0000ffff
148 #define DRV_LOAD_TIMEOUT_SHIFT 0
149 #define DRV_LOAD_NEED_FORCE_MASK 0xffff0000
150 #define DRV_LOAD_NEED_FORCE_SHIFT 16
151 struct load_rsp_stc drv_load_params;
155 /**************************************/
157 /* P R I V A T E P O R T */
159 /**************************************/
160 struct drv_port_info_t {
162 #define DRV_STATE_LINK_LOCK_FLAG 0x00000001
163 #define DRV_WAIT_DBG_PRN 0x00000002
165 /* There are maximum 8 PFs per port */
166 #define DRV_STATE_LOADED_MASK 0x0000ff00
167 #define DRV_STATE_LOADED_SHIFT 8
169 #define DRV_STATE_PF_TRANSITION_MASK 0x00ff0000
170 #define DRV_STATE_PF_TRANSITION_SHIFT 16
172 #define DRV_STATE_PF_PHY_INIT_MASK 0xff000000
173 #define DRV_STATE_PF_PHY_INIT_SHIFT 24
176 typedef enum _lldp_subscriber_e {
177 LLDP_SUBSCRIBER_MANDATORY = 0,
178 LLDP_SUBSCRIBER_DCBX_IEEE,
179 LLDP_SUBSCRIBER_DCBX_CEE,
188 #define LLDP_LEN_MASK (0x01ff)
189 #define LLDP_LEN_SHIFT (0)
190 #define LLDP_TYPE_MASK (0xfe00)
191 #define LLDP_TYPE_SHIFT (9)
195 typedef u16(*lldp_prepare_tlv_func)(u8 port, lldp_agent_e lldp_agent, u8 *buffer);
199 lldp_prepare_tlv_func func;
200 } subscriber_callback_send_s;
202 typedef u8(*lldp_process_func)(u8 port, u8 num, u8 **tlvs);
204 #define MAX_NUM_SUBTYPES 4
208 u8 subtype_list[MAX_NUM_SUBTYPES];
210 lldp_process_func func;
211 } subscriber_callback_receive_s;
213 #define MAX_ETH_HEADER 14 /* TODO: to be extended per requirements */
214 #define MAX_PACKET_SIZE (1516) /* So it can be divided by 4 */
215 #define LLDP_CHASSIS_ID_TLV_LEN 7
216 #define LLDP_PORT_ID_TLV_LEN 7
217 #define MAX_TLV_BUFFER 128 /* In dwords. 512 in bytes*/
220 u8 header[MAX_ETH_HEADER];
224 struct lldp_config_params_s lldp_config_params;
227 subscriber_callback_send_s subscriber_callback_send[MAX_SUBSCRIBERS];
228 lldp_eth_header_s lldp_eth_header;
229 u32 lldp_time_to_send;
230 u32 lldp_ttl_expired;
233 subscriber_callback_receive_s subscriber_callback_receive[MAX_SUBSCRIBERS];
238 u8 current_received_tlv_index;
239 u8 *received_tlvs[MAX_TLVS];
240 } lldp_receive_data_s;
242 #define MAX_REGISTERED_TLVS 6
245 u32 config; /* Uses same defines as local config plus some more below*/
246 #define DCBX_MODE_MASK 0x00000010
247 #define DCBX_MODE_SHIFT 4
248 #define DCBX_MODE_DRIVER 0
249 #define DCBX_MODE_DEFAULT 1
250 #define DCBX_CHANGED_MASK 0x00000f00
251 #define DCBX_CHANGED_SHIFT 8
252 #define DCBX_CONTROL_CHANGED_MASK 0x00000100
253 #define DCBX_CONTROL_CHANGED_SHIFT 8
254 #define DCBX_PFC_CHANGED_MASK 0x00000200
255 #define DCBX_PFC_CHANGED_SHIFT 9
256 #define DCBX_ETS_CHANGED_MASK 0x00000400
257 #define DCBX_ETS_CHANGED_SHIFT 10
258 #define DCBX_APP_CHANGED_MASK 0x00000800
259 #define DCBX_APP_CHANGED_SHIFT 11
268 #ifdef CONFIG_HP_DCI_SUPPORT
269 struct dci_info_port {
271 #define DCI_PORT_CFG_ENABLE_SHIFT (0)
272 #define DCI_PORT_CFG_ENABLE_MASK (1 << DCI_PORT_CFG_ENABLE_SHIFT)
273 #define DCI_PORT_CFG_ENABLE_DIAG_SHIFT (1)
274 #define DCI_PORT_CFG_ENABLE_DIAG_MASK (1 << DCI_PORT_CFG_ENABLE_DIAG_SHIFT)
275 #define DCI_PORT_CFG_DIAG_L_LOOP_SHIFT (2)
276 #define DCI_PORT_CFG_DIAG_L_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_L_LOOP_SHIFT)
277 #define DCI_PORT_CFG_DIAG_R_LOOP_SHIFT (3)
278 #define DCI_PORT_CFG_DIAG_R_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_R_LOOP_SHIFT)
283 struct private_port {
284 struct drv_port_info_t port_info;
285 active_mf_mode_t mf_mode;
286 u32 prev_link_change_count;
287 /* LLDP structures */
288 lldp_params_s lldp_params[LLDP_MAX_LLDP_AGENTS];
289 lldp_receive_data_s lldp_receive_data[MAX_SUBSCRIBERS];
292 dcbx_state_s dcbx_state;
294 u32 net_buffer[MAX_PACKET_SIZE / 4]; /* Buffer to send any packet to network */
296 /* time stamp of the end of NIG drain time for the TX drain */
297 u32 nig_drain_end_ts;
298 /* time stamp of the end of NIG drain time for the TC pause drain, this timer is used togther for all TC */
299 u32 nig_drain_tc_end_ts;
300 u32 tc_drain_en_bitmap;
301 u32 recv_lldp_tlvs[LLDP_MAX_LLDP_AGENTS][MAX_TLV_BUFFER];
302 tlv_s lldp_core_tlv_desc[LLDP_MAX_LLDP_AGENTS][MAX_REGISTERED_TLVS];
303 u8 current_core_tlv_num[LLDP_MAX_LLDP_AGENTS];
304 struct mcp_mac lldp_mac;
305 #ifdef CONFIG_HP_DCI_SUPPORT
306 struct dci_info_port dci_port;
312 /**************************************/
314 /* P R I V A T E F U N C */
316 /**************************************/
317 struct drv_func_info_t {
319 #define DRV_STATE_UNKNOWN 0x00000000
320 #define DRV_STATE_UNLOADED 0x00000001
321 #define DRV_STATE_D3 0x00000004
323 #define DRV_STATE_PRESENT_FLAG 0x00000100
324 #define DRV_STATE_RUNNING (0x00000002 | DRV_STATE_PRESENT_FLAG)
326 #define DRV_STATE_NOT_RESPONDING 0x00000003 /* Will result with non-zero value when compared with DRV_STATE_RUNNING or with DRV_STATE_UNLOADED */
327 #define DRV_STATE_BACK_AFTER_TO (DRV_STATE_NOT_RESPONDING | DRV_STATE_PRESENT_FLAG)
329 #define DRV_STATE_DIAG (0x00000010 | DRV_STATE_PRESENT_FLAG)
331 #define DRV_STATE_TRANSITION_FLAG 0x00001000
332 #define DRV_STATE_LOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG)
333 #define DRV_STATE_UNLOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG | DRV_STATE_UNLOADED)
335 u32_t driver_last_activity;
337 u32_t wol_mac_addr[2];
338 u32_t drv_feature_support; /* See DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_* */
340 u8_t unload_wol_param; /* See drv_mb_param */
344 struct dci_info_func {
346 #define DCI_FUNC_CFG_FNIC_ENABLE_SHIFT (0)
347 #define DCI_FUNC_CFG_FNIC_ENABLE_MASK (1 << DCI_FUNC_CFG_FNIC_ENABLE_SHIFT)
348 #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_SHIFT (1)
349 #define DCI_FUNC_CFG_OS_MTU_OVERRIDE_MASK (1 << DCI_FUNC_CFG_OS_MTU_OVERRIDE_SHIFT)
350 #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_SHIFT (2)
351 #define DCI_FUNC_CFG_DIAG_WOL_ENABLE_MASK (1 << DCI_FUNC_CFG_DIAG_WOL_ENABLE_SHIFT)
355 u8 fcoe_fabric_name[8];
358 struct private_func {
359 struct drv_func_info_t func_info;
363 struct dci_info_func dci_func;
367 /**************************************/
369 /* P R I V A T E D A T A */
371 /**************************************/
372 struct mcp_private_data {
373 /* Basically no need for section offsets here, since this is private data.
374 * TBD - should consider adding section offsets if we want diag to parse this correctly !!
376 struct private_global global;
377 struct private_path path[MCP_GLOB_PATH_MAX];
378 struct private_port port[MCP_GLOB_PORT_MAX];
379 struct private_func func[MCP_GLOB_FUNC_MAX];
382 #endif /* MCP_PRIVATE_H */