sys/dev/qlnx/qlnxe/nvm_map.h

   1 /*
   2  * Copyright (c) 2017-2018 Cavium, Inc.
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  *
  29  */
  30
  31 /****************************************************************************
  32  * Name:        nvm_map.h
  33  *
  34  * Description: Everest NVRAM map
  35  *
  36  ****************************************************************************/
  37
  38 #ifndef NVM_MAP_H
  39 #define NVM_MAP_H
  40
  41 #define CRC_MAGIC_VALUE                     0xDEBB20E3
  42 #define CRC32_POLYNOMIAL                    0xEDB88320
  43 #define NVM_CRC_SIZE                            (sizeof(u32))
  44 enum nvm_sw_arbitrator {
  45         NVM_SW_ARB_HOST,
  46         NVM_SW_ARB_MCP,
  47         NVM_SW_ARB_UART,
  48         NVM_SW_ARB_RESERVED
  49 };
  50
  51 /****************************************************************************
  52  * Boot Strap Region                                                        *
  53  ****************************************************************************/
  54 struct legacy_bootstrap_region {
  55         u32 magic_value;        /* a pattern not likely to occur randomly */
  56 #define NVM_MAGIC_VALUE          0x669955aa
  57         u32 sram_start_addr;    /* where to locate LIM code (byte addr) */
  58         u32 code_len;           /* boot code length (in dwords) */
  59         u32 code_start_addr;    /* location of code on media (media byte addr) */
  60         u32 crc;                /* 32-bit CRC */
  61 };
  62
  63 /****************************************************************************
  64  * Directories Region                                                       *
  65  ****************************************************************************/
  66 struct nvm_code_entry {
  67         u32 image_type;         /* Image type */
  68         u32 nvm_start_addr;     /* NVM address of the image */
  69         u32 len;                /* Include CRC */
  70         u32 sram_start_addr;    /* Where to load the image on the scratchpad */
  71         u32 sram_run_addr;      /* Relevant in case of MIM only */
  72 };
  73
  74 enum nvm_image_type {
  75         NVM_TYPE_TIM1       = 0x01,
  76         NVM_TYPE_TIM2       = 0x02,
  77         NVM_TYPE_MIM1       = 0x03,
  78         NVM_TYPE_MIM2       = 0x04,
  79         NVM_TYPE_MBA        = 0x05,
  80         NVM_TYPE_MODULES_PN = 0x06,
  81         NVM_TYPE_VPD        = 0x07,
  82         NVM_TYPE_MFW_TRACE1 = 0x08,
  83         NVM_TYPE_MFW_TRACE2 = 0x09,
  84         NVM_TYPE_NVM_CFG1   = 0x0a,
  85         NVM_TYPE_L2B        = 0x0b,
  86         NVM_TYPE_DIR1       = 0x0c,
  87         NVM_TYPE_EAGLE_FW1  = 0x0d,
  88         NVM_TYPE_FALCON_FW1 = 0x0e,
  89         NVM_TYPE_PCIE_FW1   = 0x0f,
  90         NVM_TYPE_HW_SET     = 0x10,
  91         NVM_TYPE_LIM        = 0x11,
  92         NVM_TYPE_AVS_FW1    = 0x12,
  93         NVM_TYPE_DIR2       = 0x13,
  94         NVM_TYPE_CCM        = 0x14,
  95         NVM_TYPE_EAGLE_FW2  = 0x15,
  96         NVM_TYPE_FALCON_FW2 = 0x16,
  97         NVM_TYPE_PCIE_FW2   = 0x17,
  98         NVM_TYPE_AVS_FW2    = 0x18,
  99         NVM_TYPE_INIT_HW    = 0x19,
 100         NVM_TYPE_DEFAULT_CFG= 0x1a,
 101         NVM_TYPE_MDUMP      = 0x1b,
 102         NVM_TYPE_NVM_META   = 0x1c,
 103         NVM_TYPE_ISCSI_CFG  = 0x1d,
 104         NVM_TYPE_FCOE_CFG   = 0x1f,
 105         NVM_TYPE_ETH_PHY_FW1 = 0x20,
 106         NVM_TYPE_ETH_PHY_FW2 = 0x21,
 107         NVM_TYPE_BDN        = 0x22,
 108         NVM_TYPE_8485X_PHY_FW = 0x23,
 109         NVM_TYPE_PUB_KEY    = 0x24,
 110         NVM_TYPE_RECOVERY   = 0x25,
 111         NVM_TYPE_MAX,
 112 };
 113
 114 #ifdef DEFINE_IMAGE_TABLE
 115 struct image_map {
 116         char name[32];
 117         char option[32];
 118         u32 image_type;
 119 };
 120
 121 struct image_map g_image_table[] = {
 122         {"TIM1",        "-tim1",    NVM_TYPE_TIM1},
 123         {"TIM2",        "-tim2",    NVM_TYPE_TIM2},
 124         {"MIM1",        "-mim1",    NVM_TYPE_MIM1},
 125         {"MIM2",        "-mim2",    NVM_TYPE_MIM2},
 126         {"MBA",         "-mba",     NVM_TYPE_MBA},
 127         {"OPT_MODULES", "-optm",    NVM_TYPE_MODULES_PN},
 128         {"VPD",         "-vpd",     NVM_TYPE_VPD},
 129         {"MFW_TRACE1",  "-mfwt1",   NVM_TYPE_MFW_TRACE1},
 130         {"MFW_TRACE2",  "-mfwt2",   NVM_TYPE_MFW_TRACE2},
 131         {"NVM_CFG1",    "-cfg",     NVM_TYPE_NVM_CFG1},
 132         {"L2B",         "-l2b",     NVM_TYPE_L2B},
 133         {"DIR1",        "-dir1",    NVM_TYPE_DIR1},
 134         {"EAGLE_FW1",   "-eagle1",  NVM_TYPE_EAGLE_FW1},
 135         {"FALCON_FW1",  "-falcon1", NVM_TYPE_FALCON_FW1},
 136         {"PCIE_FW1",    "-pcie1",   NVM_TYPE_PCIE_FW1},
 137         {"HW_SET",      "-hw_set",  NVM_TYPE_HW_SET},
 138         {"LIM",         "-lim",     NVM_TYPE_LIM},
 139         {"AVS_FW1",     "-avs1",    NVM_TYPE_AVS_FW1},
 140         {"DIR2",        "-dir2",    NVM_TYPE_DIR2},
 141         {"CCM",         "-ccm",     NVM_TYPE_CCM},
 142         {"EAGLE_FW2",   "-eagle2",  NVM_TYPE_EAGLE_FW2},
 143         {"FALCON_FW2",  "-falcon2", NVM_TYPE_FALCON_FW2},
 144         {"PCIE_FW2",    "-pcie2",   NVM_TYPE_PCIE_FW2},
 145         {"AVS_FW2",     "-avs2",    NVM_TYPE_AVS_FW2},
 146         {"INIT_HW",     "-init_hw", NVM_TYPE_INIT_HW},
 147         {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG},
 148         {"CRASH_DUMP",  "-mdump",   NVM_TYPE_MDUMP},
 149         {"META",            "-meta",    NVM_TYPE_NVM_META},
 150         {"ISCSI_CFG",   "-iscsi_cfg", NVM_TYPE_ISCSI_CFG},
 151         {"FCOE_CFG",    "-fcoe_cfg",NVM_TYPE_FCOE_CFG},
 152         {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1},
 153         {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2},
 154         {"BDN",         "-bdn",     NVM_TYPE_BDN},
 155         {"PK",          "-pk",      NVM_TYPE_PUB_KEY},
 156         {"RECOVERY",    "-recovery",NVM_TYPE_RECOVERY}
 157 };
 158
 159 #define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map))
 160
 161 #endif  /* #ifdef DEFINE_IMAGE_TABLE */
 162 #define MAX_NVM_DIR_ENTRIES 150
 163 /* Note: The has given 150 possible entries since anyway each file captures at least one page. */
 164
 165 struct nvm_dir {
 166         s32 seq; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */
 167 #define NVM_DIR_NEXT_MFW_MASK   0x00000001
 168 #define NVM_DIR_SEQ_MASK        0xfffffffe
 169 #define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK)
 170 #define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \
 171         do { \
 172                 _seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \
 173         } while (0)
 174 #define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK)
 175
 176         u32 num_images;
 177         u32 rsrv;
 178         struct nvm_code_entry code[1];  /* Up to MAX_NVM_DIR_ENTRIES */
 179 };
 180 #define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE)
 181
 182 struct nvm_vpd_image {
 183         u32 format_revision;
 184 #define VPD_IMAGE_VERSION        1
 185
 186         /* This array length depends on the number of VPD fields */
 187         u8 vpd_data[1];
 188 };
 189
 190 /****************************************************************************
 191  * NVRAM FULL MAP                                                           *
 192  ****************************************************************************/
 193 #define DIR_ID_1    (0)
 194 #define DIR_ID_2    (1)
 195 #define MAX_DIR_IDS (2)
 196
 197 #define MFW_BUNDLE_1    (0)
 198 #define MFW_BUNDLE_2    (1)
 199 #define MAX_MFW_BUNDLES (2)
 200
 201 #define FLASH_PAGE_SIZE 0x1000
 202 #define NVM_DIR_MAX_SIZE    (FLASH_PAGE_SIZE)           /* 4Kb */
 203 #define ASIC_MIM_MAX_SIZE   (300*FLASH_PAGE_SIZE)       /* 1.2Mb */
 204 #define FPGA_MIM_MAX_SIZE   (62*FLASH_PAGE_SIZE)        /* 250Kb */
 205
 206 /* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page.
 207  * The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it.
 208  */
 209 #define LIM_MAX_SIZE        ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE)
 210 #define LIM_OFFSET          (NVM_OFFSET(lim_image))
 211 #define NVM_RSV_SIZE            (44)
 212 #define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : FPGA_MIM_MAX_SIZE )
 213 #define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0))
 214 #define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + MIM_MAX_SIZE(is_asic)*2)
 215
 216 union nvm_dir_union {
 217         struct nvm_dir dir;
 218         u8 page[FLASH_PAGE_SIZE];
 219 };
 220
 221 /*                        Address
 222  *  +-------------------+ 0x000000
 223  *  |    Bootstrap:     |
 224  *  | magic_number      |
 225  *  | sram_start_addr   |
 226  *  | code_len          |
 227  *  | code_start_addr   |
 228  *  | crc               |
 229  *  +-------------------+ 0x000014
 230  *  | rsrv              |
 231  *  +-------------------+ 0x000040
 232  *  | LIM               |
 233  *  +-------------------+ 0x002000
 234  *  | Dir1              |
 235  *  +-------------------+ 0x003000
 236  *  | Dir2              |
 237  *  +-------------------+ 0x004000
 238  *  | MIM1              |
 239  *  +-------------------+ 0x130000
 240  *  | MIM2              |
 241  *  +-------------------+ 0x25C000
 242  *  | Rest Images:      |
 243  *  | TIM1/2            |
 244  *  | MFW_TRACE1/2      |
 245  *  | Eagle/Falcon FW   |
 246  *  | PCIE/AVS FW       |
 247  *  | MBA/CCM/L2B       |
 248  *  | VPD               |
 249  *  | optic_modules     |
 250  *  |  ...              |
 251  *  +-------------------+ 0x400000
 252 */
 253 struct nvm_image {
 254 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
 255                                                 /* NVM Offset  (size) */
 256         struct legacy_bootstrap_region bootstrap;       /* 0x000000 (0x000014) */
 257         u8 rsrv[NVM_RSV_SIZE];                  /* 0x000014 (0x00002c) */
 258         u8 lim_image[LIM_MAX_SIZE];             /* 0x000040 (0x001fc0) */
 259         union nvm_dir_union dir[MAX_MFW_BUNDLES];       /* 0x002000 (0x001000)x2 */
 260         /* MIM1_IMAGE                              0x004000 (0x12c000) */
 261         /* MIM2_IMAGE                              0x130000 (0x12c000) */
 262 /*********** !!!  FIXED SECTIONS  !!! DO NOT MODIFY !!! **********************/
 263 };                              /* 0x134 */
 264
 265 #define NVM_OFFSET(f)       ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f))))
 266
 267 struct hw_set_info {
 268         u32 reg_type;
 269 #define GRC_REG_TYPE 1
 270 #define PHY_REG_TYPE 2
 271 #define PCI_REG_TYPE 4
 272
 273         u32 bank_num;
 274         u32 pf_num;
 275         u32 operation;
 276 #define READ_OP     1
 277 #define WRITE_OP    2
 278 #define RMW_SET_OP  3
 279 #define RMW_CLR_OP  4
 280
 281         u32 reg_addr;
 282         u32 reg_data;
 283
 284         u32 reset_type;
 285 #define POR_RESET_TYPE  (1 << 0)
 286 #define HARD_RESET_TYPE (1 << 1)
 287 #define CORE_RESET_TYPE (1 << 2)
 288 #define MCP_RESET_TYPE  (1 << 3)
 289 #define PERSET_ASSERT   (1 << 4)
 290 #define PERSET_DEASSERT (1 << 5)
 291
 292 };
 293
 294 struct hw_set_image {
 295         u32 format_version;
 296 #define HW_SET_IMAGE_VERSION        1
 297         u32 no_hw_sets;
 298         /* This array length depends on the no_hw_sets */
 299         struct hw_set_info hw_sets[1];
 300 };
 301
 302 #endif                          //NVM_MAP_H