2 * Copyright (c) 2017-2018 Cavium, Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
32 /****************************************************************************
35 * Description: Global definitions
39 ****************************************************************************/
41 * Spad Layout NVM CFG MCP public
42 *==========================================================================================================
43 * MCP_REG_SCRATCH REG_RD(MISC_REG_GEN_PURP_CR0) REG_RD(MISC_REG_SHARED_MEM_ADDR)
44 * +------------------+ +-------------------------+ +-------------------+
45 * | Num Sections(4B)|Currently 4 | Num Sections(4B) | | Num Sections(4B)|Currently 6
46 * +------------------+ +-------------------------+ +-------------------+
47 * | Offsize(Trace) |4B -+ +-- | Offset(NVM_CFG1) | | Offsize(drv_mb) |
48 * +-| Offsize(NVM_CFG) |4B | | | (Size is fixed) | | Offsize(mfw_mb) |
49 *+-|-| Offsize(Public) |4B | +-> +-------------------------+ | Offsize(global) |
50 *| | | Offsize(Private) |4B | | | | Offsize(path) |
51 *| | +------------------+ <--+ | nvm_cfg1_glob | | Offsize(port) |
52 *| | | | +-------------------------+ | Offsize(func) |
53 *| | | Trace | | nvm_cfg1_path 0 | +-------------------+
54 *| +>+------------------+ | nvm_cfg1_path 1 | | drv_mb PF0/2/4..|8 Funcs of engine0
55 *| | | +-------------------------+ | drv_mb PF1/3/5..|8 Funcs of engine1
56 *| | NVM_CFG | | nvm_cfg1_port 0 | +-------------------+
57 *+-> +------------------+ | .... | | mfw_mb PF0/2/4..|8 Funcs of engine0
58 * | | | nvm_cfg1_port 3 | | mfw_mb PF1/3/5..|8 Funcs of engine1
59 * | Public Data | +-------------------------+ +-------------------+
60 * +------------------+ 8 Funcs of Engine 0| nvm_cfg1_func PF0/2/4/..| | |
61 * | | 8 Funcs of Engine 1| nvm_cfg1_func PF1/3/5/..| | public_global |
62 * | Private Data | +-------------------------+ +-------------------+
63 * +------------------+ | public_path 0 |
64 * | Code | | public_path 1 |
65 * | Static Area | +-------------------+
66 * +--- ---+ | public_port 0 |
68 * | PIM Area | | public_port 3 |
69 * +------------------+ +-------------------+
70 * | public_func 0/2/4.|8 Funcs of engine0
71 * | public_func 1/3/5.|8 Funcs of engine1
72 * +-------------------+
77 #ifndef MDUMP_PARSE_TOOL
84 #include "mcp_public.h"
89 #include "mcp_private.h"
92 extern struct spad_layout g_spad;
94 /* TBD - Consider renaming to MCP_STATIC_SPAD_SIZE, since the real size includes another 64kb */
95 #define MCP_SPAD_SIZE 0x00028000 /* 160 KB */
97 #define SPAD_OFFSET(addr) (((u32)addr - (u32)CPU_SPAD_BASE))
98 #endif /* MDUMP_PARSE_TOOL */
100 #define TO_OFFSIZE(_offset, _size) \
101 (u32)((((u32)(_offset) >> 2) << OFFSIZE_OFFSET_SHIFT) | \
102 (((u32)(_size) >> 2) << OFFSIZE_SIZE_SHIFT))
106 SPAD_SECTION_NVM_CFG,
108 SPAD_SECTION_PRIVATE,
112 #ifndef MDUMP_PARSE_TOOL
114 struct nvm_cfg nvm_cfg;
115 struct mcp_public_data public_data;
116 #ifdef MFW /* Drivers will not be compiled with this flag. */
117 /* Linux should remove this appearance at all. */
118 struct mcp_private_data private_data;
122 #endif /* MDUMP_PARSE_TOOL */
124 #define MCP_TRACE_SIZE 2048 /* 2kb */
125 #define STRUCT_OFFSET(f) (STATIC_INIT_BASE + __builtin_offsetof(struct static_init, f))
127 /* This section is located at a fixed location in the beginning of the scratchpad,
128 * to ensure that the MCP trace is not run over during MFW upgrade.
129 * All the rest of data has a floating location which differs from version to version,
130 * and is pointed by the mcp_meta_data below.
131 * Moreover, the spad_layout section is part of the MFW firmware, and is loaded with it
132 * from nvram in order to clear this portion.
135 u32 num_sections; /* 0xe20000 */
136 offsize_t sections[SPAD_SECTION_MAX]; /* 0xe20004 */
137 #define SECTION(_sec_) *((offsize_t*)(STRUCT_OFFSET(sections[_sec_])))
139 struct mcp_trace trace; /* 0xe20014 */
140 #define MCP_TRACE_P ((struct mcp_trace*)(STRUCT_OFFSET(trace)))
141 u8 trace_buffer[MCP_TRACE_SIZE]; /* 0xe20030 */
142 #define MCP_TRACE_BUF ((u8*)(STRUCT_OFFSET(trace_buffer)))
143 /* running_mfw has the same definition as in nvm_map.h.
144 * This bit indicate both the running dir, and the running bundle.
145 * It is set once when the LIM is loaded.
147 u32 running_mfw; /* 0xe20830 */
148 #define RUNNING_MFW *((u32*)(STRUCT_OFFSET(running_mfw)))
149 u32 build_time; /* 0xe20834 */
150 #define MFW_BUILD_TIME *((u32*)(STRUCT_OFFSET(build_time)))
151 u32 reset_type; /* 0xe20838 */
152 #define RESET_TYPE *((u32*)(STRUCT_OFFSET(reset_type)))
153 u32 mfw_secure_mode; /* 0xe2083c */
154 #define MFW_SECURE_MODE *((u32*)(STRUCT_OFFSET(mfw_secure_mode)))
155 u16 pme_status_pf_bitmap; /* 0xe20840 */
156 #define PME_STATUS_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_status_pf_bitmap)))
157 u16 pme_enable_pf_bitmap;
158 #define PME_ENABLE_PF_BITMAP *((u16*)(STRUCT_OFFSET(pme_enable_pf_bitmap)))
159 u32 mim_nvm_addr; /* 0xe20844 */
160 u32 mim_start_addr; /* 0xe20848 */
161 u32 ah_pcie_link_params; /* 0xe20850 Stores PCIe link configuration at start, so they can be used later also for Hot-Reset, without the need to re-reading them from nvm cfg. */
162 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_MASK (0x000000ff)
163 #define AH_PCIE_LINK_PARAMS_LINK_SPEED_SHIFT (0)
164 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_MASK (0x0000ff00)
165 #define AH_PCIE_LINK_PARAMS_LINK_WIDTH_SHIFT (8)
166 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_MASK (0x00ff0000)
167 #define AH_PCIE_LINK_PARAMS_ASPM_MODE_SHIFT (16)
168 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_MASK (0xff000000)
169 #define AH_PCIE_LINK_PARAMS_ASPM_CAP_SHIFT (24)
170 #define AH_PCIE_LINK_PARAMS *((u32*)(STRUCT_OFFSET(ah_pcie_link_params)))
172 u32 flags; /* 0xe20850 */
173 #define M_GLOB_FLAGS *((u32*)(STRUCT_OFFSET(flags)))
174 #define FLAGS_VAUX_REQUIRED (1 << 0)
175 #define FLAGS_WAIT_AVS_READY (1 << 1)
176 #define FLAGS_FAILURE_ISSUED (1 << 2)
177 #define FLAGS_FAILURE_DETECTED (1 << 3)
178 #define FLAGS_VAUX (1 << 4)
179 #define FLAGS_PERST_ASSERT_OCCURED (1 << 5)
180 #define FLAGS_HOT_RESET_STEP2 (1 << 6)
181 #define FLAGS_MSIX_SYNC_ALLOWED (1 << 7)
182 #define FLAGS_PROGRAM_PCI_COMPLETED (1 << 8)
183 #define FLAGS_SMBUS_AUX_MODE (1 << 9)
184 #define FLAGS_PEND_SMBUS_VMAIN_TO_AUX (1 << 10)
185 #define FLAGS_NVM_CFG_EFUSE_FAILURE (1 << 11)
186 #define FLAGS_OS_DRV_LOADED (1 << 29)
187 #define FLAGS_OVER_TEMP_OCCUR (1 << 30)
188 #define FLAGS_FAN_FAIL_OCCUR (1 << 31)
189 u32 rsrv_persist[4]; /* Persist reserved for MFW upgrades */ /* 0xe20854 */
193 #ifndef MDUMP_PARSE_TOOL
194 #define NVM_CFG1(x) g_spad.nvm_cfg.cfg1.x
195 #define NVM_GLOB(x) NVM_CFG1(glob).x
196 #define NVM_GLOB_VAL(n, m, o) ((NVM_GLOB(n) & m) >> o)
197 #endif /* MDUMP_PARSE_TOOL */
199 #endif /* SPAD_LAYOUT_H */