sys/dev/qlxgbe/ql_hw.h

   1 /*
   2  * Copyright (c) 2013-2014 Qlogic Corporation
   3  * All rights reserved.
   4  *
   5  *  Redistribution and use in source and binary forms, with or without
   6  *  modification, are permitted provided that the following conditions
   7  *  are met:
   8  *
   9  *  1. Redistributions of source code must retain the above copyright
  10  *     notice, this list of conditions and the following disclaimer.
  11  *  2. Redistributions in binary form must reproduce the above copyright
  12  *     notice, this list of conditions and the following disclaimer in the
  13  *     documentation and/or other materials provided with the distribution.
  14  *
  15  *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  16  *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  17  *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  18  *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  19  *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  20  *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  21  *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  22  *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  23  *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  24  *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  25  *  POSSIBILITY OF SUCH DAMAGE.
  26  *
  27  * $FreeBSD$
  28  */
  29 /*
  30  * File: ql_hw.h
  31  * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
  32  */
  33 #ifndef _QL_HW_H_
  34 #define _QL_HW_H_
  35
  36 /*
  37  * PCIe Registers; Direct Mapped; Offsets from BAR0
  38  */
  39
  40 /*
  41  * Register offsets for QLE8030
  42  */
  43
  44 /*
  45  * Firmware Mailbox Registers
  46  *      0 thru 511; offsets 0x800 thru 0xFFC; 32bits each
  47  */
  48 #define Q8_FW_MBOX0                     0x00000800
  49 #define Q8_FW_MBOX511                   0x00000FFC
  50
  51 /*
  52  * Host Mailbox Registers
  53  *      0 thru 511; offsets 0x000 thru 0x7FC; 32bits each
  54  */
  55 #define Q8_HOST_MBOX0                   0x00000000
  56 #define Q8_HOST_MBOX511                 0x000007FC
  57
  58 #define Q8_MBOX_INT_ENABLE              0x00001000
  59 #define Q8_MBOX_INT_MASK_MSIX           0x00001200
  60 #define Q8_MBOX_INT_LEGACY              0x00003010
  61
  62 #define Q8_HOST_MBOX_CNTRL              0x00003038
  63 #define Q8_FW_MBOX_CNTRL                0x0000303C
  64
  65 #define Q8_PEG_HALT_STATUS1             0x000034A8
  66 #define Q8_PEG_HALT_STATUS2             0x000034AC
  67 #define Q8_FIRMWARE_HEARTBEAT           0x000034B0
  68
  69 #define Q8_FLASH_LOCK_ID                0x00003500
  70 #define Q8_DRIVER_LOCK_ID               0x00003504
  71 #define Q8_FW_CAPABILITIES              0x00003528
  72
  73 #define Q8_FW_VER_MAJOR                 0x00003550
  74 #define Q8_FW_VER_MINOR                 0x00003554
  75 #define Q8_FW_VER_SUB                   0x00003558
  76
  77 #define Q8_BOOTLD_ADDR                  0x0000355C
  78 #define Q8_BOOTLD_SIZE                  0x00003560
  79
  80 #define Q8_FW_IMAGE_ADDR                0x00003564
  81 #define Q8_FW_BUILD_NUMBER              0x00003568
  82 #define Q8_FW_IMAGE_VALID               0x000035FC
  83
  84 #define Q8_CMDPEG_STATE                 0x00003650
  85
  86 #define Q8_LINK_STATE                   0x00003698
  87 #define Q8_LINK_STATE_2                 0x0000369C
  88
  89 #define Q8_LINK_SPEED_0                 0x000036E0
  90 #define Q8_LINK_SPEED_1                 0x000036E4
  91 #define Q8_LINK_SPEED_2                 0x000036E8
  92 #define Q8_LINK_SPEED_3                 0x000036EC
  93
  94 #define Q8_MAX_LINK_SPEED_0             0x000036F0
  95 #define Q8_MAX_LINK_SPEED_1             0x000036F4
  96 #define Q8_MAX_LINK_SPEED_2             0x000036F8
  97 #define Q8_MAX_LINK_SPEED_3             0x000036FC
  98
  99 #define Q8_ASIC_TEMPERATURE             0x000037B4
 100
 101 /*
 102  * CRB Window Registers
 103  *      0 thru 15; offsets 0x3800 thru 0x383C; 32bits each
 104  */
 105 #define Q8_CRB_WINDOW_PF0               0x00003800
 106 #define Q8_CRB_WINDOW_PF15              0x0000383C
 107
 108 #define Q8_FLASH_LOCK                   0x00003850
 109 #define Q8_FLASH_UNLOCK                 0x00003854
 110
 111 #define Q8_DRIVER_LOCK                  0x00003868
 112 #define Q8_DRIVER_UNLOCK                0x0000386C
 113
 114 #define Q8_LEGACY_INT_PTR               0x000038C0
 115 #define Q8_LEGACY_INT_TRIG              0x000038C4
 116 #define Q8_LEGACY_INT_MASK              0x000038C8
 117
 118 #define Q8_WILD_CARD                    0x000038F0
 119 #define Q8_INFORMANT                    0x000038FC
 120
 121 /*
 122  * Ethernet Interface Specific Registers
 123  */
 124 #define Q8_DRIVER_OP_MODE               0x00003570
 125 #define Q8_API_VERSION                  0x0000356C
 126 #define Q8_NPAR_STATE                   0x0000359C
 127
 128 /*
 129  * End of PCIe Registers; Direct Mapped; Offsets from BAR0
 130  */
 131
 132 /*
 133  * Indirect Registers
 134  */
 135 #define Q8_LED_DUAL_0                   0x28084C80
 136 #define Q8_LED_SINGLE_0                 0x28084C90
 137
 138 #define Q8_LED_DUAL_1                   0x28084CA0
 139 #define Q8_LED_SINGLE_1                 0x28084CB0
 140
 141 #define Q8_LED_DUAL_2                   0x28084CC0
 142 #define Q8_LED_SINGLE_2                 0x28084CD0
 143
 144 #define Q8_LED_DUAL_3                   0x28084CE0
 145 #define Q8_LED_SINGLE_3                 0x28084CF0
 146
 147 #define Q8_GPIO_1                       0x28084D00
 148 #define Q8_GPIO_2                       0x28084D10
 149 #define Q8_GPIO_3                       0x28084D20
 150 #define Q8_GPIO_4                       0x28084D40
 151 #define Q8_GPIO_5                       0x28084D50
 152 #define Q8_GPIO_6                       0x28084D60
 153 #define Q8_GPIO_7                       0x42100060
 154 #define Q8_GPIO_8                       0x42100064
 155
 156 #define Q8_FLASH_SPI_STATUS             0x2808E010
 157 #define Q8_FLASH_SPI_CONTROL            0x2808E014
 158
 159 #define Q8_FLASH_STATUS                 0x42100004
 160 #define Q8_FLASH_CONTROL                0x42110004
 161 #define Q8_FLASH_ADDRESS                0x42110008
 162 #define Q8_FLASH_WR_DATA                0x4211000C
 163 #define Q8_FLASH_RD_DATA                0x42110018
 164
 165 #define Q8_FLASH_DIRECT_WINDOW          0x42110030
 166 #define Q8_FLASH_DIRECT_DATA            0x42150000
 167
 168 #define Q8_MS_CNTRL                     0x41000090
 169
 170 #define Q8_MS_ADDR_LO                   0x41000094
 171 #define Q8_MS_ADDR_HI                   0x41000098
 172
 173 #define Q8_MS_WR_DATA_0_31              0x410000A0
 174 #define Q8_MS_WR_DATA_32_63             0x410000A4
 175 #define Q8_MS_WR_DATA_64_95             0x410000B0
 176 #define Q8_MS_WR_DATA_96_127            0x410000B4
 177
 178 #define Q8_MS_RD_DATA_0_31              0x410000A8
 179 #define Q8_MS_RD_DATA_32_63             0x410000AC
 180 #define Q8_MS_RD_DATA_64_95             0x410000B8
 181 #define Q8_MS_RD_DATA_96_127            0x410000BC
 182
 183 #define Q8_CRB_PEG_0                    0x3400003c
 184 #define Q8_CRB_PEG_1                    0x3410003c
 185 #define Q8_CRB_PEG_2                    0x3420003c
 186 #define Q8_CRB_PEG_3                    0x3430003c
 187 #define Q8_CRB_PEG_4                    0x34B0003c
 188
 189 /*
 190  * Macros for reading and writing registers
 191  */
 192
 193 #if defined(__i386__) || defined(__amd64__)
 194 #define Q8_MB()    __asm volatile("mfence" ::: "memory")
 195 #define Q8_WMB()   __asm volatile("sfence" ::: "memory")
 196 #define Q8_RMB()   __asm volatile("lfence" ::: "memory")
 197 #else
 198 #define Q8_MB()
 199 #define Q8_WMB()
 200 #define Q8_RMB()
 201 #endif
 202
 203 #define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg)
 204
 205 #define WRITE_REG32(ha, reg, val) \
 206         {\
 207                 bus_write_4((ha->pci_reg), reg, val);\
 208                 bus_read_4((ha->pci_reg), reg);\
 209         }
 210
 211 #define Q8_NUM_MBOX     512
 212
 213 #define Q8_MAX_NUM_MULTICAST_ADDRS      1023
 214 #define Q8_MAC_ADDR_LEN                 6
 215
 216 /*
 217  * Firmware Interface
 218  */
 219
 220 /*
 221  * Command Response Interface - Commands
 222  */
 223
 224 #define Q8_MBX_CONFIG_IP_ADDRESS                0x0001
 225 #define Q8_MBX_CONFIG_INTR                      0x0002
 226 #define Q8_MBX_MAP_INTR_SRC                     0x0003
 227 #define Q8_MBX_MAP_SDS_TO_RDS                   0x0006
 228 #define Q8_MBX_CREATE_RX_CNTXT                  0x0007
 229 #define Q8_MBX_DESTROY_RX_CNTXT                 0x0008
 230 #define Q8_MBX_CREATE_TX_CNTXT                  0x0009
 231 #define Q8_MBX_DESTROY_TX_CNTXT                 0x000A
 232 #define Q8_MBX_ADD_RX_RINGS                     0x000B
 233 #define Q8_MBX_CONFIG_LRO_FLOW                  0x000C
 234 #define Q8_MBX_CONFIG_MAC_LEARNING              0x000D
 235 #define Q8_MBX_GET_STATS                        0x000F
 236 #define Q8_MBX_GENERATE_INTR                    0x0011
 237 #define Q8_MBX_SET_MAX_MTU                      0x0012
 238 #define Q8_MBX_MAC_ADDR_CNTRL                   0x001F
 239 #define Q8_MBX_GET_PCI_CONFIG                   0x0020
 240 #define Q8_MBX_GET_NIC_PARTITION                0x0021
 241 #define Q8_MBX_SET_NIC_PARTITION                0x0022
 242 #define Q8_MBX_QUERY_WOL_CAP                    0x002C
 243 #define Q8_MBX_SET_WOL_CONFIG                   0x002D
 244 #define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE          0x002F
 245 #define Q8_MBX_GET_MINIDUMP_TMPLT               0x0030
 246 #define Q8_MBX_GET_FW_DCBX_CAPS                 0x0034
 247 #define Q8_MBX_QUERY_DCBX_SETTINGS              0x0035
 248 #define Q8_MBX_CONFIG_RSS                       0x0041
 249 #define Q8_MBX_CONFIG_RSS_TABLE                 0x0042
 250 #define Q8_MBX_CONFIG_INTR_COALESCE             0x0043
 251 #define Q8_MBX_CONFIG_LED                       0x0044
 252 #define Q8_MBX_CONFIG_MAC_ADDR                  0x0045
 253 #define Q8_MBX_CONFIG_STATISTICS                0x0046
 254 #define Q8_MBX_CONFIG_LOOPBACK                  0x0047
 255 #define Q8_MBX_LINK_EVENT_REQ                   0x0048
 256 #define Q8_MBX_CONFIG_MAC_RX_MODE               0x0049
 257 #define Q8_MBX_CONFIG_FW_LRO                    0x004A
 258 #define Q8_MBX_INIT_NIC_FUNC                    0x0060
 259 #define Q8_MBX_STOP_NIC_FUNC                    0x0061
 260 #define Q8_MBX_SET_PORT_CONFIG                  0x0066
 261 #define Q8_MBX_GET_PORT_CONFIG                  0x0067
 262 #define Q8_MBX_GET_LINK_STATUS                  0x0068
 263
 264
 265
 266 /*
 267  * Mailbox Command Response
 268  */
 269 #define Q8_MBX_RSP_SUCCESS                      0x0001
 270 #define Q8_MBX_RSP_RESPONSE_FAILURE             0x0002
 271 #define Q8_MBX_RSP_NO_CARD_CRB                  0x0003
 272 #define Q8_MBX_RSP_NO_CARD_MEM                  0x0004
 273 #define Q8_MBX_RSP_NO_CARD_RSRC                 0x0005
 274 #define Q8_MBX_RSP_INVALID_ARGS                 0x0006
 275 #define Q8_MBX_RSP_INVALID_ACTION               0x0007
 276 #define Q8_MBX_RSP_INVALID_STATE                0x0008
 277 #define Q8_MBX_RSP_NOT_SUPPORTED                0x0009
 278 #define Q8_MBX_RSP_NOT_PERMITTED                0x000A
 279 #define Q8_MBX_RSP_NOT_READY                    0x000B
 280 #define Q8_MBX_RSP_DOES_NOT_EXIST               0x000C
 281 #define Q8_MBX_RSP_ALREADY_EXISTS               0x000D
 282 #define Q8_MBX_RSP_BAD_SIGNATURE                0x000E
 283 #define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED          0x000F
 284 #define Q8_MBX_RSP_CMD_INVALID                  0x0010
 285 #define Q8_MBX_RSP_TIMEOUT                      0x0011
 286 #define Q8_MBX_RSP_CMD_FAILED                   0x0012
 287 #define Q8_MBX_RSP_FATAL_TEMP                   0x0013
 288 #define Q8_MBX_RSP_MAX_EXCEEDED                 0x0014
 289 #define Q8_MBX_RSP_UNSPECIFIED                  0x0015
 290 #define Q8_MBX_RSP_INTR_CREATE_FAILED           0x0017
 291 #define Q8_MBX_RSP_INTR_DELETE_FAILED           0x0018
 292 #define Q8_MBX_RSP_INTR_INVALID_OP              0x0019
 293 #define Q8_MBX_RSP_IDC_INTRMD_RSP               0x001A
 294
 295 #define Q8_MBX_CMD_VERSION      (0x2 << 13)
 296 #define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9))
 297 /*
 298  * Configure IP Address
 299  */
 300 typedef struct _q80_config_ip_addr {
 301         uint16_t        opcode;
 302         uint16_t        count_version;
 303
 304         uint8_t         cmd;
 305 #define         Q8_MBX_CONFIG_IP_ADD_IP 0x1
 306 #define         Q8_MBX_CONFIG_IP_DEL_IP 0x2
 307
 308         uint8_t         ip_type;
 309 #define         Q8_MBX_CONFIG_IP_V4     0x0
 310 #define         Q8_MBX_CONFIG_IP_V6     0x1
 311
 312         uint16_t        rsrvd;
 313         union {
 314                 struct {
 315                         uint32_t addr;
 316                         uint32_t rsrvd[3];
 317                 } ipv4;
 318                 uint8_t ipv6_addr[16];
 319         } u;
 320 } __packed q80_config_ip_addr_t;
 321
 322 typedef struct _q80_config_ip_addr_rsp {
 323         uint16_t        opcode;
 324         uint16_t        regcnt_status;
 325 } __packed q80_config_ip_addr_rsp_t;
 326
 327 /*
 328  * Configure Interrupt Command
 329  */
 330 typedef struct _q80_intr {
 331         uint8_t         cmd_type;
 332 #define         Q8_MBX_CONFIG_INTR_CREATE       0x1
 333 #define         Q8_MBX_CONFIG_INTR_DELETE       0x2
 334 #define         Q8_MBX_CONFIG_INTR_TYPE_LINE    (0x1 << 4)
 335 #define         Q8_MBX_CONFIG_INTR_TYPE_MSI_X   (0x3 << 4)
 336
 337         uint8_t         rsrvd;
 338         uint16_t        msix_index;
 339 } __packed q80_intr_t;
 340
 341 #define Q8_MAX_INTR_VECTORS     16
 342 typedef struct _q80_config_intr {
 343         uint16_t        opcode;
 344         uint16_t        count_version;
 345         uint8_t         nentries;
 346         uint8_t         rsrvd[3];
 347         q80_intr_t      intr[Q8_MAX_INTR_VECTORS];
 348 } __packed q80_config_intr_t;
 349
 350 typedef struct _q80_intr_rsp {
 351         uint8_t         status;
 352         uint8_t         cmd;
 353         uint16_t        intr_id;
 354         uint32_t        intr_src;
 355 } q80_intr_rsp_t;
 356
 357 typedef struct _q80_config_intr_rsp {
 358         uint16_t        opcode;
 359         uint16_t        regcnt_status;
 360         uint8_t         nentries;
 361         uint8_t         rsrvd[3];
 362         q80_intr_rsp_t  intr[Q8_MAX_INTR_VECTORS];
 363 } __packed q80_config_intr_rsp_t;
 364
 365 /*
 366  * Configure LRO Flow Command
 367  */
 368 typedef struct _q80_config_lro_flow {
 369         uint16_t        opcode;
 370         uint16_t        count_version;
 371
 372         uint8_t         cmd;
 373 #define Q8_MBX_CONFIG_LRO_FLOW_ADD      0x01
 374 #define Q8_MBX_CONFIG_LRO_FLOW_DELETE   0x02
 375
 376         uint8_t         type_ts;
 377 #define Q8_MBX_CONFIG_LRO_FLOW_IPV4             0x00
 378 #define Q8_MBX_CONFIG_LRO_FLOW_IPV6             0x01
 379 #define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT        0x00
 380 #define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT       0x02
 381
 382         uint16_t        rsrvd;
 383         union {
 384                 struct {
 385                         uint32_t addr;
 386                         uint32_t rsrvd[3];
 387                 } ipv4;
 388                 uint8_t ipv6_addr[16];
 389         } dst;
 390         union {
 391                 struct {
 392                         uint32_t addr;
 393                         uint32_t rsrvd[3];
 394                 } ipv4;
 395                 uint8_t ipv6_addr[16];
 396         } src;
 397         uint16_t        dst_port;
 398         uint16_t        src_port;
 399 } __packed q80_config_lro_flow_t;
 400
 401 typedef struct _q80_config_lro_flow_rsp {
 402         uint16_t        opcode;
 403         uint16_t        regcnt_status;
 404 } __packed q80_config_lro_flow_rsp_t;
 405
 406 typedef struct _q80_set_max_mtu {
 407         uint16_t        opcode;
 408         uint16_t        count_version;
 409         uint32_t        cntxt_id;
 410         uint32_t        mtu;
 411 } __packed q80_set_max_mtu_t;
 412
 413 typedef struct _q80_set_max_mtu_rsp {
 414         uint16_t        opcode;
 415         uint16_t        regcnt_status;
 416 } __packed q80_set_max_mtu_rsp_t;
 417
 418 /*
 419  * Configure RSS
 420  */
 421 typedef struct _q80_config_rss {
 422         uint16_t        opcode;
 423         uint16_t        count_version;
 424
 425         uint16_t        cntxt_id;
 426         uint16_t        rsrvd;
 427
 428         uint8_t         hash_type;
 429 #define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP        (0x3 << 4)
 430 #define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP        (0x3 << 6)
 431
 432         uint8_t         flags;
 433 #define Q8_MBX_RSS_FLAGS_ENABLE_RSS             (0x1)
 434 #define Q8_MBX_RSS_FLAGS_USE_IND_TABLE          (0x2)
 435 #define Q8_MBX_RSS_FLAGS_TYPE_CRSS              (0x4)
 436
 437         uint16_t        indtbl_mask;
 438 #define Q8_MBX_RSS_INDTBL_MASK                  0x7F
 439 #define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID        0x8000
 440
 441         uint32_t        multi_rss;
 442 #define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN      BIT_30
 443 #define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES        BIT_31
 444
 445         uint64_t        rss_key[5];
 446 } __packed q80_config_rss_t;
 447
 448 typedef struct _q80_config_rss_rsp {
 449         uint16_t        opcode;
 450         uint16_t        regcnt_status;
 451 } __packed q80_config_rss_rsp_t;
 452
 453 /*
 454  * Configure RSS Indirection Table
 455  */
 456 #define Q8_RSS_IND_TBL_SIZE     40
 457 #define Q8_RSS_IND_TBL_MIN_IDX  0
 458 #define Q8_RSS_IND_TBL_MAX_IDX  127
 459
 460 typedef struct _q80_config_rss_ind_table {
 461         uint16_t        opcode;
 462         uint16_t        count_version;
 463         uint8_t         start_idx;
 464         uint8_t         end_idx;
 465         uint16_t        cntxt_id;
 466         uint8_t         ind_table[40];
 467 } __packed q80_config_rss_ind_table_t;
 468
 469 typedef struct _q80_config_rss_ind_table_rsp {
 470         uint16_t        opcode;
 471         uint16_t        regcnt_status;
 472 } __packed q80_config_rss_ind_table_rsp_t;
 473
 474 /*
 475  * Configure Interrupt Coalescing and Generation
 476  */
 477 typedef struct _q80_config_intr_coalesc {
 478         uint16_t        opcode;
 479         uint16_t        count_version;
 480         uint16_t        flags;
 481 #define Q8_MBX_INTRC_FLAGS_RCV          1
 482 #define Q8_MBX_INTRC_FLAGS_XMT          2
 483 #define Q8_MBX_INTRC_FLAGS_PERIODIC     (1 << 3)
 484
 485         uint16_t        cntxt_id;
 486         uint16_t        max_pkts;
 487         uint16_t        max_mswait;
 488         uint8_t         timer_type;
 489 #define Q8_MBX_INTRC_TIMER_NONE                 0
 490 #define Q8_MBX_INTRC_TIMER_SINGLE               1
 491 #define Q8_MBX_INTRC_TIMER_PERIODIC             2
 492
 493         uint16_t        sds_ring_mask;
 494
 495         uint8_t         rsrvd;
 496         uint32_t        ms_timeout;
 497 } __packed q80_config_intr_coalesc_t;
 498
 499 typedef struct _q80_config_intr_coalesc_rsp {
 500         uint16_t        opcode;
 501         uint16_t        regcnt_status;
 502 } __packed q80_config_intr_coalesc_rsp_t;
 503
 504 /*
 505  * Configure MAC Address
 506  */
 507 typedef struct _q80_mac_addr {
 508         uint8_t         addr[6];
 509         uint16_t        vlan_tci;
 510 } __packed q80_mac_addr_t;
 511
 512 #define Q8_MAX_MAC_ADDRS        64
 513
 514 typedef struct _q80_config_mac_addr {
 515         uint16_t        opcode;
 516         uint16_t        count_version;
 517         uint8_t         cmd;
 518 #define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR    1
 519 #define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR    2
 520
 521 #define Q8_MBX_CMAC_CMD_CAM_BOTH        (0x0 << 6)
 522 #define Q8_MBX_CMAC_CMD_CAM_INGRESS     (0x1 << 6)
 523 #define Q8_MBX_CMAC_CMD_CAM_EGRESS      (0x2 << 6)
 524
 525         uint8_t         nmac_entries;
 526         uint16_t        cntxt_id;
 527         q80_mac_addr_t  mac_addr[Q8_MAX_MAC_ADDRS];
 528 } __packed q80_config_mac_addr_t;
 529
 530 typedef struct _q80_config_mac_addr_rsp {
 531         uint16_t        opcode;
 532         uint16_t        regcnt_status;
 533         uint8_t         cmd;
 534         uint8_t         nmac_entries;
 535         uint16_t        cntxt_id;
 536         uint32_t        status[Q8_MAX_MAC_ADDRS];
 537 } __packed q80_config_mac_addr_rsp_t;
 538
 539 /*
 540  * Configure MAC Receive Mode
 541  */
 542 typedef struct _q80_config_mac_rcv_mode {
 543         uint16_t        opcode;
 544         uint16_t        count_version;
 545
 546         uint8_t         mode;
 547 #define Q8_MBX_MAC_RCV_PROMISC_ENABLE   0x1
 548 #define Q8_MBX_MAC_ALL_MULTI_ENABLE     0x2
 549
 550         uint8_t         rsrvd;
 551         uint16_t        cntxt_id;
 552 } __packed q80_config_mac_rcv_mode_t;
 553
 554 typedef struct _q80_config_mac_rcv_mode_rsp {
 555         uint16_t        opcode;
 556         uint16_t        regcnt_status;
 557 } __packed q80_config_mac_rcv_mode_rsp_t;
 558
 559 /*
 560  * Configure Firmware Controlled LRO
 561  */
 562 typedef struct _q80_config_fw_lro {
 563         uint16_t        opcode;
 564         uint16_t        count_version;
 565
 566         uint8_t         flags;
 567 #define Q8_MBX_FW_LRO_IPV4                     0x1
 568 #define Q8_MBX_FW_LRO_IPV6                     0x2
 569 #define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK       0x4
 570 #define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK       0x8
 571
 572         uint8_t         rsrvd;
 573         uint16_t        cntxt_id;
 574 } __packed q80_config_fw_lro_t;
 575
 576 typedef struct _q80_config_fw_lro_rsp {
 577         uint16_t        opcode;
 578         uint16_t        regcnt_status;
 579 } __packed q80_config_fw_lro_rsp_t;
 580
 581 /*
 582  * Minidump mailbox commands
 583  */
 584 typedef struct _q80_config_md_templ_size {
 585         uint16_t        opcode;
 586         uint16_t        count_version;
 587 } __packed q80_config_md_templ_size_t;
 588
 589 typedef struct _q80_config_md_templ_size_rsp {
 590         uint16_t        opcode;
 591         uint16_t        regcnt_status;
 592         uint32_t        rsrvd;
 593         uint32_t        templ_size;
 594         uint32_t        templ_version;
 595 } __packed q80_config_md_templ_size_rsp_t;
 596
 597 typedef struct _q80_config_md_templ_cmd {
 598         uint16_t        opcode;
 599         uint16_t        count_version;
 600         uint64_t        buf_addr; /* physical address of buffer */
 601         uint32_t        buff_size;
 602         uint32_t        offset;
 603 } __packed q80_config_md_templ_cmd_t;
 604
 605 typedef struct _q80_config_md_templ_cmd_rsp {
 606         uint16_t        opcode;
 607         uint16_t        regcnt_status;
 608         uint32_t        rsrvd;
 609         uint32_t        templ_size;
 610         uint32_t        buff_size;
 611         uint32_t        offset;
 612 } __packed q80_config_md_templ_cmd_rsp_t;
 613
 614 /*
 615  * Link Event Request Command
 616  */
 617 typedef struct _q80_link_event {
 618         uint16_t        opcode;
 619         uint16_t        count_version;
 620         uint8_t         cmd;
 621 #define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0
 622 #define Q8_LINK_EVENT_CMD_ENABLE_ASYNC  1
 623
 624         uint8_t         flags;
 625 #define Q8_LINK_EVENT_FLAGS_SEND_RSP    1
 626
 627         uint16_t        cntxt_id;
 628 } __packed q80_link_event_t;
 629
 630 typedef struct _q80_link_event_rsp {
 631         uint16_t        opcode;
 632         uint16_t        regcnt_status;
 633 } __packed q80_link_event_rsp_t;
 634
 635 /*
 636  * Get Statistics Command
 637  */
 638 typedef struct _q80_rcv_stats {
 639         uint64_t        total_bytes;
 640         uint64_t        total_pkts;
 641         uint64_t        lro_pkt_count;
 642         uint64_t        sw_pkt_count;
 643         uint64_t        ip_chksum_err;
 644         uint64_t        pkts_wo_acntxts;
 645         uint64_t        pkts_dropped_no_sds_card;
 646         uint64_t        pkts_dropped_no_sds_host;
 647         uint64_t        oversized_pkts;
 648         uint64_t        pkts_dropped_no_rds;
 649         uint64_t        unxpctd_mcast_pkts;
 650         uint64_t        re1_fbq_error;
 651         uint64_t        invalid_mac_addr;
 652         uint64_t        rds_prime_trys;
 653         uint64_t        rds_prime_success;
 654         uint64_t        lro_flows_added;
 655         uint64_t        lro_flows_deleted;
 656         uint64_t        lro_flows_active;
 657         uint64_t        pkts_droped_unknown;
 658 } __packed q80_rcv_stats_t;
 659
 660 typedef struct _q80_xmt_stats {
 661         uint64_t        total_bytes;
 662         uint64_t        total_pkts;
 663         uint64_t        errors;
 664         uint64_t        pkts_dropped;
 665         uint64_t        switch_pkts;
 666         uint64_t        num_buffers;
 667 } __packed q80_xmt_stats_t;
 668
 669 typedef struct _q80_mac_stats {
 670         uint64_t        xmt_frames;
 671         uint64_t        xmt_bytes;
 672         uint64_t        xmt_mcast_pkts;
 673         uint64_t        xmt_bcast_pkts;
 674         uint64_t        xmt_pause_frames;
 675         uint64_t        xmt_cntrl_pkts;
 676         uint64_t        xmt_pkt_lt_64bytes;
 677         uint64_t        xmt_pkt_lt_127bytes;
 678         uint64_t        xmt_pkt_lt_255bytes;
 679         uint64_t        xmt_pkt_lt_511bytes;
 680         uint64_t        xmt_pkt_lt_1023bytes;
 681         uint64_t        xmt_pkt_lt_1518bytes;
 682         uint64_t        xmt_pkt_gt_1518bytes;
 683         uint64_t        rsrvd0[3];
 684         uint64_t        rcv_frames;
 685         uint64_t        rcv_bytes;
 686         uint64_t        rcv_mcast_pkts;
 687         uint64_t        rcv_bcast_pkts;
 688         uint64_t        rcv_pause_frames;
 689         uint64_t        rcv_cntrl_pkts;
 690         uint64_t        rcv_pkt_lt_64bytes;
 691         uint64_t        rcv_pkt_lt_127bytes;
 692         uint64_t        rcv_pkt_lt_255bytes;
 693         uint64_t        rcv_pkt_lt_511bytes;
 694         uint64_t        rcv_pkt_lt_1023bytes;
 695         uint64_t        rcv_pkt_lt_1518bytes;
 696         uint64_t        rcv_pkt_gt_1518bytes;
 697         uint64_t        rsrvd1[3];
 698         uint64_t        rcv_len_error;
 699         uint64_t        rcv_len_small;
 700         uint64_t        rcv_len_large;
 701         uint64_t        rcv_jabber;
 702         uint64_t        rcv_dropped;
 703         uint64_t        fcs_error;
 704         uint64_t        align_error;
 705 } __packed q80_mac_stats_t;
 706
 707 typedef struct _q80_get_stats {
 708         uint16_t        opcode;
 709         uint16_t        count_version;
 710
 711         uint32_t        cmd;
 712 #define Q8_GET_STATS_CMD_CLEAR          0x01
 713 #define Q8_GET_STATS_CMD_RCV            0x00
 714 #define Q8_GET_STATS_CMD_XMT            0x02
 715 #define Q8_GET_STATS_CMD_TYPE_CNTXT     0x00
 716 #define Q8_GET_STATS_CMD_TYPE_MAC       0x04
 717 #define Q8_GET_STATS_CMD_TYPE_FUNC      0x08
 718 #define Q8_GET_STATS_CMD_TYPE_VPORT     0x0C
 719
 720 } __packed q80_get_stats_t;
 721
 722 typedef struct _q80_get_stats_rsp {
 723         uint16_t        opcode;
 724         uint16_t        regcnt_status;
 725         uint32_t        cmd;
 726         union {
 727                 q80_rcv_stats_t rcv;
 728                 q80_xmt_stats_t xmt;
 729                 q80_mac_stats_t mac;
 730         } u;
 731 } __packed q80_get_stats_rsp_t;
 732
 733 /*
 734  * Init NIC Function
 735  * Used to Register DCBX Configuration Change AEN
 736  */
 737 typedef struct _q80_init_nic_func {
 738         uint16_t        opcode;
 739         uint16_t        count_version;
 740
 741         uint32_t        options;
 742 #define Q8_INIT_NIC_REG_DCBX_CHNG_AEN   0x02
 743 #define Q8_INIT_NIC_REG_SFP_CHNG_AEN    0x04
 744
 745 } __packed q80_init_nic_func_t;
 746
 747 typedef struct _q80_init_nic_func_rsp {
 748         uint16_t        opcode;
 749         uint16_t        regcnt_status;
 750 } __packed q80_init_nic_func_rsp_t;
 751
 752 /*
 753  * Stop NIC Function
 754  * Used to DeRegister DCBX Configuration Change AEN
 755  */
 756 typedef struct _q80_stop_nic_func {
 757         uint16_t        opcode;
 758         uint16_t        count_version;
 759
 760         uint32_t        options;
 761 #define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02
 762 #define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN  0x04
 763
 764 } __packed q80_stop_nic_func_t;
 765
 766 typedef struct _q80_stop_nic_func_rsp {
 767         uint16_t        opcode;
 768         uint16_t        regcnt_status;
 769 } __packed q80_stop_nic_func_rsp_t;
 770
 771 /*
 772  * Query Firmware DCBX Capabilities
 773  */
 774 typedef struct _q80_query_fw_dcbx_caps {
 775         uint16_t        opcode;
 776         uint16_t        count_version;
 777 } __packed q80_query_fw_dcbx_caps_t;
 778
 779 typedef struct _q80_query_fw_dcbx_caps_rsp {
 780         uint16_t        opcode;
 781         uint16_t        regcnt_status;
 782
 783         uint32_t        dcbx_caps;
 784 #define Q8_QUERY_FW_DCBX_CAPS_TSA               0x00000001
 785 #define Q8_QUERY_FW_DCBX_CAPS_ETS               0x00000002
 786 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01     0x00000004
 787 #define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0     0x00000008
 788 #define Q8_QUERY_FW_DCBX_MAX_TC_MASK            0x00F00000
 789 #define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK        0x0F000000
 790 #define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK        0xF0000000
 791
 792 } __packed q80_query_fw_dcbx_caps_rsp_t;
 793
 794 /*
 795  * Set Port Configuration command
 796  * Used to set Ethernet Standard Pause values
 797  */
 798
 799 typedef struct _q80_set_port_cfg {
 800         uint16_t        opcode;
 801         uint16_t        count_version;
 802
 803         uint32_t        cfg_bits;
 804
 805 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK     (0x7 << 1)
 806 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE     (0x0 << 1)
 807 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS      (0x2 << 1)
 808 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY      (0x3 << 1)
 809 #define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT      (0x4 << 1)
 810
 811 #define Q8_VALID_LOOPBACK_MODE(mode) \
 812              (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \
 813                 (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \
 814                  ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT)))
 815
 816 #define Q8_PORT_CFG_BITS_DCBX_ENABLE            BIT_4
 817
 818 #define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK         (0x3 << 5)
 819 #define Q8_PORT_CFG_BITS_PAUSE_DISABLED         (0x0 << 5)
 820 #define Q8_PORT_CFG_BITS_PAUSE_STD              (0x1 << 5)
 821 #define Q8_PORT_CFG_BITS_PAUSE_PPM              (0x2 << 5)
 822
 823 #define Q8_PORT_CFG_BITS_LNKCAP_10MB            BIT_8
 824 #define Q8_PORT_CFG_BITS_LNKCAP_100MB           BIT_9
 825 #define Q8_PORT_CFG_BITS_LNKCAP_1GB             BIT_10
 826 #define Q8_PORT_CFG_BITS_LNKCAP_10GB            BIT_11
 827
 828 #define Q8_PORT_CFG_BITS_AUTONEG                BIT_15
 829 #define Q8_PORT_CFG_BITS_XMT_DISABLE            BIT_17
 830 #define Q8_PORT_CFG_BITS_FEC_RQSTD              BIT_18
 831 #define Q8_PORT_CFG_BITS_EEE_RQSTD              BIT_19
 832
 833 #define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK      (0x3 << 20)
 834 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV       (0x0 << 20)
 835 #define Q8_PORT_CFG_BITS_STDPAUSE_XMT           (0x1 << 20)
 836 #define Q8_PORT_CFG_BITS_STDPAUSE_RCV           (0x2 << 20)
 837
 838 } __packed q80_set_port_cfg_t;
 839
 840 typedef struct _q80_set_port_cfg_rsp {
 841         uint16_t        opcode;
 842         uint16_t        regcnt_status;
 843 } __packed q80_set_port_cfg_rsp_t;
 844
 845 /*
 846  * Get Port Configuration Command
 847  */
 848
 849 typedef struct _q80_get_port_cfg {
 850         uint16_t        opcode;
 851         uint16_t        count_version;
 852 } __packed q80_get_port_cfg_t;
 853
 854 typedef struct _q80_get_port_cfg_rsp {
 855         uint16_t        opcode;
 856         uint16_t        regcnt_status;
 857
 858         uint32_t        cfg_bits; /* same as in q80_set_port_cfg_t */
 859
 860         uint8_t         phys_port_type;
 861         uint8_t         rsvd[3];
 862 } __packed q80_get_port_cfg_rsp_t;
 863
 864 /*
 865  * Get Link Status Command
 866  * Used to get current PAUSE values for the port
 867  */
 868
 869 typedef struct _q80_get_link_status {
 870         uint16_t        opcode;
 871         uint16_t        count_version;
 872 } __packed q80_get_link_status_t;
 873
 874 typedef struct _q80_get_link_status_rsp {
 875         uint16_t        opcode;
 876         uint16_t        regcnt_status;
 877
 878         uint32_t        cfg_bits;
 879 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP               BIT_0
 880
 881 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK       (0x7 << 3)
 882 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN    (0x0 << 3)
 883 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB       (0x1 << 3)
 884 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB      (0x2 << 3)
 885 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB        (0x3 << 3)
 886 #define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB       (0x4 << 3)
 887
 888 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK        (0x3 << 6)
 889 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE     (0x0 << 6)
 890 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD         (0x1 << 6)
 891 #define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM         (0x2 << 6)
 892
 893 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK         (0x7 << 8)
 894 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE         (0x0 << 6)
 895 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS          (0x2 << 6)
 896 #define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY          (0x3 << 6)
 897
 898 #define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED           BIT_12
 899 #define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED           BIT_13
 900
 901 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK     (0x3 << 20)
 902 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE         (0x0 << 20)
 903 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT          (0x1 << 20)
 904 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV          (0x2 << 20)
 905 #define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV      (0x3 << 20)
 906
 907         uint32_t        link_state;
 908 #define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL                 BIT_0
 909 #define Q8_GET_LINK_STAT_PORT_RST_DONE                  BIT_3
 910 #define Q8_GET_LINK_STAT_PHY_LINK_DOWN                  BIT_4
 911 #define Q8_GET_LINK_STAT_PCS_LINK_DOWN                  BIT_5
 912 #define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT                BIT_6
 913 #define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT               BIT_7
 914 #define Q8_GET_LINK_STAT_XMT_DISABLED                   BIT_9
 915 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT                  BIT_10
 916
 917         uint32_t        sfp_info;
 918 #define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK                0x3
 919 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED        0x0
 920 #define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE                0x1
 921 #define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID             0x2
 922 #define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID               0x3
 923
 924 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK            (0x3 << 2)
 925 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR     (0x0 << 2)
 926 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC      (0x1 << 2)
 927 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED    (0x2 << 2)
 928 #define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR    (0x3 << 2)
 929
 930 #define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK              (0x1F << 4)
 931 #define Q8_GET_LINK_STAT_SFP_MOD_NONE                   (0x00 << 4)
 932 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM                (0x01 << 4)
 933 #define Q8_GET_LINK_STAT_SFP_MOD_10GBLR                 (0x02 << 4)
 934 #define Q8_GET_LINK_STAT_SFP_MOD_10GBSR                 (0x03 << 4)
 935 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P                (0x04 << 4)
 936 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL               (0x05 << 4)
 937 #define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL               (0x06 << 4)
 938 #define Q8_GET_LINK_STAT_SFP_MOD_1GBSX                  (0x07 << 4)
 939 #define Q8_GET_LINK_STAT_SFP_MOD_1GBLX                  (0x08 << 4)
 940 #define Q8_GET_LINK_STAT_SFP_MOD_1GBCX                  (0x09 << 4)
 941 #define Q8_GET_LINK_STAT_SFP_MOD_1GBT                   (0x0A << 4)
 942 #define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL                (0x0B << 4)
 943 #define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN                (0x0F << 4)
 944
 945 #define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD             BIT_9
 946 #define Q8_GET_LINK_STAT_SFP_XMT_FAULT                  BIT_10
 947 #define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK     (0xFF << 16)
 948
 949 } __packed q80_get_link_status_rsp_t;
 950
 951
 952 /*
 953  * Transmit Related Definitions
 954  */
 955 /* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/
 956 #define MAX_TCNTXT_RINGS           8
 957
 958 /*
 959  * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data
 960  */
 961
 962 typedef struct _q80_rq_tx_ring {
 963         uint64_t        paddr;
 964         uint64_t        tx_consumer;
 965         uint16_t        nentries;
 966         uint16_t        intr_id;
 967         uint8_t         intr_src_bit;
 968         uint8_t         rsrvd[3];
 969 } __packed q80_rq_tx_ring_t;
 970
 971 typedef struct _q80_rq_tx_cntxt {
 972         uint16_t                opcode;
 973         uint16_t                count_version;
 974
 975         uint32_t                cap0;
 976 #define Q8_TX_CNTXT_CAP0_BASEFW         (1 << 0)
 977 #define Q8_TX_CNTXT_CAP0_LSO            (1 << 6)
 978 #define Q8_TX_CNTXT_CAP0_TC             (1 << 25)
 979
 980         uint32_t                cap1;
 981         uint32_t                cap2;
 982         uint32_t                cap3;
 983         uint8_t                 ntx_rings;
 984         uint8_t                 traffic_class; /* bits 8-10; others reserved */
 985         uint16_t                tx_vpid;
 986         q80_rq_tx_ring_t        tx_ring[MAX_TCNTXT_RINGS];
 987 } __packed q80_rq_tx_cntxt_t;
 988
 989 typedef struct _q80_rsp_tx_ring {
 990         uint32_t                prod_index;
 991         uint16_t                cntxt_id;
 992         uint8_t                 state;
 993         uint8_t                 rsrvd;
 994 } q80_rsp_tx_ring_t;
 995
 996 typedef struct _q80_rsp_tx_cntxt {
 997         uint16_t                opcode;
 998         uint16_t                regcnt_status;
 999         uint8_t                 ntx_rings;
1000         uint8_t                 phy_port;
1001         uint8_t                 virt_port;
1002         uint8_t                 rsrvd;
1003         q80_rsp_tx_ring_t       tx_ring[MAX_TCNTXT_RINGS];
1004 } __packed q80_rsp_tx_cntxt_t;
1005
1006 typedef struct _q80_tx_cntxt_destroy {
1007         uint16_t        opcode;
1008         uint16_t        count_version;
1009         uint32_t        cntxt_id;
1010 } __packed q80_tx_cntxt_destroy_t;
1011
1012 typedef struct _q80_tx_cntxt_destroy_rsp {
1013         uint16_t        opcode;
1014         uint16_t        regcnt_status;
1015 } __packed q80_tx_cntxt_destroy_rsp_t;
1016
1017 /*
1018  * Transmit Command Descriptor
1019  * These commands are issued on the Transmit Ring associated with a Transmit
1020  * context
1021  */
1022 typedef struct _q80_tx_cmd {
1023         uint8_t         tcp_hdr_off;    /* TCP Header Offset */
1024         uint8_t         ip_hdr_off;     /* IP Header Offset */
1025         uint16_t        flags_opcode;   /* Bits 0-6: flags; 7-12: opcode */
1026
1027         /* flags field */
1028 #define Q8_TX_CMD_FLAGS_MULTICAST       0x01
1029 #define Q8_TX_CMD_FLAGS_LSO_TSO         0x02
1030 #define Q8_TX_CMD_FLAGS_VLAN_TAGGED     0x10
1031 #define Q8_TX_CMD_FLAGS_HW_VLAN_ID      0x40
1032
1033         /* opcode field */
1034 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6        (0xC << 7)
1035 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6        (0xB << 7)
1036 #define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6           (0x6 << 7)
1037 #define Q8_TX_CMD_OP_XMT_TCP_LSO                (0x5 << 7)
1038 #define Q8_TX_CMD_OP_XMT_UDP_CHKSUM             (0x3 << 7)
1039 #define Q8_TX_CMD_OP_XMT_TCP_CHKSUM             (0x2 << 7)
1040 #define Q8_TX_CMD_OP_XMT_ETHER                  (0x1 << 7)
1041
1042         uint8_t         n_bufs;         /* # of data segs in data buffer */
1043         uint8_t         data_len_lo;    /* data length lower 8 bits */
1044         uint16_t        data_len_hi;    /* data length upper 16 bits */
1045
1046         uint64_t        buf2_addr;      /* buffer 2 address */
1047
1048         uint16_t        rsrvd0;
1049         uint16_t        mss;            /* MSS for this packet */
1050         uint8_t         cntxtid;        /* Bits 7-4: ContextId; 3-0: reserved */
1051
1052 #define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4)
1053
1054         uint8_t         total_hdr_len;  /* MAC+IP+TCP Header Length for LSO */
1055         uint16_t        rsrvd1;
1056
1057         uint64_t        buf3_addr;      /* buffer 3 address */
1058         uint64_t        buf1_addr;      /* buffer 1 address */
1059
1060         uint16_t        buf1_len;       /* length of buffer 1 */
1061         uint16_t        buf2_len;       /* length of buffer 2 */
1062         uint16_t        buf3_len;       /* length of buffer 3 */
1063         uint16_t        buf4_len;       /* length of buffer 4 */
1064
1065         uint64_t        buf4_addr;      /* buffer 4 address */
1066
1067         uint32_t        rsrvd2;
1068         uint16_t        rsrvd3;
1069         uint16_t        vlan_tci;       /* VLAN TCI when hw tagging is enabled*/
1070
1071 } __packed q80_tx_cmd_t; /* 64 bytes */
1072
1073 #define Q8_TX_CMD_MAX_SEGMENTS          4
1074 #define Q8_TX_CMD_TSO_ALIGN             2
1075 #define Q8_TX_MAX_NON_TSO_SEGS          62
1076
1077
1078 /*
1079  * Receive Related Definitions
1080  */
1081 #define MAX_RDS_RING_SETS       8 /* Max# of Receive Descriptor Rings */
1082 #define MAX_SDS_RINGS           4 /* Max# of Status Descriptor Rings */
1083
1084 typedef struct _q80_rq_sds_ring {
1085         uint64_t paddr; /* physical addr of status ring in system memory */
1086         uint64_t hdr_split1;
1087         uint64_t hdr_split2;
1088         uint16_t size; /* number of entries in status ring */
1089         uint16_t hdr_split1_size;
1090         uint16_t hdr_split2_size;
1091         uint16_t hdr_split_count;
1092         uint16_t intr_id;
1093         uint8_t  intr_src_bit;
1094         uint8_t  rsrvd[5];
1095 } __packed q80_rq_sds_ring_t; /* 10 32bit words */
1096
1097 typedef struct _q80_rq_rds_ring {
1098         uint64_t paddr_std;     /* physical addr of rcv ring in system memory */
1099         uint64_t paddr_jumbo;   /* physical addr of rcv ring in system memory */
1100         uint16_t std_bsize;
1101         uint16_t std_nentries;
1102         uint16_t jumbo_bsize;
1103         uint16_t jumbo_nentries;
1104 } __packed q80_rq_rds_ring_t; /* 6 32bit words */
1105
1106 #define MAX_RCNTXT_SDS_RINGS    8
1107
1108 typedef struct _q80_rq_rcv_cntxt {
1109         uint16_t                opcode;
1110         uint16_t                count_version;
1111         uint32_t                cap0;
1112 #define Q8_RCV_CNTXT_CAP0_BASEFW        (1 << 0)
1113 #define Q8_RCV_CNTXT_CAP0_MULTI_RDS     (1 << 1)
1114 #define Q8_RCV_CNTXT_CAP0_LRO           (1 << 5)
1115 #define Q8_RCV_CNTXT_CAP0_HW_LRO        (1 << 10)
1116 #define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN    (1 << 14)
1117 #define Q8_RCV_CNTXT_CAP0_RSS           (1 << 15)
1118 #define Q8_RCV_CNTXT_CAP0_MSFT_RSS      (1 << 16)
1119 #define Q8_RCV_CNTXT_CAP0_SGL_JUMBO     (1 << 18)
1120 #define Q8_RCV_CNTXT_CAP0_SGL_LRO       (1 << 19)
1121
1122         uint32_t                cap1;
1123         uint32_t                cap2;
1124         uint32_t                cap3;
1125         uint8_t                 nrds_sets_rings;
1126         uint8_t                 nsds_rings;
1127         uint16_t                rds_producer_mode;
1128 #define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE       0
1129 #define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED       1
1130
1131         uint16_t                rcv_vpid;
1132         uint16_t                rsrvd0;
1133         uint32_t                rsrvd1;
1134         q80_rq_sds_ring_t       sds[MAX_RCNTXT_SDS_RINGS];
1135         q80_rq_rds_ring_t       rds[MAX_RDS_RING_SETS];
1136 } __packed q80_rq_rcv_cntxt_t;
1137
1138 typedef struct _q80_rsp_rds_ring {
1139         uint32_t prod_std;
1140         uint32_t prod_jumbo;
1141 } __packed q80_rsp_rds_ring_t; /* 8 bytes */
1142
1143 typedef struct _q80_rsp_rcv_cntxt {
1144         uint16_t                opcode;
1145         uint16_t                regcnt_status;
1146         uint8_t                 nrds_sets_rings;
1147         uint8_t                 nsds_rings;
1148         uint16_t                cntxt_id;
1149         uint8_t                 state;
1150         uint8_t                 num_funcs;
1151         uint8_t                 phy_port;
1152         uint8_t                 virt_port;
1153         uint32_t                sds_cons[MAX_RCNTXT_SDS_RINGS];
1154         q80_rsp_rds_ring_t      rds[MAX_RDS_RING_SETS];
1155 } __packed q80_rsp_rcv_cntxt_t;
1156
1157 typedef struct _q80_rcv_cntxt_destroy {
1158         uint16_t        opcode;
1159         uint16_t        count_version;
1160         uint32_t        cntxt_id;
1161 } __packed q80_rcv_cntxt_destroy_t;
1162
1163 typedef struct _q80_rcv_cntxt_destroy_rsp {
1164         uint16_t        opcode;
1165         uint16_t        regcnt_status;
1166 } __packed q80_rcv_cntxt_destroy_rsp_t;
1167
1168
1169 /*
1170  * Add Receive Rings
1171  */
1172 typedef struct _q80_rq_add_rcv_rings {
1173         uint16_t                opcode;
1174         uint16_t                count_version;
1175         uint8_t                 nrds_sets_rings;
1176         uint8_t                 nsds_rings;
1177         uint16_t                cntxt_id;
1178         q80_rq_sds_ring_t       sds[MAX_RCNTXT_SDS_RINGS];
1179         q80_rq_rds_ring_t       rds[MAX_RDS_RING_SETS];
1180 } __packed q80_rq_add_rcv_rings_t;
1181
1182 typedef struct _q80_rsp_add_rcv_rings {
1183         uint16_t                opcode;
1184         uint16_t                regcnt_status;
1185         uint8_t                 nrds_sets_rings;
1186         uint8_t                 nsds_rings;
1187         uint16_t                cntxt_id;
1188         uint32_t                sds_cons[MAX_RCNTXT_SDS_RINGS];
1189         q80_rsp_rds_ring_t      rds[MAX_RDS_RING_SETS];
1190 } __packed q80_rsp_add_rcv_rings_t;
1191
1192 /*
1193  * Map Status Ring to Receive Descriptor Set
1194  */
1195
1196 #define MAX_SDS_TO_RDS_MAP      16
1197
1198 typedef struct _q80_sds_rds_map_e {
1199         uint8_t sds_ring;
1200         uint8_t rsrvd0;
1201         uint8_t rds_ring;
1202         uint8_t rsrvd1;
1203 } __packed q80_sds_rds_map_e_t;
1204
1205 typedef struct _q80_rq_map_sds_to_rds {
1206         uint16_t                opcode;
1207         uint16_t                count_version;
1208         uint16_t                cntxt_id;
1209         uint16_t                num_rings;
1210         q80_sds_rds_map_e_t     sds_rds[MAX_SDS_TO_RDS_MAP];
1211 } __packed q80_rq_map_sds_to_rds_t;
1212
1213
1214 typedef struct _q80_rsp_map_sds_to_rds {
1215         uint16_t                opcode;
1216         uint16_t                regcnt_status;
1217         uint16_t                cntxt_id;
1218         uint16_t                num_rings;
1219         q80_sds_rds_map_e_t     sds_rds[MAX_SDS_TO_RDS_MAP];
1220 } __packed q80_rsp_map_sds_to_rds_t;
1221
1222
1223 /*
1224  * Receive Descriptor corresponding to each entry in the receive ring
1225  */
1226 typedef struct _q80_rcv_desc {
1227         uint16_t handle;
1228         uint16_t rsrvd;
1229         uint32_t buf_size; /* buffer size in bytes */
1230         uint64_t buf_addr; /* physical address of buffer */
1231 } __packed q80_recv_desc_t;
1232
1233 /*
1234  * Status Descriptor corresponding to each entry in the Status ring
1235  */
1236 typedef struct _q80_stat_desc {
1237         uint64_t data[2];
1238 } __packed q80_stat_desc_t;
1239
1240 /*
1241  * definitions for data[0] field of Status Descriptor
1242  */
1243 #define Q8_STAT_DESC_RSS_HASH(data)             (data & 0xFFFFFFFF)
1244 #define Q8_STAT_DESC_TOTAL_LENGTH(data)         ((data >> 32) & 0x3FFF)
1245 #define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF)
1246 #define Q8_STAT_DESC_HANDLE(data)               ((data >> 48) & 0xFFFF)
1247 /*
1248  * definitions for data[1] field of Status Descriptor
1249  */
1250
1251 #define Q8_STAT_DESC_OPCODE(data)               ((data >> 42) & 0xF)
1252 #define         Q8_STAT_DESC_OPCODE_RCV_PKT             0x01
1253 #define         Q8_STAT_DESC_OPCODE_LRO_PKT             0x02
1254 #define         Q8_STAT_DESC_OPCODE_SGL_LRO             0x04
1255 #define         Q8_STAT_DESC_OPCODE_SGL_RCV             0x05
1256 #define         Q8_STAT_DESC_OPCODE_CONT                0x06
1257
1258 /*
1259  * definitions for data[1] field of Status Descriptor for standard frames
1260  * status descriptor opcode equals 0x04
1261  */
1262 #define Q8_STAT_DESC_STATUS(data)               ((data >> 39) & 0x0007)
1263 #define         Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE     0x00
1264 #define         Q8_STAT_DESC_STATUS_NO_CHKSUM           0x01
1265 #define         Q8_STAT_DESC_STATUS_CHKSUM_OK           0x02
1266 #define         Q8_STAT_DESC_STATUS_CHKSUM_ERR          0x03
1267
1268 #define Q8_STAT_DESC_VLAN(data)                 ((data >> 47) & 1)
1269 #define Q8_STAT_DESC_VLAN_ID(data)              ((data >> 48) & 0xFFFF)
1270
1271 #define Q8_STAT_DESC_PROTOCOL(data)             ((data >> 44) & 0x000F)
1272 #define Q8_STAT_DESC_L2_OFFSET(data)            ((data >> 48) & 0x001F)
1273 #define Q8_STAT_DESC_COUNT(data)                ((data >> 37) & 0x0007)
1274
1275 /*
1276  * definitions for data[0-1] fields of Status Descriptor for LRO
1277  * status descriptor opcode equals 0x04
1278  */
1279
1280 /* definitions for data[1] field */
1281 #define Q8_LRO_STAT_DESC_SEQ_NUM(data)          (uint32_t)(data)
1282
1283 /*
1284  * definitions specific to opcode 0x04 data[1]
1285  */
1286 #define Q8_STAT_DESC_COUNT_SGL_LRO(data)        ((data >> 13) & 0x0007)
1287 #define Q8_SGL_LRO_STAT_L2_OFFSET(data)         ((data >> 16) & 0xFF)
1288 #define Q8_SGL_LRO_STAT_L4_OFFSET(data)         ((data >> 24) & 0xFF)
1289 #define Q8_SGL_LRO_STAT_TS(data)                ((data >> 40) & 0x1)
1290 #define Q8_SGL_LRO_STAT_PUSH_BIT(data)          ((data >> 41) & 0x1)
1291
1292
1293 /*
1294  * definitions specific to opcode 0x05 data[1]
1295  */
1296 #define Q8_STAT_DESC_COUNT_SGL_RCV(data)        ((data >> 37) & 0x0003)
1297
1298 /*
1299  * definitions for opcode 0x06
1300  */
1301 /* definitions for data[0] field */
1302 #define Q8_SGL_STAT_DESC_HANDLE1(data)          (data & 0xFFFF)
1303 #define Q8_SGL_STAT_DESC_HANDLE2(data)          ((data >> 16) & 0xFFFF)
1304 #define Q8_SGL_STAT_DESC_HANDLE3(data)          ((data >> 32) & 0xFFFF)
1305 #define Q8_SGL_STAT_DESC_HANDLE4(data)          ((data >> 48) & 0xFFFF)
1306
1307 /* definitions for data[1] field */
1308 #define Q8_SGL_STAT_DESC_HANDLE5(data)          (data & 0xFFFF)
1309 #define Q8_SGL_STAT_DESC_HANDLE6(data)          ((data >> 16) & 0xFFFF)
1310 #define Q8_SGL_STAT_DESC_NUM_HANDLES(data)      ((data >> 32) & 0x7)
1311 #define Q8_SGL_STAT_DESC_HANDLE7(data)          ((data >> 48) & 0xFFFF)
1312
1313 /** Driver Related Definitions Begin **/
1314
1315 #define TX_SMALL_PKT_SIZE       128 /* size in bytes of small packets */
1316
1317 /* The number of descriptors should be a power of 2 */
1318 #define NUM_TX_DESCRIPTORS              1024
1319 #define NUM_STATUS_DESCRIPTORS          1024
1320
1321
1322 #define NUM_RX_DESCRIPTORS      2048
1323 #define MAX_RDS_RINGS           MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */
1324
1325 /*
1326  * structure describing various dma buffers
1327  */
1328
1329 typedef struct qla_dmabuf {
1330         volatile struct {
1331                 uint32_t        tx_ring         :1,
1332                                 rds_ring        :1,
1333                                 sds_ring        :1,
1334                                 minidump        :1;
1335         } flags;
1336
1337         qla_dma_t               tx_ring;
1338         qla_dma_t               rds_ring[MAX_RDS_RINGS];
1339         qla_dma_t               sds_ring[MAX_SDS_RINGS];
1340         qla_dma_t               minidump;
1341 } qla_dmabuf_t;
1342
1343 typedef struct _qla_sds {
1344         q80_stat_desc_t *sds_ring_base; /* start of sds ring */
1345         uint32_t        sdsr_next; /* next entry in SDS ring to process */
1346         struct lro_ctrl lro;
1347         void            *rxb_free;
1348         uint32_t        rx_free;
1349         volatile uint32_t rcv_active;
1350         uint32_t        sds_consumer;
1351         uint64_t        intr_count;
1352 } qla_sds_t;
1353
1354 #define Q8_MAX_LRO_CONT_DESC    7
1355 #define Q8_MAX_HANDLES_LRO      (1 + (Q8_MAX_LRO_CONT_DESC * 7))
1356 #define Q8_MAX_HANDLES_NON_LRO  8
1357
1358 typedef struct _qla_sgl_rcv {
1359         uint16_t        pkt_length;
1360         uint16_t        num_handles;
1361         uint16_t        chksum_status;
1362         uint32_t        rss_hash;
1363         uint16_t        rss_hash_flags;
1364         uint16_t        vlan_tag;
1365         uint16_t        handle[Q8_MAX_HANDLES_NON_LRO];
1366 } qla_sgl_rcv_t;
1367
1368 typedef struct _qla_sgl_lro {
1369         uint16_t        flags;
1370 #define Q8_LRO_COMP_TS          0x1
1371 #define Q8_LRO_COMP_PUSH_BIT    0x2
1372         uint16_t        l2_offset;
1373         uint16_t        l4_offset;
1374
1375         uint16_t        payload_length;
1376         uint16_t        num_handles;
1377         uint32_t        rss_hash;
1378         uint16_t        rss_hash_flags;
1379         uint16_t        vlan_tag;
1380         uint16_t        handle[Q8_MAX_HANDLES_LRO];
1381 } qla_sgl_lro_t;
1382
1383 typedef union {
1384         qla_sgl_rcv_t   rcv;
1385         qla_sgl_lro_t   lro;
1386 } qla_sgl_comp_t;
1387
1388 #define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\
1389                 sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16)
1390
1391 typedef struct _qla_hw_tx_cntxt {
1392         q80_tx_cmd_t    *tx_ring_base;
1393         bus_addr_t      tx_ring_paddr;
1394
1395         volatile uint32_t *tx_cons; /* tx consumer shadow reg */
1396         bus_addr_t      tx_cons_paddr;
1397
1398         volatile uint32_t txr_free; /* # of free entries in tx ring */
1399         volatile uint32_t txr_next; /* # next available tx ring entry */
1400         volatile uint32_t txr_comp; /* index of last tx entry completed */
1401
1402         uint32_t        tx_prod_reg;
1403         uint16_t        tx_cntxt_id;
1404         uint8_t         frame_hdr[QL_FRAME_HDR_SIZE];
1405
1406 } qla_hw_tx_cntxt_t;
1407
1408 typedef struct _qla_mcast {
1409         uint16_t        rsrvd;
1410         uint8_t         addr[6];
1411 } __packed qla_mcast_t;
1412
1413 typedef struct _qla_rdesc {
1414         volatile uint32_t prod_std;
1415         volatile uint32_t prod_jumbo;
1416         volatile uint32_t rx_next; /* next standard rcv ring to arm fw */
1417         volatile int32_t  rx_in; /* next standard rcv ring to add mbufs */
1418         volatile uint64_t count;
1419 } qla_rdesc_t;
1420
1421 typedef struct _qla_flash_desc_table {
1422         uint32_t        flash_valid;
1423         uint16_t        flash_ver;
1424         uint16_t        flash_len;
1425         uint16_t        flash_cksum;
1426         uint16_t        flash_unused;
1427         uint8_t         flash_model[16];
1428         uint16_t        flash_manuf;
1429         uint16_t        flash_id;
1430         uint8_t         flash_flag;
1431         uint8_t         erase_cmd;
1432         uint8_t         alt_erase_cmd;
1433         uint8_t         write_enable_cmd;
1434         uint8_t         write_enable_bits;
1435         uint8_t         write_statusreg_cmd;
1436         uint8_t         unprotected_sec_cmd;
1437         uint8_t         read_manuf_cmd;
1438         uint32_t        block_size;
1439         uint32_t        alt_block_size;
1440         uint32_t        flash_size;
1441         uint32_t        write_enable_data;
1442         uint8_t         readid_addr_len;
1443         uint8_t         write_disable_bits;
1444         uint8_t         read_dev_id_len;
1445         uint8_t         chip_erase_cmd;
1446         uint16_t        read_timeo;
1447         uint8_t         protected_sec_cmd;
1448         uint8_t         resvd[65];
1449 } __packed qla_flash_desc_table_t;
1450
1451 #define NUM_TX_RINGS            4
1452
1453 /*
1454  * struct for storing hardware specific information for a given interface
1455  */
1456 typedef struct _qla_hw {
1457         struct {
1458                 uint32_t
1459                         unicast_mac     :1,
1460                         bcast_mac       :1,
1461                         loopback_mode   :2,
1462                         init_tx_cnxt    :1,
1463                         init_rx_cnxt    :1,
1464                         init_intr_cnxt  :1,
1465                         fduplex         :1,
1466                         autoneg         :1,
1467                         fdt_valid       :1;
1468         } flags;
1469
1470
1471         uint16_t        link_speed;
1472         uint16_t        cable_length;
1473         uint32_t        cable_oui;
1474         uint8_t         link_up;
1475         uint8_t         module_type;
1476         uint8_t         link_faults;
1477
1478         uint8_t         mac_rcv_mode;
1479
1480         uint32_t        max_mtu;
1481
1482         uint8_t         mac_addr[ETHER_ADDR_LEN];
1483
1484         uint32_t        num_sds_rings;
1485         uint32_t        num_rds_rings;
1486         uint32_t        num_tx_rings;
1487
1488         qla_dmabuf_t    dma_buf;
1489
1490         /* Transmit Side */
1491
1492         qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS];
1493
1494         /* Receive Side */
1495
1496         uint16_t        rcv_cntxt_id;
1497
1498         uint32_t        mbx_intr_mask_offset;
1499
1500         uint16_t        intr_id[MAX_SDS_RINGS];
1501         uint32_t        intr_src[MAX_SDS_RINGS];
1502
1503         qla_sds_t       sds[MAX_SDS_RINGS];
1504         uint32_t        mbox[Q8_NUM_MBOX];
1505         qla_rdesc_t     rds[MAX_RDS_RINGS];
1506
1507         uint32_t        rds_pidx_thres;
1508         uint32_t        sds_cidx_thres;
1509
1510         /* multicast address list */
1511         uint32_t        nmcast;
1512         qla_mcast_t     mcast[Q8_MAX_NUM_MULTICAST_ADDRS];
1513
1514         /* reset sequence */
1515 #define Q8_MAX_RESET_SEQ_IDX    16
1516         uint32_t        rst_seq[Q8_MAX_RESET_SEQ_IDX];
1517         uint32_t        rst_seq_idx;
1518
1519         /* heart beat register value */
1520         uint32_t        hbeat_value;
1521         uint32_t        health_count;
1522
1523         uint32_t        max_tx_segs;
1524
1525         /* Flash Descriptor Table */
1526         qla_flash_desc_table_t fdt;
1527
1528         /* Minidump Related */
1529         uint32_t        mdump_init;
1530         uint32_t        mdump_start;
1531         uint32_t        mdump_active;
1532         uint32_t        mdump_start_seq_index;
1533 } qla_hw_t;
1534
1535 #define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \
1536                 bus_write_4((ha->pci_reg), prod_reg, val);
1537
1538 #define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \
1539                 WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val)
1540
1541 #define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \
1542         bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val);
1543
1544 #define QL_ENABLE_INTERRUPTS(ha, i) \
1545                 bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0);
1546
1547 #define QL_BUFFER_ALIGN                16
1548
1549
1550 /*
1551  * Flash Configuration
1552  */
1553 #define Q8_BOARD_CONFIG_OFFSET          0x370000
1554 #define Q8_BOARD_CONFIG_LENGTH          0x2000
1555
1556 #define Q8_BOARD_CONFIG_MAC0_LO         0x400
1557
1558 #define Q8_FDT_LOCK_MAGIC_ID            0x00FD00FD
1559 #define Q8_FDT_FLASH_ADDR_VAL           0xFD009F
1560 #define Q8_FDT_FLASH_CTRL_VAL           0x3F
1561 #define Q8_FDT_MASK_VAL                 0xFF
1562
1563 #define Q8_WR_ENABLE_FL_ADDR            0xFD0100
1564 #define Q8_WR_ENABLE_FL_CTRL            0x5
1565
1566 #define Q8_ERASE_LOCK_MAGIC_ID          0x00EF00EF
1567 #define Q8_ERASE_FL_ADDR_MASK           0xFD0300
1568 #define Q8_ERASE_FL_CTRL_MASK           0x3D
1569
1570 #define Q8_WR_FL_LOCK_MAGIC_ID          0xABCDABCD
1571 #define Q8_WR_FL_ADDR_MASK              0x800000
1572 #define Q8_WR_FL_CTRL_MASK              0x3D
1573
1574 #define QL_FDT_OFFSET                   0x3F0000
1575 #define Q8_FLASH_SECTOR_SIZE            0x10000
1576
1577 /*
1578  * Off Chip Memory Access
1579  */
1580
1581 typedef struct _q80_offchip_mem_val {
1582         uint32_t data_lo;
1583         uint32_t data_hi;
1584         uint32_t data_ulo;
1585         uint32_t data_uhi;
1586 } q80_offchip_mem_val_t;
1587
1588 #endif /* #ifndef _QL_HW_H_ */