2 * Copyright (c) 2013-2016 Qlogic Corporation
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 * POSSIBILITY OF SUCH DAMAGE.
30 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 #include <sys/cdefs.h>
34 __FBSDID("$FreeBSD$");
40 #include "ql_inline.h"
45 static void qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp,
49 qla_rcv_error(qla_host_t *ha)
51 ha->flags.stop_rcv = 1;
52 ha->qla_initiate_recovery = 1;
58 * Function: Handles normal ethernet frames received
61 qla_rx_intr(qla_host_t *ha, qla_sgl_rcv_t *sgc, uint32_t sds_idx)
64 struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL;
65 struct ifnet *ifp = ha->ifp;
67 struct ether_vlan_header *eh;
68 uint32_t i, rem_len = 0;
70 qla_rx_ring_t *rx_ring;
73 lro = &ha->hw.sds[sds_idx].lro;
75 if (ha->hw.num_rds_rings > 1)
78 ha->hw.rds[r_idx].count++;
80 sdsp = &ha->hw.sds[sds_idx];
81 rx_ring = &ha->rx_ring[r_idx];
83 for (i = 0; i < sgc->num_handles; i++) {
84 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
86 QL_ASSERT(ha, (rxb != NULL),
87 ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
90 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_RX_RXB_INVAL)) {
92 device_printf(ha->pci_dev,
93 "%s invalid rxb[%d, %d, 0x%04x]\n",
94 __func__, sds_idx, i, sgc->handle[i]);
103 QL_ASSERT(ha, (mp != NULL),
104 ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
107 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
110 rxb->next = sdsp->rxb_free;
111 sdsp->rxb_free = rxb;
114 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_RX_MP_NULL)) {
116 device_printf(ha->pci_dev,
117 "%s mp == NULL [%d, %d, 0x%04x]\n",
118 __func__, sds_idx, i, sgc->handle[i]);
125 mp->m_flags |= M_PKTHDR;
126 mp->m_pkthdr.len = sgc->pkt_length;
127 mp->m_pkthdr.rcvif = ifp;
128 rem_len = mp->m_pkthdr.len;
130 mp->m_flags &= ~M_PKTHDR;
133 rem_len = rem_len - mp->m_len;
137 mpl->m_len = rem_len;
139 eh = mtod(mpf, struct ether_vlan_header *);
141 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
142 uint32_t *data = (uint32_t *)eh;
144 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
145 mpf->m_flags |= M_VLANTAG;
147 *(data + 3) = *(data + 2);
148 *(data + 2) = *(data + 1);
151 m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
154 if (sgc->chksum_status == Q8_STAT_DESC_STATUS_CHKSUM_OK) {
155 mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
156 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
157 mpf->m_pkthdr.csum_data = 0xFFFF;
159 mpf->m_pkthdr.csum_flags = 0;
164 mpf->m_pkthdr.flowid = sgc->rss_hash;
166 #if __FreeBSD_version >= 1100000
167 M_HASHTYPE_SET(mpf, M_HASHTYPE_OPAQUE_HASH);
169 M_HASHTYPE_SET(mpf, M_HASHTYPE_NONE);
170 #endif /* #if __FreeBSD_version >= 1100000 */
172 if (ha->hw.enable_soft_lro) {
174 #if (__FreeBSD_version >= 1100101)
176 tcp_lro_queue_mbuf(lro, mpf);
179 if (tcp_lro_rx(lro, mpf, 0))
180 (*ifp->if_input)(ifp, mpf);
182 #endif /* #if (__FreeBSD_version >= 1100101) */
186 (*ifp->if_input)(ifp, mpf);
189 if (sdsp->rx_free > ha->std_replenish)
190 qla_replenish_normal_rx(ha, sdsp, r_idx);
195 #define QLA_TCP_HDR_SIZE 20
196 #define QLA_TCP_TS_OPTION_SIZE 12
200 * Function: Handles normal ethernet frames received
203 qla_lro_intr(qla_host_t *ha, qla_sgl_lro_t *sgc, uint32_t sds_idx)
206 struct mbuf *mp = NULL, *mpf = NULL, *mpl = NULL;
207 struct ifnet *ifp = ha->ifp;
209 struct ether_vlan_header *eh;
210 uint32_t i, rem_len = 0, pkt_length, iplen;
212 struct ip *ip = NULL;
213 struct ip6_hdr *ip6 = NULL;
216 qla_rx_ring_t *rx_ring;
218 if (ha->hw.num_rds_rings > 1)
221 ha->hw.rds[r_idx].count++;
223 rx_ring = &ha->rx_ring[r_idx];
227 sdsp = &ha->hw.sds[sds_idx];
229 pkt_length = sgc->payload_length + sgc->l4_offset;
231 if (sgc->flags & Q8_LRO_COMP_TS) {
232 pkt_length += QLA_TCP_HDR_SIZE + QLA_TCP_TS_OPTION_SIZE;
234 pkt_length += QLA_TCP_HDR_SIZE;
236 ha->lro_bytes += pkt_length;
238 for (i = 0; i < sgc->num_handles; i++) {
239 rxb = &rx_ring->rx_buf[sgc->handle[i] & 0x7FFF];
241 QL_ASSERT(ha, (rxb != NULL),
242 ("%s: [sds_idx]=[%d] rxb != NULL\n", __func__,\
245 if ((rxb == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_RXB_INVAL)) {
247 device_printf(ha->pci_dev,
248 "%s invalid rxb[%d, %d, 0x%04x]\n",
249 __func__, sds_idx, i, sgc->handle[i]);
258 QL_ASSERT(ha, (mp != NULL),
259 ("%s: [sds_idx]=[%d] mp != NULL\n", __func__,\
262 bus_dmamap_sync(ha->rx_tag, rxb->map, BUS_DMASYNC_POSTREAD);
265 rxb->next = sdsp->rxb_free;
266 sdsp->rxb_free = rxb;
269 if ((mp == NULL) || QL_ERR_INJECT(ha, INJCT_LRO_MP_NULL)) {
271 device_printf(ha->pci_dev,
272 "%s mp == NULL [%d, %d, 0x%04x]\n",
273 __func__, sds_idx, i, sgc->handle[i]);
280 mp->m_flags |= M_PKTHDR;
281 mp->m_pkthdr.len = pkt_length;
282 mp->m_pkthdr.rcvif = ifp;
283 rem_len = mp->m_pkthdr.len;
285 mp->m_flags &= ~M_PKTHDR;
288 rem_len = rem_len - mp->m_len;
292 mpl->m_len = rem_len;
294 th = (struct tcphdr *)(mpf->m_data + sgc->l4_offset);
296 if (sgc->flags & Q8_LRO_COMP_PUSH_BIT)
297 th->th_flags |= TH_PUSH;
299 m_adj(mpf, sgc->l2_offset);
301 eh = mtod(mpf, struct ether_vlan_header *);
303 if (eh->evl_encap_proto == htons(ETHERTYPE_VLAN)) {
304 uint32_t *data = (uint32_t *)eh;
306 mpf->m_pkthdr.ether_vtag = ntohs(eh->evl_tag);
307 mpf->m_flags |= M_VLANTAG;
309 *(data + 3) = *(data + 2);
310 *(data + 2) = *(data + 1);
313 m_adj(mpf, ETHER_VLAN_ENCAP_LEN);
315 etype = ntohs(eh->evl_proto);
317 etype = ntohs(eh->evl_encap_proto);
320 if (etype == ETHERTYPE_IP) {
321 ip = (struct ip *)(mpf->m_data + ETHER_HDR_LEN);
323 iplen = (ip->ip_hl << 2) + (th->th_off << 2) +
326 ip->ip_len = htons(iplen);
330 M_HASHTYPE_SET(mpf, M_HASHTYPE_RSS_TCP_IPV4);
332 } else if (etype == ETHERTYPE_IPV6) {
333 ip6 = (struct ip6_hdr *)(mpf->m_data + ETHER_HDR_LEN);
335 iplen = (th->th_off << 2) + sgc->payload_length;
337 ip6->ip6_plen = htons(iplen);
341 M_HASHTYPE_SET(mpf, M_HASHTYPE_RSS_TCP_IPV6);
346 if (sdsp->rx_free > ha->std_replenish)
347 qla_replenish_normal_rx(ha, sdsp, r_idx);
351 mpf->m_pkthdr.csum_flags = CSUM_IP_CHECKED | CSUM_IP_VALID |
352 CSUM_DATA_VALID | CSUM_PSEUDO_HDR;
353 mpf->m_pkthdr.csum_data = 0xFFFF;
355 mpf->m_pkthdr.flowid = sgc->rss_hash;
356 M_HASHTYPE_SET(mpf, M_HASHTYPE_OPAQUE);
360 (*ifp->if_input)(ifp, mpf);
362 if (sdsp->rx_free > ha->std_replenish)
363 qla_replenish_normal_rx(ha, sdsp, r_idx);
369 qla_rcv_cont_sds(qla_host_t *ha, uint32_t sds_idx, uint32_t comp_idx,
370 uint32_t dcount, uint16_t *handle, uint16_t *nhandles)
373 uint16_t num_handles;
374 q80_stat_desc_t *sdesc;
380 for (i = 0; i < dcount; i++) {
381 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
382 sdesc = (q80_stat_desc_t *)
383 &ha->hw.sds[sds_idx].sds_ring_base[comp_idx];
385 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
388 device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
389 __func__, (void *)sdesc->data[0],
390 (void *)sdesc->data[1]);
394 num_handles = Q8_SGL_STAT_DESC_NUM_HANDLES((sdesc->data[1]));
396 device_printf(ha->pci_dev, "%s: opcode=0 %p %p\n",
397 __func__, (void *)sdesc->data[0],
398 (void *)sdesc->data[1]);
402 if (QL_ERR_INJECT(ha, INJCT_NUM_HNDLE_INVALID))
405 switch (num_handles) {
408 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
412 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
413 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
417 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
418 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
419 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
423 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
424 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
425 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
426 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
430 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
431 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
432 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
433 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
434 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
438 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
439 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
440 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
441 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
442 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
443 *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
447 *handle++ = Q8_SGL_STAT_DESC_HANDLE1((sdesc->data[0]));
448 *handle++ = Q8_SGL_STAT_DESC_HANDLE2((sdesc->data[0]));
449 *handle++ = Q8_SGL_STAT_DESC_HANDLE3((sdesc->data[0]));
450 *handle++ = Q8_SGL_STAT_DESC_HANDLE4((sdesc->data[0]));
451 *handle++ = Q8_SGL_STAT_DESC_HANDLE5((sdesc->data[1]));
452 *handle++ = Q8_SGL_STAT_DESC_HANDLE6((sdesc->data[1]));
453 *handle++ = Q8_SGL_STAT_DESC_HANDLE7((sdesc->data[1]));
457 device_printf(ha->pci_dev,
458 "%s: invalid num handles %p %p\n",
459 __func__, (void *)sdesc->data[0],
460 (void *)sdesc->data[1]);
463 ("%s: %s [nh, sds, d0, d1]=[%d, %d, %p, %p]\n",
464 __func__, "invalid num handles", sds_idx, num_handles,
465 (void *)sdesc->data[0],(void *)sdesc->data[1]));
470 *nhandles = *nhandles + num_handles;
477 * Function: Main Interrupt Service Routine
480 ql_rcv_isr(qla_host_t *ha, uint32_t sds_idx, uint32_t count)
484 uint32_t comp_idx, c_idx = 0, desc_count = 0, opcode;
485 volatile q80_stat_desc_t *sdesc, *sdesc0 = NULL;
489 uint32_t sds_replenish_threshold = 0;
496 hw->sds[sds_idx].rcv_active = 1;
497 if (ha->flags.stop_rcv) {
498 hw->sds[sds_idx].rcv_active = 0;
502 QL_DPRINT2(ha, (dev, "%s: [%d]enter\n", __func__, sds_idx));
507 comp_idx = hw->sds[sds_idx].sdsr_next;
509 while (count-- && !ha->flags.stop_rcv) {
511 sdesc = (q80_stat_desc_t *)
512 &hw->sds[sds_idx].sds_ring_base[comp_idx];
514 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
519 hw->sds[sds_idx].intr_count++;
522 case Q8_STAT_DESC_OPCODE_RCV_PKT:
526 bzero(&sgc, sizeof(qla_sgl_comp_t));
529 Q8_STAT_DESC_TOTAL_LENGTH((sdesc->data[0]));
530 sgc.rcv.num_handles = 1;
532 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
533 sgc.rcv.chksum_status =
534 Q8_STAT_DESC_STATUS((sdesc->data[1]));
537 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
539 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
541 Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
543 qla_rx_intr(ha, &sgc.rcv, sds_idx);
546 case Q8_STAT_DESC_OPCODE_SGL_RCV:
549 Q8_STAT_DESC_COUNT_SGL_RCV((sdesc->data[1]));
551 if (desc_count > 1) {
552 c_idx = (comp_idx + desc_count -1) &
553 (NUM_STATUS_DESCRIPTORS-1);
554 sdesc0 = (q80_stat_desc_t *)
555 &hw->sds[sds_idx].sds_ring_base[c_idx];
557 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
558 Q8_STAT_DESC_OPCODE_CONT) {
564 bzero(&sgc, sizeof(qla_sgl_comp_t));
567 Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(\
569 sgc.rcv.chksum_status =
570 Q8_STAT_DESC_STATUS((sdesc->data[1]));
573 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
575 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
577 Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
580 QL_ASSERT(ha, (desc_count <= 2) ,\
581 ("%s: [sds_idx, data0, data1]="\
582 "%d, %p, %p]\n", __func__, sds_idx,\
583 (void *)sdesc->data[0],\
584 (void *)sdesc->data[1]));
586 sgc.rcv.num_handles = 1;
588 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
590 if (qla_rcv_cont_sds(ha, sds_idx, comp_idx, desc_count,
591 &sgc.rcv.handle[1], &nhandles)) {
593 "%s: [sds_idx, dcount, data0, data1]="
594 "[%d, %d, 0x%llx, 0x%llx]\n",
595 __func__, sds_idx, desc_count,
596 (long long unsigned int)sdesc->data[0],
597 (long long unsigned int)sdesc->data[1]);
602 sgc.rcv.num_handles += nhandles;
604 qla_rx_intr(ha, &sgc.rcv, sds_idx);
608 case Q8_STAT_DESC_OPCODE_SGL_LRO:
611 Q8_STAT_DESC_COUNT_SGL_LRO((sdesc->data[1]));
613 if (desc_count > 1) {
614 c_idx = (comp_idx + desc_count -1) &
615 (NUM_STATUS_DESCRIPTORS-1);
616 sdesc0 = (q80_stat_desc_t *)
617 &hw->sds[sds_idx].sds_ring_base[c_idx];
619 if (Q8_STAT_DESC_OPCODE((sdesc0->data[1])) !=
620 Q8_STAT_DESC_OPCODE_CONT) {
625 bzero(&sgc, sizeof(qla_sgl_comp_t));
627 sgc.lro.payload_length =
628 Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV((sdesc->data[0]));
631 Q8_STAT_DESC_RSS_HASH((sdesc->data[0]));
633 sgc.lro.num_handles = 1;
635 Q8_STAT_DESC_HANDLE((sdesc->data[0]));
637 if (Q8_SGL_LRO_STAT_TS((sdesc->data[1])))
638 sgc.lro.flags |= Q8_LRO_COMP_TS;
640 if (Q8_SGL_LRO_STAT_PUSH_BIT((sdesc->data[1])))
641 sgc.lro.flags |= Q8_LRO_COMP_PUSH_BIT;
644 Q8_SGL_LRO_STAT_L2_OFFSET((sdesc->data[1]));
646 Q8_SGL_LRO_STAT_L4_OFFSET((sdesc->data[1]));
648 if (Q8_STAT_DESC_VLAN((sdesc->data[1]))) {
650 Q8_STAT_DESC_VLAN_ID((sdesc->data[1]));
653 QL_ASSERT(ha, (desc_count <= 7) ,\
654 ("%s: [sds_idx, data0, data1]="\
655 "[%d, 0x%llx, 0x%llx]\n",\
657 (long long unsigned int)sdesc->data[0],\
658 (long long unsigned int)sdesc->data[1]));
660 if (qla_rcv_cont_sds(ha, sds_idx, comp_idx,
661 desc_count, &sgc.lro.handle[1], &nhandles)) {
663 "%s: [sds_idx, data0, data1]="\
664 "[%d, 0x%llx, 0x%llx]\n",\
666 (long long unsigned int)sdesc->data[0],\
667 (long long unsigned int)sdesc->data[1]);
673 sgc.lro.num_handles += nhandles;
675 if (qla_lro_intr(ha, &sgc.lro, sds_idx)) {
677 "%s: [sds_idx, data0, data1]="\
678 "[%d, 0x%llx, 0x%llx]\n",\
680 (long long unsigned int)sdesc->data[0],\
681 (long long unsigned int)sdesc->data[1]);
683 "%s: [comp_idx, c_idx, dcount, nhndls]="\
684 "[%d, %d, %d, %d]\n",\
685 __func__, comp_idx, c_idx, desc_count,
686 sgc.lro.num_handles);
687 if (desc_count > 1) {
689 "%s: [sds_idx, data0, data1]="\
690 "[%d, 0x%llx, 0x%llx]\n",\
692 (long long unsigned int)sdesc0->data[0],\
693 (long long unsigned int)sdesc0->data[1]);
700 device_printf(dev, "%s: default 0x%llx!\n", __func__,
701 (long long unsigned int)sdesc->data[0]);
708 sds_replenish_threshold += desc_count;
711 while (desc_count--) {
712 sdesc->data[0] = 0ULL;
713 sdesc->data[1] = 0ULL;
714 comp_idx = (comp_idx + 1) & (NUM_STATUS_DESCRIPTORS-1);
715 sdesc = (q80_stat_desc_t *)
716 &hw->sds[sds_idx].sds_ring_base[comp_idx];
719 if (sds_replenish_threshold > ha->hw.sds_cidx_thres) {
720 sds_replenish_threshold = 0;
721 if (hw->sds[sds_idx].sdsr_next != comp_idx) {
722 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx,\
725 hw->sds[sds_idx].sdsr_next = comp_idx;
729 if (ha->hw.enable_soft_lro) {
730 struct lro_ctrl *lro;
732 lro = &ha->hw.sds[sds_idx].lro;
734 #if (__FreeBSD_version >= 1100101)
736 tcp_lro_flush_all(lro);
739 struct lro_entry *queued;
741 while ((!SLIST_EMPTY(&lro->lro_active))) {
742 queued = SLIST_FIRST(&lro->lro_active);
743 SLIST_REMOVE_HEAD(&lro->lro_active, next);
744 tcp_lro_flush(lro, queued);
747 #endif /* #if (__FreeBSD_version >= 1100101) */
751 if (ha->flags.stop_rcv)
752 goto ql_rcv_isr_exit;
754 if (hw->sds[sds_idx].sdsr_next != comp_idx) {
755 QL_UPDATE_SDS_CONSUMER_INDEX(ha, sds_idx, comp_idx);
756 hw->sds[sds_idx].sdsr_next = comp_idx;
758 hw->sds[sds_idx].spurious_intr_count++;
760 if (ha->hw.num_rds_rings > 1)
763 sdsp = &ha->hw.sds[sds_idx];
765 if (sdsp->rx_free > ha->std_replenish)
766 qla_replenish_normal_rx(ha, sdsp, r_idx);
769 sdesc = (q80_stat_desc_t *)&hw->sds[sds_idx].sds_ring_base[comp_idx];
770 opcode = Q8_STAT_DESC_OPCODE((sdesc->data[1]));
776 hw->sds[sds_idx].rcv_active = 0;
782 ql_mbx_isr(void *arg)
786 uint32_t prev_link_state;
791 device_printf(ha->pci_dev, "%s: arg == NULL\n", __func__);
795 data = READ_REG32(ha, Q8_FW_MBOX_CNTRL);
796 if ((data & 0x3) != 0x1) {
797 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0);
801 data = READ_REG32(ha, Q8_FW_MBOX0);
803 if ((data & 0xF000) != 0x8000)
806 data = data & 0xFFFF;
810 case 0x8001: /* It's an AEN */
812 ha->hw.cable_oui = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
814 data = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
815 ha->hw.cable_length = data & 0xFFFF;
818 ha->hw.link_speed = data & 0xFFF;
820 data = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
822 prev_link_state = ha->hw.link_up;
823 ha->hw.link_up = (((data & 0xFF) == 0) ? 0 : 1);
825 if (prev_link_state != ha->hw.link_up) {
827 if_link_state_change(ha->ifp, LINK_STATE_UP);
829 if_link_state_change(ha->ifp, LINK_STATE_DOWN);
833 ha->hw.module_type = ((data >> 8) & 0xFF);
834 ha->hw.flags.fduplex = (((data & 0xFF0000) == 0) ? 0 : 1);
835 ha->hw.flags.autoneg = (((data & 0xFF000000) == 0) ? 0 : 1);
837 data = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
838 ha->hw.flags.loopback_mode = data & 0x03;
840 ha->hw.link_faults = (data >> 3) & 0xFF;
850 ha->hw.aen_mb0 = 0x8101;
851 ha->hw.aen_mb1 = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
852 ha->hw.aen_mb2 = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
853 ha->hw.aen_mb3 = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
854 ha->hw.aen_mb4 = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
858 /* for now just dump the registers */
862 ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
863 ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
864 ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
865 ombx[3] = READ_REG32(ha, (Q8_FW_MBOX0 + 16));
866 ombx[4] = READ_REG32(ha, (Q8_FW_MBOX0 + 20));
868 device_printf(ha->pci_dev, "%s: "
869 "0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
870 __func__, data, ombx[0], ombx[1], ombx[2],
877 /* sfp insertion aen */
878 device_printf(ha->pci_dev, "%s: sfp inserted [0x%08x]\n",
879 __func__, READ_REG32(ha, (Q8_FW_MBOX0 + 4)));
883 /* sfp removal aen */
884 device_printf(ha->pci_dev, "%s: sfp removed]\n", __func__);
891 ombx[0] = READ_REG32(ha, (Q8_FW_MBOX0 + 4));
892 ombx[1] = READ_REG32(ha, (Q8_FW_MBOX0 + 8));
893 ombx[2] = READ_REG32(ha, (Q8_FW_MBOX0 + 12));
895 device_printf(ha->pci_dev, "%s: "
896 "0x%08x 0x%08x 0x%08x 0x%08x \n",
897 __func__, data, ombx[0], ombx[1], ombx[2]);
902 device_printf(ha->pci_dev, "%s: AEN[0x%08x]\n", __func__, data);
905 WRITE_REG32(ha, Q8_FW_MBOX_CNTRL, 0x0);
906 WRITE_REG32(ha, ha->hw.mbx_intr_mask_offset, 0x0);
912 qla_replenish_normal_rx(qla_host_t *ha, qla_sds_t *sdsp, uint32_t r_idx)
915 int count = sdsp->rx_free;
919 /* we can play with this value via a sysctl */
920 uint32_t replenish_thresh = ha->hw.rds_pidx_thres;
922 rdesc = &ha->hw.rds[r_idx];
924 rx_next = rdesc->rx_next;
927 rxb = sdsp->rxb_free;
932 sdsp->rxb_free = rxb->next;
935 if (ql_get_mbuf(ha, rxb, NULL) == 0) {
936 qla_set_hw_rcv_desc(ha, r_idx, rdesc->rx_in,
938 rxb->paddr, (rxb->m_head)->m_pkthdr.len);
940 if (rdesc->rx_in == NUM_RX_DESCRIPTORS)
943 if (rdesc->rx_next == NUM_RX_DESCRIPTORS)
946 device_printf(ha->pci_dev,
947 "%s: qla_get_mbuf [(%d),(%d),(%d)] failed\n",
948 __func__, r_idx, rdesc->rx_in, rxb->handle);
951 rxb->next = sdsp->rxb_free;
952 sdsp->rxb_free = rxb;
957 if (replenish_thresh-- == 0) {
958 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
960 rx_next = rdesc->rx_next;
961 replenish_thresh = ha->hw.rds_pidx_thres;
965 if (rx_next != rdesc->rx_next) {
966 QL_UPDATE_RDS_PRODUCER_INDEX(ha, rdesc->prod_std,
974 qla_ivec_t *ivec = arg;
985 if ((idx = ivec->sds_idx) >= ha->hw.num_sds_rings)
989 fp = &ha->tx_fp[idx];
991 if (fp->fp_taskqueue != NULL)
992 taskqueue_enqueue(fp->fp_taskqueue, &fp->fp_task);