2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 #include <sys/cdefs.h>
27 __FBSDID("$FreeBSD$");
29 #include <sys/param.h>
30 #include <sys/systm.h>
32 #include <sys/kernel.h>
34 #include <sys/module.h>
35 #include <sys/mutex.h>
36 #include <sys/resource.h>
38 #include <sys/sysctl.h>
39 #include <sys/taskqueue.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcivar.h>
44 #include <machine/bus.h>
45 #include <machine/resource.h>
47 #include <dev/mmc/bridge.h>
49 #include <dev/sdhci/sdhci.h>
57 #define PCI_SDHCI_IFPIO 0x00
58 #define PCI_SDHCI_IFDMA 0x01
59 #define PCI_SDHCI_IFVENDOR 0x02
61 #define PCI_SLOT_INFO 0x40 /* 8 bits */
62 #define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1)
63 #define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7)
66 * RICOH specific PCI registers
68 #define SDHC_PCI_MODE_KEY 0xf9
69 #define SDHC_PCI_MODE 0x150
70 #define SDHC_PCI_MODE_SD20 0x10
71 #define SDHC_PCI_BASE_FREQ_KEY 0xfc
72 #define SDHC_PCI_BASE_FREQ 0xe1
74 static const struct sdhci_device {
80 { 0x08221180, 0xffff, "RICOH R5C822 SD",
81 SDHCI_QUIRK_FORCE_DMA },
82 { 0xe8221180, 0xffff, "RICOH R5CE822 SD",
83 SDHCI_QUIRK_FORCE_DMA |
84 SDHCI_QUIRK_LOWER_FREQUENCY },
85 { 0xe8231180, 0xffff, "RICOH R5CE823 SD",
86 SDHCI_QUIRK_LOWER_FREQUENCY },
87 { 0x8034104c, 0xffff, "TI XX21/XX11 SD",
88 SDHCI_QUIRK_FORCE_DMA },
89 { 0x05501524, 0xffff, "ENE CB712 SD",
90 SDHCI_QUIRK_BROKEN_TIMINGS },
91 { 0x05511524, 0xffff, "ENE CB712 SD 2",
92 SDHCI_QUIRK_BROKEN_TIMINGS },
93 { 0x07501524, 0xffff, "ENE CB714 SD",
94 SDHCI_QUIRK_RESET_ON_IOS |
95 SDHCI_QUIRK_BROKEN_TIMINGS },
96 { 0x07511524, 0xffff, "ENE CB714 SD 2",
97 SDHCI_QUIRK_RESET_ON_IOS |
98 SDHCI_QUIRK_BROKEN_TIMINGS },
99 { 0x410111ab, 0xffff, "Marvell CaFe SD",
100 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL },
101 { 0x2381197B, 0xffff, "JMicron JMB38X SD",
102 SDHCI_QUIRK_32BIT_DMA_SIZE |
103 SDHCI_QUIRK_RESET_AFTER_REQUEST },
104 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader",
105 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC },
106 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
107 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
108 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
109 SDHCI_QUIRK_WAIT_WHILE_BUSY },
110 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller",
111 SDHCI_QUIRK_WAIT_WHILE_BUSY },
112 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller",
113 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
114 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
115 SDHCI_QUIRK_WAIT_WHILE_BUSY },
116 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller",
117 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
118 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ |
119 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
120 SDHCI_QUIRK_WAIT_WHILE_BUSY },
121 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller",
122 SDHCI_QUIRK_WAIT_WHILE_BUSY },
123 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller",
124 SDHCI_QUIRK_WAIT_WHILE_BUSY },
125 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller",
126 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE |
127 SDHCI_QUIRK_INTEL_POWER_UP_RESET |
128 SDHCI_QUIRK_WAIT_WHILE_BUSY },
133 struct sdhci_pci_softc {
134 u_int quirks; /* Chip specific quirks */
135 struct resource *irq_res; /* IRQ resource */
136 void *intrhand; /* Interrupt handle */
138 int num_slots; /* Number of slots on this controller */
139 struct sdhci_slot slots[6];
140 struct resource *mem_res[6]; /* Memory resource */
141 uint8_t cfg_freq; /* Saved frequency */
142 uint8_t cfg_mode; /* Saved mode */
145 static int sdhci_enable_msi = 1;
146 TUNABLE_INT("hw.sdhci.enable_msi", &sdhci_enable_msi);
147 SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi,
148 0, "Enable MSI interrupts");
151 sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
153 struct sdhci_pci_softc *sc = device_get_softc(dev);
155 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
156 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
157 return bus_read_1(sc->mem_res[slot->num], off);
161 sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused,
162 bus_size_t off, uint8_t val)
164 struct sdhci_pci_softc *sc = device_get_softc(dev);
166 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
167 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
168 bus_write_1(sc->mem_res[slot->num], off, val);
172 sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
174 struct sdhci_pci_softc *sc = device_get_softc(dev);
176 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
177 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
178 return bus_read_2(sc->mem_res[slot->num], off);
182 sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused,
183 bus_size_t off, uint16_t val)
185 struct sdhci_pci_softc *sc = device_get_softc(dev);
187 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
188 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
189 bus_write_2(sc->mem_res[slot->num], off, val);
193 sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off)
195 struct sdhci_pci_softc *sc = device_get_softc(dev);
197 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
198 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
199 return bus_read_4(sc->mem_res[slot->num], off);
203 sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused,
204 bus_size_t off, uint32_t val)
206 struct sdhci_pci_softc *sc = device_get_softc(dev);
208 bus_barrier(sc->mem_res[slot->num], 0, 0xFF,
209 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE);
210 bus_write_4(sc->mem_res[slot->num], off, val);
214 sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused,
215 bus_size_t off, uint32_t *data, bus_size_t count)
217 struct sdhci_pci_softc *sc = device_get_softc(dev);
219 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count);
223 sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused,
224 bus_size_t off, uint32_t *data, bus_size_t count)
226 struct sdhci_pci_softc *sc = device_get_softc(dev);
228 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count);
231 static void sdhci_pci_intr(void *arg);
234 sdhci_lower_frequency(device_t dev)
236 struct sdhci_pci_softc *sc = device_get_softc(dev);
240 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822.
242 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
243 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1);
244 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1);
245 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
248 * Some SD/MMC cards don't work with the default base
249 * clock frequency of 200 MHz. Lower it to 50 MHz.
251 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
252 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1);
253 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1);
254 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
258 sdhci_restore_frequency(device_t dev)
260 struct sdhci_pci_softc *sc = device_get_softc(dev);
263 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1);
264 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1);
265 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1);
267 /* Restore frequency. */
268 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1);
269 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1);
270 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1);
274 sdhci_pci_probe(device_t dev)
278 uint8_t class, subclass;
281 model = (uint32_t)pci_get_device(dev) << 16;
282 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
283 subvendor = pci_get_subvendor(dev);
284 class = pci_get_class(dev);
285 subclass = pci_get_subclass(dev);
288 for (i = 0; sdhci_devices[i].model != 0; i++) {
289 if (sdhci_devices[i].model == model &&
290 (sdhci_devices[i].subvendor == 0xffff ||
291 sdhci_devices[i].subvendor == subvendor)) {
292 device_set_desc(dev, sdhci_devices[i].desc);
293 result = BUS_PROBE_DEFAULT;
297 if (result == ENXIO && class == PCIC_BASEPERIPH &&
298 subclass == PCIS_BASEPERIPH_SDHC) {
299 device_set_desc(dev, "Generic SD HCI");
300 result = BUS_PROBE_GENERIC;
307 sdhci_pci_attach(device_t dev)
309 struct sdhci_pci_softc *sc = device_get_softc(dev);
310 struct sdhci_slot *slot;
313 int bar, err, rid, slots, i;
315 model = (uint32_t)pci_get_device(dev) << 16;
316 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
317 subvendor = pci_get_subvendor(dev);
318 /* Apply chip specific quirks. */
319 for (i = 0; sdhci_devices[i].model != 0; i++) {
320 if (sdhci_devices[i].model == model &&
321 (sdhci_devices[i].subvendor == 0xffff ||
322 sdhci_devices[i].subvendor == subvendor)) {
323 sc->quirks = sdhci_devices[i].quirks;
327 /* Some controllers need to be bumped into the right mode. */
328 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
329 sdhci_lower_frequency(dev);
330 /* Read slots info from PCI registers. */
331 slots = pci_read_config(dev, PCI_SLOT_INFO, 1);
332 bar = PCI_SLOT_INFO_FIRST_BAR(slots);
333 slots = PCI_SLOT_INFO_SLOTS(slots);
334 if (slots > 6 || bar > 5) {
335 device_printf(dev, "Incorrect slots information (%d, %d).\n",
342 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0)
344 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid,
345 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE));
346 if (sc->irq_res == NULL) {
347 device_printf(dev, "Can't allocate IRQ\n");
348 pci_release_msi(dev);
351 /* Scan all slots. */
352 for (i = 0; i < slots; i++) {
353 slot = &sc->slots[sc->num_slots];
355 /* Allocate memory. */
356 rid = PCIR_BAR(bar + i);
357 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
359 if (sc->mem_res[i] == NULL) {
361 "Can't allocate memory for slot %d\n", i);
365 slot->quirks = sc->quirks;
367 if (sdhci_init_slot(dev, slot, i) != 0)
372 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots);
373 /* Activate the interrupt */
374 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE,
375 NULL, sdhci_pci_intr, sc, &sc->intrhand);
377 device_printf(dev, "Can't setup IRQ\n");
378 pci_enable_busmaster(dev);
379 /* Process cards detection. */
380 for (i = 0; i < sc->num_slots; i++)
381 sdhci_start_slot(&sc->slots[i]);
387 sdhci_pci_detach(device_t dev)
389 struct sdhci_pci_softc *sc = device_get_softc(dev);
392 bus_teardown_intr(dev, sc->irq_res, sc->intrhand);
393 bus_release_resource(dev, SYS_RES_IRQ,
394 rman_get_rid(sc->irq_res), sc->irq_res);
395 pci_release_msi(dev);
397 for (i = 0; i < sc->num_slots; i++) {
398 sdhci_cleanup_slot(&sc->slots[i]);
399 bus_release_resource(dev, SYS_RES_MEMORY,
400 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]);
402 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
403 sdhci_restore_frequency(dev);
408 sdhci_pci_shutdown(device_t dev)
410 struct sdhci_pci_softc *sc = device_get_softc(dev);
412 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
413 sdhci_restore_frequency(dev);
418 sdhci_pci_suspend(device_t dev)
420 struct sdhci_pci_softc *sc = device_get_softc(dev);
423 err = bus_generic_suspend(dev);
426 for (i = 0; i < sc->num_slots; i++)
427 sdhci_generic_suspend(&sc->slots[i]);
432 sdhci_pci_resume(device_t dev)
434 struct sdhci_pci_softc *sc = device_get_softc(dev);
437 for (i = 0; i < sc->num_slots; i++)
438 sdhci_generic_resume(&sc->slots[i]);
439 err = bus_generic_resume(dev);
442 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY)
443 sdhci_lower_frequency(dev);
448 sdhci_pci_intr(void *arg)
450 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg;
453 for (i = 0; i < sc->num_slots; i++)
454 sdhci_generic_intr(&sc->slots[i]);
457 static device_method_t sdhci_methods[] = {
459 DEVMETHOD(device_probe, sdhci_pci_probe),
460 DEVMETHOD(device_attach, sdhci_pci_attach),
461 DEVMETHOD(device_detach, sdhci_pci_detach),
462 DEVMETHOD(device_shutdown, sdhci_pci_shutdown),
463 DEVMETHOD(device_suspend, sdhci_pci_suspend),
464 DEVMETHOD(device_resume, sdhci_pci_resume),
467 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar),
468 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar),
471 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios),
472 DEVMETHOD(mmcbr_request, sdhci_generic_request),
473 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro),
474 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host),
475 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host),
477 /* SDHCI registers accessors */
478 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1),
479 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2),
480 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4),
481 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4),
482 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1),
483 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2),
484 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4),
485 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4),
490 static driver_t sdhci_pci_driver = {
493 sizeof(struct sdhci_pci_softc),
495 static devclass_t sdhci_pci_devclass;
497 DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL,
499 MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1);
500 MMC_DECLARE_BRIDGE(sdhci_pci);