2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_STATS
40 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
43 #define EFX_EV_QSTAT_INCR(_eep, _stat) \
45 (_eep)->ee_stat[_stat]++; \
46 _NOTE(CONSTANTCONDITION) \
49 #define EFX_EV_QSTAT_INCR(_eep, _stat)
53 static __checkReturn boolean_t
56 __in efx_qword_t *eqp,
57 __in const efx_ev_callbacks_t *eecp,
60 static __checkReturn boolean_t
63 __in efx_qword_t *eqp,
64 __in const efx_ev_callbacks_t *eecp,
67 static __checkReturn boolean_t
70 __in efx_qword_t *eqp,
71 __in const efx_ev_callbacks_t *eecp,
74 static __checkReturn boolean_t
77 __in efx_qword_t *eqp,
78 __in const efx_ev_callbacks_t *eecp,
81 static __checkReturn boolean_t
84 __in efx_qword_t *eqp,
85 __in const efx_ev_callbacks_t *eecp,
89 static __checkReturn efx_rc_t
92 __in uint32_t instance,
94 __in uint32_t timer_ns)
97 uint8_t payload[MAX(MC_CMD_SET_EVQ_TMR_IN_LEN,
98 MC_CMD_SET_EVQ_TMR_OUT_LEN)];
101 (void) memset(payload, 0, sizeof (payload));
102 req.emr_cmd = MC_CMD_SET_EVQ_TMR;
103 req.emr_in_buf = payload;
104 req.emr_in_length = MC_CMD_SET_EVQ_TMR_IN_LEN;
105 req.emr_out_buf = payload;
106 req.emr_out_length = MC_CMD_SET_EVQ_TMR_OUT_LEN;
108 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_INSTANCE, instance);
109 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_LOAD_REQ_NS, timer_ns);
110 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_RELOAD_REQ_NS, timer_ns);
111 MCDI_IN_SET_DWORD(req, SET_EVQ_TMR_IN_TMR_MODE, mode);
113 efx_mcdi_execute(enp, &req);
115 if (req.emr_rc != 0) {
120 if (req.emr_out_length_used < MC_CMD_SET_EVQ_TMR_OUT_LEN) {
130 EFSYS_PROBE1(fail1, efx_rc_t, rc);
135 static __checkReturn efx_rc_t
138 __in unsigned int instance,
139 __in efsys_mem_t *esmp,
144 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
147 MAX(MC_CMD_INIT_EVQ_IN_LEN(EFX_EVQ_NBUFS(EFX_EVQ_MAXNEVS)),
148 MC_CMD_INIT_EVQ_OUT_LEN)];
149 efx_qword_t *dma_addr;
153 int supports_rx_batching;
156 npages = EFX_EVQ_NBUFS(nevs);
157 if (MC_CMD_INIT_EVQ_IN_LEN(npages) > MC_CMD_INIT_EVQ_IN_LENMAX) {
162 (void) memset(payload, 0, sizeof (payload));
163 req.emr_cmd = MC_CMD_INIT_EVQ;
164 req.emr_in_buf = payload;
165 req.emr_in_length = MC_CMD_INIT_EVQ_IN_LEN(npages);
166 req.emr_out_buf = payload;
167 req.emr_out_length = MC_CMD_INIT_EVQ_OUT_LEN;
169 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_SIZE, nevs);
170 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_INSTANCE, instance);
171 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_IRQ_NUM, irq);
174 * On Huntington RX and TX event batching can only be requested
175 * together (even if the datapath firmware doesn't actually support RX
177 * Cut through is incompatible with RX batching and so enabling cut
178 * through disables RX batching (but it does not affect TX batching).
180 * So always enable RX and TX event batching, and enable cut through
181 * if RX event batching isn't supported (i.e. on low latency firmware).
183 supports_rx_batching = enp->en_nic_cfg.enc_rx_batching_enabled ? 1 : 0;
184 MCDI_IN_POPULATE_DWORD_6(req, INIT_EVQ_IN_FLAGS,
185 INIT_EVQ_IN_FLAG_INTERRUPTING, 1,
186 INIT_EVQ_IN_FLAG_RPTR_DOS, 0,
187 INIT_EVQ_IN_FLAG_INT_ARMD, 0,
188 INIT_EVQ_IN_FLAG_CUT_THRU, !supports_rx_batching,
189 INIT_EVQ_IN_FLAG_RX_MERGE, 1,
190 INIT_EVQ_IN_FLAG_TX_MERGE, 1);
193 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
194 MC_CMD_INIT_EVQ_IN_TMR_MODE_DIS);
195 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, 0);
196 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, 0);
200 /* Calculate the timer value in quanta */
201 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
203 /* Moderation value is base 0 so we need to deduct 1 */
207 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_MODE,
208 MC_CMD_INIT_EVQ_IN_TMR_INT_HLDOFF);
209 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_LOAD, timer_val);
210 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_TMR_RELOAD, timer_val);
213 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_MODE,
214 MC_CMD_INIT_EVQ_IN_COUNT_MODE_DIS);
215 MCDI_IN_SET_DWORD(req, INIT_EVQ_IN_COUNT_THRSHLD, 0);
217 dma_addr = MCDI_IN2(req, efx_qword_t, INIT_EVQ_IN_DMA_ADDR);
218 addr = EFSYS_MEM_ADDR(esmp);
220 for (i = 0; i < npages; i++) {
221 EFX_POPULATE_QWORD_2(*dma_addr,
222 EFX_DWORD_1, (uint32_t)(addr >> 32),
223 EFX_DWORD_0, (uint32_t)(addr & 0xffffffff));
226 addr += EFX_BUF_SIZE;
229 efx_mcdi_execute(enp, &req);
231 if (req.emr_rc != 0) {
236 if (req.emr_out_length_used < MC_CMD_INIT_EVQ_OUT_LEN) {
241 /* NOTE: ignore the returned IRQ param as firmware does not set it. */
250 EFSYS_PROBE1(fail1, efx_rc_t, rc);
255 static __checkReturn efx_rc_t
258 __in uint32_t instance)
261 uint8_t payload[MAX(MC_CMD_FINI_EVQ_IN_LEN,
262 MC_CMD_FINI_EVQ_OUT_LEN)];
265 (void) memset(payload, 0, sizeof (payload));
266 req.emr_cmd = MC_CMD_FINI_EVQ;
267 req.emr_in_buf = payload;
268 req.emr_in_length = MC_CMD_FINI_EVQ_IN_LEN;
269 req.emr_out_buf = payload;
270 req.emr_out_length = MC_CMD_FINI_EVQ_OUT_LEN;
272 MCDI_IN_SET_DWORD(req, FINI_EVQ_IN_INSTANCE, instance);
274 efx_mcdi_execute_quiet(enp, &req);
276 if (req.emr_rc != 0) {
284 EFSYS_PROBE1(fail1, efx_rc_t, rc);
291 __checkReturn efx_rc_t
295 _NOTE(ARGUNUSED(enp))
303 _NOTE(ARGUNUSED(enp))
306 __checkReturn efx_rc_t
309 __in unsigned int index,
310 __in efsys_mem_t *esmp,
316 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
320 _NOTE(ARGUNUSED(id)) /* buftbl id managed by MC */
321 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
322 EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
324 if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
329 if (index >= encp->enc_evq_limit) {
334 if (us > encp->enc_evq_timer_max_us) {
339 /* Set up the handler table */
340 eep->ee_rx = ef10_ev_rx;
341 eep->ee_tx = ef10_ev_tx;
342 eep->ee_driver = ef10_ev_driver;
343 eep->ee_drv_gen = ef10_ev_drv_gen;
344 eep->ee_mcdi = ef10_ev_mcdi;
346 /* Set up the event queue */
347 irq = index; /* INIT_EVQ expects function-relative vector number */
350 * Interrupts may be raised for events immediately after the queue is
351 * created. See bug58606.
353 if ((rc = efx_mcdi_init_evq(enp, index, esmp, n, irq, us)) != 0)
365 EFSYS_PROBE1(fail1, efx_rc_t, rc);
374 efx_nic_t *enp = eep->ee_enp;
376 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
377 enp->en_family == EFX_FAMILY_MEDFORD);
379 (void) efx_mcdi_fini_evq(eep->ee_enp, eep->ee_index);
382 __checkReturn efx_rc_t
385 __in unsigned int count)
387 efx_nic_t *enp = eep->ee_enp;
391 rptr = count & eep->ee_mask;
393 if (enp->en_nic_cfg.enc_bug35388_workaround) {
394 EFX_STATIC_ASSERT(EFX_EVQ_MINNEVS >
395 (1 << ERF_DD_EVQ_IND_RPTR_WIDTH));
396 EFX_STATIC_ASSERT(EFX_EVQ_MAXNEVS <
397 (1 << 2 * ERF_DD_EVQ_IND_RPTR_WIDTH));
399 EFX_POPULATE_DWORD_2(dword,
400 ERF_DD_EVQ_IND_RPTR_FLAGS,
401 EFE_DD_EVQ_IND_RPTR_FLAGS_HIGH,
403 (rptr >> ERF_DD_EVQ_IND_RPTR_WIDTH));
404 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
407 EFX_POPULATE_DWORD_2(dword,
408 ERF_DD_EVQ_IND_RPTR_FLAGS,
409 EFE_DD_EVQ_IND_RPTR_FLAGS_LOW,
411 rptr & ((1 << ERF_DD_EVQ_IND_RPTR_WIDTH) - 1));
412 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT, eep->ee_index,
415 EFX_POPULATE_DWORD_1(dword, ERF_DZ_EVQ_RPTR, rptr);
416 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_RPTR_REG, eep->ee_index,
423 static __checkReturn efx_rc_t
424 efx_mcdi_driver_event(
427 __in efx_qword_t data)
430 uint8_t payload[MAX(MC_CMD_DRIVER_EVENT_IN_LEN,
431 MC_CMD_DRIVER_EVENT_OUT_LEN)];
434 req.emr_cmd = MC_CMD_DRIVER_EVENT;
435 req.emr_in_buf = payload;
436 req.emr_in_length = MC_CMD_DRIVER_EVENT_IN_LEN;
437 req.emr_out_buf = payload;
438 req.emr_out_length = MC_CMD_DRIVER_EVENT_OUT_LEN;
440 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_EVQ, evq);
442 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_LO,
443 EFX_QWORD_FIELD(data, EFX_DWORD_0));
444 MCDI_IN_SET_DWORD(req, DRIVER_EVENT_IN_DATA_HI,
445 EFX_QWORD_FIELD(data, EFX_DWORD_1));
447 efx_mcdi_execute(enp, &req);
449 if (req.emr_rc != 0) {
457 EFSYS_PROBE1(fail1, efx_rc_t, rc);
467 efx_nic_t *enp = eep->ee_enp;
470 EFX_POPULATE_QWORD_3(event,
471 ESF_DZ_DRV_CODE, ESE_DZ_EV_CODE_DRV_GEN_EV,
472 ESF_DZ_DRV_SUB_CODE, 0,
473 ESF_DZ_DRV_SUB_DATA_DW0, (uint32_t)data);
475 (void) efx_mcdi_driver_event(enp, eep->ee_index, event);
478 __checkReturn efx_rc_t
481 __in unsigned int us)
483 efx_nic_t *enp = eep->ee_enp;
484 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
486 uint32_t timer_ns, timer_val, mode;
489 /* Check that hardware and MCDI use the same timer MODE values */
490 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_DIS ==
491 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_DIS);
492 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_IMMED_START ==
493 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_IMMED_START);
494 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_TRIG_START ==
495 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_TRIG_START);
496 EFX_STATIC_ASSERT(FFE_CZ_TIMER_MODE_INT_HLDOFF ==
497 MC_CMD_SET_EVQ_TMR_IN_TIMER_MODE_INT_HLDOFF);
499 if (us > encp->enc_evq_timer_max_us) {
504 /* If the value is zero then disable the timer */
507 mode = FFE_CZ_TIMER_MODE_DIS;
509 timer_ns = us * 1000u;
510 mode = FFE_CZ_TIMER_MODE_INT_HLDOFF;
513 if (encp->enc_bug61265_workaround) {
514 rc = efx_mcdi_set_evq_tmr(enp, eep->ee_index, mode, timer_ns);
518 /* Calculate the timer value in quanta */
519 timer_val = timer_ns / encp->enc_evq_timer_quantum_ns;
521 /* Moderation value is base 0 so we need to deduct 1 */
525 if (encp->enc_bug35388_workaround) {
526 EFX_POPULATE_DWORD_3(dword,
527 ERF_DD_EVQ_IND_TIMER_FLAGS,
528 EFE_DD_EVQ_IND_TIMER_FLAGS,
529 ERF_DD_EVQ_IND_TIMER_MODE, mode,
530 ERF_DD_EVQ_IND_TIMER_VAL, timer_val);
531 EFX_BAR_TBL_WRITED(enp, ER_DD_EVQ_INDIRECT,
532 eep->ee_index, &dword, 0);
534 EFX_POPULATE_DWORD_2(dword,
535 ERF_DZ_TC_TIMER_MODE, mode,
536 ERF_DZ_TC_TIMER_VAL, timer_val);
537 EFX_BAR_TBL_WRITED(enp, ER_DZ_EVQ_TMR_REG,
538 eep->ee_index, &dword, 0);
547 EFSYS_PROBE1(fail1, efx_rc_t, rc);
555 ef10_ev_qstats_update(
557 __inout_ecount(EV_NQSTATS) efsys_stat_t *stat)
561 for (id = 0; id < EV_NQSTATS; id++) {
562 efsys_stat_t *essp = &stat[id];
564 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
565 eep->ee_stat[id] = 0;
568 #endif /* EFSYS_OPT_QSTATS */
571 static __checkReturn boolean_t
574 __in efx_qword_t *eqp,
575 __in const efx_ev_callbacks_t *eecp,
578 efx_nic_t *enp = eep->ee_enp;
582 uint32_t eth_tag_class;
585 uint32_t next_read_lbits;
588 boolean_t should_abort;
589 efx_evq_rxq_state_t *eersp;
590 unsigned int desc_count;
591 unsigned int last_used_id;
593 EFX_EV_QSTAT_INCR(eep, EV_RX);
595 /* Discard events after RXQ/TXQ errors */
596 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
599 /* Basic packet information */
600 size = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_BYTES);
601 next_read_lbits = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DSC_PTR_LBITS);
602 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_QLABEL);
603 eth_tag_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ETH_TAG_CLASS);
604 mac_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_MAC_CLASS);
605 l3_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L3_CLASS);
606 l4_class = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_L4_CLASS);
607 cont = EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_CONT);
609 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_DROP_EVENT) != 0) {
610 /* Drop this event */
617 * This may be part of a scattered frame, or it may be a
618 * truncated frame if scatter is disabled on this RXQ.
619 * Overlength frames can be received if e.g. a VF is configured
620 * for 1500 MTU but connected to a port set to 9000 MTU
622 * FIXME: There is not yet any driver that supports scatter on
623 * Huntington. Scatter support is required for OSX.
625 flags |= EFX_PKT_CONT;
628 if (mac_class == ESE_DZ_MAC_CLASS_UCAST)
629 flags |= EFX_PKT_UNICAST;
631 /* Increment the count of descriptors read */
632 eersp = &eep->ee_rxq_state[label];
633 desc_count = (next_read_lbits - eersp->eers_rx_read_ptr) &
634 EFX_MASK32(ESF_DZ_RX_DSC_PTR_LBITS);
635 eersp->eers_rx_read_ptr += desc_count;
638 * FIXME: add error checking to make sure this a batched event.
639 * This could also be an aborted scatter, see Bug36629.
641 if (desc_count > 1) {
642 EFX_EV_QSTAT_INCR(eep, EV_RX_BATCH);
643 flags |= EFX_PKT_PREFIX_LEN;
646 /* Calculate the index of the the last descriptor consumed */
647 last_used_id = (eersp->eers_rx_read_ptr - 1) & eersp->eers_rx_mask;
649 /* Check for errors that invalidate checksum and L3/L4 fields */
650 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECC_ERR) != 0) {
651 /* RX frame truncated (error flag is misnamed) */
652 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
653 flags |= EFX_DISCARD;
656 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_ECRC_ERR) != 0) {
657 /* Bad Ethernet frame CRC */
658 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
659 flags |= EFX_DISCARD;
662 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_PARSE_INCOMPLETE)) {
664 * Hardware parse failed, due to malformed headers
665 * or headers that are too long for the parser.
666 * Headers and checksums must be validated by the host.
668 // TODO: EFX_EV_QSTAT_INCR(eep, EV_RX_PARSE_INCOMPLETE);
672 if ((eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN1) ||
673 (eth_tag_class == ESE_DZ_ETH_TAG_CLASS_VLAN2)) {
674 flags |= EFX_PKT_VLAN_TAGGED;
678 case ESE_DZ_L3_CLASS_IP4:
679 case ESE_DZ_L3_CLASS_IP4_FRAG:
680 flags |= EFX_PKT_IPV4;
681 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_IPCKSUM_ERR)) {
682 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
684 flags |= EFX_CKSUM_IPV4;
687 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
688 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
689 flags |= EFX_PKT_TCP;
690 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
691 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
692 flags |= EFX_PKT_UDP;
694 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
698 case ESE_DZ_L3_CLASS_IP6:
699 case ESE_DZ_L3_CLASS_IP6_FRAG:
700 flags |= EFX_PKT_IPV6;
702 if (l4_class == ESE_DZ_L4_CLASS_TCP) {
703 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
704 flags |= EFX_PKT_TCP;
705 } else if (l4_class == ESE_DZ_L4_CLASS_UDP) {
706 EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
707 flags |= EFX_PKT_UDP;
709 EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
714 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
718 if (flags & (EFX_PKT_TCP | EFX_PKT_UDP)) {
719 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_RX_TCPUDP_CKSUM_ERR)) {
720 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
722 flags |= EFX_CKSUM_TCPUDP;
727 /* If we're not discarding the packet then it is ok */
728 if (~flags & EFX_DISCARD)
729 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
731 EFSYS_ASSERT(eecp->eec_rx != NULL);
732 should_abort = eecp->eec_rx(arg, label, last_used_id, size, flags);
734 return (should_abort);
737 static __checkReturn boolean_t
740 __in efx_qword_t *eqp,
741 __in const efx_ev_callbacks_t *eecp,
744 efx_nic_t *enp = eep->ee_enp;
747 boolean_t should_abort;
749 EFX_EV_QSTAT_INCR(eep, EV_TX);
751 /* Discard events after RXQ/TXQ errors */
752 if (enp->en_reset_flags & (EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR))
755 if (EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DROP_EVENT) != 0) {
756 /* Drop this event */
760 /* Per-packet TX completion (was per-descriptor for Falcon/Siena) */
761 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_DESCR_INDX);
762 label = EFX_QWORD_FIELD(*eqp, ESF_DZ_TX_QLABEL);
764 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
766 EFSYS_ASSERT(eecp->eec_tx != NULL);
767 should_abort = eecp->eec_tx(arg, label, id);
769 return (should_abort);
772 static __checkReturn boolean_t
775 __in efx_qword_t *eqp,
776 __in const efx_ev_callbacks_t *eecp,
780 boolean_t should_abort;
782 EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
783 should_abort = B_FALSE;
785 code = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_CODE);
787 case ESE_DZ_DRV_TIMER_EV: {
790 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_TMR_ID);
792 EFSYS_ASSERT(eecp->eec_timer != NULL);
793 should_abort = eecp->eec_timer(arg, id);
797 case ESE_DZ_DRV_WAKE_UP_EV: {
800 id = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_EVQ_ID);
802 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
803 should_abort = eecp->eec_wake_up(arg, id);
807 case ESE_DZ_DRV_START_UP_EV:
808 EFSYS_ASSERT(eecp->eec_initialized != NULL);
809 should_abort = eecp->eec_initialized(arg);
813 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
814 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
815 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
819 return (should_abort);
822 static __checkReturn boolean_t
825 __in efx_qword_t *eqp,
826 __in const efx_ev_callbacks_t *eecp,
830 boolean_t should_abort;
832 EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
833 should_abort = B_FALSE;
835 data = EFX_QWORD_FIELD(*eqp, ESF_DZ_DRV_SUB_DATA_DW0);
836 if (data >= ((uint32_t)1 << 16)) {
837 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
838 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
839 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
844 EFSYS_ASSERT(eecp->eec_software != NULL);
845 should_abort = eecp->eec_software(arg, (uint16_t)data);
847 return (should_abort);
850 static __checkReturn boolean_t
853 __in efx_qword_t *eqp,
854 __in const efx_ev_callbacks_t *eecp,
857 efx_nic_t *enp = eep->ee_enp;
859 boolean_t should_abort = B_FALSE;
861 EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
863 code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
865 case MCDI_EVENT_CODE_BADSSERT:
866 efx_mcdi_ev_death(enp, EINTR);
869 case MCDI_EVENT_CODE_CMDDONE:
871 MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
872 MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
873 MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
876 #if EFSYS_OPT_MCDI_PROXY_AUTH
877 case MCDI_EVENT_CODE_PROXY_RESPONSE:
879 * This event notifies a function that an authorization request
880 * has been processed. If the request was authorized then the
881 * function can now re-send the original MCDI request.
882 * See SF-113652-SW "SR-IOV Proxied Network Access Control".
884 efx_mcdi_ev_proxy_response(enp,
885 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_HANDLE),
886 MCDI_EV_FIELD(eqp, PROXY_RESPONSE_RC));
888 #endif /* EFSYS_OPT_MCDI_PROXY_AUTH */
890 case MCDI_EVENT_CODE_LINKCHANGE: {
891 efx_link_mode_t link_mode;
893 ef10_phy_link_ev(enp, eqp, &link_mode);
894 should_abort = eecp->eec_link_change(arg, link_mode);
898 case MCDI_EVENT_CODE_SENSOREVT: {
899 #if EFSYS_OPT_MON_STATS
901 efx_mon_stat_value_t value;
904 /* Decode monitor stat for MCDI sensor (if supported) */
905 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0) {
906 /* Report monitor stat change */
907 should_abort = eecp->eec_monitor(arg, id, value);
908 } else if (rc == ENOTSUP) {
909 should_abort = eecp->eec_exception(arg,
910 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
911 MCDI_EV_FIELD(eqp, DATA));
913 EFSYS_ASSERT(rc == ENODEV); /* Wrong port */
919 case MCDI_EVENT_CODE_SCHEDERR:
920 /* Informational only */
923 case MCDI_EVENT_CODE_REBOOT:
924 /* Falcon/Siena only (should not been seen with Huntington). */
925 efx_mcdi_ev_death(enp, EIO);
928 case MCDI_EVENT_CODE_MC_REBOOT:
929 /* MC_REBOOT event is used for Huntington (EF10) and later. */
930 efx_mcdi_ev_death(enp, EIO);
933 case MCDI_EVENT_CODE_MAC_STATS_DMA:
934 #if EFSYS_OPT_MAC_STATS
935 if (eecp->eec_mac_stats != NULL) {
936 eecp->eec_mac_stats(arg,
937 MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
942 case MCDI_EVENT_CODE_FWALERT: {
943 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
945 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
946 should_abort = eecp->eec_exception(arg,
947 EFX_EXCEPTION_FWALERT_SRAM,
948 MCDI_EV_FIELD(eqp, FWALERT_DATA));
950 should_abort = eecp->eec_exception(arg,
951 EFX_EXCEPTION_UNKNOWN_FWALERT,
952 MCDI_EV_FIELD(eqp, DATA));
956 case MCDI_EVENT_CODE_TX_ERR: {
958 * After a TXQ error is detected, firmware sends a TX_ERR event.
959 * This may be followed by TX completions (which we discard),
960 * and then finally by a TX_FLUSH event. Firmware destroys the
961 * TXQ automatically after sending the TX_FLUSH event.
963 enp->en_reset_flags |= EFX_RESET_TXQ_ERR;
965 EFSYS_PROBE2(tx_descq_err,
966 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
967 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
969 /* Inform the driver that a reset is required. */
970 eecp->eec_exception(arg, EFX_EXCEPTION_TX_ERROR,
971 MCDI_EV_FIELD(eqp, TX_ERR_DATA));
975 case MCDI_EVENT_CODE_TX_FLUSH: {
976 uint32_t txq_index = MCDI_EV_FIELD(eqp, TX_FLUSH_TXQ);
979 * EF10 firmware sends two TX_FLUSH events: one to the txq's
980 * event queue, and one to evq 0 (with TX_FLUSH_TO_DRIVER set).
981 * We want to wait for all completions, so ignore the events
982 * with TX_FLUSH_TO_DRIVER.
984 if (MCDI_EV_FIELD(eqp, TX_FLUSH_TO_DRIVER) != 0) {
985 should_abort = B_FALSE;
989 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
991 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
993 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
994 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
998 case MCDI_EVENT_CODE_RX_ERR: {
1000 * After an RXQ error is detected, firmware sends an RX_ERR
1001 * event. This may be followed by RX events (which we discard),
1002 * and then finally by an RX_FLUSH event. Firmware destroys the
1003 * RXQ automatically after sending the RX_FLUSH event.
1005 enp->en_reset_flags |= EFX_RESET_RXQ_ERR;
1007 EFSYS_PROBE2(rx_descq_err,
1008 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1009 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1011 /* Inform the driver that a reset is required. */
1012 eecp->eec_exception(arg, EFX_EXCEPTION_RX_ERROR,
1013 MCDI_EV_FIELD(eqp, RX_ERR_DATA));
1017 case MCDI_EVENT_CODE_RX_FLUSH: {
1018 uint32_t rxq_index = MCDI_EV_FIELD(eqp, RX_FLUSH_RXQ);
1021 * EF10 firmware sends two RX_FLUSH events: one to the rxq's
1022 * event queue, and one to evq 0 (with RX_FLUSH_TO_DRIVER set).
1023 * We want to wait for all completions, so ignore the events
1024 * with RX_FLUSH_TO_DRIVER.
1026 if (MCDI_EV_FIELD(eqp, RX_FLUSH_TO_DRIVER) != 0) {
1027 should_abort = B_FALSE;
1031 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
1033 EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
1035 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
1036 should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
1041 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
1042 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
1043 uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
1047 return (should_abort);
1051 ef10_ev_rxlabel_init(
1052 __in efx_evq_t *eep,
1053 __in efx_rxq_t *erp,
1054 __in unsigned int label)
1056 efx_evq_rxq_state_t *eersp;
1058 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1059 eersp = &eep->ee_rxq_state[label];
1061 EFSYS_ASSERT3U(eersp->eers_rx_mask, ==, 0);
1063 eersp->eers_rx_read_ptr = 0;
1064 eersp->eers_rx_mask = erp->er_mask;
1068 ef10_ev_rxlabel_fini(
1069 __in efx_evq_t *eep,
1070 __in unsigned int label)
1072 efx_evq_rxq_state_t *eersp;
1074 EFSYS_ASSERT3U(label, <, EFX_ARRAY_SIZE(eep->ee_rxq_state));
1075 eersp = &eep->ee_rxq_state[label];
1077 EFSYS_ASSERT3U(eersp->eers_rx_mask, !=, 0);
1079 eersp->eers_rx_read_ptr = 0;
1080 eersp->eers_rx_mask = 0;
1083 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */