2 * Copyright (c) 2012-2016 Solarflare Communications Inc.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are met:
8 * 1. Redistributions of source code must retain the above copyright notice,
9 * this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright notice,
11 * this list of conditions and the following disclaimer in the documentation
12 * and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
15 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
16 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
17 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
18 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
19 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
20 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
21 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
22 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
23 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
24 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 * The views and conclusions contained in the software and documentation are
27 * those of the authors and should not be interpreted as representing official
28 * policies, either expressed or implied, of the FreeBSD Project.
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
36 #if EFSYS_OPT_MON_MCDI
40 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
42 #include "ef10_tlv_layout.h"
44 __checkReturn efx_rc_t
45 efx_mcdi_get_port_assignment(
47 __out uint32_t *portp)
50 uint8_t payload[MAX(MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN,
51 MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN)];
54 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
55 enp->en_family == EFX_FAMILY_MEDFORD);
57 (void) memset(payload, 0, sizeof (payload));
58 req.emr_cmd = MC_CMD_GET_PORT_ASSIGNMENT;
59 req.emr_in_buf = payload;
60 req.emr_in_length = MC_CMD_GET_PORT_ASSIGNMENT_IN_LEN;
61 req.emr_out_buf = payload;
62 req.emr_out_length = MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN;
64 efx_mcdi_execute(enp, &req);
66 if (req.emr_rc != 0) {
71 if (req.emr_out_length_used < MC_CMD_GET_PORT_ASSIGNMENT_OUT_LEN) {
76 *portp = MCDI_OUT_DWORD(req, GET_PORT_ASSIGNMENT_OUT_PORT);
83 EFSYS_PROBE1(fail1, efx_rc_t, rc);
88 __checkReturn efx_rc_t
89 efx_mcdi_get_port_modes(
91 __out uint32_t *modesp,
92 __out_opt uint32_t *current_modep)
95 uint8_t payload[MAX(MC_CMD_GET_PORT_MODES_IN_LEN,
96 MC_CMD_GET_PORT_MODES_OUT_LEN)];
99 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
100 enp->en_family == EFX_FAMILY_MEDFORD);
102 (void) memset(payload, 0, sizeof (payload));
103 req.emr_cmd = MC_CMD_GET_PORT_MODES;
104 req.emr_in_buf = payload;
105 req.emr_in_length = MC_CMD_GET_PORT_MODES_IN_LEN;
106 req.emr_out_buf = payload;
107 req.emr_out_length = MC_CMD_GET_PORT_MODES_OUT_LEN;
109 efx_mcdi_execute(enp, &req);
111 if (req.emr_rc != 0) {
117 * Require only Modes and DefaultMode fields, unless the current mode
118 * was requested (CurrentMode field was added for Medford).
120 if (req.emr_out_length_used <
121 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST) {
125 if ((current_modep != NULL) && (req.emr_out_length_used <
126 MC_CMD_GET_PORT_MODES_OUT_CURRENT_MODE_OFST + 4)) {
131 *modesp = MCDI_OUT_DWORD(req, GET_PORT_MODES_OUT_MODES);
133 if (current_modep != NULL) {
134 *current_modep = MCDI_OUT_DWORD(req,
135 GET_PORT_MODES_OUT_CURRENT_MODE);
145 EFSYS_PROBE1(fail1, efx_rc_t, rc);
150 __checkReturn efx_rc_t
151 ef10_nic_get_port_mode_bandwidth(
152 __in uint32_t port_mode,
153 __out uint32_t *bandwidth_mbpsp)
159 case TLV_PORT_MODE_10G:
162 case TLV_PORT_MODE_10G_10G:
163 bandwidth = 10000 * 2;
165 case TLV_PORT_MODE_10G_10G_10G_10G:
166 case TLV_PORT_MODE_10G_10G_10G_10G_Q:
167 case TLV_PORT_MODE_10G_10G_10G_10G_Q2:
168 bandwidth = 10000 * 4;
170 case TLV_PORT_MODE_40G:
173 case TLV_PORT_MODE_40G_40G:
174 bandwidth = 40000 * 2;
176 case TLV_PORT_MODE_40G_10G_10G:
177 case TLV_PORT_MODE_10G_10G_40G:
178 bandwidth = 40000 + (10000 * 2);
185 *bandwidth_mbpsp = bandwidth;
190 EFSYS_PROBE1(fail1, efx_rc_t, rc);
195 static __checkReturn efx_rc_t
196 efx_mcdi_vadaptor_alloc(
198 __in uint32_t port_id)
201 uint8_t payload[MAX(MC_CMD_VADAPTOR_ALLOC_IN_LEN,
202 MC_CMD_VADAPTOR_ALLOC_OUT_LEN)];
205 EFSYS_ASSERT3U(enp->en_vport_id, ==, EVB_PORT_ID_NULL);
207 (void) memset(payload, 0, sizeof (payload));
208 req.emr_cmd = MC_CMD_VADAPTOR_ALLOC;
209 req.emr_in_buf = payload;
210 req.emr_in_length = MC_CMD_VADAPTOR_ALLOC_IN_LEN;
211 req.emr_out_buf = payload;
212 req.emr_out_length = MC_CMD_VADAPTOR_ALLOC_OUT_LEN;
214 MCDI_IN_SET_DWORD(req, VADAPTOR_ALLOC_IN_UPSTREAM_PORT_ID, port_id);
215 MCDI_IN_POPULATE_DWORD_1(req, VADAPTOR_ALLOC_IN_FLAGS,
216 VADAPTOR_ALLOC_IN_FLAG_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED,
217 enp->en_nic_cfg.enc_allow_set_mac_with_installed_filters ? 1 : 0);
219 efx_mcdi_execute(enp, &req);
221 if (req.emr_rc != 0) {
229 EFSYS_PROBE1(fail1, efx_rc_t, rc);
234 static __checkReturn efx_rc_t
235 efx_mcdi_vadaptor_free(
237 __in uint32_t port_id)
240 uint8_t payload[MAX(MC_CMD_VADAPTOR_FREE_IN_LEN,
241 MC_CMD_VADAPTOR_FREE_OUT_LEN)];
244 (void) memset(payload, 0, sizeof (payload));
245 req.emr_cmd = MC_CMD_VADAPTOR_FREE;
246 req.emr_in_buf = payload;
247 req.emr_in_length = MC_CMD_VADAPTOR_FREE_IN_LEN;
248 req.emr_out_buf = payload;
249 req.emr_out_length = MC_CMD_VADAPTOR_FREE_OUT_LEN;
251 MCDI_IN_SET_DWORD(req, VADAPTOR_FREE_IN_UPSTREAM_PORT_ID, port_id);
253 efx_mcdi_execute(enp, &req);
255 if (req.emr_rc != 0) {
263 EFSYS_PROBE1(fail1, efx_rc_t, rc);
268 __checkReturn efx_rc_t
269 efx_mcdi_get_mac_address_pf(
271 __out_ecount_opt(6) uint8_t mac_addrp[6])
274 uint8_t payload[MAX(MC_CMD_GET_MAC_ADDRESSES_IN_LEN,
275 MC_CMD_GET_MAC_ADDRESSES_OUT_LEN)];
278 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
279 enp->en_family == EFX_FAMILY_MEDFORD);
281 (void) memset(payload, 0, sizeof (payload));
282 req.emr_cmd = MC_CMD_GET_MAC_ADDRESSES;
283 req.emr_in_buf = payload;
284 req.emr_in_length = MC_CMD_GET_MAC_ADDRESSES_IN_LEN;
285 req.emr_out_buf = payload;
286 req.emr_out_length = MC_CMD_GET_MAC_ADDRESSES_OUT_LEN;
288 efx_mcdi_execute(enp, &req);
290 if (req.emr_rc != 0) {
295 if (req.emr_out_length_used < MC_CMD_GET_MAC_ADDRESSES_OUT_LEN) {
300 if (MCDI_OUT_DWORD(req, GET_MAC_ADDRESSES_OUT_MAC_COUNT) < 1) {
305 if (mac_addrp != NULL) {
308 addrp = MCDI_OUT2(req, uint8_t,
309 GET_MAC_ADDRESSES_OUT_MAC_ADDR_BASE);
311 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
321 EFSYS_PROBE1(fail1, efx_rc_t, rc);
326 __checkReturn efx_rc_t
327 efx_mcdi_get_mac_address_vf(
329 __out_ecount_opt(6) uint8_t mac_addrp[6])
332 uint8_t payload[MAX(MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN,
333 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX)];
336 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
337 enp->en_family == EFX_FAMILY_MEDFORD);
339 (void) memset(payload, 0, sizeof (payload));
340 req.emr_cmd = MC_CMD_VPORT_GET_MAC_ADDRESSES;
341 req.emr_in_buf = payload;
342 req.emr_in_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_IN_LEN;
343 req.emr_out_buf = payload;
344 req.emr_out_length = MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMAX;
346 MCDI_IN_SET_DWORD(req, VPORT_GET_MAC_ADDRESSES_IN_VPORT_ID,
347 EVB_PORT_ID_ASSIGNED);
349 efx_mcdi_execute(enp, &req);
351 if (req.emr_rc != 0) {
356 if (req.emr_out_length_used <
357 MC_CMD_VPORT_GET_MAC_ADDRESSES_OUT_LENMIN) {
362 if (MCDI_OUT_DWORD(req,
363 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR_COUNT) < 1) {
368 if (mac_addrp != NULL) {
371 addrp = MCDI_OUT2(req, uint8_t,
372 VPORT_GET_MAC_ADDRESSES_OUT_MACADDR);
374 EFX_MAC_ADDR_COPY(mac_addrp, addrp);
384 EFSYS_PROBE1(fail1, efx_rc_t, rc);
389 __checkReturn efx_rc_t
392 __out uint32_t *sys_freqp,
393 __out uint32_t *dpcpu_freqp)
396 uint8_t payload[MAX(MC_CMD_GET_CLOCK_IN_LEN,
397 MC_CMD_GET_CLOCK_OUT_LEN)];
400 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
401 enp->en_family == EFX_FAMILY_MEDFORD);
403 (void) memset(payload, 0, sizeof (payload));
404 req.emr_cmd = MC_CMD_GET_CLOCK;
405 req.emr_in_buf = payload;
406 req.emr_in_length = MC_CMD_GET_CLOCK_IN_LEN;
407 req.emr_out_buf = payload;
408 req.emr_out_length = MC_CMD_GET_CLOCK_OUT_LEN;
410 efx_mcdi_execute(enp, &req);
412 if (req.emr_rc != 0) {
417 if (req.emr_out_length_used < MC_CMD_GET_CLOCK_OUT_LEN) {
422 *sys_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_SYS_FREQ);
423 if (*sys_freqp == 0) {
427 *dpcpu_freqp = MCDI_OUT_DWORD(req, GET_CLOCK_OUT_DPCPU_FREQ);
428 if (*dpcpu_freqp == 0) {
442 EFSYS_PROBE1(fail1, efx_rc_t, rc);
447 __checkReturn efx_rc_t
448 efx_mcdi_get_vector_cfg(
450 __out_opt uint32_t *vec_basep,
451 __out_opt uint32_t *pf_nvecp,
452 __out_opt uint32_t *vf_nvecp)
455 uint8_t payload[MAX(MC_CMD_GET_VECTOR_CFG_IN_LEN,
456 MC_CMD_GET_VECTOR_CFG_OUT_LEN)];
459 (void) memset(payload, 0, sizeof (payload));
460 req.emr_cmd = MC_CMD_GET_VECTOR_CFG;
461 req.emr_in_buf = payload;
462 req.emr_in_length = MC_CMD_GET_VECTOR_CFG_IN_LEN;
463 req.emr_out_buf = payload;
464 req.emr_out_length = MC_CMD_GET_VECTOR_CFG_OUT_LEN;
466 efx_mcdi_execute(enp, &req);
468 if (req.emr_rc != 0) {
473 if (req.emr_out_length_used < MC_CMD_GET_VECTOR_CFG_OUT_LEN) {
478 if (vec_basep != NULL)
479 *vec_basep = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VEC_BASE);
480 if (pf_nvecp != NULL)
481 *pf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_PF);
482 if (vf_nvecp != NULL)
483 *vf_nvecp = MCDI_OUT_DWORD(req, GET_VECTOR_CFG_OUT_VECS_PER_VF);
490 EFSYS_PROBE1(fail1, efx_rc_t, rc);
495 static __checkReturn efx_rc_t
496 efx_mcdi_get_capabilities(
498 __out uint32_t *flagsp,
499 __out uint32_t *flags2p)
502 uint8_t payload[MAX(MC_CMD_GET_CAPABILITIES_IN_LEN,
503 MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)];
506 (void) memset(payload, 0, sizeof (payload));
507 req.emr_cmd = MC_CMD_GET_CAPABILITIES;
508 req.emr_in_buf = payload;
509 req.emr_in_length = MC_CMD_GET_CAPABILITIES_IN_LEN;
510 req.emr_out_buf = payload;
511 req.emr_out_length = MC_CMD_GET_CAPABILITIES_V2_OUT_LEN;
513 efx_mcdi_execute(enp, &req);
515 if (req.emr_rc != 0) {
520 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_OUT_LEN) {
525 *flagsp = MCDI_OUT_DWORD(req, GET_CAPABILITIES_OUT_FLAGS1);
527 if (req.emr_out_length_used < MC_CMD_GET_CAPABILITIES_V2_OUT_LEN)
530 *flags2p = MCDI_OUT_DWORD(req, GET_CAPABILITIES_V2_OUT_FLAGS2);
537 EFSYS_PROBE1(fail1, efx_rc_t, rc);
543 static __checkReturn efx_rc_t
546 __in uint32_t min_vi_count,
547 __in uint32_t max_vi_count,
548 __out uint32_t *vi_basep,
549 __out uint32_t *vi_countp,
550 __out uint32_t *vi_shiftp)
553 uint8_t payload[MAX(MC_CMD_ALLOC_VIS_IN_LEN,
554 MC_CMD_ALLOC_VIS_OUT_LEN)];
557 if (vi_countp == NULL) {
562 (void) memset(payload, 0, sizeof (payload));
563 req.emr_cmd = MC_CMD_ALLOC_VIS;
564 req.emr_in_buf = payload;
565 req.emr_in_length = MC_CMD_ALLOC_VIS_IN_LEN;
566 req.emr_out_buf = payload;
567 req.emr_out_length = MC_CMD_ALLOC_VIS_OUT_LEN;
569 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MIN_VI_COUNT, min_vi_count);
570 MCDI_IN_SET_DWORD(req, ALLOC_VIS_IN_MAX_VI_COUNT, max_vi_count);
572 efx_mcdi_execute(enp, &req);
574 if (req.emr_rc != 0) {
579 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_OUT_LEN) {
584 *vi_basep = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_BASE);
585 *vi_countp = MCDI_OUT_DWORD(req, ALLOC_VIS_OUT_VI_COUNT);
587 /* Report VI_SHIFT if available (always zero for Huntington) */
588 if (req.emr_out_length_used < MC_CMD_ALLOC_VIS_EXT_OUT_LEN)
591 *vi_shiftp = MCDI_OUT_DWORD(req, ALLOC_VIS_EXT_OUT_VI_SHIFT);
600 EFSYS_PROBE1(fail1, efx_rc_t, rc);
606 static __checkReturn efx_rc_t
613 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_IN_LEN == 0);
614 EFX_STATIC_ASSERT(MC_CMD_FREE_VIS_OUT_LEN == 0);
616 req.emr_cmd = MC_CMD_FREE_VIS;
617 req.emr_in_buf = NULL;
618 req.emr_in_length = 0;
619 req.emr_out_buf = NULL;
620 req.emr_out_length = 0;
622 efx_mcdi_execute_quiet(enp, &req);
624 /* Ignore ELREADY (no allocated VIs, so nothing to free) */
625 if ((req.emr_rc != 0) && (req.emr_rc != EALREADY)) {
633 EFSYS_PROBE1(fail1, efx_rc_t, rc);
639 static __checkReturn efx_rc_t
640 efx_mcdi_alloc_piobuf(
642 __out efx_piobuf_handle_t *handlep)
645 uint8_t payload[MAX(MC_CMD_ALLOC_PIOBUF_IN_LEN,
646 MC_CMD_ALLOC_PIOBUF_OUT_LEN)];
649 if (handlep == NULL) {
654 (void) memset(payload, 0, sizeof (payload));
655 req.emr_cmd = MC_CMD_ALLOC_PIOBUF;
656 req.emr_in_buf = payload;
657 req.emr_in_length = MC_CMD_ALLOC_PIOBUF_IN_LEN;
658 req.emr_out_buf = payload;
659 req.emr_out_length = MC_CMD_ALLOC_PIOBUF_OUT_LEN;
661 efx_mcdi_execute_quiet(enp, &req);
663 if (req.emr_rc != 0) {
668 if (req.emr_out_length_used < MC_CMD_ALLOC_PIOBUF_OUT_LEN) {
673 *handlep = MCDI_OUT_DWORD(req, ALLOC_PIOBUF_OUT_PIOBUF_HANDLE);
682 EFSYS_PROBE1(fail1, efx_rc_t, rc);
687 static __checkReturn efx_rc_t
688 efx_mcdi_free_piobuf(
690 __in efx_piobuf_handle_t handle)
693 uint8_t payload[MAX(MC_CMD_FREE_PIOBUF_IN_LEN,
694 MC_CMD_FREE_PIOBUF_OUT_LEN)];
697 (void) memset(payload, 0, sizeof (payload));
698 req.emr_cmd = MC_CMD_FREE_PIOBUF;
699 req.emr_in_buf = payload;
700 req.emr_in_length = MC_CMD_FREE_PIOBUF_IN_LEN;
701 req.emr_out_buf = payload;
702 req.emr_out_length = MC_CMD_FREE_PIOBUF_OUT_LEN;
704 MCDI_IN_SET_DWORD(req, FREE_PIOBUF_IN_PIOBUF_HANDLE, handle);
706 efx_mcdi_execute_quiet(enp, &req);
708 if (req.emr_rc != 0) {
716 EFSYS_PROBE1(fail1, efx_rc_t, rc);
721 static __checkReturn efx_rc_t
722 efx_mcdi_link_piobuf(
724 __in uint32_t vi_index,
725 __in efx_piobuf_handle_t handle)
728 uint8_t payload[MAX(MC_CMD_LINK_PIOBUF_IN_LEN,
729 MC_CMD_LINK_PIOBUF_OUT_LEN)];
732 (void) memset(payload, 0, sizeof (payload));
733 req.emr_cmd = MC_CMD_LINK_PIOBUF;
734 req.emr_in_buf = payload;
735 req.emr_in_length = MC_CMD_LINK_PIOBUF_IN_LEN;
736 req.emr_out_buf = payload;
737 req.emr_out_length = MC_CMD_LINK_PIOBUF_OUT_LEN;
739 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_PIOBUF_HANDLE, handle);
740 MCDI_IN_SET_DWORD(req, LINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
742 efx_mcdi_execute(enp, &req);
744 if (req.emr_rc != 0) {
752 EFSYS_PROBE1(fail1, efx_rc_t, rc);
757 static __checkReturn efx_rc_t
758 efx_mcdi_unlink_piobuf(
760 __in uint32_t vi_index)
763 uint8_t payload[MAX(MC_CMD_UNLINK_PIOBUF_IN_LEN,
764 MC_CMD_UNLINK_PIOBUF_OUT_LEN)];
767 (void) memset(payload, 0, sizeof (payload));
768 req.emr_cmd = MC_CMD_UNLINK_PIOBUF;
769 req.emr_in_buf = payload;
770 req.emr_in_length = MC_CMD_UNLINK_PIOBUF_IN_LEN;
771 req.emr_out_buf = payload;
772 req.emr_out_length = MC_CMD_UNLINK_PIOBUF_OUT_LEN;
774 MCDI_IN_SET_DWORD(req, UNLINK_PIOBUF_IN_TXQ_INSTANCE, vi_index);
776 efx_mcdi_execute_quiet(enp, &req);
778 if (req.emr_rc != 0) {
786 EFSYS_PROBE1(fail1, efx_rc_t, rc);
792 ef10_nic_alloc_piobufs(
794 __in uint32_t max_piobuf_count)
796 efx_piobuf_handle_t *handlep;
799 EFSYS_ASSERT3U(max_piobuf_count, <=,
800 EFX_ARRAY_SIZE(enp->en_arch.ef10.ena_piobuf_handle));
802 enp->en_arch.ef10.ena_piobuf_count = 0;
804 for (i = 0; i < max_piobuf_count; i++) {
805 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
807 if (efx_mcdi_alloc_piobuf(enp, handlep) != 0)
810 enp->en_arch.ef10.ena_pio_alloc_map[i] = 0;
811 enp->en_arch.ef10.ena_piobuf_count++;
817 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
818 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
820 efx_mcdi_free_piobuf(enp, *handlep);
821 *handlep = EFX_PIOBUF_HANDLE_INVALID;
823 enp->en_arch.ef10.ena_piobuf_count = 0;
828 ef10_nic_free_piobufs(
831 efx_piobuf_handle_t *handlep;
834 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
835 handlep = &enp->en_arch.ef10.ena_piobuf_handle[i];
837 efx_mcdi_free_piobuf(enp, *handlep);
838 *handlep = EFX_PIOBUF_HANDLE_INVALID;
840 enp->en_arch.ef10.ena_piobuf_count = 0;
843 /* Sub-allocate a block from a piobuf */
844 __checkReturn efx_rc_t
846 __inout efx_nic_t *enp,
847 __out uint32_t *bufnump,
848 __out efx_piobuf_handle_t *handlep,
849 __out uint32_t *blknump,
850 __out uint32_t *offsetp,
853 efx_nic_cfg_t *encp = &enp->en_nic_cfg;
854 efx_drv_cfg_t *edcp = &enp->en_drv_cfg;
855 uint32_t blk_per_buf;
859 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
860 enp->en_family == EFX_FAMILY_MEDFORD);
861 EFSYS_ASSERT(bufnump);
862 EFSYS_ASSERT(handlep);
863 EFSYS_ASSERT(blknump);
864 EFSYS_ASSERT(offsetp);
867 if ((edcp->edc_pio_alloc_size == 0) ||
868 (enp->en_arch.ef10.ena_piobuf_count == 0)) {
872 blk_per_buf = encp->enc_piobuf_size / edcp->edc_pio_alloc_size;
874 for (buf = 0; buf < enp->en_arch.ef10.ena_piobuf_count; buf++) {
875 uint32_t *map = &enp->en_arch.ef10.ena_pio_alloc_map[buf];
880 EFSYS_ASSERT3U(blk_per_buf, <=, (8 * sizeof (*map)));
881 for (blk = 0; blk < blk_per_buf; blk++) {
882 if ((*map & (1u << blk)) == 0) {
892 *handlep = enp->en_arch.ef10.ena_piobuf_handle[buf];
895 *sizep = edcp->edc_pio_alloc_size;
896 *offsetp = blk * (*sizep);
903 EFSYS_PROBE1(fail1, efx_rc_t, rc);
908 /* Free a piobuf sub-allocated block */
909 __checkReturn efx_rc_t
911 __inout efx_nic_t *enp,
912 __in uint32_t bufnum,
913 __in uint32_t blknum)
918 if ((bufnum >= enp->en_arch.ef10.ena_piobuf_count) ||
919 (blknum >= (8 * sizeof (*map)))) {
924 map = &enp->en_arch.ef10.ena_pio_alloc_map[bufnum];
925 if ((*map & (1u << blknum)) == 0) {
929 *map &= ~(1u << blknum);
936 EFSYS_PROBE1(fail1, efx_rc_t, rc);
941 __checkReturn efx_rc_t
943 __inout efx_nic_t *enp,
944 __in uint32_t vi_index,
945 __in efx_piobuf_handle_t handle)
947 return (efx_mcdi_link_piobuf(enp, vi_index, handle));
950 __checkReturn efx_rc_t
952 __inout efx_nic_t *enp,
953 __in uint32_t vi_index)
955 return (efx_mcdi_unlink_piobuf(enp, vi_index));
958 __checkReturn efx_rc_t
959 ef10_get_datapath_caps(
962 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
967 if ((rc = efx_mcdi_get_capabilities(enp, &flags, &flags2)) != 0)
970 #define CAP_FLAG(flags1, field) \
971 ((flags1) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
973 #define CAP_FLAG2(flags2, field) \
974 ((flags2) & (1 << (MC_CMD_GET_CAPABILITIES_V2_OUT_ ## field ## _LBN)))
977 * Huntington RXDP firmware inserts a 0 or 14 byte prefix.
978 * We only support the 14 byte prefix here.
980 if (CAP_FLAG(flags, RX_PREFIX_LEN_14) == 0) {
984 encp->enc_rx_prefix_size = 14;
986 /* Check if the firmware supports TSO */
987 encp->enc_fw_assisted_tso_enabled =
988 CAP_FLAG(flags, TX_TSO) ? B_TRUE : B_FALSE;
990 /* Check if the firmware supports FATSOv2 */
991 encp->enc_fw_assisted_tso_v2_enabled =
992 CAP_FLAG2(flags2, TX_TSO_V2) ? B_TRUE : B_FALSE;
994 /* Check if the firmware has vadapter/vport/vswitch support */
995 encp->enc_datapath_cap_evb =
996 CAP_FLAG(flags, EVB) ? B_TRUE : B_FALSE;
998 /* Check if the firmware supports VLAN insertion */
999 encp->enc_hw_tx_insert_vlan_enabled =
1000 CAP_FLAG(flags, TX_VLAN_INSERTION) ? B_TRUE : B_FALSE;
1002 /* Check if the firmware supports RX event batching */
1003 encp->enc_rx_batching_enabled =
1004 CAP_FLAG(flags, RX_BATCHING) ? B_TRUE : B_FALSE;
1007 * Even if batching isn't reported as supported, we may still get
1010 encp->enc_rx_batch_max = 16;
1012 /* Check if the firmware supports disabling scatter on RXQs */
1013 encp->enc_rx_disable_scatter_supported =
1014 CAP_FLAG(flags, RX_DISABLE_SCATTER) ? B_TRUE : B_FALSE;
1016 /* Check if the firmware supports set mac with running filters */
1017 encp->enc_allow_set_mac_with_installed_filters =
1018 CAP_FLAG(flags, VADAPTOR_PERMIT_SET_MAC_WHEN_FILTERS_INSTALLED) ?
1022 * Check if firmware supports the extended MC_CMD_SET_MAC, which allows
1023 * specifying which parameters to configure.
1025 encp->enc_enhanced_set_mac_supported =
1026 CAP_FLAG(flags, SET_MAC_ENHANCED) ? B_TRUE : B_FALSE;
1036 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1042 #define EF10_LEGACY_PF_PRIVILEGE_MASK \
1043 (MC_CMD_PRIVILEGE_MASK_IN_GRP_ADMIN | \
1044 MC_CMD_PRIVILEGE_MASK_IN_GRP_LINK | \
1045 MC_CMD_PRIVILEGE_MASK_IN_GRP_ONLOAD | \
1046 MC_CMD_PRIVILEGE_MASK_IN_GRP_PTP | \
1047 MC_CMD_PRIVILEGE_MASK_IN_GRP_INSECURE_FILTERS | \
1048 MC_CMD_PRIVILEGE_MASK_IN_GRP_MAC_SPOOFING | \
1049 MC_CMD_PRIVILEGE_MASK_IN_GRP_UNICAST | \
1050 MC_CMD_PRIVILEGE_MASK_IN_GRP_MULTICAST | \
1051 MC_CMD_PRIVILEGE_MASK_IN_GRP_BROADCAST | \
1052 MC_CMD_PRIVILEGE_MASK_IN_GRP_ALL_MULTICAST | \
1053 MC_CMD_PRIVILEGE_MASK_IN_GRP_PROMISCUOUS)
1055 #define EF10_LEGACY_VF_PRIVILEGE_MASK 0
1058 __checkReturn efx_rc_t
1059 ef10_get_privilege_mask(
1060 __in efx_nic_t *enp,
1061 __out uint32_t *maskp)
1063 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1067 if ((rc = efx_mcdi_privilege_mask(enp, encp->enc_pf, encp->enc_vf,
1072 /* Fallback for old firmware without privilege mask support */
1073 if (EFX_PCI_FUNCTION_IS_PF(encp)) {
1074 /* Assume PF has admin privilege */
1075 mask = EF10_LEGACY_PF_PRIVILEGE_MASK;
1077 /* VF is always unprivileged by default */
1078 mask = EF10_LEGACY_VF_PRIVILEGE_MASK;
1087 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1094 * The external port mapping is a one-based numbering of the external
1095 * connectors on the board. It does not distinguish off-board separated
1096 * outputs such as multi-headed cables.
1097 * The number of ports that map to each external port connector
1098 * on the board is determined by the chip family and the port modes to
1099 * which the NIC can be configured. The mapping table lists modes with
1100 * port numbering requirements in increasing order.
1103 efx_family_t family;
1104 uint32_t modes_mask;
1106 } __ef10_external_port_mappings[] = {
1107 /* Supported modes requiring 1 output per port */
1109 EFX_FAMILY_HUNTINGTON,
1110 (1 << TLV_PORT_MODE_10G) |
1111 (1 << TLV_PORT_MODE_10G_10G) |
1112 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1117 (1 << TLV_PORT_MODE_10G) |
1118 (1 << TLV_PORT_MODE_10G_10G) |
1119 (1 << TLV_PORT_MODE_10G_10G_10G_10G),
1122 /* Supported modes requiring 2 outputs per port */
1124 EFX_FAMILY_HUNTINGTON,
1125 (1 << TLV_PORT_MODE_40G) |
1126 (1 << TLV_PORT_MODE_40G_40G) |
1127 (1 << TLV_PORT_MODE_40G_10G_10G) |
1128 (1 << TLV_PORT_MODE_10G_10G_40G),
1133 (1 << TLV_PORT_MODE_40G) |
1134 (1 << TLV_PORT_MODE_40G_40G) |
1135 (1 << TLV_PORT_MODE_40G_10G_10G) |
1136 (1 << TLV_PORT_MODE_10G_10G_40G),
1139 /* Supported modes requiring 4 outputs per port */
1142 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q) |
1143 (1 << TLV_PORT_MODE_10G_10G_10G_10G_Q2),
1148 __checkReturn efx_rc_t
1149 ef10_external_port_mapping(
1150 __in efx_nic_t *enp,
1152 __out uint8_t *external_portp)
1156 uint32_t port_modes;
1158 uint32_t stride = 1; /* default 1-1 mapping */
1160 if ((rc = efx_mcdi_get_port_modes(enp, &port_modes, NULL)) != 0) {
1161 /* No port mode information available - use default mapping */
1166 * Infer the internal port -> external port mapping from
1167 * the possible port modes for this NIC.
1169 for (i = 0; i < EFX_ARRAY_SIZE(__ef10_external_port_mappings); ++i) {
1170 if (__ef10_external_port_mappings[i].family !=
1173 matches = (__ef10_external_port_mappings[i].modes_mask &
1176 stride = __ef10_external_port_mappings[i].stride;
1177 port_modes &= ~matches;
1181 if (port_modes != 0) {
1182 /* Some advertised modes are not supported */
1189 * Scale as required by last matched mode and then convert to
1190 * one-based numbering
1192 *external_portp = (uint8_t)(port / stride) + 1;
1196 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1202 __checkReturn efx_rc_t
1204 __in efx_nic_t *enp)
1206 const efx_nic_ops_t *enop = enp->en_enop;
1207 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1208 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1211 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1212 enp->en_family == EFX_FAMILY_MEDFORD);
1214 /* Read and clear any assertion state */
1215 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1218 /* Exit the assertion handler */
1219 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1223 if ((rc = efx_mcdi_drv_attach(enp, B_TRUE)) != 0)
1226 if ((rc = enop->eno_board_cfg(enp)) != 0)
1231 * Set default driver config limits (based on board config).
1233 * FIXME: For now allocate a fixed number of VIs which is likely to be
1234 * sufficient and small enough to allow multiple functions on the same
1237 edcp->edc_min_vi_count = edcp->edc_max_vi_count =
1238 MIN(128, MAX(encp->enc_rxq_limit, encp->enc_txq_limit));
1240 /* The client driver must configure and enable PIO buffer support */
1241 edcp->edc_max_piobuf_count = 0;
1242 edcp->edc_pio_alloc_size = 0;
1244 #if EFSYS_OPT_MAC_STATS
1245 /* Wipe the MAC statistics */
1246 if ((rc = efx_mcdi_mac_stats_clear(enp)) != 0)
1250 #if EFSYS_OPT_LOOPBACK
1251 if ((rc = efx_mcdi_get_loopback_modes(enp)) != 0)
1255 #if EFSYS_OPT_MON_STATS
1256 if ((rc = mcdi_mon_cfg_build(enp)) != 0) {
1257 /* Unprivileged functions do not have access to sensors */
1263 encp->enc_features = enp->en_features;
1267 #if EFSYS_OPT_MON_STATS
1271 #if EFSYS_OPT_LOOPBACK
1275 #if EFSYS_OPT_MAC_STATS
1286 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1291 __checkReturn efx_rc_t
1292 ef10_nic_set_drv_limits(
1293 __inout efx_nic_t *enp,
1294 __in efx_drv_limits_t *edlp)
1296 efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1297 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1298 uint32_t min_evq_count, max_evq_count;
1299 uint32_t min_rxq_count, max_rxq_count;
1300 uint32_t min_txq_count, max_txq_count;
1308 /* Get minimum required and maximum usable VI limits */
1309 min_evq_count = MIN(edlp->edl_min_evq_count, encp->enc_evq_limit);
1310 min_rxq_count = MIN(edlp->edl_min_rxq_count, encp->enc_rxq_limit);
1311 min_txq_count = MIN(edlp->edl_min_txq_count, encp->enc_txq_limit);
1313 edcp->edc_min_vi_count =
1314 MAX(min_evq_count, MAX(min_rxq_count, min_txq_count));
1316 max_evq_count = MIN(edlp->edl_max_evq_count, encp->enc_evq_limit);
1317 max_rxq_count = MIN(edlp->edl_max_rxq_count, encp->enc_rxq_limit);
1318 max_txq_count = MIN(edlp->edl_max_txq_count, encp->enc_txq_limit);
1320 edcp->edc_max_vi_count =
1321 MAX(max_evq_count, MAX(max_rxq_count, max_txq_count));
1324 * Check limits for sub-allocated piobuf blocks.
1325 * PIO is optional, so don't fail if the limits are incorrect.
1327 if ((encp->enc_piobuf_size == 0) ||
1328 (encp->enc_piobuf_limit == 0) ||
1329 (edlp->edl_min_pio_alloc_size == 0) ||
1330 (edlp->edl_min_pio_alloc_size > encp->enc_piobuf_size)) {
1332 edcp->edc_max_piobuf_count = 0;
1333 edcp->edc_pio_alloc_size = 0;
1335 uint32_t blk_size, blk_count, blks_per_piobuf;
1338 MAX(edlp->edl_min_pio_alloc_size,
1339 encp->enc_piobuf_min_alloc_size);
1341 blks_per_piobuf = encp->enc_piobuf_size / blk_size;
1342 EFSYS_ASSERT3U(blks_per_piobuf, <=, 32);
1344 blk_count = (encp->enc_piobuf_limit * blks_per_piobuf);
1346 /* A zero max pio alloc count means unlimited */
1347 if ((edlp->edl_max_pio_alloc_count > 0) &&
1348 (edlp->edl_max_pio_alloc_count < blk_count)) {
1349 blk_count = edlp->edl_max_pio_alloc_count;
1352 edcp->edc_pio_alloc_size = blk_size;
1353 edcp->edc_max_piobuf_count =
1354 (blk_count + (blks_per_piobuf - 1)) / blks_per_piobuf;
1360 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1366 __checkReturn efx_rc_t
1368 __in efx_nic_t *enp)
1371 uint8_t payload[MAX(MC_CMD_ENTITY_RESET_IN_LEN,
1372 MC_CMD_ENTITY_RESET_OUT_LEN)];
1375 /* ef10_nic_reset() is called to recover from BADASSERT failures. */
1376 if ((rc = efx_mcdi_read_assertion(enp)) != 0)
1378 if ((rc = efx_mcdi_exit_assertion_handler(enp)) != 0)
1381 (void) memset(payload, 0, sizeof (payload));
1382 req.emr_cmd = MC_CMD_ENTITY_RESET;
1383 req.emr_in_buf = payload;
1384 req.emr_in_length = MC_CMD_ENTITY_RESET_IN_LEN;
1385 req.emr_out_buf = payload;
1386 req.emr_out_length = MC_CMD_ENTITY_RESET_OUT_LEN;
1388 MCDI_IN_POPULATE_DWORD_1(req, ENTITY_RESET_IN_FLAG,
1389 ENTITY_RESET_IN_FUNCTION_RESOURCE_RESET, 1);
1391 efx_mcdi_execute(enp, &req);
1393 if (req.emr_rc != 0) {
1398 /* Clear RX/TX DMA queue errors */
1399 enp->en_reset_flags &= ~(EFX_RESET_RXQ_ERR | EFX_RESET_TXQ_ERR);
1408 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1413 __checkReturn efx_rc_t
1415 __in efx_nic_t *enp)
1417 efx_drv_cfg_t *edcp = &(enp->en_drv_cfg);
1418 uint32_t min_vi_count, max_vi_count;
1419 uint32_t vi_count, vi_base, vi_shift;
1425 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1426 enp->en_family == EFX_FAMILY_MEDFORD);
1428 /* Enable reporting of some events (e.g. link change) */
1429 if ((rc = efx_mcdi_log_ctrl(enp)) != 0)
1432 /* Allocate (optional) on-chip PIO buffers */
1433 ef10_nic_alloc_piobufs(enp, edcp->edc_max_piobuf_count);
1436 * For best performance, PIO writes should use a write-combined
1437 * (WC) memory mapping. Using a separate WC mapping for the PIO
1438 * aperture of each VI would be a burden to drivers (and not
1439 * possible if the host page size is >4Kbyte).
1441 * To avoid this we use a single uncached (UC) mapping for VI
1442 * register access, and a single WC mapping for extra VIs used
1445 * Each piobuf must be linked to a VI in the WC mapping, and to
1446 * each VI that is using a sub-allocated block from the piobuf.
1448 min_vi_count = edcp->edc_min_vi_count;
1450 edcp->edc_max_vi_count + enp->en_arch.ef10.ena_piobuf_count;
1452 /* Ensure that the previously attached driver's VIs are freed */
1453 if ((rc = efx_mcdi_free_vis(enp)) != 0)
1457 * Reserve VI resources (EVQ+RXQ+TXQ) for this PCIe function. If this
1458 * fails then retrying the request for fewer VI resources may succeed.
1461 if ((rc = efx_mcdi_alloc_vis(enp, min_vi_count, max_vi_count,
1462 &vi_base, &vi_count, &vi_shift)) != 0)
1465 EFSYS_PROBE2(vi_alloc, uint32_t, vi_base, uint32_t, vi_count);
1467 if (vi_count < min_vi_count) {
1472 enp->en_arch.ef10.ena_vi_base = vi_base;
1473 enp->en_arch.ef10.ena_vi_count = vi_count;
1474 enp->en_arch.ef10.ena_vi_shift = vi_shift;
1476 if (vi_count < min_vi_count + enp->en_arch.ef10.ena_piobuf_count) {
1477 /* Not enough extra VIs to map piobufs */
1478 ef10_nic_free_piobufs(enp);
1481 enp->en_arch.ef10.ena_pio_write_vi_base =
1482 vi_count - enp->en_arch.ef10.ena_piobuf_count;
1484 /* Save UC memory mapping details */
1485 enp->en_arch.ef10.ena_uc_mem_map_offset = 0;
1486 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1487 enp->en_arch.ef10.ena_uc_mem_map_size =
1488 (ER_DZ_TX_PIOBUF_STEP *
1489 enp->en_arch.ef10.ena_pio_write_vi_base);
1491 enp->en_arch.ef10.ena_uc_mem_map_size =
1492 (ER_DZ_TX_PIOBUF_STEP *
1493 enp->en_arch.ef10.ena_vi_count);
1496 /* Save WC memory mapping details */
1497 enp->en_arch.ef10.ena_wc_mem_map_offset =
1498 enp->en_arch.ef10.ena_uc_mem_map_offset +
1499 enp->en_arch.ef10.ena_uc_mem_map_size;
1501 enp->en_arch.ef10.ena_wc_mem_map_size =
1502 (ER_DZ_TX_PIOBUF_STEP *
1503 enp->en_arch.ef10.ena_piobuf_count);
1505 /* Link piobufs to extra VIs in WC mapping */
1506 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1507 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1508 rc = efx_mcdi_link_piobuf(enp,
1509 enp->en_arch.ef10.ena_pio_write_vi_base + i,
1510 enp->en_arch.ef10.ena_piobuf_handle[i]);
1517 * Allocate a vAdaptor attached to our upstream vPort/pPort.
1519 * On a VF, this may fail with MC_CMD_ERR_NO_EVB_PORT (ENOENT) if the PF
1520 * driver has yet to bring up the EVB port. See bug 56147. In this case,
1521 * retry the request several times after waiting a while. The wait time
1522 * between retries starts small (10ms) and exponentially increases.
1523 * Total wait time is a little over two seconds. Retry logic in the
1524 * client driver may mean this whole loop is repeated if it continues to
1529 while ((rc = efx_mcdi_vadaptor_alloc(enp, EVB_PORT_ID_ASSIGNED)) != 0) {
1530 if (EFX_PCI_FUNCTION_IS_PF(&enp->en_nic_cfg) ||
1533 * Do not retry alloc for PF, or for other errors on
1539 /* VF startup before PF is ready. Retry allocation. */
1541 /* Too many attempts */
1545 EFSYS_PROBE1(mcdi_no_evb_port_retry, int, retry);
1546 EFSYS_SLEEP(delay_us);
1548 if (delay_us < 500000)
1552 enp->en_vport_id = EVB_PORT_ID_ASSIGNED;
1553 enp->en_nic_cfg.enc_mcdi_max_payload_length = MCDI_CTL_SDU_LEN_MAX_V2;
1568 ef10_nic_free_piobufs(enp);
1571 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1576 __checkReturn efx_rc_t
1577 ef10_nic_get_vi_pool(
1578 __in efx_nic_t *enp,
1579 __out uint32_t *vi_countp)
1581 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1582 enp->en_family == EFX_FAMILY_MEDFORD);
1585 * Report VIs that the client driver can use.
1586 * Do not include VIs used for PIO buffer writes.
1588 *vi_countp = enp->en_arch.ef10.ena_pio_write_vi_base;
1593 __checkReturn efx_rc_t
1594 ef10_nic_get_bar_region(
1595 __in efx_nic_t *enp,
1596 __in efx_nic_region_t region,
1597 __out uint32_t *offsetp,
1598 __out size_t *sizep)
1602 EFSYS_ASSERT(enp->en_family == EFX_FAMILY_HUNTINGTON ||
1603 enp->en_family == EFX_FAMILY_MEDFORD);
1606 * TODO: Specify host memory mapping alignment and granularity
1607 * in efx_drv_limits_t so that they can be taken into account
1608 * when allocating extra VIs for PIO writes.
1612 /* UC mapped memory BAR region for VI registers */
1613 *offsetp = enp->en_arch.ef10.ena_uc_mem_map_offset;
1614 *sizep = enp->en_arch.ef10.ena_uc_mem_map_size;
1617 case EFX_REGION_PIO_WRITE_VI:
1618 /* WC mapped memory BAR region for piobuf writes */
1619 *offsetp = enp->en_arch.ef10.ena_wc_mem_map_offset;
1620 *sizep = enp->en_arch.ef10.ena_wc_mem_map_size;
1631 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1638 __in efx_nic_t *enp)
1643 (void) efx_mcdi_vadaptor_free(enp, enp->en_vport_id);
1644 enp->en_vport_id = 0;
1646 /* Unlink piobufs from extra VIs in WC mapping */
1647 if (enp->en_arch.ef10.ena_piobuf_count > 0) {
1648 for (i = 0; i < enp->en_arch.ef10.ena_piobuf_count; i++) {
1649 rc = efx_mcdi_unlink_piobuf(enp,
1650 enp->en_arch.ef10.ena_pio_write_vi_base + i);
1656 ef10_nic_free_piobufs(enp);
1658 (void) efx_mcdi_free_vis(enp);
1659 enp->en_arch.ef10.ena_vi_count = 0;
1664 __in efx_nic_t *enp)
1666 #if EFSYS_OPT_MON_STATS
1667 mcdi_mon_cfg_free(enp);
1668 #endif /* EFSYS_OPT_MON_STATS */
1669 (void) efx_mcdi_drv_attach(enp, B_FALSE);
1674 __checkReturn efx_rc_t
1675 ef10_nic_register_test(
1676 __in efx_nic_t *enp)
1681 _NOTE(ARGUNUSED(enp))
1682 _NOTE(CONSTANTCONDITION)
1692 EFSYS_PROBE1(fail1, efx_rc_t, rc);
1697 #endif /* EFSYS_OPT_DIAG */
1700 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */