sys/dev/sfxge/common/efx_ev.c

   1 /*-
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  */
  30
  31 #include <sys/cdefs.h>
  32 __FBSDID("$FreeBSD$");
  33
  34 #include "efx.h"
  35 #include "efx_impl.h"
  36 #if EFSYS_OPT_MON_MCDI
  37 #include "mcdi_mon.h"
  38 #endif
  39
  40 #if EFSYS_OPT_QSTATS
  41 #define EFX_EV_QSTAT_INCR(_eep, _stat)                                  \
  42         do {                                                            \
  43                 (_eep)->ee_stat[_stat]++;                               \
  44         _NOTE(CONSTANTCONDITION)                                        \
  45         } while (B_FALSE)
  46 #else
  47 #define EFX_EV_QSTAT_INCR(_eep, _stat)
  48 #endif
  49
  50 #define EFX_EV_PRESENT(_qword)                                          \
  51         (EFX_QWORD_FIELD((_qword), EFX_DWORD_0) != 0xffffffff &&        \
  52         EFX_QWORD_FIELD((_qword), EFX_DWORD_1) != 0xffffffff)
  53
  54
  55
  56 #if EFSYS_OPT_SIENA
  57
  58 static  __checkReturn   efx_rc_t
  59 siena_ev_init(
  60         __in            efx_nic_t *enp);
  61
  62 static                  void
  63 siena_ev_fini(
  64         __in            efx_nic_t *enp);
  65
  66 static  __checkReturn   efx_rc_t
  67 siena_ev_qcreate(
  68         __in            efx_nic_t *enp,
  69         __in            unsigned int index,
  70         __in            efsys_mem_t *esmp,
  71         __in            size_t n,
  72         __in            uint32_t id,
  73         __in            uint32_t us,
  74         __in            efx_evq_t *eep);
  75
  76 static                  void
  77 siena_ev_qdestroy(
  78         __in            efx_evq_t *eep);
  79
  80 static  __checkReturn   efx_rc_t
  81 siena_ev_qprime(
  82         __in            efx_evq_t *eep,
  83         __in            unsigned int count);
  84
  85 static                  void
  86 siena_ev_qpoll(
  87         __in            efx_evq_t *eep,
  88         __inout         unsigned int *countp,
  89         __in            const efx_ev_callbacks_t *eecp,
  90         __in_opt        void *arg);
  91
  92 static                  void
  93 siena_ev_qpost(
  94         __in    efx_evq_t *eep,
  95         __in    uint16_t data);
  96
  97 static  __checkReturn   efx_rc_t
  98 siena_ev_qmoderate(
  99         __in            efx_evq_t *eep,
 100         __in            unsigned int us);
 101
 102 #if EFSYS_OPT_QSTATS
 103 static                  void
 104 siena_ev_qstats_update(
 105         __in                            efx_evq_t *eep,
 106         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat);
 107
 108 #endif
 109
 110 #endif /* EFSYS_OPT_SIENA */
 111
 112 #if EFSYS_OPT_SIENA
 113 static const efx_ev_ops_t       __efx_ev_siena_ops = {
 114         siena_ev_init,                          /* eevo_init */
 115         siena_ev_fini,                          /* eevo_fini */
 116         siena_ev_qcreate,                       /* eevo_qcreate */
 117         siena_ev_qdestroy,                      /* eevo_qdestroy */
 118         siena_ev_qprime,                        /* eevo_qprime */
 119         siena_ev_qpost,                         /* eevo_qpost */
 120         siena_ev_qmoderate,                     /* eevo_qmoderate */
 121 #if EFSYS_OPT_QSTATS
 122         siena_ev_qstats_update,                 /* eevo_qstats_update */
 123 #endif
 124 };
 125 #endif /* EFSYS_OPT_SIENA */
 126
 127 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 128 static const efx_ev_ops_t       __efx_ev_ef10_ops = {
 129         ef10_ev_init,                           /* eevo_init */
 130         ef10_ev_fini,                           /* eevo_fini */
 131         ef10_ev_qcreate,                        /* eevo_qcreate */
 132         ef10_ev_qdestroy,                       /* eevo_qdestroy */
 133         ef10_ev_qprime,                         /* eevo_qprime */
 134         ef10_ev_qpost,                          /* eevo_qpost */
 135         ef10_ev_qmoderate,                      /* eevo_qmoderate */
 136 #if EFSYS_OPT_QSTATS
 137         ef10_ev_qstats_update,                  /* eevo_qstats_update */
 138 #endif
 139 };
 140 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 141
 142
 143         __checkReturn   efx_rc_t
 144 efx_ev_init(
 145         __in            efx_nic_t *enp)
 146 {
 147         const efx_ev_ops_t *eevop;
 148         efx_rc_t rc;
 149
 150         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 151         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 152
 153         if (enp->en_mod_flags & EFX_MOD_EV) {
 154                 rc = EINVAL;
 155                 goto fail1;
 156         }
 157
 158         switch (enp->en_family) {
 159 #if EFSYS_OPT_SIENA
 160         case EFX_FAMILY_SIENA:
 161                 eevop = &__efx_ev_siena_ops;
 162                 break;
 163 #endif /* EFSYS_OPT_SIENA */
 164
 165 #if EFSYS_OPT_HUNTINGTON
 166         case EFX_FAMILY_HUNTINGTON:
 167                 eevop = &__efx_ev_ef10_ops;
 168                 break;
 169 #endif /* EFSYS_OPT_HUNTINGTON */
 170
 171 #if EFSYS_OPT_MEDFORD
 172         case EFX_FAMILY_MEDFORD:
 173                 eevop = &__efx_ev_ef10_ops;
 174                 break;
 175 #endif /* EFSYS_OPT_MEDFORD */
 176
 177         default:
 178                 EFSYS_ASSERT(0);
 179                 rc = ENOTSUP;
 180                 goto fail1;
 181         }
 182
 183         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 184
 185         if ((rc = eevop->eevo_init(enp)) != 0)
 186                 goto fail2;
 187
 188         enp->en_eevop = eevop;
 189         enp->en_mod_flags |= EFX_MOD_EV;
 190         return (0);
 191
 192 fail2:
 193         EFSYS_PROBE(fail2);
 194
 195 fail1:
 196         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 197
 198         enp->en_eevop = NULL;
 199         enp->en_mod_flags &= ~EFX_MOD_EV;
 200         return (rc);
 201 }
 202
 203                 void
 204 efx_ev_fini(
 205         __in    efx_nic_t *enp)
 206 {
 207         const efx_ev_ops_t *eevop = enp->en_eevop;
 208
 209         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 210         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_INTR);
 211         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 212         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_RX));
 213         EFSYS_ASSERT(!(enp->en_mod_flags & EFX_MOD_TX));
 214         EFSYS_ASSERT3U(enp->en_ev_qcount, ==, 0);
 215
 216         eevop->eevo_fini(enp);
 217
 218         enp->en_eevop = NULL;
 219         enp->en_mod_flags &= ~EFX_MOD_EV;
 220 }
 221
 222
 223         __checkReturn   efx_rc_t
 224 efx_ev_qcreate(
 225         __in            efx_nic_t *enp,
 226         __in            unsigned int index,
 227         __in            efsys_mem_t *esmp,
 228         __in            size_t n,
 229         __in            uint32_t id,
 230         __in            uint32_t us,
 231         __deref_out     efx_evq_t **eepp)
 232 {
 233         const efx_ev_ops_t *eevop = enp->en_eevop;
 234         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
 235         efx_evq_t *eep;
 236         efx_rc_t rc;
 237
 238         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
 239         EFSYS_ASSERT3U(enp->en_mod_flags, &, EFX_MOD_EV);
 240
 241         EFSYS_ASSERT3U(enp->en_ev_qcount + 1, <, encp->enc_evq_limit);
 242
 243         /* Allocate an EVQ object */
 244         EFSYS_KMEM_ALLOC(enp->en_esip, sizeof (efx_evq_t), eep);
 245         if (eep == NULL) {
 246                 rc = ENOMEM;
 247                 goto fail1;
 248         }
 249
 250         eep->ee_magic = EFX_EVQ_MAGIC;
 251         eep->ee_enp = enp;
 252         eep->ee_index = index;
 253         eep->ee_mask = n - 1;
 254         eep->ee_esmp = esmp;
 255
 256         /*
 257          * Set outputs before the queue is created because interrupts may be
 258          * raised for events immediately after the queue is created, before the
 259          * function call below returns. See bug58606.
 260          *
 261          * The eepp pointer passed in by the client must therefore point to data
 262          * shared with the client's event processing context.
 263          */
 264         enp->en_ev_qcount++;
 265         *eepp = eep;
 266
 267         if ((rc = eevop->eevo_qcreate(enp, index, esmp, n, id, us, eep)) != 0)
 268                 goto fail2;
 269
 270         return (0);
 271
 272 fail2:
 273         EFSYS_PROBE(fail2);
 274
 275         *eepp = NULL;
 276         enp->en_ev_qcount--;
 277         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 278 fail1:
 279         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 280         return (rc);
 281 }
 282
 283                 void
 284 efx_ev_qdestroy(
 285         __in    efx_evq_t *eep)
 286 {
 287         efx_nic_t *enp = eep->ee_enp;
 288         const efx_ev_ops_t *eevop = enp->en_eevop;
 289
 290         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 291
 292         EFSYS_ASSERT(enp->en_ev_qcount != 0);
 293         --enp->en_ev_qcount;
 294
 295         eevop->eevo_qdestroy(eep);
 296
 297         /* Free the EVQ object */
 298         EFSYS_KMEM_FREE(enp->en_esip, sizeof (efx_evq_t), eep);
 299 }
 300
 301         __checkReturn   efx_rc_t
 302 efx_ev_qprime(
 303         __in            efx_evq_t *eep,
 304         __in            unsigned int count)
 305 {
 306         efx_nic_t *enp = eep->ee_enp;
 307         const efx_ev_ops_t *eevop = enp->en_eevop;
 308         efx_rc_t rc;
 309
 310         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 311
 312         if (!(enp->en_mod_flags & EFX_MOD_INTR)) {
 313                 rc = EINVAL;
 314                 goto fail1;
 315         }
 316
 317         if ((rc = eevop->eevo_qprime(eep, count)) != 0)
 318                 goto fail2;
 319
 320         return (0);
 321
 322 fail2:
 323         EFSYS_PROBE(fail2);
 324 fail1:
 325         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 326         return (rc);
 327 }
 328
 329         __checkReturn   boolean_t
 330 efx_ev_qpending(
 331         __in            efx_evq_t *eep,
 332         __in            unsigned int count)
 333 {
 334         size_t offset;
 335         efx_qword_t qword;
 336
 337         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 338
 339         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 340         EFSYS_MEM_READQ(eep->ee_esmp, offset, &qword);
 341
 342         return (EFX_EV_PRESENT(qword));
 343 }
 344
 345 #if EFSYS_OPT_EV_PREFETCH
 346
 347                         void
 348 efx_ev_qprefetch(
 349         __in            efx_evq_t *eep,
 350         __in            unsigned int count)
 351 {
 352         efx_nic_t *enp = eep->ee_enp;
 353         unsigned int offset;
 354
 355         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 356
 357         offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
 358         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
 359 }
 360
 361 #endif  /* EFSYS_OPT_EV_PREFETCH */
 362
 363                         void
 364 efx_ev_qpoll(
 365         __in            efx_evq_t *eep,
 366         __inout         unsigned int *countp,
 367         __in            const efx_ev_callbacks_t *eecp,
 368         __in_opt        void *arg)
 369 {
 370         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 371
 372         /*
 373          * FIXME: Huntington will require support for hardware event batching
 374          * and merging, which will need a different ev_qpoll implementation.
 375          *
 376          * Without those features the Falcon/Siena code can be used unchanged.
 377          */
 378         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_LBN == FSF_AZ_EV_CODE_LBN);
 379         EFX_STATIC_ASSERT(ESF_DZ_EV_CODE_WIDTH == FSF_AZ_EV_CODE_WIDTH);
 380
 381         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_RX_EV == FSE_AZ_EV_CODE_RX_EV);
 382         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_TX_EV == FSE_AZ_EV_CODE_TX_EV);
 383         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRIVER_EV == FSE_AZ_EV_CODE_DRIVER_EV);
 384         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_DRV_GEN_EV ==
 385             FSE_AZ_EV_CODE_DRV_GEN_EV);
 386 #if EFSYS_OPT_MCDI
 387         EFX_STATIC_ASSERT(ESE_DZ_EV_CODE_MCDI_EV ==
 388             FSE_AZ_EV_CODE_MCDI_EVRESPONSE);
 389 #endif
 390         siena_ev_qpoll(eep, countp, eecp, arg);
 391 }
 392
 393                         void
 394 efx_ev_qpost(
 395         __in    efx_evq_t *eep,
 396         __in    uint16_t data)
 397 {
 398         efx_nic_t *enp = eep->ee_enp;
 399         const efx_ev_ops_t *eevop = enp->en_eevop;
 400
 401         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 402
 403         EFSYS_ASSERT(eevop != NULL &&
 404             eevop->eevo_qpost != NULL);
 405
 406         eevop->eevo_qpost(eep, data);
 407 }
 408
 409         __checkReturn   efx_rc_t
 410 efx_ev_qmoderate(
 411         __in            efx_evq_t *eep,
 412         __in            unsigned int us)
 413 {
 414         efx_nic_t *enp = eep->ee_enp;
 415         const efx_ev_ops_t *eevop = enp->en_eevop;
 416         efx_rc_t rc;
 417
 418         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 419
 420         if ((rc = eevop->eevo_qmoderate(eep, us)) != 0)
 421                 goto fail1;
 422
 423         return (0);
 424
 425 fail1:
 426         EFSYS_PROBE1(fail1, efx_rc_t, rc);
 427         return (rc);
 428 }
 429
 430 #if EFSYS_OPT_QSTATS
 431                                         void
 432 efx_ev_qstats_update(
 433         __in                            efx_evq_t *eep,
 434         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
 435
 436 {       efx_nic_t *enp = eep->ee_enp;
 437         const efx_ev_ops_t *eevop = enp->en_eevop;
 438
 439         EFSYS_ASSERT3U(eep->ee_magic, ==, EFX_EVQ_MAGIC);
 440
 441         eevop->eevo_qstats_update(eep, stat);
 442 }
 443
 444 #endif  /* EFSYS_OPT_QSTATS */
 445
 446 #if EFSYS_OPT_SIENA
 447
 448 static  __checkReturn   efx_rc_t
 449 siena_ev_init(
 450         __in            efx_nic_t *enp)
 451 {
 452         efx_oword_t oword;
 453
 454         /*
 455          * Program the event queue for receive and transmit queue
 456          * flush events.
 457          */
 458         EFX_BAR_READO(enp, FR_AZ_DP_CTRL_REG, &oword);
 459         EFX_SET_OWORD_FIELD(oword, FRF_AZ_FLS_EVQ_ID, 0);
 460         EFX_BAR_WRITEO(enp, FR_AZ_DP_CTRL_REG, &oword);
 461
 462         return (0);
 463
 464 }
 465
 466 static  __checkReturn   boolean_t
 467 siena_ev_rx_not_ok(
 468         __in            efx_evq_t *eep,
 469         __in            efx_qword_t *eqp,
 470         __in            uint32_t label,
 471         __in            uint32_t id,
 472         __inout         uint16_t *flagsp)
 473 {
 474         boolean_t ignore = B_FALSE;
 475
 476         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TOBE_DISC) != 0) {
 477                 EFX_EV_QSTAT_INCR(eep, EV_RX_TOBE_DISC);
 478                 EFSYS_PROBE(tobe_disc);
 479                 /*
 480                  * Assume this is a unicast address mismatch, unless below
 481                  * we find either FSF_AZ_RX_EV_ETH_CRC_ERR or
 482                  * EV_RX_PAUSE_FRM_ERR is set.
 483                  */
 484                 (*flagsp) |= EFX_ADDR_MISMATCH;
 485         }
 486
 487         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_FRM_TRUNC) != 0) {
 488                 EFSYS_PROBE2(frm_trunc, uint32_t, label, uint32_t, id);
 489                 EFX_EV_QSTAT_INCR(eep, EV_RX_FRM_TRUNC);
 490                 (*flagsp) |= EFX_DISCARD;
 491
 492 #if EFSYS_OPT_RX_SCATTER
 493                 /*
 494                  * Lookout for payload queue ran dry errors and ignore them.
 495                  *
 496                  * Sadly for the header/data split cases, the descriptor
 497                  * pointer in this event refers to the header queue and
 498                  * therefore cannot be easily detected as duplicate.
 499                  * So we drop these and rely on the receive processing seeing
 500                  * a subsequent packet with FSF_AZ_RX_EV_SOP set to discard
 501                  * the partially received packet.
 502                  */
 503                 if ((EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) == 0) &&
 504                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) == 0) &&
 505                     (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT) == 0))
 506                         ignore = B_TRUE;
 507 #endif  /* EFSYS_OPT_RX_SCATTER */
 508         }
 509
 510         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_ETH_CRC_ERR) != 0) {
 511                 EFX_EV_QSTAT_INCR(eep, EV_RX_ETH_CRC_ERR);
 512                 EFSYS_PROBE(crc_err);
 513                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 514                 (*flagsp) |= EFX_DISCARD;
 515         }
 516
 517         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PAUSE_FRM_ERR) != 0) {
 518                 EFX_EV_QSTAT_INCR(eep, EV_RX_PAUSE_FRM_ERR);
 519                 EFSYS_PROBE(pause_frm_err);
 520                 (*flagsp) &= ~EFX_ADDR_MISMATCH;
 521                 (*flagsp) |= EFX_DISCARD;
 522         }
 523
 524         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BUF_OWNER_ID_ERR) != 0) {
 525                 EFX_EV_QSTAT_INCR(eep, EV_RX_BUF_OWNER_ID_ERR);
 526                 EFSYS_PROBE(owner_id_err);
 527                 (*flagsp) |= EFX_DISCARD;
 528         }
 529
 530         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_HDR_CHKSUM_ERR) != 0) {
 531                 EFX_EV_QSTAT_INCR(eep, EV_RX_IPV4_HDR_CHKSUM_ERR);
 532                 EFSYS_PROBE(ipv4_err);
 533                 (*flagsp) &= ~EFX_CKSUM_IPV4;
 534         }
 535
 536         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_TCP_UDP_CHKSUM_ERR) != 0) {
 537                 EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_UDP_CHKSUM_ERR);
 538                 EFSYS_PROBE(udp_chk_err);
 539                 (*flagsp) &= ~EFX_CKSUM_TCPUDP;
 540         }
 541
 542         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_IP_FRAG_ERR) != 0) {
 543                 EFX_EV_QSTAT_INCR(eep, EV_RX_IP_FRAG_ERR);
 544
 545                 /*
 546                  * If IP is fragmented FSF_AZ_RX_EV_IP_FRAG_ERR is set. This
 547                  * causes FSF_AZ_RX_EV_PKT_OK to be clear. This is not an error
 548                  * condition.
 549                  */
 550                 (*flagsp) &= ~(EFX_PKT_TCP | EFX_PKT_UDP | EFX_CKSUM_TCPUDP);
 551         }
 552
 553         return (ignore);
 554 }
 555
 556 static  __checkReturn   boolean_t
 557 siena_ev_rx(
 558         __in            efx_evq_t *eep,
 559         __in            efx_qword_t *eqp,
 560         __in            const efx_ev_callbacks_t *eecp,
 561         __in_opt        void *arg)
 562 {
 563         uint32_t id;
 564         uint32_t size;
 565         uint32_t label;
 566         boolean_t ok;
 567 #if EFSYS_OPT_RX_SCATTER
 568         boolean_t sop;
 569         boolean_t jumbo_cont;
 570 #endif  /* EFSYS_OPT_RX_SCATTER */
 571         uint32_t hdr_type;
 572         boolean_t is_v6;
 573         uint16_t flags;
 574         boolean_t ignore;
 575         boolean_t should_abort;
 576
 577         EFX_EV_QSTAT_INCR(eep, EV_RX);
 578
 579         /* Basic packet information */
 580         id = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_DESC_PTR);
 581         size = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_BYTE_CNT);
 582         label = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_Q_LABEL);
 583         ok = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_OK) != 0);
 584
 585 #if EFSYS_OPT_RX_SCATTER
 586         sop = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_SOP) != 0);
 587         jumbo_cont = (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_JUMBO_CONT) != 0);
 588 #endif  /* EFSYS_OPT_RX_SCATTER */
 589
 590         hdr_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_HDR_TYPE);
 591
 592         is_v6 = (EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_IPV6_PKT) != 0);
 593
 594         /*
 595          * If packet is marked as OK and packet type is TCP/IP or
 596          * UDP/IP or other IP, then we can rely on the hardware checksums.
 597          */
 598         switch (hdr_type) {
 599         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_TCP:
 600                 flags = EFX_PKT_TCP | EFX_CKSUM_TCPUDP;
 601                 if (is_v6) {
 602                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV6);
 603                         flags |= EFX_PKT_IPV6;
 604                 } else {
 605                         EFX_EV_QSTAT_INCR(eep, EV_RX_TCP_IPV4);
 606                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 607                 }
 608                 break;
 609
 610         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_UDP:
 611                 flags = EFX_PKT_UDP | EFX_CKSUM_TCPUDP;
 612                 if (is_v6) {
 613                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV6);
 614                         flags |= EFX_PKT_IPV6;
 615                 } else {
 616                         EFX_EV_QSTAT_INCR(eep, EV_RX_UDP_IPV4);
 617                         flags |= EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 618                 }
 619                 break;
 620
 621         case FSE_AZ_RX_EV_HDR_TYPE_IPV4V6_OTHER:
 622                 if (is_v6) {
 623                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV6);
 624                         flags = EFX_PKT_IPV6;
 625                 } else {
 626                         EFX_EV_QSTAT_INCR(eep, EV_RX_OTHER_IPV4);
 627                         flags = EFX_PKT_IPV4 | EFX_CKSUM_IPV4;
 628                 }
 629                 break;
 630
 631         case FSE_AZ_RX_EV_HDR_TYPE_OTHER:
 632                 EFX_EV_QSTAT_INCR(eep, EV_RX_NON_IP);
 633                 flags = 0;
 634                 break;
 635
 636         default:
 637                 EFSYS_ASSERT(B_FALSE);
 638                 flags = 0;
 639                 break;
 640         }
 641
 642 #if EFSYS_OPT_RX_SCATTER
 643         /* Report scatter and header/lookahead split buffer flags */
 644         if (sop)
 645                 flags |= EFX_PKT_START;
 646         if (jumbo_cont)
 647                 flags |= EFX_PKT_CONT;
 648 #endif  /* EFSYS_OPT_RX_SCATTER */
 649
 650         /* Detect errors included in the FSF_AZ_RX_EV_PKT_OK indication */
 651         if (!ok) {
 652                 ignore = siena_ev_rx_not_ok(eep, eqp, label, id, &flags);
 653                 if (ignore) {
 654                         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 655                             uint32_t, size, uint16_t, flags);
 656
 657                         return (B_FALSE);
 658                 }
 659         }
 660
 661         /* If we're not discarding the packet then it is ok */
 662         if (~flags & EFX_DISCARD)
 663                 EFX_EV_QSTAT_INCR(eep, EV_RX_OK);
 664
 665         /* Detect multicast packets that didn't match the filter */
 666         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_PKT) != 0) {
 667                 EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_PKT);
 668
 669                 if (EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_MCAST_HASH_MATCH) != 0) {
 670                         EFX_EV_QSTAT_INCR(eep, EV_RX_MCAST_HASH_MATCH);
 671                 } else {
 672                         EFSYS_PROBE(mcast_mismatch);
 673                         flags |= EFX_ADDR_MISMATCH;
 674                 }
 675         } else {
 676                 flags |= EFX_PKT_UNICAST;
 677         }
 678
 679         /*
 680          * The packet parser in Siena can abort parsing packets under
 681          * certain error conditions, setting the PKT_NOT_PARSED bit
 682          * (which clears PKT_OK). If this is set, then don't trust
 683          * the PKT_TYPE field.
 684          */
 685         if (!ok) {
 686                 uint32_t parse_err;
 687
 688                 parse_err = EFX_QWORD_FIELD(*eqp, FSF_CZ_RX_EV_PKT_NOT_PARSED);
 689                 if (parse_err != 0)
 690                         flags |= EFX_CHECK_VLAN;
 691         }
 692
 693         if (~flags & EFX_CHECK_VLAN) {
 694                 uint32_t pkt_type;
 695
 696                 pkt_type = EFX_QWORD_FIELD(*eqp, FSF_AZ_RX_EV_PKT_TYPE);
 697                 if (pkt_type >= FSE_AZ_RX_EV_PKT_TYPE_VLAN)
 698                         flags |= EFX_PKT_VLAN_TAGGED;
 699         }
 700
 701         EFSYS_PROBE4(rx_complete, uint32_t, label, uint32_t, id,
 702             uint32_t, size, uint16_t, flags);
 703
 704         EFSYS_ASSERT(eecp->eec_rx != NULL);
 705         should_abort = eecp->eec_rx(arg, label, id, size, flags);
 706
 707         return (should_abort);
 708 }
 709
 710 static  __checkReturn   boolean_t
 711 siena_ev_tx(
 712         __in            efx_evq_t *eep,
 713         __in            efx_qword_t *eqp,
 714         __in            const efx_ev_callbacks_t *eecp,
 715         __in_opt        void *arg)
 716 {
 717         uint32_t id;
 718         uint32_t label;
 719         boolean_t should_abort;
 720
 721         EFX_EV_QSTAT_INCR(eep, EV_TX);
 722
 723         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0 &&
 724             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) == 0 &&
 725             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) == 0 &&
 726             EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) == 0) {
 727
 728                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_DESC_PTR);
 729                 label = EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_Q_LABEL);
 730
 731                 EFSYS_PROBE2(tx_complete, uint32_t, label, uint32_t, id);
 732
 733                 EFSYS_ASSERT(eecp->eec_tx != NULL);
 734                 should_abort = eecp->eec_tx(arg, label, id);
 735
 736                 return (should_abort);
 737         }
 738
 739         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_COMP) != 0)
 740                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 741                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 742                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 743
 744         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_ERR) != 0)
 745                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_ERR);
 746
 747         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_PKT_TOO_BIG) != 0)
 748                 EFX_EV_QSTAT_INCR(eep, EV_TX_PKT_TOO_BIG);
 749
 750         if (EFX_QWORD_FIELD(*eqp, FSF_AZ_TX_EV_WQ_FF_FULL) != 0)
 751                 EFX_EV_QSTAT_INCR(eep, EV_TX_WQ_FF_FULL);
 752
 753         EFX_EV_QSTAT_INCR(eep, EV_TX_UNEXPECTED);
 754         return (B_FALSE);
 755 }
 756
 757 static  __checkReturn   boolean_t
 758 siena_ev_global(
 759         __in            efx_evq_t *eep,
 760         __in            efx_qword_t *eqp,
 761         __in            const efx_ev_callbacks_t *eecp,
 762         __in_opt        void *arg)
 763 {
 764         _NOTE(ARGUNUSED(eqp, eecp, arg))
 765
 766         EFX_EV_QSTAT_INCR(eep, EV_GLOBAL);
 767
 768         return (B_FALSE);
 769 }
 770
 771 static  __checkReturn   boolean_t
 772 siena_ev_driver(
 773         __in            efx_evq_t *eep,
 774         __in            efx_qword_t *eqp,
 775         __in            const efx_ev_callbacks_t *eecp,
 776         __in_opt        void *arg)
 777 {
 778         boolean_t should_abort;
 779
 780         EFX_EV_QSTAT_INCR(eep, EV_DRIVER);
 781         should_abort = B_FALSE;
 782
 783         switch (EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBCODE)) {
 784         case FSE_AZ_TX_DESCQ_FLS_DONE_EV: {
 785                 uint32_t txq_index;
 786
 787                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DESCQ_FLS_DONE);
 788
 789                 txq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 790
 791                 EFSYS_PROBE1(tx_descq_fls_done, uint32_t, txq_index);
 792
 793                 EFSYS_ASSERT(eecp->eec_txq_flush_done != NULL);
 794                 should_abort = eecp->eec_txq_flush_done(arg, txq_index);
 795
 796                 break;
 797         }
 798         case FSE_AZ_RX_DESCQ_FLS_DONE_EV: {
 799                 uint32_t rxq_index;
 800                 uint32_t failed;
 801
 802                 rxq_index = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_DESCQ_ID);
 803                 failed = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_RX_FLUSH_FAIL);
 804
 805                 EFSYS_ASSERT(eecp->eec_rxq_flush_done != NULL);
 806                 EFSYS_ASSERT(eecp->eec_rxq_flush_failed != NULL);
 807
 808                 if (failed) {
 809                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_FAILED);
 810
 811                         EFSYS_PROBE1(rx_descq_fls_failed, uint32_t, rxq_index);
 812
 813                         should_abort = eecp->eec_rxq_flush_failed(arg,
 814                                                                     rxq_index);
 815                 } else {
 816                         EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DESCQ_FLS_DONE);
 817
 818                         EFSYS_PROBE1(rx_descq_fls_done, uint32_t, rxq_index);
 819
 820                         should_abort = eecp->eec_rxq_flush_done(arg, rxq_index);
 821                 }
 822
 823                 break;
 824         }
 825         case FSE_AZ_EVQ_INIT_DONE_EV:
 826                 EFSYS_ASSERT(eecp->eec_initialized != NULL);
 827                 should_abort = eecp->eec_initialized(arg);
 828
 829                 break;
 830
 831         case FSE_AZ_EVQ_NOT_EN_EV:
 832                 EFSYS_PROBE(evq_not_en);
 833                 break;
 834
 835         case FSE_AZ_SRM_UPD_DONE_EV: {
 836                 uint32_t code;
 837
 838                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_SRM_UPD_DONE);
 839
 840                 code = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 841
 842                 EFSYS_ASSERT(eecp->eec_sram != NULL);
 843                 should_abort = eecp->eec_sram(arg, code);
 844
 845                 break;
 846         }
 847         case FSE_AZ_WAKE_UP_EV: {
 848                 uint32_t id;
 849
 850                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 851
 852                 EFSYS_ASSERT(eecp->eec_wake_up != NULL);
 853                 should_abort = eecp->eec_wake_up(arg, id);
 854
 855                 break;
 856         }
 857         case FSE_AZ_TX_PKT_NON_TCP_UDP:
 858                 EFSYS_PROBE(tx_pkt_non_tcp_udp);
 859                 break;
 860
 861         case FSE_AZ_TIMER_EV: {
 862                 uint32_t id;
 863
 864                 id = EFX_QWORD_FIELD(*eqp, FSF_AZ_DRIVER_EV_SUBDATA);
 865
 866                 EFSYS_ASSERT(eecp->eec_timer != NULL);
 867                 should_abort = eecp->eec_timer(arg, id);
 868
 869                 break;
 870         }
 871         case FSE_AZ_RX_DSC_ERROR_EV:
 872                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_RX_DSC_ERROR);
 873
 874                 EFSYS_PROBE(rx_dsc_error);
 875
 876                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 877                 should_abort = eecp->eec_exception(arg,
 878                         EFX_EXCEPTION_RX_DSC_ERROR, 0);
 879
 880                 break;
 881
 882         case FSE_AZ_TX_DSC_ERROR_EV:
 883                 EFX_EV_QSTAT_INCR(eep, EV_DRIVER_TX_DSC_ERROR);
 884
 885                 EFSYS_PROBE(tx_dsc_error);
 886
 887                 EFSYS_ASSERT(eecp->eec_exception != NULL);
 888                 should_abort = eecp->eec_exception(arg,
 889                         EFX_EXCEPTION_TX_DSC_ERROR, 0);
 890
 891                 break;
 892
 893         default:
 894                 break;
 895         }
 896
 897         return (should_abort);
 898 }
 899
 900 static  __checkReturn   boolean_t
 901 siena_ev_drv_gen(
 902         __in            efx_evq_t *eep,
 903         __in            efx_qword_t *eqp,
 904         __in            const efx_ev_callbacks_t *eecp,
 905         __in_opt        void *arg)
 906 {
 907         uint32_t data;
 908         boolean_t should_abort;
 909
 910         EFX_EV_QSTAT_INCR(eep, EV_DRV_GEN);
 911
 912         data = EFX_QWORD_FIELD(*eqp, FSF_AZ_EV_DATA_DW0);
 913         if (data >= ((uint32_t)1 << 16)) {
 914                 EFSYS_PROBE3(bad_event, unsigned int, eep->ee_index,
 915                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_1),
 916                             uint32_t, EFX_QWORD_FIELD(*eqp, EFX_DWORD_0));
 917                 return (B_TRUE);
 918         }
 919
 920         EFSYS_ASSERT(eecp->eec_software != NULL);
 921         should_abort = eecp->eec_software(arg, (uint16_t)data);
 922
 923         return (should_abort);
 924 }
 925
 926 #if EFSYS_OPT_MCDI
 927
 928 static  __checkReturn   boolean_t
 929 siena_ev_mcdi(
 930         __in            efx_evq_t *eep,
 931         __in            efx_qword_t *eqp,
 932         __in            const efx_ev_callbacks_t *eecp,
 933         __in_opt        void *arg)
 934 {
 935         efx_nic_t *enp = eep->ee_enp;
 936         unsigned code;
 937         boolean_t should_abort = B_FALSE;
 938
 939         EFSYS_ASSERT3U(enp->en_family, ==, EFX_FAMILY_SIENA);
 940
 941         if (enp->en_family != EFX_FAMILY_SIENA)
 942                 goto out;
 943
 944         EFSYS_ASSERT(eecp->eec_link_change != NULL);
 945         EFSYS_ASSERT(eecp->eec_exception != NULL);
 946 #if EFSYS_OPT_MON_STATS
 947         EFSYS_ASSERT(eecp->eec_monitor != NULL);
 948 #endif
 949
 950         EFX_EV_QSTAT_INCR(eep, EV_MCDI_RESPONSE);
 951
 952         code = EFX_QWORD_FIELD(*eqp, MCDI_EVENT_CODE);
 953         switch (code) {
 954         case MCDI_EVENT_CODE_BADSSERT:
 955                 efx_mcdi_ev_death(enp, EINTR);
 956                 break;
 957
 958         case MCDI_EVENT_CODE_CMDDONE:
 959                 efx_mcdi_ev_cpl(enp,
 960                     MCDI_EV_FIELD(eqp, CMDDONE_SEQ),
 961                     MCDI_EV_FIELD(eqp, CMDDONE_DATALEN),
 962                     MCDI_EV_FIELD(eqp, CMDDONE_ERRNO));
 963                 break;
 964
 965         case MCDI_EVENT_CODE_LINKCHANGE: {
 966                 efx_link_mode_t link_mode;
 967
 968                 siena_phy_link_ev(enp, eqp, &link_mode);
 969                 should_abort = eecp->eec_link_change(arg, link_mode);
 970                 break;
 971         }
 972         case MCDI_EVENT_CODE_SENSOREVT: {
 973 #if EFSYS_OPT_MON_STATS
 974                 efx_mon_stat_t id;
 975                 efx_mon_stat_value_t value;
 976                 efx_rc_t rc;
 977
 978                 if ((rc = mcdi_mon_ev(enp, eqp, &id, &value)) == 0)
 979                         should_abort = eecp->eec_monitor(arg, id, value);
 980                 else if (rc == ENOTSUP) {
 981                         should_abort = eecp->eec_exception(arg,
 982                                 EFX_EXCEPTION_UNKNOWN_SENSOREVT,
 983                                 MCDI_EV_FIELD(eqp, DATA));
 984                 } else
 985                         EFSYS_ASSERT(rc == ENODEV);     /* Wrong port */
 986 #else
 987                 should_abort = B_FALSE;
 988 #endif
 989                 break;
 990         }
 991         case MCDI_EVENT_CODE_SCHEDERR:
 992                 /* Informational only */
 993                 break;
 994
 995         case MCDI_EVENT_CODE_REBOOT:
 996                 efx_mcdi_ev_death(enp, EIO);
 997                 break;
 998
 999         case MCDI_EVENT_CODE_MAC_STATS_DMA:
1000 #if EFSYS_OPT_MAC_STATS
1001                 if (eecp->eec_mac_stats != NULL) {
1002                         eecp->eec_mac_stats(arg,
1003                             MCDI_EV_FIELD(eqp, MAC_STATS_DMA_GENERATION));
1004                 }
1005 #endif
1006                 break;
1007
1008         case MCDI_EVENT_CODE_FWALERT: {
1009                 uint32_t reason = MCDI_EV_FIELD(eqp, FWALERT_REASON);
1010
1011                 if (reason == MCDI_EVENT_FWALERT_REASON_SRAM_ACCESS)
1012                         should_abort = eecp->eec_exception(arg,
1013                                 EFX_EXCEPTION_FWALERT_SRAM,
1014                                 MCDI_EV_FIELD(eqp, FWALERT_DATA));
1015                 else
1016                         should_abort = eecp->eec_exception(arg,
1017                                 EFX_EXCEPTION_UNKNOWN_FWALERT,
1018                                 MCDI_EV_FIELD(eqp, DATA));
1019                 break;
1020         }
1021
1022         default:
1023                 EFSYS_PROBE1(mc_pcol_error, int, code);
1024                 break;
1025         }
1026
1027 out:
1028         return (should_abort);
1029 }
1030
1031 #endif  /* EFSYS_OPT_MCDI */
1032
1033 static  __checkReturn   efx_rc_t
1034 siena_ev_qprime(
1035         __in            efx_evq_t *eep,
1036         __in            unsigned int count)
1037 {
1038         efx_nic_t *enp = eep->ee_enp;
1039         uint32_t rptr;
1040         efx_dword_t dword;
1041
1042         rptr = count & eep->ee_mask;
1043
1044         EFX_POPULATE_DWORD_1(dword, FRF_AZ_EVQ_RPTR, rptr);
1045
1046         EFX_BAR_TBL_WRITED(enp, FR_AZ_EVQ_RPTR_REG, eep->ee_index,
1047                             &dword, B_FALSE);
1048
1049         return (0);
1050 }
1051
1052 #define EFX_EV_BATCH    8
1053
1054 static                  void
1055 siena_ev_qpoll(
1056         __in            efx_evq_t *eep,
1057         __inout         unsigned int *countp,
1058         __in            const efx_ev_callbacks_t *eecp,
1059         __in_opt        void *arg)
1060 {
1061         efx_qword_t ev[EFX_EV_BATCH];
1062         unsigned int batch;
1063         unsigned int total;
1064         unsigned int count;
1065         unsigned int index;
1066         size_t offset;
1067
1068         EFSYS_ASSERT(countp != NULL);
1069         EFSYS_ASSERT(eecp != NULL);
1070
1071         count = *countp;
1072         do {
1073                 /* Read up until the end of the batch period */
1074                 batch = EFX_EV_BATCH - (count & (EFX_EV_BATCH - 1));
1075                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1076                 for (total = 0; total < batch; ++total) {
1077                         EFSYS_MEM_READQ(eep->ee_esmp, offset, &(ev[total]));
1078
1079                         if (!EFX_EV_PRESENT(ev[total]))
1080                                 break;
1081
1082                         EFSYS_PROBE3(event, unsigned int, eep->ee_index,
1083                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_1),
1084                             uint32_t, EFX_QWORD_FIELD(ev[total], EFX_DWORD_0));
1085
1086                         offset += sizeof (efx_qword_t);
1087                 }
1088
1089 #if EFSYS_OPT_EV_PREFETCH && (EFSYS_OPT_EV_PREFETCH_PERIOD > 1)
1090                 /*
1091                  * Prefetch the next batch when we get within PREFETCH_PERIOD
1092                  * of a completed batch. If the batch is smaller, then prefetch
1093                  * immediately.
1094                  */
1095                 if (total == batch && total < EFSYS_OPT_EV_PREFETCH_PERIOD)
1096                         EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1097 #endif  /* EFSYS_OPT_EV_PREFETCH */
1098
1099                 /* Process the batch of events */
1100                 for (index = 0; index < total; ++index) {
1101                         boolean_t should_abort;
1102                         uint32_t code;
1103
1104 #if EFSYS_OPT_EV_PREFETCH
1105                         /* Prefetch if we've now reached the batch period */
1106                         if (total == batch &&
1107                             index + EFSYS_OPT_EV_PREFETCH_PERIOD == total) {
1108                                 offset = (count + batch) & eep->ee_mask;
1109                                 offset *= sizeof (efx_qword_t);
1110
1111                                 EFSYS_MEM_PREFETCH(eep->ee_esmp, offset);
1112                         }
1113 #endif  /* EFSYS_OPT_EV_PREFETCH */
1114
1115                         EFX_EV_QSTAT_INCR(eep, EV_ALL);
1116
1117                         code = EFX_QWORD_FIELD(ev[index], FSF_AZ_EV_CODE);
1118                         switch (code) {
1119                         case FSE_AZ_EV_CODE_RX_EV:
1120                                 should_abort = eep->ee_rx(eep,
1121                                     &(ev[index]), eecp, arg);
1122                                 break;
1123                         case FSE_AZ_EV_CODE_TX_EV:
1124                                 should_abort = eep->ee_tx(eep,
1125                                     &(ev[index]), eecp, arg);
1126                                 break;
1127                         case FSE_AZ_EV_CODE_DRIVER_EV:
1128                                 should_abort = eep->ee_driver(eep,
1129                                     &(ev[index]), eecp, arg);
1130                                 break;
1131                         case FSE_AZ_EV_CODE_DRV_GEN_EV:
1132                                 should_abort = eep->ee_drv_gen(eep,
1133                                     &(ev[index]), eecp, arg);
1134                                 break;
1135 #if EFSYS_OPT_MCDI
1136                         case FSE_AZ_EV_CODE_MCDI_EVRESPONSE:
1137                                 should_abort = eep->ee_mcdi(eep,
1138                                     &(ev[index]), eecp, arg);
1139                                 break;
1140 #endif
1141                         case FSE_AZ_EV_CODE_GLOBAL_EV:
1142                                 if (eep->ee_global) {
1143                                         should_abort = eep->ee_global(eep,
1144                                             &(ev[index]), eecp, arg);
1145                                         break;
1146                                 }
1147                                 /* else fallthrough */
1148                         default:
1149                                 EFSYS_PROBE3(bad_event,
1150                                     unsigned int, eep->ee_index,
1151                                     uint32_t,
1152                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_1),
1153                                     uint32_t,
1154                                     EFX_QWORD_FIELD(ev[index], EFX_DWORD_0));
1155
1156                                 EFSYS_ASSERT(eecp->eec_exception != NULL);
1157                                 (void) eecp->eec_exception(arg,
1158                                         EFX_EXCEPTION_EV_ERROR, code);
1159                                 should_abort = B_TRUE;
1160                         }
1161                         if (should_abort) {
1162                                 /* Ignore subsequent events */
1163                                 total = index + 1;
1164                                 break;
1165                         }
1166                 }
1167
1168                 /*
1169                  * Now that the hardware has most likely moved onto dma'ing
1170                  * into the next cache line, clear the processed events. Take
1171                  * care to only clear out events that we've processed
1172                  */
1173                 EFX_SET_QWORD(ev[0]);
1174                 offset = (count & eep->ee_mask) * sizeof (efx_qword_t);
1175                 for (index = 0; index < total; ++index) {
1176                         EFSYS_MEM_WRITEQ(eep->ee_esmp, offset, &(ev[0]));
1177                         offset += sizeof (efx_qword_t);
1178                 }
1179
1180                 count += total;
1181
1182         } while (total == batch);
1183
1184         *countp = count;
1185 }
1186
1187 static          void
1188 siena_ev_qpost(
1189         __in    efx_evq_t *eep,
1190         __in    uint16_t data)
1191 {
1192         efx_nic_t *enp = eep->ee_enp;
1193         efx_qword_t ev;
1194         efx_oword_t oword;
1195
1196         EFX_POPULATE_QWORD_2(ev, FSF_AZ_EV_CODE, FSE_AZ_EV_CODE_DRV_GEN_EV,
1197             FSF_AZ_EV_DATA_DW0, (uint32_t)data);
1198
1199         EFX_POPULATE_OWORD_3(oword, FRF_AZ_DRV_EV_QID, eep->ee_index,
1200             EFX_DWORD_0, EFX_QWORD_FIELD(ev, EFX_DWORD_0),
1201             EFX_DWORD_1, EFX_QWORD_FIELD(ev, EFX_DWORD_1));
1202
1203         EFX_BAR_WRITEO(enp, FR_AZ_DRV_EV_REG, &oword);
1204 }
1205
1206 static  __checkReturn   efx_rc_t
1207 siena_ev_qmoderate(
1208         __in            efx_evq_t *eep,
1209         __in            unsigned int us)
1210 {
1211         efx_nic_t *enp = eep->ee_enp;
1212         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1213         unsigned int locked;
1214         efx_dword_t dword;
1215         efx_rc_t rc;
1216
1217         if (us > encp->enc_evq_timer_max_us) {
1218                 rc = EINVAL;
1219                 goto fail1;
1220         }
1221
1222         /* If the value is zero then disable the timer */
1223         if (us == 0) {
1224                 EFX_POPULATE_DWORD_2(dword,
1225                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_DIS,
1226                     FRF_CZ_TC_TIMER_VAL, 0);
1227         } else {
1228                 uint32_t timer_val;
1229
1230                 /* Calculate the timer value in quanta */
1231                 timer_val = us * 1000 / encp->enc_evq_timer_quantum_ns;
1232
1233                 /* Moderation value is base 0 so we need to deduct 1 */
1234                 if (timer_val > 0)
1235                         timer_val--;
1236
1237                 EFX_POPULATE_DWORD_2(dword,
1238                     FRF_CZ_TC_TIMER_MODE, FFE_CZ_TIMER_MODE_INT_HLDOFF,
1239                     FRF_CZ_TC_TIMER_VAL, timer_val);
1240         }
1241
1242         locked = (eep->ee_index == 0) ? 1 : 0;
1243
1244         EFX_BAR_TBL_WRITED(enp, FR_BZ_TIMER_COMMAND_REGP0,
1245             eep->ee_index, &dword, locked);
1246
1247         return (0);
1248
1249 fail1:
1250         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1251
1252         return (rc);
1253 }
1254
1255 static  __checkReturn   efx_rc_t
1256 siena_ev_qcreate(
1257         __in            efx_nic_t *enp,
1258         __in            unsigned int index,
1259         __in            efsys_mem_t *esmp,
1260         __in            size_t n,
1261         __in            uint32_t id,
1262         __in            uint32_t us,
1263         __in            efx_evq_t *eep)
1264 {
1265         efx_nic_cfg_t *encp = &(enp->en_nic_cfg);
1266         uint32_t size;
1267         efx_oword_t oword;
1268         efx_rc_t rc;
1269
1270         _NOTE(ARGUNUSED(esmp))
1271
1272         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MAXNEVS));
1273         EFX_STATIC_ASSERT(ISP2(EFX_EVQ_MINNEVS));
1274
1275         if (!ISP2(n) || (n < EFX_EVQ_MINNEVS) || (n > EFX_EVQ_MAXNEVS)) {
1276                 rc = EINVAL;
1277                 goto fail1;
1278         }
1279         if (index >= encp->enc_evq_limit) {
1280                 rc = EINVAL;
1281                 goto fail2;
1282         }
1283 #if EFSYS_OPT_RX_SCALE
1284         if (enp->en_intr.ei_type == EFX_INTR_LINE &&
1285             index >= EFX_MAXRSS_LEGACY) {
1286                 rc = EINVAL;
1287                 goto fail3;
1288         }
1289 #endif
1290         for (size = 0; (1 << size) <= (EFX_EVQ_MAXNEVS / EFX_EVQ_MINNEVS);
1291             size++)
1292                 if ((1 << size) == (int)(n / EFX_EVQ_MINNEVS))
1293                         break;
1294         if (id + (1 << size) >= encp->enc_buftbl_limit) {
1295                 rc = EINVAL;
1296                 goto fail4;
1297         }
1298
1299         /* Set up the handler table */
1300         eep->ee_rx      = siena_ev_rx;
1301         eep->ee_tx      = siena_ev_tx;
1302         eep->ee_driver  = siena_ev_driver;
1303         eep->ee_global  = siena_ev_global;
1304         eep->ee_drv_gen = siena_ev_drv_gen;
1305 #if EFSYS_OPT_MCDI
1306         eep->ee_mcdi    = siena_ev_mcdi;
1307 #endif  /* EFSYS_OPT_MCDI */
1308
1309         /* Set up the new event queue */
1310         EFX_POPULATE_OWORD_1(oword, FRF_CZ_TIMER_Q_EN, 1);
1311         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, index, &oword, B_TRUE);
1312
1313         EFX_POPULATE_OWORD_3(oword, FRF_AZ_EVQ_EN, 1, FRF_AZ_EVQ_SIZE, size,
1314             FRF_AZ_EVQ_BUF_BASE_ID, id);
1315
1316         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL, index, &oword, B_TRUE);
1317
1318         /* Set initial interrupt moderation */
1319         siena_ev_qmoderate(eep, us);
1320
1321         return (0);
1322
1323 fail4:
1324         EFSYS_PROBE(fail4);
1325 #if EFSYS_OPT_RX_SCALE
1326 fail3:
1327         EFSYS_PROBE(fail3);
1328 #endif
1329 fail2:
1330         EFSYS_PROBE(fail2);
1331 fail1:
1332         EFSYS_PROBE1(fail1, efx_rc_t, rc);
1333
1334         return (rc);
1335 }
1336
1337 #endif /* EFSYS_OPT_SIENA */
1338
1339 #if EFSYS_OPT_QSTATS
1340 #if EFSYS_OPT_NAMES
1341 /* START MKCONFIG GENERATED EfxEventQueueStatNamesBlock b693ddf85aee1bfd */
1342 static const char       *__efx_ev_qstat_name[] = {
1343         "all",
1344         "rx",
1345         "rx_ok",
1346         "rx_frm_trunc",
1347         "rx_tobe_disc",
1348         "rx_pause_frm_err",
1349         "rx_buf_owner_id_err",
1350         "rx_ipv4_hdr_chksum_err",
1351         "rx_tcp_udp_chksum_err",
1352         "rx_eth_crc_err",
1353         "rx_ip_frag_err",
1354         "rx_mcast_pkt",
1355         "rx_mcast_hash_match",
1356         "rx_tcp_ipv4",
1357         "rx_tcp_ipv6",
1358         "rx_udp_ipv4",
1359         "rx_udp_ipv6",
1360         "rx_other_ipv4",
1361         "rx_other_ipv6",
1362         "rx_non_ip",
1363         "rx_batch",
1364         "tx",
1365         "tx_wq_ff_full",
1366         "tx_pkt_err",
1367         "tx_pkt_too_big",
1368         "tx_unexpected",
1369         "global",
1370         "global_mnt",
1371         "driver",
1372         "driver_srm_upd_done",
1373         "driver_tx_descq_fls_done",
1374         "driver_rx_descq_fls_done",
1375         "driver_rx_descq_fls_failed",
1376         "driver_rx_dsc_error",
1377         "driver_tx_dsc_error",
1378         "drv_gen",
1379         "mcdi_response",
1380 };
1381 /* END MKCONFIG GENERATED EfxEventQueueStatNamesBlock */
1382
1383                 const char *
1384 efx_ev_qstat_name(
1385         __in    efx_nic_t *enp,
1386         __in    unsigned int id)
1387 {
1388         EFSYS_ASSERT3U(enp->en_magic, ==, EFX_NIC_MAGIC);
1389         EFSYS_ASSERT3U(id, <, EV_NQSTATS);
1390
1391         return (__efx_ev_qstat_name[id]);
1392 }
1393 #endif  /* EFSYS_OPT_NAMES */
1394 #endif  /* EFSYS_OPT_QSTATS */
1395
1396 #if EFSYS_OPT_SIENA
1397
1398 #if EFSYS_OPT_QSTATS
1399 static                                  void
1400 siena_ev_qstats_update(
1401         __in                            efx_evq_t *eep,
1402         __inout_ecount(EV_NQSTATS)      efsys_stat_t *stat)
1403 {
1404         unsigned int id;
1405
1406         for (id = 0; id < EV_NQSTATS; id++) {
1407                 efsys_stat_t *essp = &stat[id];
1408
1409                 EFSYS_STAT_INCR(essp, eep->ee_stat[id]);
1410                 eep->ee_stat[id] = 0;
1411         }
1412 }
1413 #endif  /* EFSYS_OPT_QSTATS */
1414
1415 static          void
1416 siena_ev_qdestroy(
1417         __in    efx_evq_t *eep)
1418 {
1419         efx_nic_t *enp = eep->ee_enp;
1420         efx_oword_t oword;
1421
1422         /* Purge event queue */
1423         EFX_ZERO_OWORD(oword);
1424
1425         EFX_BAR_TBL_WRITEO(enp, FR_AZ_EVQ_PTR_TBL,
1426             eep->ee_index, &oword, B_TRUE);
1427
1428         EFX_ZERO_OWORD(oword);
1429         EFX_BAR_TBL_WRITEO(enp, FR_AZ_TIMER_TBL, eep->ee_index, &oword, B_TRUE);
1430 }
1431
1432 static          void
1433 siena_ev_fini(
1434         __in    efx_nic_t *enp)
1435 {
1436         _NOTE(ARGUNUSED(enp))
1437 }
1438
1439 #endif /* EFSYS_OPT_SIENA */