sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * Copyright (c) 2007-2016 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _SYS_EFX_IMPL_H
  34 #define _SYS_EFX_IMPL_H
  35
  36 #include "efx.h"
  37 #include "efx_regs.h"
  38 #include "efx_regs_ef10.h"
  39
  40 /* FIXME: Add definition for driver generated software events */
  41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  43 #endif
  44
  45
  46 #if EFSYS_OPT_SIENA
  47 #include "siena_impl.h"
  48 #endif  /* EFSYS_OPT_SIENA */
  49
  50 #if EFSYS_OPT_HUNTINGTON
  51 #include "hunt_impl.h"
  52 #endif  /* EFSYS_OPT_HUNTINGTON */
  53
  54 #if EFSYS_OPT_MEDFORD
  55 #include "medford_impl.h"
  56 #endif  /* EFSYS_OPT_MEDFORD */
  57
  58 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  59 #include "ef10_impl.h"
  60 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  61
  62 #ifdef  __cplusplus
  63 extern "C" {
  64 #endif
  65
  66 #define EFX_MOD_MCDI            0x00000001
  67 #define EFX_MOD_PROBE           0x00000002
  68 #define EFX_MOD_NVRAM           0x00000004
  69 #define EFX_MOD_VPD             0x00000008
  70 #define EFX_MOD_NIC             0x00000010
  71 #define EFX_MOD_INTR            0x00000020
  72 #define EFX_MOD_EV              0x00000040
  73 #define EFX_MOD_RX              0x00000080
  74 #define EFX_MOD_TX              0x00000100
  75 #define EFX_MOD_PORT            0x00000200
  76 #define EFX_MOD_MON             0x00000400
  77 #define EFX_MOD_WOL             0x00000800
  78 #define EFX_MOD_FILTER          0x00001000
  79 #define EFX_MOD_LIC             0x00002000
  80
  81 #define EFX_RESET_PHY           0x00000001
  82 #define EFX_RESET_RXQ_ERR       0x00000002
  83 #define EFX_RESET_TXQ_ERR       0x00000004
  84
  85 typedef enum efx_mac_type_e {
  86         EFX_MAC_INVALID = 0,
  87         EFX_MAC_SIENA,
  88         EFX_MAC_HUNTINGTON,
  89         EFX_MAC_MEDFORD,
  90         EFX_MAC_NTYPES
  91 } efx_mac_type_t;
  92
  93 typedef struct efx_ev_ops_s {
  94         efx_rc_t        (*eevo_init)(efx_nic_t *);
  95         void            (*eevo_fini)(efx_nic_t *);
  96         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  97                                           efsys_mem_t *, size_t, uint32_t,
  98                                           uint32_t, efx_evq_t *);
  99         void            (*eevo_qdestroy)(efx_evq_t *);
 100         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 101         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 102         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 103 #if EFSYS_OPT_QSTATS
 104         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 105 #endif
 106 } efx_ev_ops_t;
 107
 108 typedef struct efx_tx_ops_s {
 109         efx_rc_t        (*etxo_init)(efx_nic_t *);
 110         void            (*etxo_fini)(efx_nic_t *);
 111         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 112                                         unsigned int, unsigned int,
 113                                         efsys_mem_t *, size_t,
 114                                         uint32_t, uint16_t,
 115                                         efx_evq_t *, efx_txq_t *,
 116                                         unsigned int *);
 117         void            (*etxo_qdestroy)(efx_txq_t *);
 118         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 119                                       unsigned int, unsigned int,
 120                                       unsigned int *);
 121         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 122         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 123         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 124         void            (*etxo_qenable)(efx_txq_t *);
 125         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 126         void            (*etxo_qpio_disable)(efx_txq_t *);
 127         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
 128                                            size_t);
 129         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 130                                            unsigned int *);
 131         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 132                                       unsigned int, unsigned int,
 133                                       unsigned int *);
 134         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 135                                                 size_t, boolean_t,
 136                                                 efx_desc_t *);
 137         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 138                                                 uint32_t, uint8_t,
 139                                                 efx_desc_t *);
 140         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 141                                                 uint32_t, uint16_t,
 142                                                 efx_desc_t *, int);
 143         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 144                                                 efx_desc_t *);
 145 #if EFSYS_OPT_QSTATS
 146         void            (*etxo_qstats_update)(efx_txq_t *,
 147                                               efsys_stat_t *);
 148 #endif
 149 } efx_tx_ops_t;
 150
 151 typedef struct efx_rx_ops_s {
 152         efx_rc_t        (*erxo_init)(efx_nic_t *);
 153         void            (*erxo_fini)(efx_nic_t *);
 154 #if EFSYS_OPT_RX_SCATTER
 155         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 156 #endif
 157 #if EFSYS_OPT_RX_SCALE
 158         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 159                                                efx_rx_hash_type_t, boolean_t);
 160         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 161         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 162                                               size_t);
 163         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 164                                             uint8_t *);
 165 #endif /* EFSYS_OPT_RX_SCALE */
 166         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 167                                               uint16_t *);
 168         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 169                                       unsigned int, unsigned int,
 170                                       unsigned int);
 171         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 172         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 173         void            (*erxo_qenable)(efx_rxq_t *);
 174         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 175                                         unsigned int, efx_rxq_type_t,
 176                                         efsys_mem_t *, size_t, uint32_t,
 177                                         efx_evq_t *, efx_rxq_t *);
 178         void            (*erxo_qdestroy)(efx_rxq_t *);
 179 } efx_rx_ops_t;
 180
 181 typedef struct efx_mac_ops_s {
 182         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 183         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 184         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 185         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 186         efx_rc_t        (*emo_pdu_get)(efx_nic_t *, size_t *);
 187         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 188         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 189         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 190                                                       efx_rxq_t *, boolean_t);
 191         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 192 #if EFSYS_OPT_LOOPBACK
 193         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 194                                             efx_loopback_type_t);
 195 #endif  /* EFSYS_OPT_LOOPBACK */
 196 #if EFSYS_OPT_MAC_STATS
 197         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 198         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 199                                               uint16_t, boolean_t);
 200         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 201                                             efsys_stat_t *, uint32_t *);
 202 #endif  /* EFSYS_OPT_MAC_STATS */
 203 } efx_mac_ops_t;
 204
 205 typedef struct efx_phy_ops_s {
 206         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 207         efx_rc_t        (*epo_reset)(efx_nic_t *);
 208         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 209         efx_rc_t        (*epo_verify)(efx_nic_t *);
 210         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 211 #if EFSYS_OPT_PHY_STATS
 212         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 213                                             uint32_t *);
 214 #endif  /* EFSYS_OPT_PHY_STATS */
 215 #if EFSYS_OPT_BIST
 216         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 217         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 218         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 219                                          efx_bist_result_t *, uint32_t *,
 220                                          unsigned long *, size_t);
 221         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 222 #endif  /* EFSYS_OPT_BIST */
 223 } efx_phy_ops_t;
 224
 225 #if EFSYS_OPT_FILTER
 226 typedef struct efx_filter_ops_s {
 227         efx_rc_t        (*efo_init)(efx_nic_t *);
 228         void            (*efo_fini)(efx_nic_t *);
 229         efx_rc_t        (*efo_restore)(efx_nic_t *);
 230         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 231                                    boolean_t may_replace);
 232         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 233         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 234         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 235                                    boolean_t, boolean_t, boolean_t,
 236                                    uint8_t const *, uint32_t);
 237 } efx_filter_ops_t;
 238
 239 extern  __checkReturn   efx_rc_t
 240 efx_filter_reconfigure(
 241         __in                            efx_nic_t *enp,
 242         __in_ecount(6)                  uint8_t const *mac_addr,
 243         __in                            boolean_t all_unicst,
 244         __in                            boolean_t mulcst,
 245         __in                            boolean_t all_mulcst,
 246         __in                            boolean_t brdcst,
 247         __in_ecount(6*count)            uint8_t const *addrs,
 248         __in                            uint32_t count);
 249
 250 #endif /* EFSYS_OPT_FILTER */
 251
 252
 253 typedef struct efx_port_s {
 254         efx_mac_type_t          ep_mac_type;
 255         uint32_t                ep_phy_type;
 256         uint8_t                 ep_port;
 257         uint32_t                ep_mac_pdu;
 258         uint8_t                 ep_mac_addr[6];
 259         efx_link_mode_t         ep_link_mode;
 260         boolean_t               ep_all_unicst;
 261         boolean_t               ep_mulcst;
 262         boolean_t               ep_all_mulcst;
 263         boolean_t               ep_brdcst;
 264         unsigned int            ep_fcntl;
 265         boolean_t               ep_fcntl_autoneg;
 266         efx_oword_t             ep_multicst_hash[2];
 267         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 268                                                     EFX_MAC_MULTICAST_LIST_MAX];
 269         uint32_t                ep_mulcst_addr_count;
 270 #if EFSYS_OPT_LOOPBACK
 271         efx_loopback_type_t     ep_loopback_type;
 272         efx_link_mode_t         ep_loopback_link_mode;
 273 #endif  /* EFSYS_OPT_LOOPBACK */
 274 #if EFSYS_OPT_PHY_FLAGS
 275         uint32_t                ep_phy_flags;
 276 #endif  /* EFSYS_OPT_PHY_FLAGS */
 277 #if EFSYS_OPT_PHY_LED_CONTROL
 278         efx_phy_led_mode_t      ep_phy_led_mode;
 279 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 280         efx_phy_media_type_t    ep_fixed_port_type;
 281         efx_phy_media_type_t    ep_module_type;
 282         uint32_t                ep_adv_cap_mask;
 283         uint32_t                ep_lp_cap_mask;
 284         uint32_t                ep_default_adv_cap_mask;
 285         uint32_t                ep_phy_cap_mask;
 286         boolean_t               ep_mac_drain;
 287         boolean_t               ep_mac_stats_pending;
 288 #if EFSYS_OPT_BIST
 289         efx_bist_type_t         ep_current_bist;
 290 #endif
 291         const efx_mac_ops_t     *ep_emop;
 292         const efx_phy_ops_t     *ep_epop;
 293 } efx_port_t;
 294
 295 typedef struct efx_mon_ops_s {
 296 #if EFSYS_OPT_MON_STATS
 297         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 298                                             efx_mon_stat_value_t *);
 299 #endif  /* EFSYS_OPT_MON_STATS */
 300 } efx_mon_ops_t;
 301
 302 typedef struct efx_mon_s {
 303         efx_mon_type_t          em_type;
 304         const efx_mon_ops_t     *em_emop;
 305 } efx_mon_t;
 306
 307 typedef struct efx_intr_ops_s {
 308         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 309         void            (*eio_enable)(efx_nic_t *);
 310         void            (*eio_disable)(efx_nic_t *);
 311         void            (*eio_disable_unlocked)(efx_nic_t *);
 312         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 313         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 314         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 315                                  boolean_t *);
 316         void            (*eio_fatal)(efx_nic_t *);
 317         void            (*eio_fini)(efx_nic_t *);
 318 } efx_intr_ops_t;
 319
 320 typedef struct efx_intr_s {
 321         const efx_intr_ops_t    *ei_eiop;
 322         efsys_mem_t             *ei_esmp;
 323         efx_intr_type_t         ei_type;
 324         unsigned int            ei_level;
 325 } efx_intr_t;
 326
 327 typedef struct efx_nic_ops_s {
 328         efx_rc_t        (*eno_probe)(efx_nic_t *);
 329         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 330         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 331         efx_rc_t        (*eno_reset)(efx_nic_t *);
 332         efx_rc_t        (*eno_init)(efx_nic_t *);
 333         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 334         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 335                                         uint32_t *, size_t *);
 336 #if EFSYS_OPT_DIAG
 337         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 338 #endif  /* EFSYS_OPT_DIAG */
 339         void            (*eno_fini)(efx_nic_t *);
 340         void            (*eno_unprobe)(efx_nic_t *);
 341 } efx_nic_ops_t;
 342
 343 #ifndef EFX_TXQ_LIMIT_TARGET
 344 #define EFX_TXQ_LIMIT_TARGET 259
 345 #endif
 346 #ifndef EFX_RXQ_LIMIT_TARGET
 347 #define EFX_RXQ_LIMIT_TARGET 512
 348 #endif
 349 #ifndef EFX_TXQ_DC_SIZE
 350 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 351 #endif
 352 #ifndef EFX_RXQ_DC_SIZE
 353 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 354 #endif
 355
 356 #if EFSYS_OPT_FILTER
 357
 358 typedef struct siena_filter_spec_s {
 359         uint8_t         sfs_type;
 360         uint32_t        sfs_flags;
 361         uint32_t        sfs_dmaq_id;
 362         uint32_t        sfs_dword[3];
 363 } siena_filter_spec_t;
 364
 365 typedef enum siena_filter_type_e {
 366         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 367         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 368         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 369         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 370         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 371         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 372
 373         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 374         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 375         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 376         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 377         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 378         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 379
 380         EFX_SIENA_FILTER_NTYPES
 381 } siena_filter_type_t;
 382
 383 typedef enum siena_filter_tbl_id_e {
 384         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 385         EFX_SIENA_FILTER_TBL_RX_MAC,
 386         EFX_SIENA_FILTER_TBL_TX_IP,
 387         EFX_SIENA_FILTER_TBL_TX_MAC,
 388         EFX_SIENA_FILTER_NTBLS
 389 } siena_filter_tbl_id_t;
 390
 391 typedef struct siena_filter_tbl_s {
 392         int                     sft_size;       /* number of entries */
 393         int                     sft_used;       /* active count */
 394         uint32_t                *sft_bitmap;    /* active bitmap */
 395         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 396 } siena_filter_tbl_t;
 397
 398 typedef struct siena_filter_s {
 399         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 400         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 401 } siena_filter_t;
 402
 403 typedef struct efx_filter_s {
 404 #if EFSYS_OPT_SIENA
 405         siena_filter_t          *ef_siena_filter;
 406 #endif /* EFSYS_OPT_SIENA */
 407 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 408         ef10_filter_table_t     *ef_ef10_filter_table;
 409 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 410 } efx_filter_t;
 411
 412 extern                  void
 413 siena_filter_tbl_clear(
 414         __in            efx_nic_t *enp,
 415         __in            siena_filter_tbl_id_t tbl);
 416
 417 #endif  /* EFSYS_OPT_FILTER */
 418
 419 #if EFSYS_OPT_MCDI
 420
 421 typedef struct efx_mcdi_ops_s {
 422         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 423         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 424                                         void *, size_t);
 425         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 426         boolean_t       (*emco_poll_response)(efx_nic_t *);
 427         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 428         void            (*emco_fini)(efx_nic_t *);
 429         efx_rc_t        (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
 430 } efx_mcdi_ops_t;
 431
 432 typedef struct efx_mcdi_s {
 433         const efx_mcdi_ops_t            *em_emcop;
 434         const efx_mcdi_transport_t      *em_emtp;
 435         efx_mcdi_iface_t                em_emip;
 436 } efx_mcdi_t;
 437
 438 #endif /* EFSYS_OPT_MCDI */
 439
 440 #if EFSYS_OPT_NVRAM
 441 typedef struct efx_nvram_ops_s {
 442 #if EFSYS_OPT_DIAG
 443         efx_rc_t        (*envo_test)(efx_nic_t *);
 444 #endif  /* EFSYS_OPT_DIAG */
 445         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 446                                             uint32_t *);
 447         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 448         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 449         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 450                                             unsigned int, caddr_t, size_t);
 451         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 452                                             unsigned int, size_t);
 453         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 454                                             unsigned int, caddr_t, size_t);
 455         void            (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 456         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 457                                             uint32_t *, uint16_t *);
 458         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 459                                             uint16_t *);
 460         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 461                                             caddr_t, size_t);
 462 } efx_nvram_ops_t;
 463 #endif /* EFSYS_OPT_NVRAM */
 464
 465 #if EFSYS_OPT_VPD
 466 typedef struct efx_vpd_ops_s {
 467         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 468         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 469         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 470         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 471         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 472         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 473                                         efx_vpd_value_t *);
 474         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 475                                         efx_vpd_value_t *);
 476         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 477                                         efx_vpd_value_t *, unsigned int *);
 478         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 479         void            (*evpdo_fini)(efx_nic_t *);
 480 } efx_vpd_ops_t;
 481 #endif  /* EFSYS_OPT_VPD */
 482
 483 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 484
 485         __checkReturn           efx_rc_t
 486 efx_mcdi_nvram_partitions(
 487         __in                    efx_nic_t *enp,
 488         __out_bcount(size)      caddr_t data,
 489         __in                    size_t size,
 490         __out                   unsigned int *npartnp);
 491
 492         __checkReturn           efx_rc_t
 493 efx_mcdi_nvram_metadata(
 494         __in                    efx_nic_t *enp,
 495         __in                    uint32_t partn,
 496         __out                   uint32_t *subtypep,
 497         __out_ecount(4)         uint16_t version[4],
 498         __out_bcount_opt(size)  char *descp,
 499         __in                    size_t size);
 500
 501         __checkReturn           efx_rc_t
 502 efx_mcdi_nvram_info(
 503         __in                    efx_nic_t *enp,
 504         __in                    uint32_t partn,
 505         __out_opt               size_t *sizep,
 506         __out_opt               uint32_t *addressp,
 507         __out_opt               uint32_t *erase_sizep,
 508         __out_opt               uint32_t *write_sizep);
 509
 510         __checkReturn           efx_rc_t
 511 efx_mcdi_nvram_update_start(
 512         __in                    efx_nic_t *enp,
 513         __in                    uint32_t partn);
 514
 515         __checkReturn           efx_rc_t
 516 efx_mcdi_nvram_read(
 517         __in                    efx_nic_t *enp,
 518         __in                    uint32_t partn,
 519         __in                    uint32_t offset,
 520         __out_bcount(size)      caddr_t data,
 521         __in                    size_t size,
 522         __in                    uint32_t mode);
 523
 524         __checkReturn           efx_rc_t
 525 efx_mcdi_nvram_erase(
 526         __in                    efx_nic_t *enp,
 527         __in                    uint32_t partn,
 528         __in                    uint32_t offset,
 529         __in                    size_t size);
 530
 531         __checkReturn           efx_rc_t
 532 efx_mcdi_nvram_write(
 533         __in                    efx_nic_t *enp,
 534         __in                    uint32_t partn,
 535         __in                    uint32_t offset,
 536         __out_bcount(size)      caddr_t data,
 537         __in                    size_t size);
 538
 539         __checkReturn           efx_rc_t
 540 efx_mcdi_nvram_update_finish(
 541         __in                    efx_nic_t *enp,
 542         __in                    uint32_t partn,
 543         __in                    boolean_t reboot);
 544
 545 #if EFSYS_OPT_DIAG
 546
 547         __checkReturn           efx_rc_t
 548 efx_mcdi_nvram_test(
 549         __in                    efx_nic_t *enp,
 550         __in                    uint32_t partn);
 551
 552 #endif  /* EFSYS_OPT_DIAG */
 553
 554 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 555
 556 #if EFSYS_OPT_LICENSING
 557
 558 typedef struct efx_lic_ops_s {
 559         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 560         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 561         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 562         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 563                                       size_t *, uint8_t *);
 564         efx_rc_t        (*elo_find_start)
 565                                 (efx_nic_t *, caddr_t, size_t, uint32_t *);
 566         efx_rc_t        (*elo_find_end)(efx_nic_t *, caddr_t, size_t,
 567                                 uint32_t, uint32_t *);
 568         boolean_t       (*elo_find_key)(efx_nic_t *, caddr_t, size_t,
 569                                 uint32_t, uint32_t *, uint32_t *);
 570         boolean_t       (*elo_validate_key)(efx_nic_t *,
 571                                 caddr_t, uint32_t);
 572         efx_rc_t        (*elo_read_key)(efx_nic_t *,
 573                                 caddr_t, size_t, uint32_t, uint32_t,
 574                                 caddr_t, size_t, uint32_t *);
 575         efx_rc_t        (*elo_write_key)(efx_nic_t *,
 576                                 caddr_t, size_t, uint32_t,
 577                                 caddr_t, uint32_t, uint32_t *);
 578         efx_rc_t        (*elo_delete_key)(efx_nic_t *,
 579                                 caddr_t, size_t, uint32_t,
 580                                 uint32_t, uint32_t, uint32_t *);
 581         efx_rc_t        (*elo_create_partition)(efx_nic_t *,
 582                                 caddr_t, size_t);
 583         efx_rc_t        (*elo_finish_partition)(efx_nic_t *,
 584                                 caddr_t, size_t);
 585 } efx_lic_ops_t;
 586
 587 #endif
 588
 589 typedef struct efx_drv_cfg_s {
 590         uint32_t                edc_min_vi_count;
 591         uint32_t                edc_max_vi_count;
 592
 593         uint32_t                edc_max_piobuf_count;
 594         uint32_t                edc_pio_alloc_size;
 595 } efx_drv_cfg_t;
 596
 597 struct efx_nic_s {
 598         uint32_t                en_magic;
 599         efx_family_t            en_family;
 600         uint32_t                en_features;
 601         efsys_identifier_t      *en_esip;
 602         efsys_lock_t            *en_eslp;
 603         efsys_bar_t             *en_esbp;
 604         unsigned int            en_mod_flags;
 605         unsigned int            en_reset_flags;
 606         efx_nic_cfg_t           en_nic_cfg;
 607         efx_drv_cfg_t           en_drv_cfg;
 608         efx_port_t              en_port;
 609         efx_mon_t               en_mon;
 610         efx_intr_t              en_intr;
 611         uint32_t                en_ev_qcount;
 612         uint32_t                en_rx_qcount;
 613         uint32_t                en_tx_qcount;
 614         const efx_nic_ops_t     *en_enop;
 615         const efx_ev_ops_t      *en_eevop;
 616         const efx_tx_ops_t      *en_etxop;
 617         const efx_rx_ops_t      *en_erxop;
 618 #if EFSYS_OPT_FILTER
 619         efx_filter_t            en_filter;
 620         const efx_filter_ops_t  *en_efop;
 621 #endif  /* EFSYS_OPT_FILTER */
 622 #if EFSYS_OPT_MCDI
 623         efx_mcdi_t              en_mcdi;
 624 #endif  /* EFSYS_OPT_MCDI */
 625 #if EFSYS_OPT_NVRAM
 626         efx_nvram_type_t        en_nvram_locked;
 627         const efx_nvram_ops_t   *en_envop;
 628 #endif  /* EFSYS_OPT_NVRAM */
 629 #if EFSYS_OPT_VPD
 630         const efx_vpd_ops_t     *en_evpdop;
 631 #endif  /* EFSYS_OPT_VPD */
 632 #if EFSYS_OPT_RX_SCALE
 633         efx_rx_hash_support_t   en_hash_support;
 634         efx_rx_scale_support_t  en_rss_support;
 635         uint32_t                en_rss_context;
 636 #endif  /* EFSYS_OPT_RX_SCALE */
 637         uint32_t                en_vport_id;
 638 #if EFSYS_OPT_LICENSING
 639         const efx_lic_ops_t     *en_elop;
 640         boolean_t               en_licensing_supported;
 641 #endif
 642         union {
 643 #if EFSYS_OPT_SIENA
 644                 struct {
 645 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 646                         unsigned int            enu_partn_mask;
 647 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 648 #if EFSYS_OPT_VPD
 649                         caddr_t                 enu_svpd;
 650                         size_t                  enu_svpd_length;
 651 #endif  /* EFSYS_OPT_VPD */
 652                         int                     enu_unused;
 653                 } siena;
 654 #endif  /* EFSYS_OPT_SIENA */
 655                 int     enu_unused;
 656         } en_u;
 657 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 658         union en_arch {
 659                 struct {
 660                         int                     ena_vi_base;
 661                         int                     ena_vi_count;
 662                         int                     ena_vi_shift;
 663 #if EFSYS_OPT_VPD
 664                         caddr_t                 ena_svpd;
 665                         size_t                  ena_svpd_length;
 666 #endif  /* EFSYS_OPT_VPD */
 667                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 668                         uint32_t                ena_piobuf_count;
 669                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 670                         uint32_t                ena_pio_write_vi_base;
 671                         /* Memory BAR mapping regions */
 672                         uint32_t                ena_uc_mem_map_offset;
 673                         size_t                  ena_uc_mem_map_size;
 674                         uint32_t                ena_wc_mem_map_offset;
 675                         size_t                  ena_wc_mem_map_size;
 676                 } ef10;
 677         } en_arch;
 678 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 679 };
 680
 681
 682 #define EFX_NIC_MAGIC   0x02121996
 683
 684 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 685     const efx_ev_callbacks_t *, void *);
 686
 687 typedef struct efx_evq_rxq_state_s {
 688         unsigned int                    eers_rx_read_ptr;
 689         unsigned int                    eers_rx_mask;
 690 } efx_evq_rxq_state_t;
 691
 692 struct efx_evq_s {
 693         uint32_t                        ee_magic;
 694         efx_nic_t                       *ee_enp;
 695         unsigned int                    ee_index;
 696         unsigned int                    ee_mask;
 697         efsys_mem_t                     *ee_esmp;
 698 #if EFSYS_OPT_QSTATS
 699         uint32_t                        ee_stat[EV_NQSTATS];
 700 #endif  /* EFSYS_OPT_QSTATS */
 701
 702         efx_ev_handler_t                ee_rx;
 703         efx_ev_handler_t                ee_tx;
 704         efx_ev_handler_t                ee_driver;
 705         efx_ev_handler_t                ee_global;
 706         efx_ev_handler_t                ee_drv_gen;
 707 #if EFSYS_OPT_MCDI
 708         efx_ev_handler_t                ee_mcdi;
 709 #endif  /* EFSYS_OPT_MCDI */
 710
 711         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 712 };
 713
 714 #define EFX_EVQ_MAGIC   0x08081997
 715
 716 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 717
 718 struct efx_rxq_s {
 719         uint32_t                        er_magic;
 720         efx_nic_t                       *er_enp;
 721         efx_evq_t                       *er_eep;
 722         unsigned int                    er_index;
 723         unsigned int                    er_label;
 724         unsigned int                    er_mask;
 725         efsys_mem_t                     *er_esmp;
 726 };
 727
 728 #define EFX_RXQ_MAGIC   0x15022005
 729
 730 struct efx_txq_s {
 731         uint32_t                        et_magic;
 732         efx_nic_t                       *et_enp;
 733         unsigned int                    et_index;
 734         unsigned int                    et_mask;
 735         efsys_mem_t                     *et_esmp;
 736 #if EFSYS_OPT_HUNTINGTON
 737         uint32_t                        et_pio_bufnum;
 738         uint32_t                        et_pio_blknum;
 739         uint32_t                        et_pio_write_offset;
 740         uint32_t                        et_pio_offset;
 741         size_t                          et_pio_size;
 742 #endif
 743 #if EFSYS_OPT_QSTATS
 744         uint32_t                        et_stat[TX_NQSTATS];
 745 #endif  /* EFSYS_OPT_QSTATS */
 746 };
 747
 748 #define EFX_TXQ_MAGIC   0x05092005
 749
 750 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 751         do {                                                            \
 752                 (_dst)[0] = (_src)[0];                                  \
 753                 (_dst)[1] = (_src)[1];                                  \
 754                 (_dst)[2] = (_src)[2];                                  \
 755                 (_dst)[3] = (_src)[3];                                  \
 756                 (_dst)[4] = (_src)[4];                                  \
 757                 (_dst)[5] = (_src)[5];                                  \
 758         _NOTE(CONSTANTCONDITION)                                        \
 759         } while (B_FALSE)
 760
 761 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 762         do {                                                            \
 763                 uint16_t *_d = (uint16_t *)(_dst);                      \
 764                 _d[0] = 0xffff;                                         \
 765                 _d[1] = 0xffff;                                         \
 766                 _d[2] = 0xffff;                                         \
 767         _NOTE(CONSTANTCONDITION)                                        \
 768         } while (B_FALSE)
 769
 770 #if EFSYS_OPT_CHECK_REG
 771 #define EFX_CHECK_REG(_enp, _reg)                                       \
 772         do {                                                            \
 773                 const char *name = #_reg;                               \
 774                 char min = name[4];                                     \
 775                 char max = name[5];                                     \
 776                 char rev;                                               \
 777                                                                         \
 778                 switch ((_enp)->en_family) {                            \
 779                 case EFX_FAMILY_SIENA:                                  \
 780                         rev = 'C';                                      \
 781                         break;                                          \
 782                                                                         \
 783                 case EFX_FAMILY_HUNTINGTON:                             \
 784                         rev = 'D';                                      \
 785                         break;                                          \
 786                                                                         \
 787                 case EFX_FAMILY_MEDFORD:                                \
 788                         rev = 'E';                                      \
 789                         break;                                          \
 790                                                                         \
 791                 default:                                                \
 792                         rev = '?';                                      \
 793                         break;                                          \
 794                 }                                                       \
 795                                                                         \
 796                 EFSYS_ASSERT3S(rev, >=, min);                           \
 797                 EFSYS_ASSERT3S(rev, <=, max);                           \
 798                                                                         \
 799         _NOTE(CONSTANTCONDITION)                                        \
 800         } while (B_FALSE)
 801 #else
 802 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 803         _NOTE(CONSTANTCONDITION)                                        \
 804         } while(B_FALSE)
 805 #endif
 806
 807 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 808         do {                                                            \
 809                 EFX_CHECK_REG((_enp), (_reg));                          \
 810                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 811                     (_edp), (_lock));                                   \
 812                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 813                     uint32_t, _reg ## _OFST,                            \
 814                     uint32_t, (_edp)->ed_u32[0]);                       \
 815         _NOTE(CONSTANTCONDITION)                                        \
 816         } while (B_FALSE)
 817
 818 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 819         do {                                                            \
 820                 EFX_CHECK_REG((_enp), (_reg));                          \
 821                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 822                     uint32_t, _reg ## _OFST,                            \
 823                     uint32_t, (_edp)->ed_u32[0]);                       \
 824                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 825                     (_edp), (_lock));                                   \
 826         _NOTE(CONSTANTCONDITION)                                        \
 827         } while (B_FALSE)
 828
 829 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 830         do {                                                            \
 831                 EFX_CHECK_REG((_enp), (_reg));                          \
 832                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 833                     (_eqp));                                            \
 834                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 835                     uint32_t, _reg ## _OFST,                            \
 836                     uint32_t, (_eqp)->eq_u32[1],                        \
 837                     uint32_t, (_eqp)->eq_u32[0]);                       \
 838         _NOTE(CONSTANTCONDITION)                                        \
 839         } while (B_FALSE)
 840
 841 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 842         do {                                                            \
 843                 EFX_CHECK_REG((_enp), (_reg));                          \
 844                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 845                     uint32_t, _reg ## _OFST,                            \
 846                     uint32_t, (_eqp)->eq_u32[1],                        \
 847                     uint32_t, (_eqp)->eq_u32[0]);                       \
 848                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 849                     (_eqp));                                            \
 850         _NOTE(CONSTANTCONDITION)                                        \
 851         } while (B_FALSE)
 852
 853 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 854         do {                                                            \
 855                 EFX_CHECK_REG((_enp), (_reg));                          \
 856                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 857                     (_eop), B_TRUE);                                    \
 858                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 859                     uint32_t, _reg ## _OFST,                            \
 860                     uint32_t, (_eop)->eo_u32[3],                        \
 861                     uint32_t, (_eop)->eo_u32[2],                        \
 862                     uint32_t, (_eop)->eo_u32[1],                        \
 863                     uint32_t, (_eop)->eo_u32[0]);                       \
 864         _NOTE(CONSTANTCONDITION)                                        \
 865         } while (B_FALSE)
 866
 867 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 868         do {                                                            \
 869                 EFX_CHECK_REG((_enp), (_reg));                          \
 870                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 871                     uint32_t, _reg ## _OFST,                            \
 872                     uint32_t, (_eop)->eo_u32[3],                        \
 873                     uint32_t, (_eop)->eo_u32[2],                        \
 874                     uint32_t, (_eop)->eo_u32[1],                        \
 875                     uint32_t, (_eop)->eo_u32[0]);                       \
 876                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 877                     (_eop), B_TRUE);                                    \
 878         _NOTE(CONSTANTCONDITION)                                        \
 879         } while (B_FALSE)
 880
 881 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 882         do {                                                            \
 883                 EFX_CHECK_REG((_enp), (_reg));                          \
 884                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 885                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 886                     (_edp), (_lock));                                   \
 887                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 888                     uint32_t, (_index),                                 \
 889                     uint32_t, _reg ## _OFST,                            \
 890                     uint32_t, (_edp)->ed_u32[0]);                       \
 891         _NOTE(CONSTANTCONDITION)                                        \
 892         } while (B_FALSE)
 893
 894 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 895         do {                                                            \
 896                 EFX_CHECK_REG((_enp), (_reg));                          \
 897                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 898                     uint32_t, (_index),                                 \
 899                     uint32_t, _reg ## _OFST,                            \
 900                     uint32_t, (_edp)->ed_u32[0]);                       \
 901                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 902                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 903                     (_edp), (_lock));                                   \
 904         _NOTE(CONSTANTCONDITION)                                        \
 905         } while (B_FALSE)
 906
 907 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 908         do {                                                            \
 909                 EFX_CHECK_REG((_enp), (_reg));                          \
 910                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 911                     uint32_t, (_index),                                 \
 912                     uint32_t, _reg ## _OFST,                            \
 913                     uint32_t, (_edp)->ed_u32[0]);                       \
 914                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 915                     (_reg ## _OFST +                                    \
 916                     (2 * sizeof (efx_dword_t)) +                        \
 917                     ((_index) * _reg ## _STEP)),                        \
 918                     (_edp), (_lock));                                   \
 919         _NOTE(CONSTANTCONDITION)                                        \
 920         } while (B_FALSE)
 921
 922 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 923         do {                                                            \
 924                 EFX_CHECK_REG((_enp), (_reg));                          \
 925                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 926                     uint32_t, (_index),                                 \
 927                     uint32_t, _reg ## _OFST,                            \
 928                     uint32_t, (_edp)->ed_u32[0]);                       \
 929                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 930                     (_reg ## _OFST +                                    \
 931                     (3 * sizeof (efx_dword_t)) +                        \
 932                     ((_index) * _reg ## _STEP)),                        \
 933                     (_edp), (_lock));                                   \
 934         _NOTE(CONSTANTCONDITION)                                        \
 935         } while (B_FALSE)
 936
 937 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 938         do {                                                            \
 939                 EFX_CHECK_REG((_enp), (_reg));                          \
 940                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 941                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 942                     (_eqp));                                            \
 943                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 944                     uint32_t, (_index),                                 \
 945                     uint32_t, _reg ## _OFST,                            \
 946                     uint32_t, (_eqp)->eq_u32[1],                        \
 947                     uint32_t, (_eqp)->eq_u32[0]);                       \
 948         _NOTE(CONSTANTCONDITION)                                        \
 949         } while (B_FALSE)
 950
 951 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 952         do {                                                            \
 953                 EFX_CHECK_REG((_enp), (_reg));                          \
 954                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 955                     uint32_t, (_index),                                 \
 956                     uint32_t, _reg ## _OFST,                            \
 957                     uint32_t, (_eqp)->eq_u32[1],                        \
 958                     uint32_t, (_eqp)->eq_u32[0]);                       \
 959                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 960                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 961                     (_eqp));                                            \
 962         _NOTE(CONSTANTCONDITION)                                        \
 963         } while (B_FALSE)
 964
 965 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 966         do {                                                            \
 967                 EFX_CHECK_REG((_enp), (_reg));                          \
 968                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 969                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 970                     (_eop), (_lock));                                   \
 971                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 972                     uint32_t, (_index),                                 \
 973                     uint32_t, _reg ## _OFST,                            \
 974                     uint32_t, (_eop)->eo_u32[3],                        \
 975                     uint32_t, (_eop)->eo_u32[2],                        \
 976                     uint32_t, (_eop)->eo_u32[1],                        \
 977                     uint32_t, (_eop)->eo_u32[0]);                       \
 978         _NOTE(CONSTANTCONDITION)                                        \
 979         } while (B_FALSE)
 980
 981 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 982         do {                                                            \
 983                 EFX_CHECK_REG((_enp), (_reg));                          \
 984                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 985                     uint32_t, (_index),                                 \
 986                     uint32_t, _reg ## _OFST,                            \
 987                     uint32_t, (_eop)->eo_u32[3],                        \
 988                     uint32_t, (_eop)->eo_u32[2],                        \
 989                     uint32_t, (_eop)->eo_u32[1],                        \
 990                     uint32_t, (_eop)->eo_u32[0]);                       \
 991                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 992                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 993                     (_eop), (_lock));                                   \
 994         _NOTE(CONSTANTCONDITION)                                        \
 995         } while (B_FALSE)
 996
 997 /*
 998  * Allow drivers to perform optimised 128-bit doorbell writes.
 999  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
1000  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
1001  * the need for locking in the host, and are the only ones known to be safe to
1002  * use 128-bites write with.
1003  */
1004 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
1005         do {                                                            \
1006                 EFX_CHECK_REG((_enp), (_reg));                          \
1007                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
1008                     const char *,                                       \
1009                     #_reg,                                              \
1010                     uint32_t, (_index),                                 \
1011                     uint32_t, _reg ## _OFST,                            \
1012                     uint32_t, (_eop)->eo_u32[3],                        \
1013                     uint32_t, (_eop)->eo_u32[2],                        \
1014                     uint32_t, (_eop)->eo_u32[1],                        \
1015                     uint32_t, (_eop)->eo_u32[0]);                       \
1016                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1017                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1018                     (_eop));                                            \
1019         _NOTE(CONSTANTCONDITION)                                        \
1020         } while (B_FALSE)
1021
1022 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1023         do {                                                            \
1024                 unsigned int _new = (_wptr);                            \
1025                 unsigned int _old = (_owptr);                           \
1026                                                                         \
1027                 if ((_new) >= (_old))                                   \
1028                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1029                             (_old) * sizeof (efx_desc_t),               \
1030                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1031                 else                                                    \
1032                         /*                                              \
1033                          * It is cheaper to sync entire map than sync   \
1034                          * two parts especially when offset/size are    \
1035                          * ignored and entire map is synced in any case.\
1036                          */                                             \
1037                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1038                             0,                                          \
1039                             (_entries) * sizeof (efx_desc_t));          \
1040         _NOTE(CONSTANTCONDITION)                                        \
1041         } while (B_FALSE)
1042
1043 extern  __checkReturn   efx_rc_t
1044 efx_nic_biu_test(
1045         __in            efx_nic_t *enp);
1046
1047 extern  __checkReturn   efx_rc_t
1048 efx_mac_select(
1049         __in            efx_nic_t *enp);
1050
1051 extern  void
1052 efx_mac_multicast_hash_compute(
1053         __in_ecount(6*count)            uint8_t const *addrs,
1054         __in                            int count,
1055         __out                           efx_oword_t *hash_low,
1056         __out                           efx_oword_t *hash_high);
1057
1058 extern  __checkReturn   efx_rc_t
1059 efx_phy_probe(
1060         __in            efx_nic_t *enp);
1061
1062 extern                  void
1063 efx_phy_unprobe(
1064         __in            efx_nic_t *enp);
1065
1066 #if EFSYS_OPT_VPD
1067
1068 /* VPD utility functions */
1069
1070 extern  __checkReturn           efx_rc_t
1071 efx_vpd_hunk_length(
1072         __in_bcount(size)       caddr_t data,
1073         __in                    size_t size,
1074         __out                   size_t *lengthp);
1075
1076 extern  __checkReturn           efx_rc_t
1077 efx_vpd_hunk_verify(
1078         __in_bcount(size)       caddr_t data,
1079         __in                    size_t size,
1080         __out_opt               boolean_t *cksummedp);
1081
1082 extern  __checkReturn           efx_rc_t
1083 efx_vpd_hunk_reinit(
1084         __in_bcount(size)       caddr_t data,
1085         __in                    size_t size,
1086         __in                    boolean_t wantpid);
1087
1088 extern  __checkReturn           efx_rc_t
1089 efx_vpd_hunk_get(
1090         __in_bcount(size)       caddr_t data,
1091         __in                    size_t size,
1092         __in                    efx_vpd_tag_t tag,
1093         __in                    efx_vpd_keyword_t keyword,
1094         __out                   unsigned int *payloadp,
1095         __out                   uint8_t *paylenp);
1096
1097 extern  __checkReturn                   efx_rc_t
1098 efx_vpd_hunk_next(
1099         __in_bcount(size)               caddr_t data,
1100         __in                            size_t size,
1101         __out                           efx_vpd_tag_t *tagp,
1102         __out                           efx_vpd_keyword_t *keyword,
1103         __out_opt                       unsigned int *payloadp,
1104         __out_opt                       uint8_t *paylenp,
1105         __inout                         unsigned int *contp);
1106
1107 extern  __checkReturn           efx_rc_t
1108 efx_vpd_hunk_set(
1109         __in_bcount(size)       caddr_t data,
1110         __in                    size_t size,
1111         __in                    efx_vpd_value_t *evvp);
1112
1113 #endif  /* EFSYS_OPT_VPD */
1114
1115 #if EFSYS_OPT_DIAG
1116
1117 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1118
1119 typedef struct efx_register_set_s {
1120         unsigned int            address;
1121         unsigned int            step;
1122         unsigned int            rows;
1123         efx_oword_t             mask;
1124 } efx_register_set_t;
1125
1126 extern  __checkReturn   efx_rc_t
1127 efx_nic_test_registers(
1128         __in            efx_nic_t *enp,
1129         __in            efx_register_set_t *rsp,
1130         __in            size_t count);
1131
1132 extern  __checkReturn   efx_rc_t
1133 efx_nic_test_tables(
1134         __in            efx_nic_t *enp,
1135         __in            efx_register_set_t *rsp,
1136         __in            efx_pattern_type_t pattern,
1137         __in            size_t count);
1138
1139 #endif  /* EFSYS_OPT_DIAG */
1140
1141 #if EFSYS_OPT_MCDI
1142
1143 extern  __checkReturn           efx_rc_t
1144 efx_mcdi_set_workaround(
1145         __in                    efx_nic_t *enp,
1146         __in                    uint32_t type,
1147         __in                    boolean_t enabled,
1148         __out_opt               uint32_t *flagsp);
1149
1150 extern  __checkReturn           efx_rc_t
1151 efx_mcdi_get_workarounds(
1152         __in                    efx_nic_t *enp,
1153         __out_opt               uint32_t *implementedp,
1154         __out_opt               uint32_t *enabledp);
1155
1156 #endif /* EFSYS_OPT_MCDI */
1157
1158 #ifdef  __cplusplus
1159 }
1160 #endif
1161
1162 #endif  /* _SYS_EFX_IMPL_H */