sys/dev/sfxge/common/efx_impl.h

   1 /*-
   2  * Copyright (c) 2007-2015 Solarflare Communications Inc.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *
   8  * 1. Redistributions of source code must retain the above copyright notice,
   9  *    this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright notice,
  11  *    this list of conditions and the following disclaimer in the documentation
  12  *    and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  15  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  16  * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  17  * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  18  * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  19  * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  20  * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
  21  * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
  22  * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
  23  * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
  24  * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * The views and conclusions contained in the software and documentation are
  27  * those of the authors and should not be interpreted as representing official
  28  * policies, either expressed or implied, of the FreeBSD Project.
  29  *
  30  * $FreeBSD$
  31  */
  32
  33 #ifndef _SYS_EFX_IMPL_H
  34 #define _SYS_EFX_IMPL_H
  35
  36 #include "efx.h"
  37 #include "efx_regs.h"
  38 #include "efx_regs_ef10.h"
  39
  40 /* FIXME: Add definition for driver generated software events */
  41 #ifndef ESE_DZ_EV_CODE_DRV_GEN_EV
  42 #define ESE_DZ_EV_CODE_DRV_GEN_EV FSE_AZ_EV_CODE_DRV_GEN_EV
  43 #endif
  44
  45
  46 #if EFSYS_OPT_SIENA
  47 #include "siena_impl.h"
  48 #endif  /* EFSYS_OPT_SIENA */
  49
  50 #if EFSYS_OPT_HUNTINGTON
  51 #include "hunt_impl.h"
  52 #endif  /* EFSYS_OPT_HUNTINGTON */
  53
  54 #if EFSYS_OPT_MEDFORD
  55 #include "medford_impl.h"
  56 #endif  /* EFSYS_OPT_MEDFORD */
  57
  58 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
  59 #include "ef10_impl.h"
  60 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
  61
  62 #ifdef  __cplusplus
  63 extern "C" {
  64 #endif
  65
  66 #define EFX_MOD_MCDI            0x00000001
  67 #define EFX_MOD_PROBE           0x00000002
  68 #define EFX_MOD_NVRAM           0x00000004
  69 #define EFX_MOD_VPD             0x00000008
  70 #define EFX_MOD_NIC             0x00000010
  71 #define EFX_MOD_INTR            0x00000020
  72 #define EFX_MOD_EV              0x00000040
  73 #define EFX_MOD_RX              0x00000080
  74 #define EFX_MOD_TX              0x00000100
  75 #define EFX_MOD_PORT            0x00000200
  76 #define EFX_MOD_MON             0x00000400
  77 #define EFX_MOD_WOL             0x00000800
  78 #define EFX_MOD_FILTER          0x00001000
  79 #define EFX_MOD_LIC             0x00002000
  80
  81 #define EFX_RESET_MAC           0x00000001
  82 #define EFX_RESET_PHY           0x00000002
  83 #define EFX_RESET_RXQ_ERR       0x00000004
  84 #define EFX_RESET_TXQ_ERR       0x00000008
  85
  86 typedef enum efx_mac_type_e {
  87         EFX_MAC_INVALID = 0,
  88         EFX_MAC_SIENA,
  89         EFX_MAC_HUNTINGTON,
  90         EFX_MAC_MEDFORD,
  91         EFX_MAC_NTYPES
  92 } efx_mac_type_t;
  93
  94 typedef struct efx_ev_ops_s {
  95         efx_rc_t        (*eevo_init)(efx_nic_t *);
  96         void            (*eevo_fini)(efx_nic_t *);
  97         efx_rc_t        (*eevo_qcreate)(efx_nic_t *, unsigned int,
  98                                           efsys_mem_t *, size_t, uint32_t,
  99                                           efx_evq_t *);
 100         void            (*eevo_qdestroy)(efx_evq_t *);
 101         efx_rc_t        (*eevo_qprime)(efx_evq_t *, unsigned int);
 102         void            (*eevo_qpost)(efx_evq_t *, uint16_t);
 103         efx_rc_t        (*eevo_qmoderate)(efx_evq_t *, unsigned int);
 104 #if EFSYS_OPT_QSTATS
 105         void            (*eevo_qstats_update)(efx_evq_t *, efsys_stat_t *);
 106 #endif
 107 } efx_ev_ops_t;
 108
 109 typedef struct efx_tx_ops_s {
 110         efx_rc_t        (*etxo_init)(efx_nic_t *);
 111         void            (*etxo_fini)(efx_nic_t *);
 112         efx_rc_t        (*etxo_qcreate)(efx_nic_t *,
 113                                         unsigned int, unsigned int,
 114                                         efsys_mem_t *, size_t,
 115                                         uint32_t, uint16_t,
 116                                         efx_evq_t *, efx_txq_t *,
 117                                         unsigned int *);
 118         void            (*etxo_qdestroy)(efx_txq_t *);
 119         efx_rc_t        (*etxo_qpost)(efx_txq_t *, efx_buffer_t *,
 120                                       unsigned int, unsigned int,
 121                                       unsigned int *);
 122         void            (*etxo_qpush)(efx_txq_t *, unsigned int, unsigned int);
 123         efx_rc_t        (*etxo_qpace)(efx_txq_t *, unsigned int);
 124         efx_rc_t        (*etxo_qflush)(efx_txq_t *);
 125         void            (*etxo_qenable)(efx_txq_t *);
 126         efx_rc_t        (*etxo_qpio_enable)(efx_txq_t *);
 127         void            (*etxo_qpio_disable)(efx_txq_t *);
 128         efx_rc_t        (*etxo_qpio_write)(efx_txq_t *,uint8_t *, size_t,
 129                                            size_t);
 130         efx_rc_t        (*etxo_qpio_post)(efx_txq_t *, size_t, unsigned int,
 131                                            unsigned int *);
 132         efx_rc_t        (*etxo_qdesc_post)(efx_txq_t *, efx_desc_t *,
 133                                       unsigned int, unsigned int,
 134                                       unsigned int *);
 135         void            (*etxo_qdesc_dma_create)(efx_txq_t *, efsys_dma_addr_t,
 136                                                 size_t, boolean_t,
 137                                                 efx_desc_t *);
 138         void            (*etxo_qdesc_tso_create)(efx_txq_t *, uint16_t,
 139                                                 uint32_t, uint8_t,
 140                                                 efx_desc_t *);
 141         void            (*etxo_qdesc_tso2_create)(efx_txq_t *, uint16_t,
 142                                                 uint32_t, uint16_t,
 143                                                 efx_desc_t *, int);
 144         void            (*etxo_qdesc_vlantci_create)(efx_txq_t *, uint16_t,
 145                                                 efx_desc_t *);
 146 #if EFSYS_OPT_QSTATS
 147         void            (*etxo_qstats_update)(efx_txq_t *,
 148                                               efsys_stat_t *);
 149 #endif
 150 } efx_tx_ops_t;
 151
 152 typedef struct efx_rx_ops_s {
 153         efx_rc_t        (*erxo_init)(efx_nic_t *);
 154         void            (*erxo_fini)(efx_nic_t *);
 155 #if EFSYS_OPT_RX_SCATTER
 156         efx_rc_t        (*erxo_scatter_enable)(efx_nic_t *, unsigned int);
 157 #endif
 158 #if EFSYS_OPT_RX_SCALE
 159         efx_rc_t        (*erxo_scale_mode_set)(efx_nic_t *, efx_rx_hash_alg_t,
 160                                                efx_rx_hash_type_t, boolean_t);
 161         efx_rc_t        (*erxo_scale_key_set)(efx_nic_t *, uint8_t *, size_t);
 162         efx_rc_t        (*erxo_scale_tbl_set)(efx_nic_t *, unsigned int *,
 163                                               size_t);
 164         uint32_t        (*erxo_prefix_hash)(efx_nic_t *, efx_rx_hash_alg_t,
 165                                             uint8_t *);
 166 #endif /* EFSYS_OPT_RX_SCALE */
 167         efx_rc_t        (*erxo_prefix_pktlen)(efx_nic_t *, uint8_t *,
 168                                               uint16_t *);
 169         void            (*erxo_qpost)(efx_rxq_t *, efsys_dma_addr_t *, size_t,
 170                                       unsigned int, unsigned int,
 171                                       unsigned int);
 172         void            (*erxo_qpush)(efx_rxq_t *, unsigned int, unsigned int *);
 173         efx_rc_t        (*erxo_qflush)(efx_rxq_t *);
 174         void            (*erxo_qenable)(efx_rxq_t *);
 175         efx_rc_t        (*erxo_qcreate)(efx_nic_t *enp, unsigned int,
 176                                         unsigned int, efx_rxq_type_t,
 177                                         efsys_mem_t *, size_t, uint32_t,
 178                                         efx_evq_t *, efx_rxq_t *);
 179         void            (*erxo_qdestroy)(efx_rxq_t *);
 180 } efx_rx_ops_t;
 181
 182 typedef struct efx_mac_ops_s {
 183         efx_rc_t        (*emo_reset)(efx_nic_t *); /* optional */
 184         efx_rc_t        (*emo_poll)(efx_nic_t *, efx_link_mode_t *);
 185         efx_rc_t        (*emo_up)(efx_nic_t *, boolean_t *);
 186         efx_rc_t        (*emo_addr_set)(efx_nic_t *);
 187         efx_rc_t        (*emo_pdu_set)(efx_nic_t *);
 188         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 189         efx_rc_t        (*emo_multicast_list_set)(efx_nic_t *);
 190         efx_rc_t        (*emo_filter_default_rxq_set)(efx_nic_t *,
 191                                                       efx_rxq_t *, boolean_t);
 192         void            (*emo_filter_default_rxq_clear)(efx_nic_t *);
 193 #if EFSYS_OPT_LOOPBACK
 194         efx_rc_t        (*emo_loopback_set)(efx_nic_t *, efx_link_mode_t,
 195                                             efx_loopback_type_t);
 196 #endif  /* EFSYS_OPT_LOOPBACK */
 197 #if EFSYS_OPT_MAC_STATS
 198         efx_rc_t        (*emo_stats_upload)(efx_nic_t *, efsys_mem_t *);
 199         efx_rc_t        (*emo_stats_periodic)(efx_nic_t *, efsys_mem_t *,
 200                                               uint16_t, boolean_t);
 201         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 202                                             efsys_stat_t *, uint32_t *);
 203 #endif  /* EFSYS_OPT_MAC_STATS */
 204 } efx_mac_ops_t;
 205
 206 typedef struct efx_phy_ops_s {
 207         efx_rc_t        (*epo_power)(efx_nic_t *, boolean_t); /* optional */
 208         efx_rc_t        (*epo_reset)(efx_nic_t *);
 209         efx_rc_t        (*epo_reconfigure)(efx_nic_t *);
 210         efx_rc_t        (*epo_verify)(efx_nic_t *);
 211         efx_rc_t        (*epo_oui_get)(efx_nic_t *, uint32_t *);
 212 #if EFSYS_OPT_PHY_STATS
 213         efx_rc_t        (*epo_stats_update)(efx_nic_t *, efsys_mem_t *,
 214                                             uint32_t *);
 215 #endif  /* EFSYS_OPT_PHY_STATS */
 216 #if EFSYS_OPT_BIST
 217         efx_rc_t        (*epo_bist_enable_offline)(efx_nic_t *);
 218         efx_rc_t        (*epo_bist_start)(efx_nic_t *, efx_bist_type_t);
 219         efx_rc_t        (*epo_bist_poll)(efx_nic_t *, efx_bist_type_t,
 220                                          efx_bist_result_t *, uint32_t *,
 221                                          unsigned long *, size_t);
 222         void            (*epo_bist_stop)(efx_nic_t *, efx_bist_type_t);
 223 #endif  /* EFSYS_OPT_BIST */
 224 } efx_phy_ops_t;
 225
 226 #if EFSYS_OPT_FILTER
 227 typedef struct efx_filter_ops_s {
 228         efx_rc_t        (*efo_init)(efx_nic_t *);
 229         void            (*efo_fini)(efx_nic_t *);
 230         efx_rc_t        (*efo_restore)(efx_nic_t *);
 231         efx_rc_t        (*efo_add)(efx_nic_t *, efx_filter_spec_t *,
 232                                    boolean_t may_replace);
 233         efx_rc_t        (*efo_delete)(efx_nic_t *, efx_filter_spec_t *);
 234         efx_rc_t        (*efo_supported_filters)(efx_nic_t *, uint32_t *, size_t *);
 235         efx_rc_t        (*efo_reconfigure)(efx_nic_t *, uint8_t const *, boolean_t,
 236                                    boolean_t, boolean_t, boolean_t,
 237                                    uint8_t const *, uint32_t);
 238 } efx_filter_ops_t;
 239
 240 extern  __checkReturn   efx_rc_t
 241 efx_filter_reconfigure(
 242         __in                            efx_nic_t *enp,
 243         __in_ecount(6)                  uint8_t const *mac_addr,
 244         __in                            boolean_t all_unicst,
 245         __in                            boolean_t mulcst,
 246         __in                            boolean_t all_mulcst,
 247         __in                            boolean_t brdcst,
 248         __in_ecount(6*count)            uint8_t const *addrs,
 249         __in                            uint32_t count);
 250
 251 #endif /* EFSYS_OPT_FILTER */
 252
 253
 254 typedef struct efx_port_s {
 255         efx_mac_type_t          ep_mac_type;
 256         uint32_t                ep_phy_type;
 257         uint8_t                 ep_port;
 258         uint32_t                ep_mac_pdu;
 259         uint8_t                 ep_mac_addr[6];
 260         efx_link_mode_t         ep_link_mode;
 261         boolean_t               ep_all_unicst;
 262         boolean_t               ep_mulcst;
 263         boolean_t               ep_all_mulcst;
 264         boolean_t               ep_brdcst;
 265         unsigned int            ep_fcntl;
 266         boolean_t               ep_fcntl_autoneg;
 267         efx_oword_t             ep_multicst_hash[2];
 268         uint8_t                 ep_mulcst_addr_list[EFX_MAC_ADDR_LEN *
 269                                                     EFX_MAC_MULTICAST_LIST_MAX];
 270         uint32_t                ep_mulcst_addr_count;
 271 #if EFSYS_OPT_LOOPBACK
 272         efx_loopback_type_t     ep_loopback_type;
 273         efx_link_mode_t         ep_loopback_link_mode;
 274 #endif  /* EFSYS_OPT_LOOPBACK */
 275 #if EFSYS_OPT_PHY_FLAGS
 276         uint32_t                ep_phy_flags;
 277 #endif  /* EFSYS_OPT_PHY_FLAGS */
 278 #if EFSYS_OPT_PHY_LED_CONTROL
 279         efx_phy_led_mode_t      ep_phy_led_mode;
 280 #endif  /* EFSYS_OPT_PHY_LED_CONTROL */
 281         efx_phy_media_type_t    ep_fixed_port_type;
 282         efx_phy_media_type_t    ep_module_type;
 283         uint32_t                ep_adv_cap_mask;
 284         uint32_t                ep_lp_cap_mask;
 285         uint32_t                ep_default_adv_cap_mask;
 286         uint32_t                ep_phy_cap_mask;
 287         boolean_t               ep_mac_drain;
 288         boolean_t               ep_mac_stats_pending;
 289 #if EFSYS_OPT_BIST
 290         efx_bist_type_t         ep_current_bist;
 291 #endif
 292         const efx_mac_ops_t     *ep_emop;
 293         const efx_phy_ops_t     *ep_epop;
 294 } efx_port_t;
 295
 296 typedef struct efx_mon_ops_s {
 297         efx_rc_t        (*emo_reset)(efx_nic_t *);
 298         efx_rc_t        (*emo_reconfigure)(efx_nic_t *);
 299 #if EFSYS_OPT_MON_STATS
 300         efx_rc_t        (*emo_stats_update)(efx_nic_t *, efsys_mem_t *,
 301                                             efx_mon_stat_value_t *);
 302 #endif  /* EFSYS_OPT_MON_STATS */
 303 } efx_mon_ops_t;
 304
 305 typedef struct efx_mon_s {
 306         efx_mon_type_t          em_type;
 307         const efx_mon_ops_t     *em_emop;
 308 } efx_mon_t;
 309
 310 typedef struct efx_intr_ops_s {
 311         efx_rc_t        (*eio_init)(efx_nic_t *, efx_intr_type_t, efsys_mem_t *);
 312         void            (*eio_enable)(efx_nic_t *);
 313         void            (*eio_disable)(efx_nic_t *);
 314         void            (*eio_disable_unlocked)(efx_nic_t *);
 315         efx_rc_t        (*eio_trigger)(efx_nic_t *, unsigned int);
 316         void            (*eio_status_line)(efx_nic_t *, boolean_t *, uint32_t *);
 317         void            (*eio_status_message)(efx_nic_t *, unsigned int,
 318                                  boolean_t *);
 319         void            (*eio_fatal)(efx_nic_t *);
 320         void            (*eio_fini)(efx_nic_t *);
 321 } efx_intr_ops_t;
 322
 323 typedef struct efx_intr_s {
 324         const efx_intr_ops_t    *ei_eiop;
 325         efsys_mem_t             *ei_esmp;
 326         efx_intr_type_t         ei_type;
 327         unsigned int            ei_level;
 328 } efx_intr_t;
 329
 330 typedef struct efx_nic_ops_s {
 331         efx_rc_t        (*eno_probe)(efx_nic_t *);
 332         efx_rc_t        (*eno_board_cfg)(efx_nic_t *);
 333         efx_rc_t        (*eno_set_drv_limits)(efx_nic_t *, efx_drv_limits_t*);
 334         efx_rc_t        (*eno_reset)(efx_nic_t *);
 335         efx_rc_t        (*eno_init)(efx_nic_t *);
 336         efx_rc_t        (*eno_get_vi_pool)(efx_nic_t *, uint32_t *);
 337         efx_rc_t        (*eno_get_bar_region)(efx_nic_t *, efx_nic_region_t,
 338                                         uint32_t *, size_t *);
 339 #if EFSYS_OPT_DIAG
 340         efx_rc_t        (*eno_register_test)(efx_nic_t *);
 341 #endif  /* EFSYS_OPT_DIAG */
 342         void            (*eno_fini)(efx_nic_t *);
 343         void            (*eno_unprobe)(efx_nic_t *);
 344 } efx_nic_ops_t;
 345
 346 #ifndef EFX_TXQ_LIMIT_TARGET
 347 #define EFX_TXQ_LIMIT_TARGET 259
 348 #endif
 349 #ifndef EFX_RXQ_LIMIT_TARGET
 350 #define EFX_RXQ_LIMIT_TARGET 512
 351 #endif
 352 #ifndef EFX_TXQ_DC_SIZE
 353 #define EFX_TXQ_DC_SIZE 1 /* 16 descriptors */
 354 #endif
 355 #ifndef EFX_RXQ_DC_SIZE
 356 #define EFX_RXQ_DC_SIZE 3 /* 64 descriptors */
 357 #endif
 358
 359 #if EFSYS_OPT_FILTER
 360
 361 typedef struct siena_filter_spec_s {
 362         uint8_t         sfs_type;
 363         uint32_t        sfs_flags;
 364         uint32_t        sfs_dmaq_id;
 365         uint32_t        sfs_dword[3];
 366 } siena_filter_spec_t;
 367
 368 typedef enum siena_filter_type_e {
 369         EFX_SIENA_FILTER_RX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 370         EFX_SIENA_FILTER_RX_TCP_WILD,   /* TCP/IPv4 {dIP,dTCP,  -,   -} */
 371         EFX_SIENA_FILTER_RX_UDP_FULL,   /* UDP/IPv4 {dIP,dUDP,sIP,sUDP} */
 372         EFX_SIENA_FILTER_RX_UDP_WILD,   /* UDP/IPv4 {dIP,dUDP,  -,   -} */
 373         EFX_SIENA_FILTER_RX_MAC_FULL,   /* Ethernet {dMAC,VLAN} */
 374         EFX_SIENA_FILTER_RX_MAC_WILD,   /* Ethernet {dMAC,   -} */
 375
 376         EFX_SIENA_FILTER_TX_TCP_FULL,   /* TCP/IPv4 {dIP,dTCP,sIP,sTCP} */
 377         EFX_SIENA_FILTER_TX_TCP_WILD,   /* TCP/IPv4 {  -,   -,sIP,sTCP} */
 378         EFX_SIENA_FILTER_TX_UDP_FULL,   /* UDP/IPv4 {dIP,dTCP,sIP,sTCP} */
 379         EFX_SIENA_FILTER_TX_UDP_WILD,   /* UDP/IPv4 {  -,   -,sIP,sUDP} */
 380         EFX_SIENA_FILTER_TX_MAC_FULL,   /* Ethernet {sMAC,VLAN} */
 381         EFX_SIENA_FILTER_TX_MAC_WILD,   /* Ethernet {sMAC,   -} */
 382
 383         EFX_SIENA_FILTER_NTYPES
 384 } siena_filter_type_t;
 385
 386 typedef enum siena_filter_tbl_id_e {
 387         EFX_SIENA_FILTER_TBL_RX_IP = 0,
 388         EFX_SIENA_FILTER_TBL_RX_MAC,
 389         EFX_SIENA_FILTER_TBL_TX_IP,
 390         EFX_SIENA_FILTER_TBL_TX_MAC,
 391         EFX_SIENA_FILTER_NTBLS
 392 } siena_filter_tbl_id_t;
 393
 394 typedef struct siena_filter_tbl_s {
 395         int                     sft_size;       /* number of entries */
 396         int                     sft_used;       /* active count */
 397         uint32_t                *sft_bitmap;    /* active bitmap */
 398         siena_filter_spec_t     *sft_spec;      /* array of saved specs */
 399 } siena_filter_tbl_t;
 400
 401 typedef struct siena_filter_s {
 402         siena_filter_tbl_t      sf_tbl[EFX_SIENA_FILTER_NTBLS];
 403         unsigned int            sf_depth[EFX_SIENA_FILTER_NTYPES];
 404 } siena_filter_t;
 405
 406 typedef struct efx_filter_s {
 407 #if EFSYS_OPT_SIENA
 408         siena_filter_t          *ef_siena_filter;
 409 #endif /* EFSYS_OPT_SIENA */
 410 #if EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD
 411         ef10_filter_table_t     *ef_ef10_filter_table;
 412 #endif /* EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD */
 413 } efx_filter_t;
 414
 415 extern                  void
 416 siena_filter_tbl_clear(
 417         __in            efx_nic_t *enp,
 418         __in            siena_filter_tbl_id_t tbl);
 419
 420 #endif  /* EFSYS_OPT_FILTER */
 421
 422 #if EFSYS_OPT_MCDI
 423
 424 typedef struct efx_mcdi_ops_s {
 425         efx_rc_t        (*emco_init)(efx_nic_t *, const efx_mcdi_transport_t *);
 426         void            (*emco_send_request)(efx_nic_t *, void *, size_t,
 427                                         void *, size_t);
 428         efx_rc_t        (*emco_poll_reboot)(efx_nic_t *);
 429         boolean_t       (*emco_poll_response)(efx_nic_t *);
 430         void            (*emco_read_response)(efx_nic_t *, void *, size_t, size_t);
 431         void            (*emco_fini)(efx_nic_t *);
 432         efx_rc_t        (*emco_feature_supported)(efx_nic_t *, efx_mcdi_feature_id_t, boolean_t *);
 433 } efx_mcdi_ops_t;
 434
 435 typedef struct efx_mcdi_s {
 436         const efx_mcdi_ops_t            *em_emcop;
 437         const efx_mcdi_transport_t      *em_emtp;
 438         efx_mcdi_iface_t                em_emip;
 439 } efx_mcdi_t;
 440
 441 #endif /* EFSYS_OPT_MCDI */
 442
 443 #if EFSYS_OPT_NVRAM
 444 typedef struct efx_nvram_ops_s {
 445 #if EFSYS_OPT_DIAG
 446         efx_rc_t        (*envo_test)(efx_nic_t *);
 447 #endif  /* EFSYS_OPT_DIAG */
 448         efx_rc_t        (*envo_type_to_partn)(efx_nic_t *, efx_nvram_type_t,
 449                                             uint32_t *);
 450         efx_rc_t        (*envo_partn_size)(efx_nic_t *, uint32_t, size_t *);
 451         efx_rc_t        (*envo_partn_rw_start)(efx_nic_t *, uint32_t, size_t *);
 452         efx_rc_t        (*envo_partn_read)(efx_nic_t *, uint32_t,
 453                                             unsigned int, caddr_t, size_t);
 454         efx_rc_t        (*envo_partn_erase)(efx_nic_t *, uint32_t,
 455                                             unsigned int, size_t);
 456         efx_rc_t        (*envo_partn_write)(efx_nic_t *, uint32_t,
 457                                             unsigned int, caddr_t, size_t);
 458         void            (*envo_partn_rw_finish)(efx_nic_t *, uint32_t);
 459         efx_rc_t        (*envo_partn_get_version)(efx_nic_t *, uint32_t,
 460                                             uint32_t *, uint16_t *);
 461         efx_rc_t        (*envo_partn_set_version)(efx_nic_t *, uint32_t,
 462                                             uint16_t *);
 463         efx_rc_t        (*envo_buffer_validate)(efx_nic_t *, uint32_t,
 464                                             caddr_t, size_t);
 465 } efx_nvram_ops_t;
 466 #endif /* EFSYS_OPT_NVRAM */
 467
 468 extern  __checkReturn           efx_rc_t
 469 efx_nvram_tlv_validate(
 470         __in                    efx_nic_t *enp,
 471         __in                    uint32_t partn,
 472         __in_bcount(partn_size) caddr_t partn_data,
 473         __in                    size_t partn_size);
 474
 475
 476 #if EFSYS_OPT_VPD
 477 typedef struct efx_vpd_ops_s {
 478         efx_rc_t        (*evpdo_init)(efx_nic_t *);
 479         efx_rc_t        (*evpdo_size)(efx_nic_t *, size_t *);
 480         efx_rc_t        (*evpdo_read)(efx_nic_t *, caddr_t, size_t);
 481         efx_rc_t        (*evpdo_verify)(efx_nic_t *, caddr_t, size_t);
 482         efx_rc_t        (*evpdo_reinit)(efx_nic_t *, caddr_t, size_t);
 483         efx_rc_t        (*evpdo_get)(efx_nic_t *, caddr_t, size_t,
 484                                         efx_vpd_value_t *);
 485         efx_rc_t        (*evpdo_set)(efx_nic_t *, caddr_t, size_t,
 486                                         efx_vpd_value_t *);
 487         efx_rc_t        (*evpdo_next)(efx_nic_t *, caddr_t, size_t,
 488                                         efx_vpd_value_t *, unsigned int *);
 489         efx_rc_t        (*evpdo_write)(efx_nic_t *, caddr_t, size_t);
 490         void            (*evpdo_fini)(efx_nic_t *);
 491 } efx_vpd_ops_t;
 492 #endif  /* EFSYS_OPT_VPD */
 493
 494 #if EFSYS_OPT_VPD || EFSYS_OPT_NVRAM
 495
 496         __checkReturn           efx_rc_t
 497 efx_mcdi_nvram_partitions(
 498         __in                    efx_nic_t *enp,
 499         __out_bcount(size)      caddr_t data,
 500         __in                    size_t size,
 501         __out                   unsigned int *npartnp);
 502
 503         __checkReturn           efx_rc_t
 504 efx_mcdi_nvram_metadata(
 505         __in                    efx_nic_t *enp,
 506         __in                    uint32_t partn,
 507         __out                   uint32_t *subtypep,
 508         __out_ecount(4)         uint16_t version[4],
 509         __out_bcount_opt(size)  char *descp,
 510         __in                    size_t size);
 511
 512         __checkReturn           efx_rc_t
 513 efx_mcdi_nvram_info(
 514         __in                    efx_nic_t *enp,
 515         __in                    uint32_t partn,
 516         __out_opt               size_t *sizep,
 517         __out_opt               uint32_t *addressp,
 518         __out_opt               uint32_t *erase_sizep,
 519         __out_opt               uint32_t *write_sizep);
 520
 521         __checkReturn           efx_rc_t
 522 efx_mcdi_nvram_update_start(
 523         __in                    efx_nic_t *enp,
 524         __in                    uint32_t partn);
 525
 526         __checkReturn           efx_rc_t
 527 efx_mcdi_nvram_read(
 528         __in                    efx_nic_t *enp,
 529         __in                    uint32_t partn,
 530         __in                    uint32_t offset,
 531         __out_bcount(size)      caddr_t data,
 532         __in                    size_t size,
 533         __in                    uint32_t mode);
 534
 535         __checkReturn           efx_rc_t
 536 efx_mcdi_nvram_erase(
 537         __in                    efx_nic_t *enp,
 538         __in                    uint32_t partn,
 539         __in                    uint32_t offset,
 540         __in                    size_t size);
 541
 542         __checkReturn           efx_rc_t
 543 efx_mcdi_nvram_write(
 544         __in                    efx_nic_t *enp,
 545         __in                    uint32_t partn,
 546         __in                    uint32_t offset,
 547         __out_bcount(size)      caddr_t data,
 548         __in                    size_t size);
 549
 550         __checkReturn           efx_rc_t
 551 efx_mcdi_nvram_update_finish(
 552         __in                    efx_nic_t *enp,
 553         __in                    uint32_t partn,
 554         __in                    boolean_t reboot);
 555
 556 #if EFSYS_OPT_DIAG
 557
 558         __checkReturn           efx_rc_t
 559 efx_mcdi_nvram_test(
 560         __in                    efx_nic_t *enp,
 561         __in                    uint32_t partn);
 562
 563 #endif  /* EFSYS_OPT_DIAG */
 564
 565 #endif /* EFSYS_OPT_VPD || EFSYS_OPT_NVRAM */
 566
 567 #if EFSYS_OPT_LICENSING
 568
 569 typedef struct efx_lic_ops_s {
 570         efx_rc_t        (*elo_update_licenses)(efx_nic_t *);
 571         efx_rc_t        (*elo_get_key_stats)(efx_nic_t *, efx_key_stats_t *);
 572         efx_rc_t        (*elo_app_state)(efx_nic_t *, uint64_t, boolean_t *);
 573         efx_rc_t        (*elo_get_id)(efx_nic_t *, size_t, uint32_t *,
 574                                       size_t *, uint8_t *);
 575 } efx_lic_ops_t;
 576
 577 #endif
 578
 579 typedef struct efx_drv_cfg_s {
 580         uint32_t                edc_min_vi_count;
 581         uint32_t                edc_max_vi_count;
 582
 583         uint32_t                edc_max_piobuf_count;
 584         uint32_t                edc_pio_alloc_size;
 585 } efx_drv_cfg_t;
 586
 587 struct efx_nic_s {
 588         uint32_t                en_magic;
 589         efx_family_t            en_family;
 590         uint32_t                en_features;
 591         efsys_identifier_t      *en_esip;
 592         efsys_lock_t            *en_eslp;
 593         efsys_bar_t             *en_esbp;
 594         unsigned int            en_mod_flags;
 595         unsigned int            en_reset_flags;
 596         efx_nic_cfg_t           en_nic_cfg;
 597         efx_drv_cfg_t           en_drv_cfg;
 598         efx_port_t              en_port;
 599         efx_mon_t               en_mon;
 600         efx_intr_t              en_intr;
 601         uint32_t                en_ev_qcount;
 602         uint32_t                en_rx_qcount;
 603         uint32_t                en_tx_qcount;
 604         const efx_nic_ops_t     *en_enop;
 605         const efx_ev_ops_t      *en_eevop;
 606         const efx_tx_ops_t      *en_etxop;
 607         const efx_rx_ops_t      *en_erxop;
 608 #if EFSYS_OPT_FILTER
 609         efx_filter_t            en_filter;
 610         const efx_filter_ops_t  *en_efop;
 611 #endif  /* EFSYS_OPT_FILTER */
 612 #if EFSYS_OPT_MCDI
 613         efx_mcdi_t              en_mcdi;
 614 #endif  /* EFSYS_OPT_MCDI */
 615 #if EFSYS_OPT_NVRAM
 616         efx_nvram_type_t        en_nvram_locked;
 617         const efx_nvram_ops_t   *en_envop;
 618 #endif  /* EFSYS_OPT_NVRAM */
 619 #if EFSYS_OPT_VPD
 620         const efx_vpd_ops_t     *en_evpdop;
 621 #endif  /* EFSYS_OPT_VPD */
 622 #if EFSYS_OPT_RX_SCALE
 623         efx_rx_hash_support_t   en_hash_support;
 624         efx_rx_scale_support_t  en_rss_support;
 625         uint32_t                en_rss_context;
 626 #endif  /* EFSYS_OPT_RX_SCALE */
 627         uint32_t                en_vport_id;
 628 #if EFSYS_OPT_LICENSING
 629         const efx_lic_ops_t     *en_elop;
 630 #endif
 631         union {
 632 #if EFSYS_OPT_SIENA
 633                 struct {
 634 #if EFSYS_OPT_NVRAM || EFSYS_OPT_VPD
 635                         unsigned int            enu_partn_mask;
 636 #endif  /* EFSYS_OPT_NVRAM || EFSYS_OPT_VPD */
 637 #if EFSYS_OPT_VPD
 638                         caddr_t                 enu_svpd;
 639                         size_t                  enu_svpd_length;
 640 #endif  /* EFSYS_OPT_VPD */
 641                         int                     enu_unused;
 642                 } siena;
 643 #endif  /* EFSYS_OPT_SIENA */
 644                 int     enu_unused;
 645         } en_u;
 646 #if (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD)
 647         union en_arch {
 648                 struct {
 649                         int                     ena_vi_base;
 650                         int                     ena_vi_count;
 651                         int                     ena_vi_shift;
 652 #if EFSYS_OPT_VPD
 653                         caddr_t                 ena_svpd;
 654                         size_t                  ena_svpd_length;
 655 #endif  /* EFSYS_OPT_VPD */
 656                         efx_piobuf_handle_t     ena_piobuf_handle[EF10_MAX_PIOBUF_NBUFS];
 657                         uint32_t                ena_piobuf_count;
 658                         uint32_t                ena_pio_alloc_map[EF10_MAX_PIOBUF_NBUFS];
 659                         uint32_t                ena_pio_write_vi_base;
 660                         /* Memory BAR mapping regions */
 661                         uint32_t                ena_uc_mem_map_offset;
 662                         size_t                  ena_uc_mem_map_size;
 663                         uint32_t                ena_wc_mem_map_offset;
 664                         size_t                  ena_wc_mem_map_size;
 665                 } ef10;
 666         } en_arch;
 667 #endif  /* (EFSYS_OPT_HUNTINGTON || EFSYS_OPT_MEDFORD) */
 668 };
 669
 670
 671 #define EFX_NIC_MAGIC   0x02121996
 672
 673 typedef boolean_t (*efx_ev_handler_t)(efx_evq_t *, efx_qword_t *,
 674     const efx_ev_callbacks_t *, void *);
 675
 676 typedef struct efx_evq_rxq_state_s {
 677         unsigned int                    eers_rx_read_ptr;
 678         unsigned int                    eers_rx_mask;
 679 } efx_evq_rxq_state_t;
 680
 681 struct efx_evq_s {
 682         uint32_t                        ee_magic;
 683         efx_nic_t                       *ee_enp;
 684         unsigned int                    ee_index;
 685         unsigned int                    ee_mask;
 686         efsys_mem_t                     *ee_esmp;
 687 #if EFSYS_OPT_QSTATS
 688         uint32_t                        ee_stat[EV_NQSTATS];
 689 #endif  /* EFSYS_OPT_QSTATS */
 690
 691         efx_ev_handler_t                ee_rx;
 692         efx_ev_handler_t                ee_tx;
 693         efx_ev_handler_t                ee_driver;
 694         efx_ev_handler_t                ee_global;
 695         efx_ev_handler_t                ee_drv_gen;
 696 #if EFSYS_OPT_MCDI
 697         efx_ev_handler_t                ee_mcdi;
 698 #endif  /* EFSYS_OPT_MCDI */
 699
 700         efx_evq_rxq_state_t             ee_rxq_state[EFX_EV_RX_NLABELS];
 701 };
 702
 703 #define EFX_EVQ_MAGIC   0x08081997
 704
 705 #define EFX_EVQ_FALCON_TIMER_QUANTUM_NS 4968 /* 621 cycles */
 706 #define EFX_EVQ_SIENA_TIMER_QUANTUM_NS  6144 /* 768 cycles */
 707
 708 struct efx_rxq_s {
 709         uint32_t                        er_magic;
 710         efx_nic_t                       *er_enp;
 711         efx_evq_t                       *er_eep;
 712         unsigned int                    er_index;
 713         unsigned int                    er_label;
 714         unsigned int                    er_mask;
 715         efsys_mem_t                     *er_esmp;
 716 };
 717
 718 #define EFX_RXQ_MAGIC   0x15022005
 719
 720 struct efx_txq_s {
 721         uint32_t                        et_magic;
 722         efx_nic_t                       *et_enp;
 723         unsigned int                    et_index;
 724         unsigned int                    et_mask;
 725         efsys_mem_t                     *et_esmp;
 726 #if EFSYS_OPT_HUNTINGTON
 727         uint32_t                        et_pio_bufnum;
 728         uint32_t                        et_pio_blknum;
 729         uint32_t                        et_pio_write_offset;
 730         uint32_t                        et_pio_offset;
 731         size_t                          et_pio_size;
 732 #endif
 733 #if EFSYS_OPT_QSTATS
 734         uint32_t                        et_stat[TX_NQSTATS];
 735 #endif  /* EFSYS_OPT_QSTATS */
 736 };
 737
 738 #define EFX_TXQ_MAGIC   0x05092005
 739
 740 #define EFX_MAC_ADDR_COPY(_dst, _src)                                   \
 741         do {                                                            \
 742                 (_dst)[0] = (_src)[0];                                  \
 743                 (_dst)[1] = (_src)[1];                                  \
 744                 (_dst)[2] = (_src)[2];                                  \
 745                 (_dst)[3] = (_src)[3];                                  \
 746                 (_dst)[4] = (_src)[4];                                  \
 747                 (_dst)[5] = (_src)[5];                                  \
 748         _NOTE(CONSTANTCONDITION)                                        \
 749         } while (B_FALSE)
 750
 751 #define EFX_MAC_BROADCAST_ADDR_SET(_dst)                                \
 752         do {                                                            \
 753                 uint16_t *_d = (uint16_t *)(_dst);                      \
 754                 _d[0] = 0xffff;                                         \
 755                 _d[1] = 0xffff;                                         \
 756                 _d[2] = 0xffff;                                         \
 757         _NOTE(CONSTANTCONDITION)                                        \
 758         } while (B_FALSE)
 759
 760 #if EFSYS_OPT_CHECK_REG
 761 #define EFX_CHECK_REG(_enp, _reg)                                       \
 762         do {                                                            \
 763                 const char *name = #_reg;                               \
 764                 char min = name[4];                                     \
 765                 char max = name[5];                                     \
 766                 char rev;                                               \
 767                                                                         \
 768                 switch ((_enp)->en_family) {                            \
 769                 case EFX_FAMILY_SIENA:                                  \
 770                         rev = 'C';                                      \
 771                         break;                                          \
 772                                                                         \
 773                 case EFX_FAMILY_HUNTINGTON:                             \
 774                         rev = 'D';                                      \
 775                         break;                                          \
 776                                                                         \
 777                 case EFX_FAMILY_MEDFORD:                                \
 778                         rev = 'E';                                      \
 779                         break;                                          \
 780                                                                         \
 781                 default:                                                \
 782                         rev = '?';                                      \
 783                         break;                                          \
 784                 }                                                       \
 785                                                                         \
 786                 EFSYS_ASSERT3S(rev, >=, min);                           \
 787                 EFSYS_ASSERT3S(rev, <=, max);                           \
 788                                                                         \
 789         _NOTE(CONSTANTCONDITION)                                        \
 790         } while (B_FALSE)
 791 #else
 792 #define EFX_CHECK_REG(_enp, _reg) do {                                  \
 793         _NOTE(CONSTANTCONDITION)                                        \
 794         } while(B_FALSE)
 795 #endif
 796
 797 #define EFX_BAR_READD(_enp, _reg, _edp, _lock)                          \
 798         do {                                                            \
 799                 EFX_CHECK_REG((_enp), (_reg));                          \
 800                 EFSYS_BAR_READD((_enp)->en_esbp, _reg ## _OFST,         \
 801                     (_edp), (_lock));                                   \
 802                 EFSYS_PROBE3(efx_bar_readd, const char *, #_reg,        \
 803                     uint32_t, _reg ## _OFST,                            \
 804                     uint32_t, (_edp)->ed_u32[0]);                       \
 805         _NOTE(CONSTANTCONDITION)                                        \
 806         } while (B_FALSE)
 807
 808 #define EFX_BAR_WRITED(_enp, _reg, _edp, _lock)                         \
 809         do {                                                            \
 810                 EFX_CHECK_REG((_enp), (_reg));                          \
 811                 EFSYS_PROBE3(efx_bar_writed, const char *, #_reg,       \
 812                     uint32_t, _reg ## _OFST,                            \
 813                     uint32_t, (_edp)->ed_u32[0]);                       \
 814                 EFSYS_BAR_WRITED((_enp)->en_esbp, _reg ## _OFST,        \
 815                     (_edp), (_lock));                                   \
 816         _NOTE(CONSTANTCONDITION)                                        \
 817         } while (B_FALSE)
 818
 819 #define EFX_BAR_READQ(_enp, _reg, _eqp)                                 \
 820         do {                                                            \
 821                 EFX_CHECK_REG((_enp), (_reg));                          \
 822                 EFSYS_BAR_READQ((_enp)->en_esbp, _reg ## _OFST,         \
 823                     (_eqp));                                            \
 824                 EFSYS_PROBE4(efx_bar_readq, const char *, #_reg,        \
 825                     uint32_t, _reg ## _OFST,                            \
 826                     uint32_t, (_eqp)->eq_u32[1],                        \
 827                     uint32_t, (_eqp)->eq_u32[0]);                       \
 828         _NOTE(CONSTANTCONDITION)                                        \
 829         } while (B_FALSE)
 830
 831 #define EFX_BAR_WRITEQ(_enp, _reg, _eqp)                                \
 832         do {                                                            \
 833                 EFX_CHECK_REG((_enp), (_reg));                          \
 834                 EFSYS_PROBE4(efx_bar_writeq, const char *, #_reg,       \
 835                     uint32_t, _reg ## _OFST,                            \
 836                     uint32_t, (_eqp)->eq_u32[1],                        \
 837                     uint32_t, (_eqp)->eq_u32[0]);                       \
 838                 EFSYS_BAR_WRITEQ((_enp)->en_esbp, _reg ## _OFST,        \
 839                     (_eqp));                                            \
 840         _NOTE(CONSTANTCONDITION)                                        \
 841         } while (B_FALSE)
 842
 843 #define EFX_BAR_READO(_enp, _reg, _eop)                                 \
 844         do {                                                            \
 845                 EFX_CHECK_REG((_enp), (_reg));                          \
 846                 EFSYS_BAR_READO((_enp)->en_esbp, _reg ## _OFST,         \
 847                     (_eop), B_TRUE);                                    \
 848                 EFSYS_PROBE6(efx_bar_reado, const char *, #_reg,        \
 849                     uint32_t, _reg ## _OFST,                            \
 850                     uint32_t, (_eop)->eo_u32[3],                        \
 851                     uint32_t, (_eop)->eo_u32[2],                        \
 852                     uint32_t, (_eop)->eo_u32[1],                        \
 853                     uint32_t, (_eop)->eo_u32[0]);                       \
 854         _NOTE(CONSTANTCONDITION)                                        \
 855         } while (B_FALSE)
 856
 857 #define EFX_BAR_WRITEO(_enp, _reg, _eop)                                \
 858         do {                                                            \
 859                 EFX_CHECK_REG((_enp), (_reg));                          \
 860                 EFSYS_PROBE6(efx_bar_writeo, const char *, #_reg,       \
 861                     uint32_t, _reg ## _OFST,                            \
 862                     uint32_t, (_eop)->eo_u32[3],                        \
 863                     uint32_t, (_eop)->eo_u32[2],                        \
 864                     uint32_t, (_eop)->eo_u32[1],                        \
 865                     uint32_t, (_eop)->eo_u32[0]);                       \
 866                 EFSYS_BAR_WRITEO((_enp)->en_esbp, _reg ## _OFST,        \
 867                     (_eop), B_TRUE);                                    \
 868         _NOTE(CONSTANTCONDITION)                                        \
 869         } while (B_FALSE)
 870
 871 #define EFX_BAR_TBL_READD(_enp, _reg, _index, _edp, _lock)              \
 872         do {                                                            \
 873                 EFX_CHECK_REG((_enp), (_reg));                          \
 874                 EFSYS_BAR_READD((_enp)->en_esbp,                        \
 875                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 876                     (_edp), (_lock));                                   \
 877                 EFSYS_PROBE4(efx_bar_tbl_readd, const char *, #_reg,    \
 878                     uint32_t, (_index),                                 \
 879                     uint32_t, _reg ## _OFST,                            \
 880                     uint32_t, (_edp)->ed_u32[0]);                       \
 881         _NOTE(CONSTANTCONDITION)                                        \
 882         } while (B_FALSE)
 883
 884 #define EFX_BAR_TBL_WRITED(_enp, _reg, _index, _edp, _lock)             \
 885         do {                                                            \
 886                 EFX_CHECK_REG((_enp), (_reg));                          \
 887                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 888                     uint32_t, (_index),                                 \
 889                     uint32_t, _reg ## _OFST,                            \
 890                     uint32_t, (_edp)->ed_u32[0]);                       \
 891                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 892                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 893                     (_edp), (_lock));                                   \
 894         _NOTE(CONSTANTCONDITION)                                        \
 895         } while (B_FALSE)
 896
 897 #define EFX_BAR_TBL_WRITED2(_enp, _reg, _index, _edp, _lock)            \
 898         do {                                                            \
 899                 EFX_CHECK_REG((_enp), (_reg));                          \
 900                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 901                     uint32_t, (_index),                                 \
 902                     uint32_t, _reg ## _OFST,                            \
 903                     uint32_t, (_edp)->ed_u32[0]);                       \
 904                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 905                     (_reg ## _OFST +                                    \
 906                     (2 * sizeof (efx_dword_t)) +                        \
 907                     ((_index) * _reg ## _STEP)),                        \
 908                     (_edp), (_lock));                                   \
 909         _NOTE(CONSTANTCONDITION)                                        \
 910         } while (B_FALSE)
 911
 912 #define EFX_BAR_TBL_WRITED3(_enp, _reg, _index, _edp, _lock)            \
 913         do {                                                            \
 914                 EFX_CHECK_REG((_enp), (_reg));                          \
 915                 EFSYS_PROBE4(efx_bar_tbl_writed, const char *, #_reg,   \
 916                     uint32_t, (_index),                                 \
 917                     uint32_t, _reg ## _OFST,                            \
 918                     uint32_t, (_edp)->ed_u32[0]);                       \
 919                 EFSYS_BAR_WRITED((_enp)->en_esbp,                       \
 920                     (_reg ## _OFST +                                    \
 921                     (3 * sizeof (efx_dword_t)) +                        \
 922                     ((_index) * _reg ## _STEP)),                        \
 923                     (_edp), (_lock));                                   \
 924         _NOTE(CONSTANTCONDITION)                                        \
 925         } while (B_FALSE)
 926
 927 #define EFX_BAR_TBL_READQ(_enp, _reg, _index, _eqp)                     \
 928         do {                                                            \
 929                 EFX_CHECK_REG((_enp), (_reg));                          \
 930                 EFSYS_BAR_READQ((_enp)->en_esbp,                        \
 931                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 932                     (_eqp));                                            \
 933                 EFSYS_PROBE5(efx_bar_tbl_readq, const char *, #_reg,    \
 934                     uint32_t, (_index),                                 \
 935                     uint32_t, _reg ## _OFST,                            \
 936                     uint32_t, (_eqp)->eq_u32[1],                        \
 937                     uint32_t, (_eqp)->eq_u32[0]);                       \
 938         _NOTE(CONSTANTCONDITION)                                        \
 939         } while (B_FALSE)
 940
 941 #define EFX_BAR_TBL_WRITEQ(_enp, _reg, _index, _eqp)                    \
 942         do {                                                            \
 943                 EFX_CHECK_REG((_enp), (_reg));                          \
 944                 EFSYS_PROBE5(efx_bar_tbl_writeq, const char *, #_reg,   \
 945                     uint32_t, (_index),                                 \
 946                     uint32_t, _reg ## _OFST,                            \
 947                     uint32_t, (_eqp)->eq_u32[1],                        \
 948                     uint32_t, (_eqp)->eq_u32[0]);                       \
 949                 EFSYS_BAR_WRITEQ((_enp)->en_esbp,                       \
 950                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 951                     (_eqp));                                            \
 952         _NOTE(CONSTANTCONDITION)                                        \
 953         } while (B_FALSE)
 954
 955 #define EFX_BAR_TBL_READO(_enp, _reg, _index, _eop, _lock)              \
 956         do {                                                            \
 957                 EFX_CHECK_REG((_enp), (_reg));                          \
 958                 EFSYS_BAR_READO((_enp)->en_esbp,                        \
 959                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 960                     (_eop), (_lock));                                   \
 961                 EFSYS_PROBE7(efx_bar_tbl_reado, const char *, #_reg,    \
 962                     uint32_t, (_index),                                 \
 963                     uint32_t, _reg ## _OFST,                            \
 964                     uint32_t, (_eop)->eo_u32[3],                        \
 965                     uint32_t, (_eop)->eo_u32[2],                        \
 966                     uint32_t, (_eop)->eo_u32[1],                        \
 967                     uint32_t, (_eop)->eo_u32[0]);                       \
 968         _NOTE(CONSTANTCONDITION)                                        \
 969         } while (B_FALSE)
 970
 971 #define EFX_BAR_TBL_WRITEO(_enp, _reg, _index, _eop, _lock)             \
 972         do {                                                            \
 973                 EFX_CHECK_REG((_enp), (_reg));                          \
 974                 EFSYS_PROBE7(efx_bar_tbl_writeo, const char *, #_reg,   \
 975                     uint32_t, (_index),                                 \
 976                     uint32_t, _reg ## _OFST,                            \
 977                     uint32_t, (_eop)->eo_u32[3],                        \
 978                     uint32_t, (_eop)->eo_u32[2],                        \
 979                     uint32_t, (_eop)->eo_u32[1],                        \
 980                     uint32_t, (_eop)->eo_u32[0]);                       \
 981                 EFSYS_BAR_WRITEO((_enp)->en_esbp,                       \
 982                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
 983                     (_eop), (_lock));                                   \
 984         _NOTE(CONSTANTCONDITION)                                        \
 985         } while (B_FALSE)
 986
 987 /*
 988  * Allow drivers to perform optimised 128-bit doorbell writes.
 989  * The DMA descriptor pointers (RX_DESC_UPD and TX_DESC_UPD) are
 990  * special-cased in the BIU on the Falcon/Siena and EF10 architectures to avoid
 991  * the need for locking in the host, and are the only ones known to be safe to
 992  * use 128-bites write with.
 993  */
 994 #define EFX_BAR_TBL_DOORBELL_WRITEO(_enp, _reg, _index, _eop)           \
 995         do {                                                            \
 996                 EFX_CHECK_REG((_enp), (_reg));                          \
 997                 EFSYS_PROBE7(efx_bar_tbl_doorbell_writeo,               \
 998                     const char *,                                       \
 999                     #_reg,                                              \
1000                     uint32_t, (_index),                                 \
1001                     uint32_t, _reg ## _OFST,                            \
1002                     uint32_t, (_eop)->eo_u32[3],                        \
1003                     uint32_t, (_eop)->eo_u32[2],                        \
1004                     uint32_t, (_eop)->eo_u32[1],                        \
1005                     uint32_t, (_eop)->eo_u32[0]);                       \
1006                 EFSYS_BAR_DOORBELL_WRITEO((_enp)->en_esbp,              \
1007                     (_reg ## _OFST + ((_index) * _reg ## _STEP)),       \
1008                     (_eop));                                            \
1009         _NOTE(CONSTANTCONDITION)                                        \
1010         } while (B_FALSE)
1011
1012 #define EFX_DMA_SYNC_QUEUE_FOR_DEVICE(_esmp, _entries, _wptr, _owptr)   \
1013         do {                                                            \
1014                 unsigned int _new = (_wptr);                            \
1015                 unsigned int _old = (_owptr);                           \
1016                                                                         \
1017                 if ((_new) >= (_old))                                   \
1018                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1019                             (_old) * sizeof (efx_desc_t),               \
1020                             ((_new) - (_old)) * sizeof (efx_desc_t));   \
1021                 else                                                    \
1022                         /*                                              \
1023                          * It is cheaper to sync entire map than sync   \
1024                          * two parts especially when offset/size are    \
1025                          * ignored and entire map is synced in any case.\
1026                          */                                             \
1027                         EFSYS_DMA_SYNC_FOR_DEVICE((_esmp),              \
1028                             0,                                          \
1029                             (_entries) * sizeof (efx_desc_t));          \
1030         _NOTE(CONSTANTCONDITION)                                        \
1031         } while (B_FALSE)
1032
1033 extern  __checkReturn   efx_rc_t
1034 efx_nic_biu_test(
1035         __in            efx_nic_t *enp);
1036
1037 extern  __checkReturn   efx_rc_t
1038 efx_mac_select(
1039         __in            efx_nic_t *enp);
1040
1041 extern  void
1042 efx_mac_multicast_hash_compute(
1043         __in_ecount(6*count)            uint8_t const *addrs,
1044         __in                            int count,
1045         __out                           efx_oword_t *hash_low,
1046         __out                           efx_oword_t *hash_high);
1047
1048 extern  __checkReturn   efx_rc_t
1049 efx_phy_probe(
1050         __in            efx_nic_t *enp);
1051
1052 extern                  void
1053 efx_phy_unprobe(
1054         __in            efx_nic_t *enp);
1055
1056 #if EFSYS_OPT_VPD
1057
1058 /* VPD utility functions */
1059
1060 extern  __checkReturn           efx_rc_t
1061 efx_vpd_hunk_length(
1062         __in_bcount(size)       caddr_t data,
1063         __in                    size_t size,
1064         __out                   size_t *lengthp);
1065
1066 extern  __checkReturn           efx_rc_t
1067 efx_vpd_hunk_verify(
1068         __in_bcount(size)       caddr_t data,
1069         __in                    size_t size,
1070         __out_opt               boolean_t *cksummedp);
1071
1072 extern  __checkReturn           efx_rc_t
1073 efx_vpd_hunk_reinit(
1074         __in_bcount(size)       caddr_t data,
1075         __in                    size_t size,
1076         __in                    boolean_t wantpid);
1077
1078 extern  __checkReturn           efx_rc_t
1079 efx_vpd_hunk_get(
1080         __in_bcount(size)       caddr_t data,
1081         __in                    size_t size,
1082         __in                    efx_vpd_tag_t tag,
1083         __in                    efx_vpd_keyword_t keyword,
1084         __out                   unsigned int *payloadp,
1085         __out                   uint8_t *paylenp);
1086
1087 extern  __checkReturn                   efx_rc_t
1088 efx_vpd_hunk_next(
1089         __in_bcount(size)               caddr_t data,
1090         __in                            size_t size,
1091         __out                           efx_vpd_tag_t *tagp,
1092         __out                           efx_vpd_keyword_t *keyword,
1093         __out_opt                       unsigned int *payloadp,
1094         __out_opt                       uint8_t *paylenp,
1095         __inout                         unsigned int *contp);
1096
1097 extern  __checkReturn           efx_rc_t
1098 efx_vpd_hunk_set(
1099         __in_bcount(size)       caddr_t data,
1100         __in                    size_t size,
1101         __in                    efx_vpd_value_t *evvp);
1102
1103 #endif  /* EFSYS_OPT_VPD */
1104
1105 #if EFSYS_OPT_DIAG
1106
1107 extern  efx_sram_pattern_fn_t   __efx_sram_pattern_fns[];
1108
1109 typedef struct efx_register_set_s {
1110         unsigned int            address;
1111         unsigned int            step;
1112         unsigned int            rows;
1113         efx_oword_t             mask;
1114 } efx_register_set_t;
1115
1116 extern  __checkReturn   efx_rc_t
1117 efx_nic_test_registers(
1118         __in            efx_nic_t *enp,
1119         __in            efx_register_set_t *rsp,
1120         __in            size_t count);
1121
1122 extern  __checkReturn   efx_rc_t
1123 efx_nic_test_tables(
1124         __in            efx_nic_t *enp,
1125         __in            efx_register_set_t *rsp,
1126         __in            efx_pattern_type_t pattern,
1127         __in            size_t count);
1128
1129 #endif  /* EFSYS_OPT_DIAG */
1130
1131 #if EFSYS_OPT_MCDI
1132
1133 extern  __checkReturn           efx_rc_t
1134 efx_mcdi_set_workaround(
1135         __in                    efx_nic_t *enp,
1136         __in                    uint32_t type,
1137         __in                    boolean_t enabled,
1138         __out_opt               uint32_t *flagsp);
1139
1140 extern  __checkReturn           efx_rc_t
1141 efx_mcdi_get_workarounds(
1142         __in                    efx_nic_t *enp,
1143         __out_opt               uint32_t *implementedp,
1144         __out_opt               uint32_t *enabledp);
1145
1146 #endif /* EFSYS_OPT_MCDI */
1147
1148 #ifdef  __cplusplus
1149 }
1150 #endif
1151
1152 #endif  /* _SYS_EFX_IMPL_H */