sys/dev/sound/pci/hda/hdac.c

   1 /*-
   2  * Copyright (c) 2006 Stephane E. Potvin <sepotvin@videotron.ca>
   3  * Copyright (c) 2006 Ariff Abdullah <ariff@FreeBSD.org>
   4  * Copyright (c) 2008-2012 Alexander Motin <mav@FreeBSD.org>
   5  * All rights reserved.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  17  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  20  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  21  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  22  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  23  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  24  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  26  * SUCH DAMAGE.
  27  */
  28
  29 /*
  30  * Intel High Definition Audio (Controller) driver for FreeBSD.
  31  */
  32
  33 #ifdef HAVE_KERNEL_OPTION_HEADERS
  34 #include "opt_snd.h"
  35 #endif
  36
  37 #include <dev/sound/pcm/sound.h>
  38 #include <dev/pci/pcireg.h>
  39 #include <dev/pci/pcivar.h>
  40
  41 #include <sys/ctype.h>
  42 #include <sys/taskqueue.h>
  43
  44 #include <dev/sound/pci/hda/hdac_private.h>
  45 #include <dev/sound/pci/hda/hdac_reg.h>
  46 #include <dev/sound/pci/hda/hda_reg.h>
  47 #include <dev/sound/pci/hda/hdac.h>
  48
  49 #define HDA_DRV_TEST_REV        "20120126_0002"
  50
  51 SND_DECLARE_FILE("$FreeBSD$");
  52
  53 #define hdac_lock(sc)           snd_mtxlock((sc)->lock)
  54 #define hdac_unlock(sc)         snd_mtxunlock((sc)->lock)
  55 #define hdac_lockassert(sc)     snd_mtxassert((sc)->lock)
  56 #define hdac_lockowned(sc)      mtx_owned((sc)->lock)
  57
  58 #define HDAC_QUIRK_64BIT        (1 << 0)
  59 #define HDAC_QUIRK_DMAPOS       (1 << 1)
  60 #define HDAC_QUIRK_MSI          (1 << 2)
  61
  62 static const struct {
  63         const char *key;
  64         uint32_t value;
  65 } hdac_quirks_tab[] = {
  66         { "64bit", HDAC_QUIRK_DMAPOS },
  67         { "dmapos", HDAC_QUIRK_DMAPOS },
  68         { "msi", HDAC_QUIRK_MSI },
  69 };
  70
  71 MALLOC_DEFINE(M_HDAC, "hdac", "HDA Controller");
  72
  73 static const struct {
  74         uint32_t        model;
  75         const char      *desc;
  76         char            quirks_on;
  77         char            quirks_off;
  78 } hdac_devices[] = {
  79         { HDA_INTEL_OAK,     "Intel Oaktrail",  0, 0 },
  80         { HDA_INTEL_BAY,     "Intel BayTrail",  0, 0 },
  81         { HDA_INTEL_HSW1,    "Intel Haswell",   0, 0 },
  82         { HDA_INTEL_HSW2,    "Intel Haswell",   0, 0 },
  83         { HDA_INTEL_HSW3,    "Intel Haswell",   0, 0 },
  84         { HDA_INTEL_BDW1,    "Intel Broadwell", 0, 0 },
  85         { HDA_INTEL_BDW2,    "Intel Broadwell", 0, 0 },
  86         { HDA_INTEL_CPT,     "Intel Cougar Point",      0, 0 },
  87         { HDA_INTEL_PATSBURG,"Intel Patsburg",  0, 0 },
  88         { HDA_INTEL_PPT1,    "Intel Panther Point",     0, 0 },
  89         { HDA_INTEL_LPT1,    "Intel Lynx Point",        0, 0 },
  90         { HDA_INTEL_LPT2,    "Intel Lynx Point",        0, 0 },
  91         { HDA_INTEL_WCPT,    "Intel Wildcat Point",     0, 0 },
  92         { HDA_INTEL_WELLS1,  "Intel Wellsburg", 0, 0 },
  93         { HDA_INTEL_WELLS2,  "Intel Wellsburg", 0, 0 },
  94         { HDA_INTEL_LPTLP1,  "Intel Lynx Point-LP",     0, 0 },
  95         { HDA_INTEL_LPTLP2,  "Intel Lynx Point-LP",     0, 0 },
  96         { HDA_INTEL_SRPTLP,  "Intel Sunrise Point-LP",  0, 0 },
  97         { HDA_INTEL_SRPT,    "Intel Sunrise Point",     0, 0 },
  98         { HDA_INTEL_82801F,  "Intel 82801F",    0, 0 },
  99         { HDA_INTEL_63XXESB, "Intel 631x/632xESB",      0, 0 },
 100         { HDA_INTEL_82801G,  "Intel 82801G",    0, 0 },
 101         { HDA_INTEL_82801H,  "Intel 82801H",    0, 0 },
 102         { HDA_INTEL_82801I,  "Intel 82801I",    0, 0 },
 103         { HDA_INTEL_82801JI, "Intel 82801JI",   0, 0 },
 104         { HDA_INTEL_82801JD, "Intel 82801JD",   0, 0 },
 105         { HDA_INTEL_PCH,     "Intel 5 Series/3400 Series",      0, 0 },
 106         { HDA_INTEL_PCH2,    "Intel 5 Series/3400 Series",      0, 0 },
 107         { HDA_INTEL_SCH,     "Intel SCH",       0, 0 },
 108         { HDA_NVIDIA_MCP51,  "NVIDIA MCP51",    0, HDAC_QUIRK_MSI },
 109         { HDA_NVIDIA_MCP55,  "NVIDIA MCP55",    0, HDAC_QUIRK_MSI },
 110         { HDA_NVIDIA_MCP61_1, "NVIDIA MCP61",   0, 0 },
 111         { HDA_NVIDIA_MCP61_2, "NVIDIA MCP61",   0, 0 },
 112         { HDA_NVIDIA_MCP65_1, "NVIDIA MCP65",   0, 0 },
 113         { HDA_NVIDIA_MCP65_2, "NVIDIA MCP65",   0, 0 },
 114         { HDA_NVIDIA_MCP67_1, "NVIDIA MCP67",   0, 0 },
 115         { HDA_NVIDIA_MCP67_2, "NVIDIA MCP67",   0, 0 },
 116         { HDA_NVIDIA_MCP73_1, "NVIDIA MCP73",   0, 0 },
 117         { HDA_NVIDIA_MCP73_2, "NVIDIA MCP73",   0, 0 },
 118         { HDA_NVIDIA_MCP78_1, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 119         { HDA_NVIDIA_MCP78_2, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 120         { HDA_NVIDIA_MCP78_3, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 121         { HDA_NVIDIA_MCP78_4, "NVIDIA MCP78",   0, HDAC_QUIRK_64BIT },
 122         { HDA_NVIDIA_MCP79_1, "NVIDIA MCP79",   0, 0 },
 123         { HDA_NVIDIA_MCP79_2, "NVIDIA MCP79",   0, 0 },
 124         { HDA_NVIDIA_MCP79_3, "NVIDIA MCP79",   0, 0 },
 125         { HDA_NVIDIA_MCP79_4, "NVIDIA MCP79",   0, 0 },
 126         { HDA_NVIDIA_MCP89_1, "NVIDIA MCP89",   0, 0 },
 127         { HDA_NVIDIA_MCP89_2, "NVIDIA MCP89",   0, 0 },
 128         { HDA_NVIDIA_MCP89_3, "NVIDIA MCP89",   0, 0 },
 129         { HDA_NVIDIA_MCP89_4, "NVIDIA MCP89",   0, 0 },
 130         { HDA_NVIDIA_0BE2,   "NVIDIA (0x0be2)", 0, HDAC_QUIRK_MSI },
 131         { HDA_NVIDIA_0BE3,   "NVIDIA (0x0be3)", 0, HDAC_QUIRK_MSI },
 132         { HDA_NVIDIA_0BE4,   "NVIDIA (0x0be4)", 0, HDAC_QUIRK_MSI },
 133         { HDA_NVIDIA_GT100,  "NVIDIA GT100",    0, HDAC_QUIRK_MSI },
 134         { HDA_NVIDIA_GT104,  "NVIDIA GT104",    0, HDAC_QUIRK_MSI },
 135         { HDA_NVIDIA_GT106,  "NVIDIA GT106",    0, HDAC_QUIRK_MSI },
 136         { HDA_NVIDIA_GT108,  "NVIDIA GT108",    0, HDAC_QUIRK_MSI },
 137         { HDA_NVIDIA_GT116,  "NVIDIA GT116",    0, HDAC_QUIRK_MSI },
 138         { HDA_NVIDIA_GF119,  "NVIDIA GF119",    0, 0 },
 139         { HDA_NVIDIA_GF110_1, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 140         { HDA_NVIDIA_GF110_2, "NVIDIA GF110",   0, HDAC_QUIRK_MSI },
 141         { HDA_ATI_SB450,     "ATI SB450",       0, 0 },
 142         { HDA_ATI_SB600,     "ATI SB600",       0, 0 },
 143         { HDA_ATI_RS600,     "ATI RS600",       0, 0 },
 144         { HDA_ATI_RS690,     "ATI RS690",       0, 0 },
 145         { HDA_ATI_RS780,     "ATI RS780",       0, 0 },
 146         { HDA_ATI_R600,      "ATI R600",        0, 0 },
 147         { HDA_ATI_RV610,     "ATI RV610",       0, 0 },
 148         { HDA_ATI_RV620,     "ATI RV620",       0, 0 },
 149         { HDA_ATI_RV630,     "ATI RV630",       0, 0 },
 150         { HDA_ATI_RV635,     "ATI RV635",       0, 0 },
 151         { HDA_ATI_RV710,     "ATI RV710",       0, 0 },
 152         { HDA_ATI_RV730,     "ATI RV730",       0, 0 },
 153         { HDA_ATI_RV740,     "ATI RV740",       0, 0 },
 154         { HDA_ATI_RV770,     "ATI RV770",       0, 0 },
 155         { HDA_ATI_RV810,     "ATI RV810",       0, 0 },
 156         { HDA_ATI_RV830,     "ATI RV830",       0, 0 },
 157         { HDA_ATI_RV840,     "ATI RV840",       0, 0 },
 158         { HDA_ATI_RV870,     "ATI RV870",       0, 0 },
 159         { HDA_ATI_RV910,     "ATI RV910",       0, 0 },
 160         { HDA_ATI_RV930,     "ATI RV930",       0, 0 },
 161         { HDA_ATI_RV940,     "ATI RV940",       0, 0 },
 162         { HDA_ATI_RV970,     "ATI RV970",       0, 0 },
 163         { HDA_ATI_R1000,     "ATI R1000",       0, 0 },
 164         { HDA_AMD_HUDSON2,   "AMD Hudson-2",    0, 0 },
 165         { HDA_RDC_M3010,     "RDC M3010",       0, 0 },
 166         { HDA_VIA_VT82XX,    "VIA VT8251/8237A",0, 0 },
 167         { HDA_SIS_966,       "SiS 966",         0, 0 },
 168         { HDA_ULI_M5461,     "ULI M5461",       0, 0 },
 169         /* Unknown */
 170         { HDA_INTEL_ALL,  "Intel",              0, 0 },
 171         { HDA_NVIDIA_ALL, "NVIDIA",             0, 0 },
 172         { HDA_ATI_ALL,    "ATI",                0, 0 },
 173         { HDA_AMD_ALL,    "AMD",                0, 0 },
 174         { HDA_VIA_ALL,    "VIA",                0, 0 },
 175         { HDA_SIS_ALL,    "SiS",                0, 0 },
 176         { HDA_ULI_ALL,    "ULI",                0, 0 },
 177 };
 178
 179 static const struct {
 180         uint16_t vendor;
 181         uint8_t reg;
 182         uint8_t mask;
 183         uint8_t enable;
 184 } hdac_pcie_snoop[] = {
 185         {  INTEL_VENDORID, 0x00, 0x00, 0x00 },
 186         {    ATI_VENDORID, 0x42, 0xf8, 0x02 },
 187         { NVIDIA_VENDORID, 0x4e, 0xf0, 0x0f },
 188 };
 189
 190 /****************************************************************************
 191  * Function prototypes
 192  ****************************************************************************/
 193 static void     hdac_intr_handler(void *);
 194 static int      hdac_reset(struct hdac_softc *, int);
 195 static int      hdac_get_capabilities(struct hdac_softc *);
 196 static void     hdac_dma_cb(void *, bus_dma_segment_t *, int, int);
 197 static int      hdac_dma_alloc(struct hdac_softc *,
 198                                         struct hdac_dma *, bus_size_t);
 199 static void     hdac_dma_free(struct hdac_softc *, struct hdac_dma *);
 200 static int      hdac_mem_alloc(struct hdac_softc *);
 201 static void     hdac_mem_free(struct hdac_softc *);
 202 static int      hdac_irq_alloc(struct hdac_softc *);
 203 static void     hdac_irq_free(struct hdac_softc *);
 204 static void     hdac_corb_init(struct hdac_softc *);
 205 static void     hdac_rirb_init(struct hdac_softc *);
 206 static void     hdac_corb_start(struct hdac_softc *);
 207 static void     hdac_rirb_start(struct hdac_softc *);
 208
 209 static void     hdac_attach2(void *);
 210
 211 static uint32_t hdac_send_command(struct hdac_softc *, nid_t, uint32_t);
 212
 213 static int      hdac_probe(device_t);
 214 static int      hdac_attach(device_t);
 215 static int      hdac_detach(device_t);
 216 static int      hdac_suspend(device_t);
 217 static int      hdac_resume(device_t);
 218
 219 static int      hdac_rirb_flush(struct hdac_softc *sc);
 220 static int      hdac_unsolq_flush(struct hdac_softc *sc);
 221
 222 #define hdac_command(a1, a2, a3)        \
 223                 hdac_send_command(a1, a3, a2)
 224
 225 /* This function surely going to make its way into upper level someday. */
 226 static void
 227 hdac_config_fetch(struct hdac_softc *sc, uint32_t *on, uint32_t *off)
 228 {
 229         const char *res = NULL;
 230         int i = 0, j, k, len, inv;
 231
 232         if (resource_string_value(device_get_name(sc->dev),
 233             device_get_unit(sc->dev), "config", &res) != 0)
 234                 return;
 235         if (!(res != NULL && strlen(res) > 0))
 236                 return;
 237         HDA_BOOTVERBOSE(
 238                 device_printf(sc->dev, "Config options:");
 239         );
 240         for (;;) {
 241                 while (res[i] != '\0' &&
 242                     (res[i] == ',' || isspace(res[i]) != 0))
 243                         i++;
 244                 if (res[i] == '\0') {
 245                         HDA_BOOTVERBOSE(
 246                                 printf("\n");
 247                         );
 248                         return;
 249                 }
 250                 j = i;
 251                 while (res[j] != '\0' &&
 252                     !(res[j] == ',' || isspace(res[j]) != 0))
 253                         j++;
 254                 len = j - i;
 255                 if (len > 2 && strncmp(res + i, "no", 2) == 0)
 256                         inv = 2;
 257                 else
 258                         inv = 0;
 259                 for (k = 0; len > inv && k < nitems(hdac_quirks_tab); k++) {
 260                         if (strncmp(res + i + inv,
 261                             hdac_quirks_tab[k].key, len - inv) != 0)
 262                                 continue;
 263                         if (len - inv != strlen(hdac_quirks_tab[k].key))
 264                                 continue;
 265                         HDA_BOOTVERBOSE(
 266                                 printf(" %s%s", (inv != 0) ? "no" : "",
 267                                     hdac_quirks_tab[k].key);
 268                         );
 269                         if (inv == 0) {
 270                                 *on |= hdac_quirks_tab[k].value;
 271                                 *on &= ~hdac_quirks_tab[k].value;
 272                         } else if (inv != 0) {
 273                                 *off |= hdac_quirks_tab[k].value;
 274                                 *off &= ~hdac_quirks_tab[k].value;
 275                         }
 276                         break;
 277                 }
 278                 i = j;
 279         }
 280 }
 281
 282 /****************************************************************************
 283  * void hdac_intr_handler(void *)
 284  *
 285  * Interrupt handler. Processes interrupts received from the hdac.
 286  ****************************************************************************/
 287 static void
 288 hdac_intr_handler(void *context)
 289 {
 290         struct hdac_softc *sc;
 291         device_t dev;
 292         uint32_t intsts;
 293         uint8_t rirbsts;
 294         int i;
 295
 296         sc = (struct hdac_softc *)context;
 297         hdac_lock(sc);
 298
 299         /* Do we have anything to do? */
 300         intsts = HDAC_READ_4(&sc->mem, HDAC_INTSTS);
 301         if ((intsts & HDAC_INTSTS_GIS) == 0) {
 302                 hdac_unlock(sc);
 303                 return;
 304         }
 305
 306         /* Was this a controller interrupt? */
 307         if (intsts & HDAC_INTSTS_CIS) {
 308                 rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 309                 /* Get as many responses that we can */
 310                 while (rirbsts & HDAC_RIRBSTS_RINTFL) {
 311                         HDAC_WRITE_1(&sc->mem,
 312                             HDAC_RIRBSTS, HDAC_RIRBSTS_RINTFL);
 313                         hdac_rirb_flush(sc);
 314                         rirbsts = HDAC_READ_1(&sc->mem, HDAC_RIRBSTS);
 315                 }
 316                 if (sc->unsolq_rp != sc->unsolq_wp)
 317                         taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
 318         }
 319
 320         if (intsts & HDAC_INTSTS_SIS_MASK) {
 321                 for (i = 0; i < sc->num_ss; i++) {
 322                         if ((intsts & (1 << i)) == 0)
 323                                 continue;
 324                         HDAC_WRITE_1(&sc->mem, (i << 5) + HDAC_SDSTS,
 325                             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS );
 326                         if ((dev = sc->streams[i].dev) != NULL) {
 327                                 HDAC_STREAM_INTR(dev,
 328                                     sc->streams[i].dir, sc->streams[i].stream);
 329                         }
 330                 }
 331         }
 332
 333         HDAC_WRITE_4(&sc->mem, HDAC_INTSTS, intsts);
 334         hdac_unlock(sc);
 335 }
 336
 337 static void
 338 hdac_poll_callback(void *arg)
 339 {
 340         struct hdac_softc *sc = arg;
 341
 342         if (sc == NULL)
 343                 return;
 344
 345         hdac_lock(sc);
 346         if (sc->polling == 0) {
 347                 hdac_unlock(sc);
 348                 return;
 349         }
 350         callout_reset(&sc->poll_callout, sc->poll_ival,
 351             hdac_poll_callback, sc);
 352         hdac_unlock(sc);
 353
 354         hdac_intr_handler(sc);
 355 }
 356
 357 /****************************************************************************
 358  * int hdac_reset(hdac_softc *, int)
 359  *
 360  * Reset the hdac to a quiescent and known state.
 361  ****************************************************************************/
 362 static int
 363 hdac_reset(struct hdac_softc *sc, int wakeup)
 364 {
 365         uint32_t gctl;
 366         int count, i;
 367
 368         /*
 369          * Stop all Streams DMA engine
 370          */
 371         for (i = 0; i < sc->num_iss; i++)
 372                 HDAC_WRITE_4(&sc->mem, HDAC_ISDCTL(sc, i), 0x0);
 373         for (i = 0; i < sc->num_oss; i++)
 374                 HDAC_WRITE_4(&sc->mem, HDAC_OSDCTL(sc, i), 0x0);
 375         for (i = 0; i < sc->num_bss; i++)
 376                 HDAC_WRITE_4(&sc->mem, HDAC_BSDCTL(sc, i), 0x0);
 377
 378         /*
 379          * Stop Control DMA engines.
 380          */
 381         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, 0x0);
 382         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, 0x0);
 383
 384         /*
 385          * Reset DMA position buffer.
 386          */
 387         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE, 0x0);
 388         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, 0x0);
 389
 390         /*
 391          * Reset the controller. The reset must remain asserted for
 392          * a minimum of 100us.
 393          */
 394         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 395         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl & ~HDAC_GCTL_CRST);
 396         count = 10000;
 397         do {
 398                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 399                 if (!(gctl & HDAC_GCTL_CRST))
 400                         break;
 401                 DELAY(10);
 402         } while (--count);
 403         if (gctl & HDAC_GCTL_CRST) {
 404                 device_printf(sc->dev, "Unable to put hdac in reset\n");
 405                 return (ENXIO);
 406         }
 407
 408         /* If wakeup is not requested - leave the controller in reset state. */
 409         if (!wakeup)
 410                 return (0);
 411
 412         DELAY(100);
 413         gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 414         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, gctl | HDAC_GCTL_CRST);
 415         count = 10000;
 416         do {
 417                 gctl = HDAC_READ_4(&sc->mem, HDAC_GCTL);
 418                 if (gctl & HDAC_GCTL_CRST)
 419                         break;
 420                 DELAY(10);
 421         } while (--count);
 422         if (!(gctl & HDAC_GCTL_CRST)) {
 423                 device_printf(sc->dev, "Device stuck in reset\n");
 424                 return (ENXIO);
 425         }
 426
 427         /*
 428          * Wait for codecs to finish their own reset sequence. The delay here
 429          * should be of 250us but for some reasons, on it's not enough on my
 430          * computer. Let's use twice as much as necessary to make sure that
 431          * it's reset properly.
 432          */
 433         DELAY(1000);
 434
 435         return (0);
 436 }
 437
 438
 439 /****************************************************************************
 440  * int hdac_get_capabilities(struct hdac_softc *);
 441  *
 442  * Retreive the general capabilities of the hdac;
 443  *      Number of Input Streams
 444  *      Number of Output Streams
 445  *      Number of bidirectional Streams
 446  *      64bit ready
 447  *      CORB and RIRB sizes
 448  ****************************************************************************/
 449 static int
 450 hdac_get_capabilities(struct hdac_softc *sc)
 451 {
 452         uint16_t gcap;
 453         uint8_t corbsize, rirbsize;
 454
 455         gcap = HDAC_READ_2(&sc->mem, HDAC_GCAP);
 456         sc->num_iss = HDAC_GCAP_ISS(gcap);
 457         sc->num_oss = HDAC_GCAP_OSS(gcap);
 458         sc->num_bss = HDAC_GCAP_BSS(gcap);
 459         sc->num_ss = sc->num_iss + sc->num_oss + sc->num_bss;
 460         sc->num_sdo = HDAC_GCAP_NSDO(gcap);
 461         sc->support_64bit = (gcap & HDAC_GCAP_64OK) != 0;
 462         if (sc->quirks_on & HDAC_QUIRK_64BIT)
 463                 sc->support_64bit = 1;
 464         else if (sc->quirks_off & HDAC_QUIRK_64BIT)
 465                 sc->support_64bit = 0;
 466
 467         corbsize = HDAC_READ_1(&sc->mem, HDAC_CORBSIZE);
 468         if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_256) ==
 469             HDAC_CORBSIZE_CORBSZCAP_256)
 470                 sc->corb_size = 256;
 471         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_16) ==
 472             HDAC_CORBSIZE_CORBSZCAP_16)
 473                 sc->corb_size = 16;
 474         else if ((corbsize & HDAC_CORBSIZE_CORBSZCAP_2) ==
 475             HDAC_CORBSIZE_CORBSZCAP_2)
 476                 sc->corb_size = 2;
 477         else {
 478                 device_printf(sc->dev, "%s: Invalid corb size (%x)\n",
 479                     __func__, corbsize);
 480                 return (ENXIO);
 481         }
 482
 483         rirbsize = HDAC_READ_1(&sc->mem, HDAC_RIRBSIZE);
 484         if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_256) ==
 485             HDAC_RIRBSIZE_RIRBSZCAP_256)
 486                 sc->rirb_size = 256;
 487         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_16) ==
 488             HDAC_RIRBSIZE_RIRBSZCAP_16)
 489                 sc->rirb_size = 16;
 490         else if ((rirbsize & HDAC_RIRBSIZE_RIRBSZCAP_2) ==
 491             HDAC_RIRBSIZE_RIRBSZCAP_2)
 492                 sc->rirb_size = 2;
 493         else {
 494                 device_printf(sc->dev, "%s: Invalid rirb size (%x)\n",
 495                     __func__, rirbsize);
 496                 return (ENXIO);
 497         }
 498
 499         HDA_BOOTVERBOSE(
 500                 device_printf(sc->dev, "Caps: OSS %d, ISS %d, BSS %d, "
 501                     "NSDO %d%s, CORB %d, RIRB %d\n",
 502                     sc->num_oss, sc->num_iss, sc->num_bss, 1 << sc->num_sdo,
 503                     sc->support_64bit ? ", 64bit" : "",
 504                     sc->corb_size, sc->rirb_size);
 505         );
 506
 507         return (0);
 508 }
 509
 510
 511 /****************************************************************************
 512  * void hdac_dma_cb
 513  *
 514  * This function is called by bus_dmamap_load when the mapping has been
 515  * established. We just record the physical address of the mapping into
 516  * the struct hdac_dma passed in.
 517  ****************************************************************************/
 518 static void
 519 hdac_dma_cb(void *callback_arg, bus_dma_segment_t *segs, int nseg, int error)
 520 {
 521         struct hdac_dma *dma;
 522
 523         if (error == 0) {
 524                 dma = (struct hdac_dma *)callback_arg;
 525                 dma->dma_paddr = segs[0].ds_addr;
 526         }
 527 }
 528
 529
 530 /****************************************************************************
 531  * int hdac_dma_alloc
 532  *
 533  * This function allocate and setup a dma region (struct hdac_dma).
 534  * It must be freed by a corresponding hdac_dma_free.
 535  ****************************************************************************/
 536 static int
 537 hdac_dma_alloc(struct hdac_softc *sc, struct hdac_dma *dma, bus_size_t size)
 538 {
 539         bus_size_t roundsz;
 540         int result;
 541
 542         roundsz = roundup2(size, HDA_DMA_ALIGNMENT);
 543         bzero(dma, sizeof(*dma));
 544
 545         /*
 546          * Create a DMA tag
 547          */
 548         result = bus_dma_tag_create(
 549             bus_get_dma_tag(sc->dev),           /* parent */
 550             HDA_DMA_ALIGNMENT,                  /* alignment */
 551             0,                                  /* boundary */
 552             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
 553                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
 554             BUS_SPACE_MAXADDR,                  /* highaddr */
 555             NULL,                               /* filtfunc */
 556             NULL,                               /* fistfuncarg */
 557             roundsz,                            /* maxsize */
 558             1,                                  /* nsegments */
 559             roundsz,                            /* maxsegsz */
 560             0,                                  /* flags */
 561             NULL,                               /* lockfunc */
 562             NULL,                               /* lockfuncarg */
 563             &dma->dma_tag);                     /* dmat */
 564         if (result != 0) {
 565                 device_printf(sc->dev, "%s: bus_dma_tag_create failed (%x)\n",
 566                     __func__, result);
 567                 goto hdac_dma_alloc_fail;
 568         }
 569
 570         /*
 571          * Allocate DMA memory
 572          */
 573         result = bus_dmamem_alloc(dma->dma_tag, (void **)&dma->dma_vaddr,
 574             BUS_DMA_NOWAIT | BUS_DMA_ZERO |
 575             ((sc->flags & HDAC_F_DMA_NOCACHE) ? BUS_DMA_NOCACHE : 0),
 576             &dma->dma_map);
 577         if (result != 0) {
 578                 device_printf(sc->dev, "%s: bus_dmamem_alloc failed (%x)\n",
 579                     __func__, result);
 580                 goto hdac_dma_alloc_fail;
 581         }
 582
 583         dma->dma_size = roundsz;
 584
 585         /*
 586          * Map the memory
 587          */
 588         result = bus_dmamap_load(dma->dma_tag, dma->dma_map,
 589             (void *)dma->dma_vaddr, roundsz, hdac_dma_cb, (void *)dma, 0);
 590         if (result != 0 || dma->dma_paddr == 0) {
 591                 if (result == 0)
 592                         result = ENOMEM;
 593                 device_printf(sc->dev, "%s: bus_dmamem_load failed (%x)\n",
 594                     __func__, result);
 595                 goto hdac_dma_alloc_fail;
 596         }
 597
 598         HDA_BOOTHVERBOSE(
 599                 device_printf(sc->dev, "%s: size=%ju -> roundsz=%ju\n",
 600                     __func__, (uintmax_t)size, (uintmax_t)roundsz);
 601         );
 602
 603         return (0);
 604
 605 hdac_dma_alloc_fail:
 606         hdac_dma_free(sc, dma);
 607
 608         return (result);
 609 }
 610
 611
 612 /****************************************************************************
 613  * void hdac_dma_free(struct hdac_softc *, struct hdac_dma *)
 614  *
 615  * Free a struct dhac_dma that has been previously allocated via the
 616  * hdac_dma_alloc function.
 617  ****************************************************************************/
 618 static void
 619 hdac_dma_free(struct hdac_softc *sc, struct hdac_dma *dma)
 620 {
 621         if (dma->dma_map != NULL) {
 622 #if 0
 623                 /* Flush caches */
 624                 bus_dmamap_sync(dma->dma_tag, dma->dma_map,
 625                     BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE);
 626 #endif
 627                 bus_dmamap_unload(dma->dma_tag, dma->dma_map);
 628         }
 629         if (dma->dma_vaddr != NULL) {
 630                 bus_dmamem_free(dma->dma_tag, dma->dma_vaddr, dma->dma_map);
 631                 dma->dma_vaddr = NULL;
 632         }
 633         dma->dma_map = NULL;
 634         if (dma->dma_tag != NULL) {
 635                 bus_dma_tag_destroy(dma->dma_tag);
 636                 dma->dma_tag = NULL;
 637         }
 638         dma->dma_size = 0;
 639 }
 640
 641 /****************************************************************************
 642  * int hdac_mem_alloc(struct hdac_softc *)
 643  *
 644  * Allocate all the bus resources necessary to speak with the physical
 645  * controller.
 646  ****************************************************************************/
 647 static int
 648 hdac_mem_alloc(struct hdac_softc *sc)
 649 {
 650         struct hdac_mem *mem;
 651
 652         mem = &sc->mem;
 653         mem->mem_rid = PCIR_BAR(0);
 654         mem->mem_res = bus_alloc_resource_any(sc->dev, SYS_RES_MEMORY,
 655             &mem->mem_rid, RF_ACTIVE);
 656         if (mem->mem_res == NULL) {
 657                 device_printf(sc->dev,
 658                     "%s: Unable to allocate memory resource\n", __func__);
 659                 return (ENOMEM);
 660         }
 661         mem->mem_tag = rman_get_bustag(mem->mem_res);
 662         mem->mem_handle = rman_get_bushandle(mem->mem_res);
 663
 664         return (0);
 665 }
 666
 667 /****************************************************************************
 668  * void hdac_mem_free(struct hdac_softc *)
 669  *
 670  * Free up resources previously allocated by hdac_mem_alloc.
 671  ****************************************************************************/
 672 static void
 673 hdac_mem_free(struct hdac_softc *sc)
 674 {
 675         struct hdac_mem *mem;
 676
 677         mem = &sc->mem;
 678         if (mem->mem_res != NULL)
 679                 bus_release_resource(sc->dev, SYS_RES_MEMORY, mem->mem_rid,
 680                     mem->mem_res);
 681         mem->mem_res = NULL;
 682 }
 683
 684 /****************************************************************************
 685  * int hdac_irq_alloc(struct hdac_softc *)
 686  *
 687  * Allocate and setup the resources necessary for interrupt handling.
 688  ****************************************************************************/
 689 static int
 690 hdac_irq_alloc(struct hdac_softc *sc)
 691 {
 692         struct hdac_irq *irq;
 693         int result;
 694
 695         irq = &sc->irq;
 696         irq->irq_rid = 0x0;
 697
 698         if ((sc->quirks_off & HDAC_QUIRK_MSI) == 0 &&
 699             (result = pci_msi_count(sc->dev)) == 1 &&
 700             pci_alloc_msi(sc->dev, &result) == 0)
 701                 irq->irq_rid = 0x1;
 702
 703         irq->irq_res = bus_alloc_resource_any(sc->dev, SYS_RES_IRQ,
 704             &irq->irq_rid, RF_SHAREABLE | RF_ACTIVE);
 705         if (irq->irq_res == NULL) {
 706                 device_printf(sc->dev, "%s: Unable to allocate irq\n",
 707                     __func__);
 708                 goto hdac_irq_alloc_fail;
 709         }
 710         result = bus_setup_intr(sc->dev, irq->irq_res, INTR_MPSAFE | INTR_TYPE_AV,
 711             NULL, hdac_intr_handler, sc, &irq->irq_handle);
 712         if (result != 0) {
 713                 device_printf(sc->dev,
 714                     "%s: Unable to setup interrupt handler (%x)\n",
 715                     __func__, result);
 716                 goto hdac_irq_alloc_fail;
 717         }
 718
 719         return (0);
 720
 721 hdac_irq_alloc_fail:
 722         hdac_irq_free(sc);
 723
 724         return (ENXIO);
 725 }
 726
 727 /****************************************************************************
 728  * void hdac_irq_free(struct hdac_softc *)
 729  *
 730  * Free up resources previously allocated by hdac_irq_alloc.
 731  ****************************************************************************/
 732 static void
 733 hdac_irq_free(struct hdac_softc *sc)
 734 {
 735         struct hdac_irq *irq;
 736
 737         irq = &sc->irq;
 738         if (irq->irq_res != NULL && irq->irq_handle != NULL)
 739                 bus_teardown_intr(sc->dev, irq->irq_res, irq->irq_handle);
 740         if (irq->irq_res != NULL)
 741                 bus_release_resource(sc->dev, SYS_RES_IRQ, irq->irq_rid,
 742                     irq->irq_res);
 743         if (irq->irq_rid == 0x1)
 744                 pci_release_msi(sc->dev);
 745         irq->irq_handle = NULL;
 746         irq->irq_res = NULL;
 747         irq->irq_rid = 0x0;
 748 }
 749
 750 /****************************************************************************
 751  * void hdac_corb_init(struct hdac_softc *)
 752  *
 753  * Initialize the corb registers for operations but do not start it up yet.
 754  * The CORB engine must not be running when this function is called.
 755  ****************************************************************************/
 756 static void
 757 hdac_corb_init(struct hdac_softc *sc)
 758 {
 759         uint8_t corbsize;
 760         uint64_t corbpaddr;
 761
 762         /* Setup the CORB size. */
 763         switch (sc->corb_size) {
 764         case 256:
 765                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_256);
 766                 break;
 767         case 16:
 768                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_16);
 769                 break;
 770         case 2:
 771                 corbsize = HDAC_CORBSIZE_CORBSIZE(HDAC_CORBSIZE_CORBSIZE_2);
 772                 break;
 773         default:
 774                 panic("%s: Invalid CORB size (%x)\n", __func__, sc->corb_size);
 775         }
 776         HDAC_WRITE_1(&sc->mem, HDAC_CORBSIZE, corbsize);
 777
 778         /* Setup the CORB Address in the hdac */
 779         corbpaddr = (uint64_t)sc->corb_dma.dma_paddr;
 780         HDAC_WRITE_4(&sc->mem, HDAC_CORBLBASE, (uint32_t)corbpaddr);
 781         HDAC_WRITE_4(&sc->mem, HDAC_CORBUBASE, (uint32_t)(corbpaddr >> 32));
 782
 783         /* Set the WP and RP */
 784         sc->corb_wp = 0;
 785         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 786         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, HDAC_CORBRP_CORBRPRST);
 787         /*
 788          * The HDA specification indicates that the CORBRPRST bit will always
 789          * read as zero. Unfortunately, it seems that at least the 82801G
 790          * doesn't reset the bit to zero, which stalls the corb engine.
 791          * manually reset the bit to zero before continuing.
 792          */
 793         HDAC_WRITE_2(&sc->mem, HDAC_CORBRP, 0x0);
 794
 795         /* Enable CORB error reporting */
 796 #if 0
 797         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, HDAC_CORBCTL_CMEIE);
 798 #endif
 799 }
 800
 801 /****************************************************************************
 802  * void hdac_rirb_init(struct hdac_softc *)
 803  *
 804  * Initialize the rirb registers for operations but do not start it up yet.
 805  * The RIRB engine must not be running when this function is called.
 806  ****************************************************************************/
 807 static void
 808 hdac_rirb_init(struct hdac_softc *sc)
 809 {
 810         uint8_t rirbsize;
 811         uint64_t rirbpaddr;
 812
 813         /* Setup the RIRB size. */
 814         switch (sc->rirb_size) {
 815         case 256:
 816                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_256);
 817                 break;
 818         case 16:
 819                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_16);
 820                 break;
 821         case 2:
 822                 rirbsize = HDAC_RIRBSIZE_RIRBSIZE(HDAC_RIRBSIZE_RIRBSIZE_2);
 823                 break;
 824         default:
 825                 panic("%s: Invalid RIRB size (%x)\n", __func__, sc->rirb_size);
 826         }
 827         HDAC_WRITE_1(&sc->mem, HDAC_RIRBSIZE, rirbsize);
 828
 829         /* Setup the RIRB Address in the hdac */
 830         rirbpaddr = (uint64_t)sc->rirb_dma.dma_paddr;
 831         HDAC_WRITE_4(&sc->mem, HDAC_RIRBLBASE, (uint32_t)rirbpaddr);
 832         HDAC_WRITE_4(&sc->mem, HDAC_RIRBUBASE, (uint32_t)(rirbpaddr >> 32));
 833
 834         /* Setup the WP and RP */
 835         sc->rirb_rp = 0;
 836         HDAC_WRITE_2(&sc->mem, HDAC_RIRBWP, HDAC_RIRBWP_RIRBWPRST);
 837
 838         /* Setup the interrupt threshold */
 839         HDAC_WRITE_2(&sc->mem, HDAC_RINTCNT, sc->rirb_size / 2);
 840
 841         /* Enable Overrun and response received reporting */
 842 #if 0
 843         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL,
 844             HDAC_RIRBCTL_RIRBOIC | HDAC_RIRBCTL_RINTCTL);
 845 #else
 846         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, HDAC_RIRBCTL_RINTCTL);
 847 #endif
 848
 849 #if 0
 850         /*
 851          * Make sure that the Host CPU cache doesn't contain any dirty
 852          * cache lines that falls in the rirb. If I understood correctly, it
 853          * should be sufficient to do this only once as the rirb is purely
 854          * read-only from now on.
 855          */
 856         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 857             BUS_DMASYNC_PREREAD);
 858 #endif
 859 }
 860
 861 /****************************************************************************
 862  * void hdac_corb_start(hdac_softc *)
 863  *
 864  * Startup the corb DMA engine
 865  ****************************************************************************/
 866 static void
 867 hdac_corb_start(struct hdac_softc *sc)
 868 {
 869         uint32_t corbctl;
 870
 871         corbctl = HDAC_READ_1(&sc->mem, HDAC_CORBCTL);
 872         corbctl |= HDAC_CORBCTL_CORBRUN;
 873         HDAC_WRITE_1(&sc->mem, HDAC_CORBCTL, corbctl);
 874 }
 875
 876 /****************************************************************************
 877  * void hdac_rirb_start(hdac_softc *)
 878  *
 879  * Startup the rirb DMA engine
 880  ****************************************************************************/
 881 static void
 882 hdac_rirb_start(struct hdac_softc *sc)
 883 {
 884         uint32_t rirbctl;
 885
 886         rirbctl = HDAC_READ_1(&sc->mem, HDAC_RIRBCTL);
 887         rirbctl |= HDAC_RIRBCTL_RIRBDMAEN;
 888         HDAC_WRITE_1(&sc->mem, HDAC_RIRBCTL, rirbctl);
 889 }
 890
 891 static int
 892 hdac_rirb_flush(struct hdac_softc *sc)
 893 {
 894         struct hdac_rirb *rirb_base, *rirb;
 895         nid_t cad;
 896         uint32_t resp;
 897         uint8_t rirbwp;
 898         int ret;
 899
 900         rirb_base = (struct hdac_rirb *)sc->rirb_dma.dma_vaddr;
 901         rirbwp = HDAC_READ_1(&sc->mem, HDAC_RIRBWP);
 902 #if 0
 903         bus_dmamap_sync(sc->rirb_dma.dma_tag, sc->rirb_dma.dma_map,
 904             BUS_DMASYNC_POSTREAD);
 905 #endif
 906
 907         ret = 0;
 908         while (sc->rirb_rp != rirbwp) {
 909                 sc->rirb_rp++;
 910                 sc->rirb_rp %= sc->rirb_size;
 911                 rirb = &rirb_base[sc->rirb_rp];
 912                 cad = HDAC_RIRB_RESPONSE_EX_SDATA_IN(rirb->response_ex);
 913                 resp = rirb->response;
 914                 if (rirb->response_ex & HDAC_RIRB_RESPONSE_EX_UNSOLICITED) {
 915                         sc->unsolq[sc->unsolq_wp++] = resp;
 916                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 917                         sc->unsolq[sc->unsolq_wp++] = cad;
 918                         sc->unsolq_wp %= HDAC_UNSOLQ_MAX;
 919                 } else if (sc->codecs[cad].pending <= 0) {
 920                         device_printf(sc->dev, "Unexpected unsolicited "
 921                             "response from address %d: %08x\n", cad, resp);
 922                 } else {
 923                         sc->codecs[cad].response = resp;
 924                         sc->codecs[cad].pending--;
 925                 }
 926                 ret++;
 927         }
 928         return (ret);
 929 }
 930
 931 static int
 932 hdac_unsolq_flush(struct hdac_softc *sc)
 933 {
 934         device_t child;
 935         nid_t cad;
 936         uint32_t resp;
 937         int ret = 0;
 938
 939         if (sc->unsolq_st == HDAC_UNSOLQ_READY) {
 940                 sc->unsolq_st = HDAC_UNSOLQ_BUSY;
 941                 while (sc->unsolq_rp != sc->unsolq_wp) {
 942                         resp = sc->unsolq[sc->unsolq_rp++];
 943                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 944                         cad = sc->unsolq[sc->unsolq_rp++];
 945                         sc->unsolq_rp %= HDAC_UNSOLQ_MAX;
 946                         if ((child = sc->codecs[cad].dev) != NULL)
 947                                 HDAC_UNSOL_INTR(child, resp);
 948                         ret++;
 949                 }
 950                 sc->unsolq_st = HDAC_UNSOLQ_READY;
 951         }
 952
 953         return (ret);
 954 }
 955
 956 /****************************************************************************
 957  * uint32_t hdac_command_sendone_internal
 958  *
 959  * Wrapper function that sends only one command to a given codec
 960  ****************************************************************************/
 961 static uint32_t
 962 hdac_send_command(struct hdac_softc *sc, nid_t cad, uint32_t verb)
 963 {
 964         int timeout;
 965         uint32_t *corb;
 966
 967         if (!hdac_lockowned(sc))
 968                 device_printf(sc->dev, "WARNING!!!! mtx not owned!!!!\n");
 969         verb &= ~HDA_CMD_CAD_MASK;
 970         verb |= ((uint32_t)cad) << HDA_CMD_CAD_SHIFT;
 971         sc->codecs[cad].response = HDA_INVALID;
 972
 973         sc->codecs[cad].pending++;
 974         sc->corb_wp++;
 975         sc->corb_wp %= sc->corb_size;
 976         corb = (uint32_t *)sc->corb_dma.dma_vaddr;
 977 #if 0
 978         bus_dmamap_sync(sc->corb_dma.dma_tag,
 979             sc->corb_dma.dma_map, BUS_DMASYNC_PREWRITE);
 980 #endif
 981         corb[sc->corb_wp] = verb;
 982 #if 0
 983         bus_dmamap_sync(sc->corb_dma.dma_tag,
 984             sc->corb_dma.dma_map, BUS_DMASYNC_POSTWRITE);
 985 #endif
 986         HDAC_WRITE_2(&sc->mem, HDAC_CORBWP, sc->corb_wp);
 987
 988         timeout = 10000;
 989         do {
 990                 if (hdac_rirb_flush(sc) == 0)
 991                         DELAY(10);
 992         } while (sc->codecs[cad].pending != 0 && --timeout);
 993
 994         if (sc->codecs[cad].pending != 0) {
 995                 device_printf(sc->dev, "Command timeout on address %d\n", cad);
 996                 sc->codecs[cad].pending = 0;
 997         }
 998
 999         if (sc->unsolq_rp != sc->unsolq_wp)
1000                 taskqueue_enqueue(taskqueue_thread, &sc->unsolq_task);
1001         return (sc->codecs[cad].response);
1002 }
1003
1004 /****************************************************************************
1005  * Device Methods
1006  ****************************************************************************/
1007
1008 /****************************************************************************
1009  * int hdac_probe(device_t)
1010  *
1011  * Probe for the presence of an hdac. If none is found, check for a generic
1012  * match using the subclass of the device.
1013  ****************************************************************************/
1014 static int
1015 hdac_probe(device_t dev)
1016 {
1017         int i, result;
1018         uint32_t model;
1019         uint16_t class, subclass;
1020         char desc[64];
1021
1022         model = (uint32_t)pci_get_device(dev) << 16;
1023         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1024         class = pci_get_class(dev);
1025         subclass = pci_get_subclass(dev);
1026
1027         bzero(desc, sizeof(desc));
1028         result = ENXIO;
1029         for (i = 0; i < nitems(hdac_devices); i++) {
1030                 if (hdac_devices[i].model == model) {
1031                         strlcpy(desc, hdac_devices[i].desc, sizeof(desc));
1032                         result = BUS_PROBE_DEFAULT;
1033                         break;
1034                 }
1035                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1036                     class == PCIC_MULTIMEDIA &&
1037                     subclass == PCIS_MULTIMEDIA_HDA) {
1038                         snprintf(desc, sizeof(desc),
1039                             "%s (0x%04x)",
1040                             hdac_devices[i].desc, pci_get_device(dev));
1041                         result = BUS_PROBE_GENERIC;
1042                         break;
1043                 }
1044         }
1045         if (result == ENXIO && class == PCIC_MULTIMEDIA &&
1046             subclass == PCIS_MULTIMEDIA_HDA) {
1047                 snprintf(desc, sizeof(desc), "Generic (0x%08x)", model);
1048                 result = BUS_PROBE_GENERIC;
1049         }
1050         if (result != ENXIO) {
1051                 strlcat(desc, " HDA Controller", sizeof(desc));
1052                 device_set_desc_copy(dev, desc);
1053         }
1054
1055         return (result);
1056 }
1057
1058 static void
1059 hdac_unsolq_task(void *context, int pending)
1060 {
1061         struct hdac_softc *sc;
1062
1063         sc = (struct hdac_softc *)context;
1064
1065         hdac_lock(sc);
1066         hdac_unsolq_flush(sc);
1067         hdac_unlock(sc);
1068 }
1069
1070 /****************************************************************************
1071  * int hdac_attach(device_t)
1072  *
1073  * Attach the device into the kernel. Interrupts usually won't be enabled
1074  * when this function is called. Setup everything that doesn't require
1075  * interrupts and defer probing of codecs until interrupts are enabled.
1076  ****************************************************************************/
1077 static int
1078 hdac_attach(device_t dev)
1079 {
1080         struct hdac_softc *sc;
1081         int result;
1082         int i, devid = -1;
1083         uint32_t model;
1084         uint16_t class, subclass;
1085         uint16_t vendor;
1086         uint8_t v;
1087
1088         sc = device_get_softc(dev);
1089         HDA_BOOTVERBOSE(
1090                 device_printf(dev, "PCI card vendor: 0x%04x, device: 0x%04x\n",
1091                     pci_get_subvendor(dev), pci_get_subdevice(dev));
1092                 device_printf(dev, "HDA Driver Revision: %s\n",
1093                     HDA_DRV_TEST_REV);
1094         );
1095
1096         model = (uint32_t)pci_get_device(dev) << 16;
1097         model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff;
1098         class = pci_get_class(dev);
1099         subclass = pci_get_subclass(dev);
1100
1101         for (i = 0; i < nitems(hdac_devices); i++) {
1102                 if (hdac_devices[i].model == model) {
1103                         devid = i;
1104                         break;
1105                 }
1106                 if (HDA_DEV_MATCH(hdac_devices[i].model, model) &&
1107                     class == PCIC_MULTIMEDIA &&
1108                     subclass == PCIS_MULTIMEDIA_HDA) {
1109                         devid = i;
1110                         break;
1111                 }
1112         }
1113
1114         sc->lock = snd_mtxcreate(device_get_nameunit(dev), "HDA driver mutex");
1115         sc->dev = dev;
1116         TASK_INIT(&sc->unsolq_task, 0, hdac_unsolq_task, sc);
1117         callout_init(&sc->poll_callout, CALLOUT_MPSAFE);
1118         for (i = 0; i < HDAC_CODEC_MAX; i++)
1119                 sc->codecs[i].dev = NULL;
1120         if (devid >= 0) {
1121                 sc->quirks_on = hdac_devices[devid].quirks_on;
1122                 sc->quirks_off = hdac_devices[devid].quirks_off;
1123         } else {
1124                 sc->quirks_on = 0;
1125                 sc->quirks_off = 0;
1126         }
1127         if (resource_int_value(device_get_name(dev),
1128             device_get_unit(dev), "msi", &i) == 0) {
1129                 if (i == 0)
1130                         sc->quirks_off |= HDAC_QUIRK_MSI;
1131                 else {
1132                         sc->quirks_on |= HDAC_QUIRK_MSI;
1133                         sc->quirks_off |= ~HDAC_QUIRK_MSI;
1134                 }
1135         }
1136         hdac_config_fetch(sc, &sc->quirks_on, &sc->quirks_off);
1137         HDA_BOOTVERBOSE(
1138                 device_printf(sc->dev,
1139                     "Config options: on=0x%08x off=0x%08x\n",
1140                     sc->quirks_on, sc->quirks_off);
1141         );
1142         sc->poll_ival = hz;
1143         if (resource_int_value(device_get_name(dev),
1144             device_get_unit(dev), "polling", &i) == 0 && i != 0)
1145                 sc->polling = 1;
1146         else
1147                 sc->polling = 0;
1148
1149         pci_enable_busmaster(dev);
1150
1151         vendor = pci_get_vendor(dev);
1152         if (vendor == INTEL_VENDORID) {
1153                 /* TCSEL -> TC0 */
1154                 v = pci_read_config(dev, 0x44, 1);
1155                 pci_write_config(dev, 0x44, v & 0xf8, 1);
1156                 HDA_BOOTHVERBOSE(
1157                         device_printf(dev, "TCSEL: 0x%02d -> 0x%02d\n", v,
1158                             pci_read_config(dev, 0x44, 1));
1159                 );
1160         }
1161
1162 #if defined(__i386__) || defined(__amd64__)
1163         sc->flags |= HDAC_F_DMA_NOCACHE;
1164
1165         if (resource_int_value(device_get_name(dev),
1166             device_get_unit(dev), "snoop", &i) == 0 && i != 0) {
1167 #else
1168         sc->flags &= ~HDAC_F_DMA_NOCACHE;
1169 #endif
1170                 /*
1171                  * Try to enable PCIe snoop to avoid messing around with
1172                  * uncacheable DMA attribute. Since PCIe snoop register
1173                  * config is pretty much vendor specific, there are no
1174                  * general solutions on how to enable it, forcing us (even
1175                  * Microsoft) to enable uncacheable or write combined DMA
1176                  * by default.
1177                  *
1178                  * http://msdn2.microsoft.com/en-us/library/ms790324.aspx
1179                  */
1180                 for (i = 0; i < nitems(hdac_pcie_snoop); i++) {
1181                         if (hdac_pcie_snoop[i].vendor != vendor)
1182                                 continue;
1183                         sc->flags &= ~HDAC_F_DMA_NOCACHE;
1184                         if (hdac_pcie_snoop[i].reg == 0x00)
1185                                 break;
1186                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1187                         if ((v & hdac_pcie_snoop[i].enable) ==
1188                             hdac_pcie_snoop[i].enable)
1189                                 break;
1190                         v &= hdac_pcie_snoop[i].mask;
1191                         v |= hdac_pcie_snoop[i].enable;
1192                         pci_write_config(dev, hdac_pcie_snoop[i].reg, v, 1);
1193                         v = pci_read_config(dev, hdac_pcie_snoop[i].reg, 1);
1194                         if ((v & hdac_pcie_snoop[i].enable) !=
1195                             hdac_pcie_snoop[i].enable) {
1196                                 HDA_BOOTVERBOSE(
1197                                         device_printf(dev,
1198                                             "WARNING: Failed to enable PCIe "
1199                                             "snoop!\n");
1200                                 );
1201 #if defined(__i386__) || defined(__amd64__)
1202                                 sc->flags |= HDAC_F_DMA_NOCACHE;
1203 #endif
1204                         }
1205                         break;
1206                 }
1207 #if defined(__i386__) || defined(__amd64__)
1208         }
1209 #endif
1210
1211         HDA_BOOTHVERBOSE(
1212                 device_printf(dev, "DMA Coherency: %s / vendor=0x%04x\n",
1213                     (sc->flags & HDAC_F_DMA_NOCACHE) ?
1214                     "Uncacheable" : "PCIe snoop", vendor);
1215         );
1216
1217         /* Allocate resources */
1218         result = hdac_mem_alloc(sc);
1219         if (result != 0)
1220                 goto hdac_attach_fail;
1221         result = hdac_irq_alloc(sc);
1222         if (result != 0)
1223                 goto hdac_attach_fail;
1224
1225         /* Get Capabilities */
1226         result = hdac_get_capabilities(sc);
1227         if (result != 0)
1228                 goto hdac_attach_fail;
1229
1230         /* Allocate CORB, RIRB, POS and BDLs dma memory */
1231         result = hdac_dma_alloc(sc, &sc->corb_dma,
1232             sc->corb_size * sizeof(uint32_t));
1233         if (result != 0)
1234                 goto hdac_attach_fail;
1235         result = hdac_dma_alloc(sc, &sc->rirb_dma,
1236             sc->rirb_size * sizeof(struct hdac_rirb));
1237         if (result != 0)
1238                 goto hdac_attach_fail;
1239         sc->streams = malloc(sizeof(struct hdac_stream) * sc->num_ss,
1240             M_HDAC, M_ZERO | M_WAITOK);
1241         for (i = 0; i < sc->num_ss; i++) {
1242                 result = hdac_dma_alloc(sc, &sc->streams[i].bdl,
1243                     sizeof(struct hdac_bdle) * HDA_BDL_MAX);
1244                 if (result != 0)
1245                         goto hdac_attach_fail;
1246         }
1247         if (sc->quirks_on & HDAC_QUIRK_DMAPOS) {
1248                 if (hdac_dma_alloc(sc, &sc->pos_dma, (sc->num_ss) * 8) != 0) {
1249                         HDA_BOOTVERBOSE(
1250                                 device_printf(dev, "Failed to "
1251                                     "allocate DMA pos buffer "
1252                                     "(non-fatal)\n");
1253                         );
1254                 } else {
1255                         uint64_t addr = sc->pos_dma.dma_paddr;
1256
1257                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBUBASE, addr >> 32);
1258                         HDAC_WRITE_4(&sc->mem, HDAC_DPIBLBASE,
1259                             (addr & HDAC_DPLBASE_DPLBASE_MASK) |
1260                             HDAC_DPLBASE_DPLBASE_DMAPBE);
1261                 }
1262         }
1263
1264         result = bus_dma_tag_create(
1265             bus_get_dma_tag(sc->dev),           /* parent */
1266             HDA_DMA_ALIGNMENT,                  /* alignment */
1267             0,                                  /* boundary */
1268             (sc->support_64bit) ? BUS_SPACE_MAXADDR :
1269                 BUS_SPACE_MAXADDR_32BIT,        /* lowaddr */
1270             BUS_SPACE_MAXADDR,                  /* highaddr */
1271             NULL,                               /* filtfunc */
1272             NULL,                               /* fistfuncarg */
1273             HDA_BUFSZ_MAX,                      /* maxsize */
1274             1,                                  /* nsegments */
1275             HDA_BUFSZ_MAX,                      /* maxsegsz */
1276             0,                                  /* flags */
1277             NULL,                               /* lockfunc */
1278             NULL,                               /* lockfuncarg */
1279             &sc->chan_dmat);                    /* dmat */
1280         if (result != 0) {
1281                 device_printf(dev, "%s: bus_dma_tag_create failed (%x)\n",
1282                      __func__, result);
1283                 goto hdac_attach_fail;
1284         }
1285
1286         /* Quiesce everything */
1287         HDA_BOOTHVERBOSE(
1288                 device_printf(dev, "Reset controller...\n");
1289         );
1290         hdac_reset(sc, 1);
1291
1292         /* Initialize the CORB and RIRB */
1293         hdac_corb_init(sc);
1294         hdac_rirb_init(sc);
1295
1296         /* Defer remaining of initialization until interrupts are enabled */
1297         sc->intrhook.ich_func = hdac_attach2;
1298         sc->intrhook.ich_arg = (void *)sc;
1299         if (cold == 0 || config_intrhook_establish(&sc->intrhook) != 0) {
1300                 sc->intrhook.ich_func = NULL;
1301                 hdac_attach2((void *)sc);
1302         }
1303
1304         return (0);
1305
1306 hdac_attach_fail:
1307         hdac_irq_free(sc);
1308         for (i = 0; i < sc->num_ss; i++)
1309                 hdac_dma_free(sc, &sc->streams[i].bdl);
1310         free(sc->streams, M_HDAC);
1311         hdac_dma_free(sc, &sc->rirb_dma);
1312         hdac_dma_free(sc, &sc->corb_dma);
1313         hdac_mem_free(sc);
1314         snd_mtxfree(sc->lock);
1315
1316         return (ENXIO);
1317 }
1318
1319 static int
1320 sysctl_hdac_pindump(SYSCTL_HANDLER_ARGS)
1321 {
1322         struct hdac_softc *sc;
1323         device_t *devlist;
1324         device_t dev;
1325         int devcount, i, err, val;
1326
1327         dev = oidp->oid_arg1;
1328         sc = device_get_softc(dev);
1329         if (sc == NULL)
1330                 return (EINVAL);
1331         val = 0;
1332         err = sysctl_handle_int(oidp, &val, 0, req);
1333         if (err != 0 || req->newptr == NULL || val == 0)
1334                 return (err);
1335
1336         /* XXX: Temporary. For debugging. */
1337         if (val == 100) {
1338                 hdac_suspend(dev);
1339                 return (0);
1340         } else if (val == 101) {
1341                 hdac_resume(dev);
1342                 return (0);
1343         }
1344
1345         if ((err = device_get_children(dev, &devlist, &devcount)) != 0)
1346                 return (err);
1347         hdac_lock(sc);
1348         for (i = 0; i < devcount; i++)
1349                 HDAC_PINDUMP(devlist[i]);
1350         hdac_unlock(sc);
1351         free(devlist, M_TEMP);
1352         return (0);
1353 }
1354
1355 static int
1356 hdac_mdata_rate(uint16_t fmt)
1357 {
1358         static const int mbits[8] = { 8, 16, 32, 32, 32, 32, 32, 32 };
1359         int rate, bits;
1360
1361         if (fmt & (1 << 14))
1362                 rate = 44100;
1363         else
1364                 rate = 48000;
1365         rate *= ((fmt >> 11) & 0x07) + 1;
1366         rate /= ((fmt >> 8) & 0x07) + 1;
1367         bits = mbits[(fmt >> 4) & 0x03];
1368         bits *= (fmt & 0x0f) + 1;
1369         return (rate * bits);
1370 }
1371
1372 static int
1373 hdac_bdata_rate(uint16_t fmt, int output)
1374 {
1375         static const int bbits[8] = { 8, 16, 20, 24, 32, 32, 32, 32 };
1376         int rate, bits;
1377
1378         rate = 48000;
1379         rate *= ((fmt >> 11) & 0x07) + 1;
1380         bits = bbits[(fmt >> 4) & 0x03];
1381         bits *= (fmt & 0x0f) + 1;
1382         if (!output)
1383                 bits = ((bits + 7) & ~0x07) + 10;
1384         return (rate * bits);
1385 }
1386
1387 static void
1388 hdac_poll_reinit(struct hdac_softc *sc)
1389 {
1390         int i, pollticks, min = 1000000;
1391         struct hdac_stream *s;
1392
1393         if (sc->polling == 0)
1394                 return;
1395         if (sc->unsol_registered > 0)
1396                 min = hz / 2;
1397         for (i = 0; i < sc->num_ss; i++) {
1398                 s = &sc->streams[i];
1399                 if (s->running == 0)
1400                         continue;
1401                 pollticks = ((uint64_t)hz * s->blksz) /
1402                     (hdac_mdata_rate(s->format) / 8);
1403                 pollticks >>= 1;
1404                 if (pollticks > hz)
1405                         pollticks = hz;
1406                 if (pollticks < 1) {
1407                         HDA_BOOTVERBOSE(
1408                                 device_printf(sc->dev,
1409                                     "poll interval < 1 tick !\n");
1410                         );
1411                         pollticks = 1;
1412                 }
1413                 if (min > pollticks)
1414                         min = pollticks;
1415         }
1416         HDA_BOOTVERBOSE(
1417                 device_printf(sc->dev,
1418                     "poll interval %d -> %d ticks\n",
1419                     sc->poll_ival, min);
1420         );
1421         sc->poll_ival = min;
1422         if (min == 1000000)
1423                 callout_stop(&sc->poll_callout);
1424         else
1425                 callout_reset(&sc->poll_callout, 1, hdac_poll_callback, sc);
1426 }
1427
1428 static int
1429 sysctl_hdac_polling(SYSCTL_HANDLER_ARGS)
1430 {
1431         struct hdac_softc *sc;
1432         device_t dev;
1433         uint32_t ctl;
1434         int err, val;
1435
1436         dev = oidp->oid_arg1;
1437         sc = device_get_softc(dev);
1438         if (sc == NULL)
1439                 return (EINVAL);
1440         hdac_lock(sc);
1441         val = sc->polling;
1442         hdac_unlock(sc);
1443         err = sysctl_handle_int(oidp, &val, 0, req);
1444
1445         if (err != 0 || req->newptr == NULL)
1446                 return (err);
1447         if (val < 0 || val > 1)
1448                 return (EINVAL);
1449
1450         hdac_lock(sc);
1451         if (val != sc->polling) {
1452                 if (val == 0) {
1453                         callout_stop(&sc->poll_callout);
1454                         hdac_unlock(sc);
1455                         callout_drain(&sc->poll_callout);
1456                         hdac_lock(sc);
1457                         sc->polling = 0;
1458                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1459                         ctl |= HDAC_INTCTL_GIE;
1460                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1461                 } else {
1462                         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1463                         ctl &= ~HDAC_INTCTL_GIE;
1464                         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1465                         sc->polling = 1;
1466                         hdac_poll_reinit(sc);
1467                 }
1468         }
1469         hdac_unlock(sc);
1470
1471         return (err);
1472 }
1473
1474 static void
1475 hdac_attach2(void *arg)
1476 {
1477         struct hdac_softc *sc;
1478         device_t child;
1479         uint32_t vendorid, revisionid;
1480         int i;
1481         uint16_t statests;
1482
1483         sc = (struct hdac_softc *)arg;
1484
1485         hdac_lock(sc);
1486
1487         /* Remove ourselves from the config hooks */
1488         if (sc->intrhook.ich_func != NULL) {
1489                 config_intrhook_disestablish(&sc->intrhook);
1490                 sc->intrhook.ich_func = NULL;
1491         }
1492
1493         HDA_BOOTHVERBOSE(
1494                 device_printf(sc->dev, "Starting CORB Engine...\n");
1495         );
1496         hdac_corb_start(sc);
1497         HDA_BOOTHVERBOSE(
1498                 device_printf(sc->dev, "Starting RIRB Engine...\n");
1499         );
1500         hdac_rirb_start(sc);
1501         HDA_BOOTHVERBOSE(
1502                 device_printf(sc->dev,
1503                     "Enabling controller interrupt...\n");
1504         );
1505         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1506             HDAC_GCTL_UNSOL);
1507         if (sc->polling == 0) {
1508                 HDAC_WRITE_4(&sc->mem, HDAC_INTCTL,
1509                     HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1510         }
1511         DELAY(1000);
1512
1513         HDA_BOOTHVERBOSE(
1514                 device_printf(sc->dev, "Scanning HDA codecs ...\n");
1515         );
1516         statests = HDAC_READ_2(&sc->mem, HDAC_STATESTS);
1517         hdac_unlock(sc);
1518         for (i = 0; i < HDAC_CODEC_MAX; i++) {
1519                 if (HDAC_STATESTS_SDIWAKE(statests, i)) {
1520                         HDA_BOOTHVERBOSE(
1521                                 device_printf(sc->dev,
1522                                     "Found CODEC at address %d\n", i);
1523                         );
1524                         hdac_lock(sc);
1525                         vendorid = hdac_send_command(sc, i,
1526                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_VENDOR_ID));
1527                         revisionid = hdac_send_command(sc, i,
1528                             HDA_CMD_GET_PARAMETER(0, 0x0, HDA_PARAM_REVISION_ID));
1529                         hdac_unlock(sc);
1530                         if (vendorid == HDA_INVALID &&
1531                             revisionid == HDA_INVALID) {
1532                                 device_printf(sc->dev,
1533                                     "CODEC is not responding!\n");
1534                                 continue;
1535                         }
1536                         sc->codecs[i].vendor_id =
1537                             HDA_PARAM_VENDOR_ID_VENDOR_ID(vendorid);
1538                         sc->codecs[i].device_id =
1539                             HDA_PARAM_VENDOR_ID_DEVICE_ID(vendorid);
1540                         sc->codecs[i].revision_id =
1541                             HDA_PARAM_REVISION_ID_REVISION_ID(revisionid);
1542                         sc->codecs[i].stepping_id =
1543                             HDA_PARAM_REVISION_ID_STEPPING_ID(revisionid);
1544                         child = device_add_child(sc->dev, "hdacc", -1);
1545                         if (child == NULL) {
1546                                 device_printf(sc->dev,
1547                                     "Failed to add CODEC device\n");
1548                                 continue;
1549                         }
1550                         device_set_ivars(child, (void *)(intptr_t)i);
1551                         sc->codecs[i].dev = child;
1552                 }
1553         }
1554         bus_generic_attach(sc->dev);
1555
1556         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1557             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1558             "pindump", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1559             sysctl_hdac_pindump, "I", "Dump pin states/data");
1560         SYSCTL_ADD_PROC(device_get_sysctl_ctx(sc->dev),
1561             SYSCTL_CHILDREN(device_get_sysctl_tree(sc->dev)), OID_AUTO,
1562             "polling", CTLTYPE_INT | CTLFLAG_RW, sc->dev, sizeof(sc->dev),
1563             sysctl_hdac_polling, "I", "Enable polling mode");
1564 }
1565
1566 /****************************************************************************
1567  * int hdac_suspend(device_t)
1568  *
1569  * Suspend and power down HDA bus and codecs.
1570  ****************************************************************************/
1571 static int
1572 hdac_suspend(device_t dev)
1573 {
1574         struct hdac_softc *sc = device_get_softc(dev);
1575
1576         HDA_BOOTHVERBOSE(
1577                 device_printf(dev, "Suspend...\n");
1578         );
1579         bus_generic_suspend(dev);
1580
1581         hdac_lock(sc);
1582         HDA_BOOTHVERBOSE(
1583                 device_printf(dev, "Reset controller...\n");
1584         );
1585         callout_stop(&sc->poll_callout);
1586         hdac_reset(sc, 0);
1587         hdac_unlock(sc);
1588         callout_drain(&sc->poll_callout);
1589         taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1590         HDA_BOOTHVERBOSE(
1591                 device_printf(dev, "Suspend done\n");
1592         );
1593         return (0);
1594 }
1595
1596 /****************************************************************************
1597  * int hdac_resume(device_t)
1598  *
1599  * Powerup and restore HDA bus and codecs state.
1600  ****************************************************************************/
1601 static int
1602 hdac_resume(device_t dev)
1603 {
1604         struct hdac_softc *sc = device_get_softc(dev);
1605         int error;
1606
1607         HDA_BOOTHVERBOSE(
1608                 device_printf(dev, "Resume...\n");
1609         );
1610         hdac_lock(sc);
1611
1612         /* Quiesce everything */
1613         HDA_BOOTHVERBOSE(
1614                 device_printf(dev, "Reset controller...\n");
1615         );
1616         hdac_reset(sc, 1);
1617
1618         /* Initialize the CORB and RIRB */
1619         hdac_corb_init(sc);
1620         hdac_rirb_init(sc);
1621
1622         HDA_BOOTHVERBOSE(
1623                 device_printf(dev, "Starting CORB Engine...\n");
1624         );
1625         hdac_corb_start(sc);
1626         HDA_BOOTHVERBOSE(
1627                 device_printf(dev, "Starting RIRB Engine...\n");
1628         );
1629         hdac_rirb_start(sc);
1630         HDA_BOOTHVERBOSE(
1631                 device_printf(dev, "Enabling controller interrupt...\n");
1632         );
1633         HDAC_WRITE_4(&sc->mem, HDAC_GCTL, HDAC_READ_4(&sc->mem, HDAC_GCTL) |
1634             HDAC_GCTL_UNSOL);
1635         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, HDAC_INTCTL_CIE | HDAC_INTCTL_GIE);
1636         DELAY(1000);
1637         hdac_poll_reinit(sc);
1638         hdac_unlock(sc);
1639
1640         error = bus_generic_resume(dev);
1641         HDA_BOOTHVERBOSE(
1642                 device_printf(dev, "Resume done\n");
1643         );
1644         return (error);
1645 }
1646
1647 /****************************************************************************
1648  * int hdac_detach(device_t)
1649  *
1650  * Detach and free up resources utilized by the hdac device.
1651  ****************************************************************************/
1652 static int
1653 hdac_detach(device_t dev)
1654 {
1655         struct hdac_softc *sc = device_get_softc(dev);
1656         device_t *devlist;
1657         int cad, i, devcount, error;
1658
1659         if ((error = device_get_children(dev, &devlist, &devcount)) != 0)
1660                 return (error);
1661         for (i = 0; i < devcount; i++) {
1662                 cad = (intptr_t)device_get_ivars(devlist[i]);
1663                 if ((error = device_delete_child(dev, devlist[i])) != 0) {
1664                         free(devlist, M_TEMP);
1665                         return (error);
1666                 }
1667                 sc->codecs[cad].dev = NULL;
1668         }
1669         free(devlist, M_TEMP);
1670
1671         hdac_lock(sc);
1672         hdac_reset(sc, 0);
1673         hdac_unlock(sc);
1674         taskqueue_drain(taskqueue_thread, &sc->unsolq_task);
1675         hdac_irq_free(sc);
1676
1677         for (i = 0; i < sc->num_ss; i++)
1678                 hdac_dma_free(sc, &sc->streams[i].bdl);
1679         free(sc->streams, M_HDAC);
1680         hdac_dma_free(sc, &sc->pos_dma);
1681         hdac_dma_free(sc, &sc->rirb_dma);
1682         hdac_dma_free(sc, &sc->corb_dma);
1683         if (sc->chan_dmat != NULL) {
1684                 bus_dma_tag_destroy(sc->chan_dmat);
1685                 sc->chan_dmat = NULL;
1686         }
1687         hdac_mem_free(sc);
1688         snd_mtxfree(sc->lock);
1689         return (0);
1690 }
1691
1692 static bus_dma_tag_t
1693 hdac_get_dma_tag(device_t dev, device_t child)
1694 {
1695         struct hdac_softc *sc = device_get_softc(dev);
1696
1697         return (sc->chan_dmat);
1698 }
1699
1700 static int
1701 hdac_print_child(device_t dev, device_t child)
1702 {
1703         int retval;
1704
1705         retval = bus_print_child_header(dev, child);
1706         retval += printf(" at cad %d",
1707             (int)(intptr_t)device_get_ivars(child));
1708         retval += bus_print_child_footer(dev, child);
1709
1710         return (retval);
1711 }
1712
1713 static int
1714 hdac_child_location_str(device_t dev, device_t child, char *buf,
1715     size_t buflen)
1716 {
1717
1718         snprintf(buf, buflen, "cad=%d",
1719             (int)(intptr_t)device_get_ivars(child));
1720         return (0);
1721 }
1722
1723 static int
1724 hdac_child_pnpinfo_str_method(device_t dev, device_t child, char *buf,
1725     size_t buflen)
1726 {
1727         struct hdac_softc *sc = device_get_softc(dev);
1728         nid_t cad = (uintptr_t)device_get_ivars(child);
1729
1730         snprintf(buf, buflen, "vendor=0x%04x device=0x%04x revision=0x%02x "
1731             "stepping=0x%02x",
1732             sc->codecs[cad].vendor_id, sc->codecs[cad].device_id,
1733             sc->codecs[cad].revision_id, sc->codecs[cad].stepping_id);
1734         return (0);
1735 }
1736
1737 static int
1738 hdac_read_ivar(device_t dev, device_t child, int which, uintptr_t *result)
1739 {
1740         struct hdac_softc *sc = device_get_softc(dev);
1741         nid_t cad = (uintptr_t)device_get_ivars(child);
1742
1743         switch (which) {
1744         case HDA_IVAR_CODEC_ID:
1745                 *result = cad;
1746                 break;
1747         case HDA_IVAR_VENDOR_ID:
1748                 *result = sc->codecs[cad].vendor_id;
1749                 break;
1750         case HDA_IVAR_DEVICE_ID:
1751                 *result = sc->codecs[cad].device_id;
1752                 break;
1753         case HDA_IVAR_REVISION_ID:
1754                 *result = sc->codecs[cad].revision_id;
1755                 break;
1756         case HDA_IVAR_STEPPING_ID:
1757                 *result = sc->codecs[cad].stepping_id;
1758                 break;
1759         case HDA_IVAR_SUBVENDOR_ID:
1760                 *result = pci_get_subvendor(dev);
1761                 break;
1762         case HDA_IVAR_SUBDEVICE_ID:
1763                 *result = pci_get_subdevice(dev);
1764                 break;
1765         case HDA_IVAR_DMA_NOCACHE:
1766                 *result = (sc->flags & HDAC_F_DMA_NOCACHE) != 0;
1767                 break;
1768         default:
1769                 return (ENOENT);
1770         }
1771         return (0);
1772 }
1773
1774 static struct mtx *
1775 hdac_get_mtx(device_t dev, device_t child)
1776 {
1777         struct hdac_softc *sc = device_get_softc(dev);
1778
1779         return (sc->lock);
1780 }
1781
1782 static uint32_t
1783 hdac_codec_command(device_t dev, device_t child, uint32_t verb)
1784 {
1785
1786         return (hdac_send_command(device_get_softc(dev),
1787             (intptr_t)device_get_ivars(child), verb));
1788 }
1789
1790 static int
1791 hdac_find_stream(struct hdac_softc *sc, int dir, int stream)
1792 {
1793         int i, ss;
1794
1795         ss = -1;
1796         /* Allocate ISS/BSS first. */
1797         if (dir == 0) {
1798                 for (i = 0; i < sc->num_iss; i++) {
1799                         if (sc->streams[i].stream == stream) {
1800                                 ss = i;
1801                                 break;
1802                         }
1803                 }
1804         } else {
1805                 for (i = 0; i < sc->num_oss; i++) {
1806                         if (sc->streams[i + sc->num_iss].stream == stream) {
1807                                 ss = i + sc->num_iss;
1808                                 break;
1809                         }
1810                 }
1811         }
1812         /* Fallback to BSS. */
1813         if (ss == -1) {
1814                 for (i = 0; i < sc->num_bss; i++) {
1815                         if (sc->streams[i + sc->num_iss + sc->num_oss].stream
1816                             == stream) {
1817                                 ss = i + sc->num_iss + sc->num_oss;
1818                                 break;
1819                         }
1820                 }
1821         }
1822         return (ss);
1823 }
1824
1825 static int
1826 hdac_stream_alloc(device_t dev, device_t child, int dir, int format, int stripe,
1827     uint32_t **dmapos)
1828 {
1829         struct hdac_softc *sc = device_get_softc(dev);
1830         nid_t cad = (uintptr_t)device_get_ivars(child);
1831         int stream, ss, bw, maxbw, prevbw;
1832
1833         /* Look for empty stream. */
1834         ss = hdac_find_stream(sc, dir, 0);
1835
1836         /* Return if found nothing. */
1837         if (ss < 0)
1838                 return (0);
1839
1840         /* Check bus bandwidth. */
1841         bw = hdac_bdata_rate(format, dir);
1842         if (dir == 1) {
1843                 bw *= 1 << (sc->num_sdo - stripe);
1844                 prevbw = sc->sdo_bw_used;
1845                 maxbw = 48000 * 960 * (1 << sc->num_sdo);
1846         } else {
1847                 prevbw = sc->codecs[cad].sdi_bw_used;
1848                 maxbw = 48000 * 464;
1849         }
1850         HDA_BOOTHVERBOSE(
1851                 device_printf(dev, "%dKbps of %dKbps bandwidth used%s\n",
1852                     (bw + prevbw) / 1000, maxbw / 1000,
1853                     bw + prevbw > maxbw ? " -- OVERFLOW!" : "");
1854         );
1855         if (bw + prevbw > maxbw)
1856                 return (0);
1857         if (dir == 1)
1858                 sc->sdo_bw_used += bw;
1859         else
1860                 sc->codecs[cad].sdi_bw_used += bw;
1861
1862         /* Allocate stream number */
1863         if (ss >= sc->num_iss + sc->num_oss)
1864                 stream = 15 - (ss - sc->num_iss + sc->num_oss);
1865         else if (ss >= sc->num_iss)
1866                 stream = ss - sc->num_iss + 1;
1867         else
1868                 stream = ss + 1;
1869
1870         sc->streams[ss].dev = child;
1871         sc->streams[ss].dir = dir;
1872         sc->streams[ss].stream = stream;
1873         sc->streams[ss].bw = bw;
1874         sc->streams[ss].format = format;
1875         sc->streams[ss].stripe = stripe;
1876         if (dmapos != NULL) {
1877                 if (sc->pos_dma.dma_vaddr != NULL)
1878                         *dmapos = (uint32_t *)(sc->pos_dma.dma_vaddr + ss * 8);
1879                 else
1880                         *dmapos = NULL;
1881         }
1882         return (stream);
1883 }
1884
1885 static void
1886 hdac_stream_free(device_t dev, device_t child, int dir, int stream)
1887 {
1888         struct hdac_softc *sc = device_get_softc(dev);
1889         nid_t cad = (uintptr_t)device_get_ivars(child);
1890         int ss;
1891
1892         ss = hdac_find_stream(sc, dir, stream);
1893         KASSERT(ss >= 0,
1894             ("Free for not allocated stream (%d/%d)\n", dir, stream));
1895         if (dir == 1)
1896                 sc->sdo_bw_used -= sc->streams[ss].bw;
1897         else
1898                 sc->codecs[cad].sdi_bw_used -= sc->streams[ss].bw;
1899         sc->streams[ss].stream = 0;
1900         sc->streams[ss].dev = NULL;
1901 }
1902
1903 static int
1904 hdac_stream_start(device_t dev, device_t child,
1905     int dir, int stream, bus_addr_t buf, int blksz, int blkcnt)
1906 {
1907         struct hdac_softc *sc = device_get_softc(dev);
1908         struct hdac_bdle *bdle;
1909         uint64_t addr;
1910         int i, ss, off;
1911         uint32_t ctl;
1912
1913         ss = hdac_find_stream(sc, dir, stream);
1914         KASSERT(ss >= 0,
1915             ("Start for not allocated stream (%d/%d)\n", dir, stream));
1916
1917         addr = (uint64_t)buf;
1918         bdle = (struct hdac_bdle *)sc->streams[ss].bdl.dma_vaddr;
1919         for (i = 0; i < blkcnt; i++, bdle++) {
1920                 bdle->addrl = (uint32_t)addr;
1921                 bdle->addrh = (uint32_t)(addr >> 32);
1922                 bdle->len = blksz;
1923                 bdle->ioc = 1;
1924                 addr += blksz;
1925         }
1926
1927         off = ss << 5;
1928         HDAC_WRITE_4(&sc->mem, off + HDAC_SDCBL, blksz * blkcnt);
1929         HDAC_WRITE_2(&sc->mem, off + HDAC_SDLVI, blkcnt - 1);
1930         addr = sc->streams[ss].bdl.dma_paddr;
1931         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPL, (uint32_t)addr);
1932         HDAC_WRITE_4(&sc->mem, off + HDAC_SDBDPU, (uint32_t)(addr >> 32));
1933
1934         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL2);
1935         if (dir)
1936                 ctl |= HDAC_SDCTL2_DIR;
1937         else
1938                 ctl &= ~HDAC_SDCTL2_DIR;
1939         ctl &= ~HDAC_SDCTL2_STRM_MASK;
1940         ctl |= stream << HDAC_SDCTL2_STRM_SHIFT;
1941         ctl &= ~HDAC_SDCTL2_STRIPE_MASK;
1942         ctl |= sc->streams[ss].stripe << HDAC_SDCTL2_STRIPE_SHIFT;
1943         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL2, ctl);
1944
1945         HDAC_WRITE_2(&sc->mem, off + HDAC_SDFMT, sc->streams[ss].format);
1946
1947         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1948         ctl |= 1 << ss;
1949         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1950
1951         HDAC_WRITE_1(&sc->mem, off + HDAC_SDSTS,
1952             HDAC_SDSTS_DESE | HDAC_SDSTS_FIFOE | HDAC_SDSTS_BCIS);
1953         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1954         ctl |= HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1955             HDAC_SDCTL_RUN;
1956         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1957
1958         sc->streams[ss].blksz = blksz;
1959         sc->streams[ss].running = 1;
1960         hdac_poll_reinit(sc);
1961         return (0);
1962 }
1963
1964 static void
1965 hdac_stream_stop(device_t dev, device_t child, int dir, int stream)
1966 {
1967         struct hdac_softc *sc = device_get_softc(dev);
1968         int ss, off;
1969         uint32_t ctl;
1970
1971         ss = hdac_find_stream(sc, dir, stream);
1972         KASSERT(ss >= 0,
1973             ("Stop for not allocated stream (%d/%d)\n", dir, stream));
1974
1975         off = ss << 5;
1976         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
1977         ctl &= ~(HDAC_SDCTL_IOCE | HDAC_SDCTL_FEIE | HDAC_SDCTL_DEIE |
1978             HDAC_SDCTL_RUN);
1979         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
1980
1981         ctl = HDAC_READ_4(&sc->mem, HDAC_INTCTL);
1982         ctl &= ~(1 << ss);
1983         HDAC_WRITE_4(&sc->mem, HDAC_INTCTL, ctl);
1984
1985         sc->streams[ss].running = 0;
1986         hdac_poll_reinit(sc);
1987 }
1988
1989 static void
1990 hdac_stream_reset(device_t dev, device_t child, int dir, int stream)
1991 {
1992         struct hdac_softc *sc = device_get_softc(dev);
1993         int timeout = 1000;
1994         int to = timeout;
1995         int ss, off;
1996         uint32_t ctl;
1997
1998         ss = hdac_find_stream(sc, dir, stream);
1999         KASSERT(ss >= 0,
2000             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2001
2002         off = ss << 5;
2003         ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2004         ctl |= HDAC_SDCTL_SRST;
2005         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2006         do {
2007                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2008                 if (ctl & HDAC_SDCTL_SRST)
2009                         break;
2010                 DELAY(10);
2011         } while (--to);
2012         if (!(ctl & HDAC_SDCTL_SRST))
2013                 device_printf(dev, "Reset setting timeout\n");
2014         ctl &= ~HDAC_SDCTL_SRST;
2015         HDAC_WRITE_1(&sc->mem, off + HDAC_SDCTL0, ctl);
2016         to = timeout;
2017         do {
2018                 ctl = HDAC_READ_1(&sc->mem, off + HDAC_SDCTL0);
2019                 if (!(ctl & HDAC_SDCTL_SRST))
2020                         break;
2021                 DELAY(10);
2022         } while (--to);
2023         if (ctl & HDAC_SDCTL_SRST)
2024                 device_printf(dev, "Reset timeout!\n");
2025 }
2026
2027 static uint32_t
2028 hdac_stream_getptr(device_t dev, device_t child, int dir, int stream)
2029 {
2030         struct hdac_softc *sc = device_get_softc(dev);
2031         int ss, off;
2032
2033         ss = hdac_find_stream(sc, dir, stream);
2034         KASSERT(ss >= 0,
2035             ("Reset for not allocated stream (%d/%d)\n", dir, stream));
2036
2037         off = ss << 5;
2038         return (HDAC_READ_4(&sc->mem, off + HDAC_SDLPIB));
2039 }
2040
2041 static int
2042 hdac_unsol_alloc(device_t dev, device_t child, int tag)
2043 {
2044         struct hdac_softc *sc = device_get_softc(dev);
2045
2046         sc->unsol_registered++;
2047         hdac_poll_reinit(sc);
2048         return (tag);
2049 }
2050
2051 static void
2052 hdac_unsol_free(device_t dev, device_t child, int tag)
2053 {
2054         struct hdac_softc *sc = device_get_softc(dev);
2055
2056         sc->unsol_registered--;
2057         hdac_poll_reinit(sc);
2058 }
2059
2060 static device_method_t hdac_methods[] = {
2061         /* device interface */
2062         DEVMETHOD(device_probe,         hdac_probe),
2063         DEVMETHOD(device_attach,        hdac_attach),
2064         DEVMETHOD(device_detach,        hdac_detach),
2065         DEVMETHOD(device_suspend,       hdac_suspend),
2066         DEVMETHOD(device_resume,        hdac_resume),
2067         /* Bus interface */
2068         DEVMETHOD(bus_get_dma_tag,      hdac_get_dma_tag),
2069         DEVMETHOD(bus_print_child,      hdac_print_child),
2070         DEVMETHOD(bus_child_location_str, hdac_child_location_str),
2071         DEVMETHOD(bus_child_pnpinfo_str, hdac_child_pnpinfo_str_method),
2072         DEVMETHOD(bus_read_ivar,        hdac_read_ivar),
2073         DEVMETHOD(hdac_get_mtx,         hdac_get_mtx),
2074         DEVMETHOD(hdac_codec_command,   hdac_codec_command),
2075         DEVMETHOD(hdac_stream_alloc,    hdac_stream_alloc),
2076         DEVMETHOD(hdac_stream_free,     hdac_stream_free),
2077         DEVMETHOD(hdac_stream_start,    hdac_stream_start),
2078         DEVMETHOD(hdac_stream_stop,     hdac_stream_stop),
2079         DEVMETHOD(hdac_stream_reset,    hdac_stream_reset),
2080         DEVMETHOD(hdac_stream_getptr,   hdac_stream_getptr),
2081         DEVMETHOD(hdac_unsol_alloc,     hdac_unsol_alloc),
2082         DEVMETHOD(hdac_unsol_free,      hdac_unsol_free),
2083         DEVMETHOD_END
2084 };
2085
2086 static driver_t hdac_driver = {
2087         "hdac",
2088         hdac_methods,
2089         sizeof(struct hdac_softc),
2090 };
2091
2092 static devclass_t hdac_devclass;
2093
2094 DRIVER_MODULE(snd_hda, pci, hdac_driver, hdac_devclass, NULL, NULL);