2 * Copyright (c) 2003 Marcel Moolenaar
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include "opt_platform.h"
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
36 #include <sys/kernel.h>
37 #include <sys/sysctl.h>
38 #include <machine/bus.h>
41 #include <dev/fdt/fdt_common.h>
42 #include <dev/ofw/ofw_bus.h>
43 #include <dev/ofw/ofw_bus_subr.h>
46 #include <dev/uart/uart.h>
47 #include <dev/uart/uart_cpu.h>
49 #include <dev/uart/uart_cpu_fdt.h>
51 #include <dev/uart/uart_bus.h>
52 #include <dev/uart/uart_dev_ns8250.h>
53 #include <dev/uart/uart_ppstypes.h>
55 #include <dev/ic/ns16550.h>
59 #define DEFAULT_RCLK 1843200
61 static int broken_txfifo = 0;
62 SYSCTL_INT(_hw, OID_AUTO, broken_txfifo, CTLFLAG_RW | CTLFLAG_TUN,
63 &broken_txfifo, 0, "UART FIFO has QEMU emulation bug");
64 TUNABLE_INT("hw.broken_txfifo", &broken_txfifo);
67 * Clear pending interrupts. THRE is cleared by reading IIR. Data
68 * that may have been received gets lost here.
71 ns8250_clrint(struct uart_bas *bas)
75 iir = uart_getreg(bas, REG_IIR);
76 while ((iir & IIR_NOPEND) == 0) {
79 lsr = uart_getreg(bas, REG_LSR);
80 if (lsr & (LSR_BI|LSR_FE|LSR_PE))
81 (void)uart_getreg(bas, REG_DATA);
82 } else if (iir == IIR_RXRDY || iir == IIR_RXTOUT)
83 (void)uart_getreg(bas, REG_DATA);
84 else if (iir == IIR_MLSC)
85 (void)uart_getreg(bas, REG_MSR);
87 iir = uart_getreg(bas, REG_IIR);
92 ns8250_delay(struct uart_bas *bas)
97 lcr = uart_getreg(bas, REG_LCR);
98 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
100 divisor = uart_getreg(bas, REG_DLL) | (uart_getreg(bas, REG_DLH) << 8);
102 uart_setreg(bas, REG_LCR, lcr);
105 /* 1/10th the time to transmit 1 character (estimate). */
107 return (16000000 * divisor / bas->rclk);
108 return (16000 * divisor / (bas->rclk / 1000));
112 ns8250_divisor(int rclk, int baudrate)
114 int actual_baud, divisor;
120 divisor = (rclk / (baudrate << 3) + 1) >> 1;
121 if (divisor == 0 || divisor >= 65536)
123 actual_baud = rclk / (divisor << 4);
125 /* 10 times error in percent: */
126 error = ((actual_baud - baudrate) * 2000 / baudrate + 1) >> 1;
128 /* 3.0% maximum error tolerance: */
129 if (error < -30 || error > 30)
136 ns8250_drain(struct uart_bas *bas, int what)
140 delay = ns8250_delay(bas);
142 if (what & UART_DRAIN_TRANSMITTER) {
144 * Pick an arbitrary high limit to avoid getting stuck in
145 * an infinite loop when the hardware is broken. Make the
146 * limit high enough to handle large FIFOs.
149 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
152 /* printf("ns8250: transmitter appears stuck... "); */
157 if (what & UART_DRAIN_RECEIVER) {
159 * Pick an arbitrary high limit to avoid getting stuck in
160 * an infinite loop when the hardware is broken. Make the
161 * limit high enough to handle large FIFOs and integrated
162 * UARTs. The HP rx2600 for example has 3 UARTs on the
163 * management board that tend to get a lot of data send
164 * to it when the UART is first activated.
167 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) && --limit) {
168 (void)uart_getreg(bas, REG_DATA);
173 /* printf("ns8250: receiver appears broken... "); */
182 * We can only flush UARTs with FIFOs. UARTs without FIFOs should be
183 * drained. WARNING: this function clobbers the FIFO setting!
186 ns8250_flush(struct uart_bas *bas, int what)
194 if (what & UART_FLUSH_TRANSMITTER)
196 if (what & UART_FLUSH_RECEIVER)
198 uart_setreg(bas, REG_FCR, fcr);
203 ns8250_param(struct uart_bas *bas, int baudrate, int databits, int stopbits,
212 else if (databits == 7)
214 else if (databits == 6)
224 divisor = ns8250_divisor(bas->rclk, baudrate);
227 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
229 uart_setreg(bas, REG_DLL, divisor & 0xff);
230 uart_setreg(bas, REG_DLH, (divisor >> 8) & 0xff);
234 /* Set LCR and clear DLAB. */
235 uart_setreg(bas, REG_LCR, lcr);
241 * Low-level UART interface.
243 static int ns8250_probe(struct uart_bas *bas);
244 static void ns8250_init(struct uart_bas *bas, int, int, int, int);
245 static void ns8250_term(struct uart_bas *bas);
246 static void ns8250_putc(struct uart_bas *bas, int);
247 static int ns8250_rxready(struct uart_bas *bas);
248 static int ns8250_getc(struct uart_bas *bas, struct mtx *);
250 struct uart_ops uart_ns8250_ops = {
251 .probe = ns8250_probe,
255 .rxready = ns8250_rxready,
260 ns8250_probe(struct uart_bas *bas)
265 uart_setreg(bas, REG_FCR, FCR_UART_ON);
268 /* Check known 0 bits that don't depend on DLAB. */
269 val = uart_getreg(bas, REG_IIR);
273 * Bit 6 of the MCR (= 0x40) appears to be 1 for the Sun1699
274 * chip, but otherwise doesn't seem to have a function. In
275 * other words, uart(4) works regardless. Ignore that bit so
276 * the probe succeeds.
278 val = uart_getreg(bas, REG_MCR);
286 ns8250_init(struct uart_bas *bas, int baudrate, int databits, int stopbits,
292 bas->rclk = DEFAULT_RCLK;
293 ns8250_param(bas, baudrate, databits, stopbits, parity);
295 /* Disable all interrupt sources. */
297 * We use 0xe0 instead of 0xf0 as the mask because the XScale PXA
298 * UARTs split the receive time-out interrupt bit out separately as
299 * 0x10. This gets handled by ier_mask and ier_rxbits below.
301 ier = uart_getreg(bas, REG_IER) & 0xe0;
302 uart_setreg(bas, REG_IER, ier);
305 /* Disable the FIFO (if present). */
310 uart_setreg(bas, REG_FCR, val);
314 uart_setreg(bas, REG_MCR, MCR_IE | MCR_RTS | MCR_DTR);
321 ns8250_term(struct uart_bas *bas)
324 /* Clear RTS & DTR. */
325 uart_setreg(bas, REG_MCR, MCR_IE);
330 ns8250_putc(struct uart_bas *bas, int c)
335 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0 && --limit)
337 uart_setreg(bas, REG_DATA, c);
340 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0 && --limit)
345 ns8250_rxready(struct uart_bas *bas)
348 return ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) != 0 ? 1 : 0);
352 ns8250_getc(struct uart_bas *bas, struct mtx *hwmtx)
358 while ((uart_getreg(bas, REG_LSR) & LSR_RXRDY) == 0) {
364 c = uart_getreg(bas, REG_DATA);
371 static kobj_method_t ns8250_methods[] = {
372 KOBJMETHOD(uart_attach, ns8250_bus_attach),
373 KOBJMETHOD(uart_detach, ns8250_bus_detach),
374 KOBJMETHOD(uart_flush, ns8250_bus_flush),
375 KOBJMETHOD(uart_getsig, ns8250_bus_getsig),
376 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl),
377 KOBJMETHOD(uart_ipend, ns8250_bus_ipend),
378 KOBJMETHOD(uart_param, ns8250_bus_param),
379 KOBJMETHOD(uart_probe, ns8250_bus_probe),
380 KOBJMETHOD(uart_receive, ns8250_bus_receive),
381 KOBJMETHOD(uart_setsig, ns8250_bus_setsig),
382 KOBJMETHOD(uart_transmit, ns8250_bus_transmit),
383 KOBJMETHOD(uart_grab, ns8250_bus_grab),
384 KOBJMETHOD(uart_ungrab, ns8250_bus_ungrab),
388 struct uart_class uart_ns8250_class = {
391 sizeof(struct ns8250_softc),
392 .uc_ops = &uart_ns8250_ops,
394 .uc_rclk = DEFAULT_RCLK
398 static struct ofw_compat_data compat_data[] = {
399 {"ns16550", (uintptr_t)&uart_ns8250_class},
400 {NULL, (uintptr_t)NULL},
402 UART_FDT_CLASS_AND_DEVICE(compat_data);
405 /* Use token-pasting to form SER_ and MSR_ named constants. */
406 #define SER(sig) SER_##sig
407 #define SERD(sig) SER_D##sig
408 #define MSR(sig) MSR_##sig
409 #define MSRD(sig) MSR_D##sig
412 * Detect signal changes using software delta detection. The previous state of
413 * the signals is in 'var' the new hardware state is in 'msr', and 'sig' is the
414 * short name (DCD, CTS, etc) of the signal bit being processed; 'var' gets the
415 * new state of both the signal and the delta bits.
417 #define SIGCHGSW(var, msr, sig) \
418 if ((msr) & MSR(sig)) { \
419 if ((var & SER(sig)) == 0) \
420 var |= SERD(sig) | SER(sig); \
422 if ((var & SER(sig)) != 0) \
423 var = SERD(sig) | (var & ~SER(sig)); \
427 * Detect signal changes using the hardware msr delta bits. This is currently
428 * used only when PPS timing information is being captured using the "narrow
429 * pulse" option. With a narrow PPS pulse the signal may not still be asserted
430 * by time the interrupt handler is invoked. The hardware will latch the fact
431 * that it changed in the delta bits.
433 #define SIGCHGHW(var, msr, sig) \
434 if ((msr) & MSRD(sig)) { \
435 if (((msr) & MSR(sig)) != 0) \
436 var |= SERD(sig) | SER(sig); \
438 var = SERD(sig) | (var & ~SER(sig)); \
442 ns8250_bus_attach(struct uart_softc *sc)
444 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
445 struct uart_bas *bas;
452 ns8250->busy_detect = 0;
456 * Check whether uart requires to read USR reg when IIR_BUSY and
459 node = ofw_bus_get_node(sc->sc_dev);
460 if ((OF_getprop(node, "busy-detect", &cell, sizeof(cell))) > 0)
461 ns8250->busy_detect = 1;
462 if ((OF_getprop(node, "broken-txfifo", &cell, sizeof(cell))) > 0)
468 ns8250->mcr = uart_getreg(bas, REG_MCR);
469 ns8250->fcr = FCR_ENABLE;
471 ns8250->fcr |= FCR_UART_ON;
473 if (!resource_int_value("uart", device_get_unit(sc->sc_dev), "flags",
475 if (UART_FLAGS_FCR_RX_LOW(ivar))
476 ns8250->fcr |= FCR_RX_LOW;
477 else if (UART_FLAGS_FCR_RX_MEDL(ivar))
478 ns8250->fcr |= FCR_RX_MEDL;
479 else if (UART_FLAGS_FCR_RX_HIGH(ivar))
480 ns8250->fcr |= FCR_RX_HIGH;
482 ns8250->fcr |= FCR_RX_MEDH;
484 ns8250->fcr |= FCR_RX_MEDH;
488 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_mask",
490 ns8250->ier_mask = (uint8_t)(ivar & 0xff);
492 /* Get IER RX interrupt bits */
493 ivar = IER_EMSC | IER_ERLS | IER_ERXRDY;
494 resource_int_value("uart", device_get_unit(sc->sc_dev), "ier_rxbits",
496 ns8250->ier_rxbits = (uint8_t)(ivar & 0xff);
498 uart_setreg(bas, REG_FCR, ns8250->fcr);
500 ns8250_bus_flush(sc, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
502 if (ns8250->mcr & MCR_DTR)
503 sc->sc_hwsig |= SER_DTR;
504 if (ns8250->mcr & MCR_RTS)
505 sc->sc_hwsig |= SER_RTS;
506 ns8250_bus_getsig(sc);
509 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
510 ns8250->ier |= ns8250->ier_rxbits;
511 uart_setreg(bas, REG_IER, ns8250->ier);
515 * Timing of the H/W access was changed with r253161 of uart_core.c
516 * It has been observed that an ITE IT8513E would signal a break
517 * condition with pretty much every character it received, unless
518 * it had enough time to settle between ns8250_bus_attach() and
519 * ns8250_bus_ipend() -- which it accidentally had before r253161.
520 * It's not understood why the UART chip behaves this way and it
521 * could very well be that the DELAY make the H/W work in the same
522 * accidental manner as before. More analysis is warranted, but
523 * at least now we fixed a known regression.
530 ns8250_bus_detach(struct uart_softc *sc)
532 struct ns8250_softc *ns8250;
533 struct uart_bas *bas;
536 ns8250 = (struct ns8250_softc *)sc;
538 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
539 uart_setreg(bas, REG_IER, ier);
546 ns8250_bus_flush(struct uart_softc *sc, int what)
548 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
549 struct uart_bas *bas;
553 uart_lock(sc->sc_hwmtx);
554 if (sc->sc_rxfifosz > 1) {
555 ns8250_flush(bas, what);
556 uart_setreg(bas, REG_FCR, ns8250->fcr);
560 error = ns8250_drain(bas, what);
561 uart_unlock(sc->sc_hwmtx);
566 ns8250_bus_getsig(struct uart_softc *sc)
572 * The delta bits are reputed to be broken on some hardware, so use
573 * software delta detection by default. Use the hardware delta bits
574 * when capturing PPS pulses which are too narrow for software detection
575 * to see the edges. Hardware delta for RI doesn't work like the
576 * others, so always use software for it. Other threads may be changing
577 * other (non-MSR) bits in sc_hwsig, so loop until it can succesfully
578 * update without other changes happening. Note that the SIGCHGxx()
579 * macros carefully preserve the delta bits when we have to loop several
580 * times and a signal transitions between iterations.
585 uart_lock(sc->sc_hwmtx);
586 msr = uart_getreg(&sc->sc_bas, REG_MSR);
587 uart_unlock(sc->sc_hwmtx);
588 if (sc->sc_pps_mode & UART_PPS_NARROW_PULSE) {
589 SIGCHGHW(sig, msr, DSR);
590 SIGCHGHW(sig, msr, CTS);
591 SIGCHGHW(sig, msr, DCD);
593 SIGCHGSW(sig, msr, DSR);
594 SIGCHGSW(sig, msr, CTS);
595 SIGCHGSW(sig, msr, DCD);
597 SIGCHGSW(sig, msr, RI);
598 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, sig & ~SER_MASK_DELTA));
603 ns8250_bus_ioctl(struct uart_softc *sc, int request, intptr_t data)
605 struct uart_bas *bas;
606 int baudrate, divisor, error;
611 uart_lock(sc->sc_hwmtx);
613 case UART_IOCTL_BREAK:
614 lcr = uart_getreg(bas, REG_LCR);
619 uart_setreg(bas, REG_LCR, lcr);
622 case UART_IOCTL_IFLOW:
623 lcr = uart_getreg(bas, REG_LCR);
625 uart_setreg(bas, REG_LCR, 0xbf);
627 efr = uart_getreg(bas, REG_EFR);
632 uart_setreg(bas, REG_EFR, efr);
634 uart_setreg(bas, REG_LCR, lcr);
637 case UART_IOCTL_OFLOW:
638 lcr = uart_getreg(bas, REG_LCR);
640 uart_setreg(bas, REG_LCR, 0xbf);
642 efr = uart_getreg(bas, REG_EFR);
647 uart_setreg(bas, REG_EFR, efr);
649 uart_setreg(bas, REG_LCR, lcr);
652 case UART_IOCTL_BAUD:
653 lcr = uart_getreg(bas, REG_LCR);
654 uart_setreg(bas, REG_LCR, lcr | LCR_DLAB);
656 divisor = uart_getreg(bas, REG_DLL) |
657 (uart_getreg(bas, REG_DLH) << 8);
659 uart_setreg(bas, REG_LCR, lcr);
661 baudrate = (divisor > 0) ? bas->rclk / divisor / 16 : 0;
663 *(int*)data = baudrate;
671 uart_unlock(sc->sc_hwmtx);
676 ns8250_bus_ipend(struct uart_softc *sc)
678 struct uart_bas *bas;
679 struct ns8250_softc *ns8250;
683 ns8250 = (struct ns8250_softc *)sc;
685 uart_lock(sc->sc_hwmtx);
686 iir = uart_getreg(bas, REG_IIR);
688 if (ns8250->busy_detect && (iir & IIR_BUSY) == IIR_BUSY) {
689 (void)uart_getreg(bas, DW_REG_USR);
690 uart_unlock(sc->sc_hwmtx);
693 if (iir & IIR_NOPEND) {
694 uart_unlock(sc->sc_hwmtx);
698 if (iir & IIR_RXRDY) {
699 lsr = uart_getreg(bas, REG_LSR);
701 ipend |= SER_INT_OVERRUN;
703 ipend |= SER_INT_BREAK;
705 ipend |= SER_INT_RXREADY;
707 if (iir & IIR_TXRDY) {
708 ipend |= SER_INT_TXIDLE;
709 uart_setreg(bas, REG_IER, ns8250->ier);
711 ipend |= SER_INT_SIGCHG;
715 uart_unlock(sc->sc_hwmtx);
720 ns8250_bus_param(struct uart_softc *sc, int baudrate, int databits,
721 int stopbits, int parity)
723 struct ns8250_softc *ns8250;
724 struct uart_bas *bas;
727 ns8250 = (struct ns8250_softc*)sc;
729 uart_lock(sc->sc_hwmtx);
731 * When using DW UART with BUSY detection it is necessary to wait
732 * until all serial transfers are finished before manipulating the
733 * line control. LCR will not be affected when UART is busy.
735 if (ns8250->busy_detect != 0) {
737 * Pick an arbitrary high limit to avoid getting stuck in
738 * an infinite loop in case when the hardware is broken.
741 while (((uart_getreg(bas, DW_REG_USR) & USR_BUSY) != 0) &&
746 /* UART appears to be stuck */
747 uart_unlock(sc->sc_hwmtx);
752 error = ns8250_param(bas, baudrate, databits, stopbits, parity);
753 uart_unlock(sc->sc_hwmtx);
758 ns8250_bus_probe(struct uart_softc *sc)
760 struct ns8250_softc *ns8250;
761 struct uart_bas *bas;
762 int count, delay, error, limit;
763 uint8_t lsr, mcr, ier;
766 ns8250 = (struct ns8250_softc *)sc;
769 error = ns8250_probe(bas);
774 if (sc->sc_sysdev == NULL) {
775 /* By using ns8250_init() we also set DTR and RTS. */
776 ns8250_init(bas, 115200, 8, 1, UART_PARITY_NONE);
778 mcr |= MCR_DTR | MCR_RTS;
780 error = ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
785 * Set loopback mode. This avoids having garbage on the wire and
786 * also allows us send and receive data. We set DTR and RTS to
787 * avoid the possibility that automatic flow-control prevents
788 * any data from being sent.
790 uart_setreg(bas, REG_MCR, MCR_LOOPBACK | MCR_IE | MCR_DTR | MCR_RTS);
794 * Enable FIFOs. And check that the UART has them. If not, we're
795 * done. Since this is the first time we enable the FIFOs, we reset
802 uart_setreg(bas, REG_FCR, val);
804 if (!(uart_getreg(bas, REG_IIR) & IIR_FIFO_MASK)) {
806 * NS16450 or INS8250. We don't bother to differentiate
807 * between them. They're too old to be interesting.
809 uart_setreg(bas, REG_MCR, mcr);
811 sc->sc_rxfifosz = sc->sc_txfifosz = 1;
812 device_set_desc(sc->sc_dev, "8250 or 16450 or compatible");
816 val = FCR_ENABLE | FCR_XMT_RST | FCR_RCV_RST;
820 uart_setreg(bas, REG_FCR, val);
824 delay = ns8250_delay(bas);
826 /* We have FIFOs. Drain the transmitter and receiver. */
827 error = ns8250_drain(bas, UART_DRAIN_RECEIVER|UART_DRAIN_TRANSMITTER);
829 uart_setreg(bas, REG_MCR, mcr);
834 uart_setreg(bas, REG_FCR, val);
840 * We should have a sufficiently clean "pipe" to determine the
841 * size of the FIFOs. We send as much characters as is reasonable
842 * and wait for the overflow bit in the LSR register to be
843 * asserted, counting the characters as we send them. Based on
844 * that count we know the FIFO size.
847 uart_setreg(bas, REG_DATA, 0);
854 * LSR bits are cleared upon read, so we must accumulate
855 * them to be able to test LSR_OE below.
857 while (((lsr |= uart_getreg(bas, REG_LSR)) & LSR_TEMT) == 0 &&
861 ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask;
862 uart_setreg(bas, REG_IER, ier);
863 uart_setreg(bas, REG_MCR, mcr);
868 uart_setreg(bas, REG_FCR, val);
873 } while ((lsr & LSR_OE) == 0 && count < 130);
876 uart_setreg(bas, REG_MCR, mcr);
879 ns8250_flush(bas, UART_FLUSH_RECEIVER|UART_FLUSH_TRANSMITTER);
882 if (count >= 14 && count <= 16) {
883 sc->sc_rxfifosz = 16;
884 device_set_desc(sc->sc_dev, "16550 or compatible");
885 } else if (count >= 28 && count <= 32) {
886 sc->sc_rxfifosz = 32;
887 device_set_desc(sc->sc_dev, "16650 or compatible");
888 } else if (count >= 56 && count <= 64) {
889 sc->sc_rxfifosz = 64;
890 device_set_desc(sc->sc_dev, "16750 or compatible");
891 } else if (count >= 112 && count <= 128) {
892 sc->sc_rxfifosz = 128;
893 device_set_desc(sc->sc_dev, "16950 or compatible");
895 sc->sc_rxfifosz = 16;
896 device_set_desc(sc->sc_dev,
897 "Non-standard ns8250 class UART with FIFOs");
901 * Force the Tx FIFO size to 16 bytes for now. We don't program the
902 * Tx trigger. Also, we assume that all data has been sent when the
905 sc->sc_txfifosz = 16;
909 * XXX there are some issues related to hardware flow control and
910 * it's likely that uart(4) is the cause. This basicly needs more
911 * investigation, but we avoid using for hardware flow control
914 /* 16650s or higher have automatic flow control. */
915 if (sc->sc_rxfifosz > 16) {
925 ns8250_bus_receive(struct uart_softc *sc)
927 struct uart_bas *bas;
932 uart_lock(sc->sc_hwmtx);
933 lsr = uart_getreg(bas, REG_LSR);
934 while (lsr & LSR_RXRDY) {
935 if (uart_rx_full(sc)) {
936 sc->sc_rxbuf[sc->sc_rxput] = UART_STAT_OVERRUN;
939 xc = uart_getreg(bas, REG_DATA);
941 xc |= UART_STAT_FRAMERR;
943 xc |= UART_STAT_PARERR;
945 lsr = uart_getreg(bas, REG_LSR);
947 /* Discard everything left in the Rx FIFO. */
948 while (lsr & LSR_RXRDY) {
949 (void)uart_getreg(bas, REG_DATA);
951 lsr = uart_getreg(bas, REG_LSR);
953 uart_unlock(sc->sc_hwmtx);
958 ns8250_bus_setsig(struct uart_softc *sc, int sig)
960 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
961 struct uart_bas *bas;
968 if (sig & SER_DDTR) {
969 new = (new & ~SER_DTR) | (sig & (SER_DTR | SER_DDTR));
971 if (sig & SER_DRTS) {
972 new = (new & ~SER_RTS) | (sig & (SER_RTS | SER_DRTS));
974 } while (!atomic_cmpset_32(&sc->sc_hwsig, old, new));
975 uart_lock(sc->sc_hwmtx);
976 ns8250->mcr &= ~(MCR_DTR|MCR_RTS);
978 ns8250->mcr |= MCR_DTR;
980 ns8250->mcr |= MCR_RTS;
981 uart_setreg(bas, REG_MCR, ns8250->mcr);
983 uart_unlock(sc->sc_hwmtx);
988 ns8250_bus_transmit(struct uart_softc *sc)
990 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
991 struct uart_bas *bas;
995 uart_lock(sc->sc_hwmtx);
996 while ((uart_getreg(bas, REG_LSR) & LSR_THRE) == 0)
998 uart_setreg(bas, REG_IER, ns8250->ier | IER_ETXRDY);
1000 for (i = 0; i < sc->sc_txdatasz; i++) {
1001 uart_setreg(bas, REG_DATA, sc->sc_txbuf[i]);
1005 ns8250_drain(bas, UART_DRAIN_TRANSMITTER);
1008 uart_unlock(sc->sc_hwmtx);
1010 uart_sched_softih(sc, SER_INT_TXIDLE);
1015 ns8250_bus_grab(struct uart_softc *sc)
1017 struct uart_bas *bas = &sc->sc_bas;
1020 * turn off all interrupts to enter polling mode. Leave the
1021 * saved mask alone. We'll restore whatever it was in ungrab.
1022 * All pending interupt signals are reset when IER is set to 0.
1024 uart_lock(sc->sc_hwmtx);
1025 uart_setreg(bas, REG_IER, 0);
1027 uart_unlock(sc->sc_hwmtx);
1031 ns8250_bus_ungrab(struct uart_softc *sc)
1033 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc;
1034 struct uart_bas *bas = &sc->sc_bas;
1037 * Restore previous interrupt mask
1039 uart_lock(sc->sc_hwmtx);
1040 uart_setreg(bas, REG_IER, ns8250->ier);
1042 uart_unlock(sc->sc_hwmtx);