sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  29  *
  30  * The XHCI 1.0 spec can be found at
  31  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  32  * and the USB 3.0 spec at
  33  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  34  */
  35
  36 /*
  37  * A few words about the design implementation: This driver emulates
  38  * the concept about TDs which is found in EHCI specification. This
  39  * way we achieve that the USB controller drivers look similar to
  40  * eachother which makes it easier to understand the code.
  41  */
  42
  43 #ifdef USB_GLOBAL_INCLUDE_FILE
  44 #include USB_GLOBAL_INCLUDE_FILE
  45 #else
  46 #include <sys/stdint.h>
  47 #include <sys/stddef.h>
  48 #include <sys/param.h>
  49 #include <sys/queue.h>
  50 #include <sys/types.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/bus.h>
  54 #include <sys/module.h>
  55 #include <sys/lock.h>
  56 #include <sys/mutex.h>
  57 #include <sys/condvar.h>
  58 #include <sys/sysctl.h>
  59 #include <sys/sx.h>
  60 #include <sys/unistd.h>
  61 #include <sys/callout.h>
  62 #include <sys/malloc.h>
  63 #include <sys/priv.h>
  64
  65 #include <dev/usb/usb.h>
  66 #include <dev/usb/usbdi.h>
  67
  68 #define USB_DEBUG_VAR xhcidebug
  69
  70 #include <dev/usb/usb_core.h>
  71 #include <dev/usb/usb_debug.h>
  72 #include <dev/usb/usb_busdma.h>
  73 #include <dev/usb/usb_process.h>
  74 #include <dev/usb/usb_transfer.h>
  75 #include <dev/usb/usb_device.h>
  76 #include <dev/usb/usb_hub.h>
  77 #include <dev/usb/usb_util.h>
  78
  79 #include <dev/usb/usb_controller.h>
  80 #include <dev/usb/usb_bus.h>
  81 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  82
  83 #include <dev/usb/controller/xhci.h>
  84 #include <dev/usb/controller/xhcireg.h>
  85
  86 #define XHCI_BUS2SC(bus) \
  87    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  88     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  89
  90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91
  92 static int xhcistreams;
  93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
  94     &xhcistreams, 0, "Set to enable streams mode support");
  95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
  96
  97 #ifdef USB_DEBUG
  98 static int xhcidebug;
  99 static int xhciroute;
 100 static int xhcipolling;
 101
 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
 103     &xhcidebug, 0, "Debug level");
 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
 106     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
 109     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 111 #else
 112 #define xhciroute 0
 113 #endif
 114
 115 #define XHCI_INTR_ENDPT 1
 116
 117 struct xhci_std_temp {
 118         struct xhci_softc       *sc;
 119         struct usb_page_cache   *pc;
 120         struct xhci_td          *td;
 121         struct xhci_td          *td_next;
 122         uint32_t                len;
 123         uint32_t                offset;
 124         uint32_t                max_packet_size;
 125         uint32_t                average;
 126         uint16_t                isoc_delta;
 127         uint16_t                isoc_frame;
 128         uint8_t                 shortpkt;
 129         uint8_t                 multishort;
 130         uint8_t                 last_frame;
 131         uint8_t                 trb_type;
 132         uint8_t                 direction;
 133         uint8_t                 tbc;
 134         uint8_t                 tlbpc;
 135         uint8_t                 step_td;
 136         uint8_t                 do_isoc_sync;
 137 };
 138
 139 static void     xhci_do_poll(struct usb_bus *);
 140 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 141 static void     xhci_root_intr(struct xhci_softc *);
 142 static void     xhci_free_device_ext(struct usb_device *);
 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 144                     struct usb_endpoint_descriptor *);
 145 static usb_proc_callback_t xhci_configure_msg;
 146 static usb_error_t xhci_configure_device(struct usb_device *);
 147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 148                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 149                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 150                    uint8_t);
 151 static usb_error_t xhci_configure_mask(struct usb_device *,
 152                     uint32_t, uint8_t);
 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 154                     uint64_t, uint8_t);
 155 static void xhci_endpoint_doorbell(struct usb_xfer *);
 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 159 #ifdef USB_DEBUG
 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 161 #endif
 162
 163 extern struct usb_bus_methods xhci_bus_methods;
 164
 165 #ifdef USB_DEBUG
 166 static void
 167 xhci_dump_trb(struct xhci_trb *trb)
 168 {
 169         DPRINTFN(5, "trb = %p\n", trb);
 170         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 171         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 172         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 173 }
 174
 175 static void
 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 177 {
 178         DPRINTFN(5, "pep = %p\n", pep);
 179         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 180         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 181         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 182         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 183         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 184         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 185         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 186 }
 187
 188 static void
 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 190 {
 191         DPRINTFN(5, "psl = %p\n", psl);
 192         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 193         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 194         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 195         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 196 }
 197 #endif
 198
 199 uint8_t
 200 xhci_use_polling(void)
 201 {
 202 #ifdef USB_DEBUG
 203         return (xhcipolling != 0);
 204 #else
 205         return (0);
 206 #endif
 207 }
 208
 209 static void
 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 211 {
 212         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 213         uint8_t i;
 214
 215         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 216            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 217
 218         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 219            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 220
 221         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 222                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 223                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 224         }
 225 }
 226
 227 static void
 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 229 {
 230         if (sc->sc_ctx_is_64_byte) {
 231                 uint32_t offset;
 232                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 233                 /* all contexts are initially 32-bytes */
 234                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 235                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 236         }
 237         *ptr = htole32(val);
 238 }
 239
 240 static uint32_t
 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 242 {
 243         if (sc->sc_ctx_is_64_byte) {
 244                 uint32_t offset;
 245                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 246                 /* all contexts are initially 32-bytes */
 247                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 248                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 249         }
 250         return (le32toh(*ptr));
 251 }
 252
 253 static void
 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 255 {
 256         if (sc->sc_ctx_is_64_byte) {
 257                 uint32_t offset;
 258                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 259                 /* all contexts are initially 32-bytes */
 260                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 261                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 262         }
 263         *ptr = htole64(val);
 264 }
 265
 266 #ifdef USB_DEBUG
 267 static uint64_t
 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 269 {
 270         if (sc->sc_ctx_is_64_byte) {
 271                 uint32_t offset;
 272                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 273                 /* all contexts are initially 32-bytes */
 274                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 275                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 276         }
 277         return (le64toh(*ptr));
 278 }
 279 #endif
 280
 281 static int
 282 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 283 {
 284         struct usb_page_search buf_res;
 285         struct xhci_hw_root *phwr;
 286         uint64_t addr;
 287         uint32_t temp;
 288
 289         DPRINTF("\n");
 290
 291         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 292         if (temp & XHCI_CRCR_LO_CRR) {
 293                 DPRINTF("Command ring running\n");
 294                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 295
 296                 /*
 297                  * Try to abort the last command as per section
 298                  * 4.6.1.2 "Aborting a Command" of the XHCI
 299                  * specification:
 300                  */
 301
 302                 /* stop and cancel */
 303                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 304                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 305
 306                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 307                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 308
 309                 /* wait 250ms */
 310                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 311
 312                 /* check if command ring is still running */
 313                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 314                 if (temp & XHCI_CRCR_LO_CRR) {
 315                         DPRINTF("Comand ring still running\n");
 316                         return (USB_ERR_IOERROR);
 317                 }
 318         }
 319
 320         /* reset command ring */
 321         sc->sc_command_ccs = 1;
 322         sc->sc_command_idx = 0;
 323
 324         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 325
 326         /* setup command ring control base address */
 327         addr = buf_res.physaddr;
 328         phwr = buf_res.buffer;
 329         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 330
 331         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 332
 333         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 334         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 335
 336         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 337
 338         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 339         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 340
 341         return (0);
 342 }
 343
 344 usb_error_t
 345 xhci_start_controller(struct xhci_softc *sc)
 346 {
 347         struct usb_page_search buf_res;
 348         struct xhci_hw_root *phwr;
 349         struct xhci_dev_ctx_addr *pdctxa;
 350         uint64_t addr;
 351         uint32_t temp;
 352         uint16_t i;
 353
 354         DPRINTF("\n");
 355
 356         sc->sc_capa_off = 0;
 357         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 358         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 359         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 360
 361         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 362         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 363         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 364
 365         sc->sc_event_ccs = 1;
 366         sc->sc_event_idx = 0;
 367         sc->sc_command_ccs = 1;
 368         sc->sc_command_idx = 0;
 369
 370         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 371
 372         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 373
 374         DPRINTF("HCS0 = 0x%08x\n", temp);
 375
 376         if (XHCI_HCS0_CSZ(temp)) {
 377                 sc->sc_ctx_is_64_byte = 1;
 378                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 379         } else {
 380                 sc->sc_ctx_is_64_byte = 0;
 381                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 382         }
 383
 384         /* Reset controller */
 385         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 386
 387         for (i = 0; i != 100; i++) {
 388                 usb_pause_mtx(NULL, hz / 100);
 389                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 390                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 391                 if (!temp)
 392                         break;
 393         }
 394
 395         if (temp) {
 396                 device_printf(sc->sc_bus.parent, "Controller "
 397                     "reset timeout.\n");
 398                 return (USB_ERR_IOERROR);
 399         }
 400
 401         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 402                 device_printf(sc->sc_bus.parent, "Controller does "
 403                     "not support 4K page size.\n");
 404                 return (USB_ERR_IOERROR);
 405         }
 406
 407         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 408
 409         i = XHCI_HCS1_N_PORTS(temp);
 410
 411         if (i == 0) {
 412                 device_printf(sc->sc_bus.parent, "Invalid number "
 413                     "of ports: %u\n", i);
 414                 return (USB_ERR_IOERROR);
 415         }
 416
 417         sc->sc_noport = i;
 418         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 419
 420         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 421                 sc->sc_noslot = XHCI_MAX_DEVICES;
 422
 423         /* setup number of device slots */
 424
 425         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 426             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 427
 428         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 429
 430         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 431
 432         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 433
 434         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 435
 436         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 437                 device_printf(sc->sc_bus.parent, "XHCI request "
 438                     "too many scratchpads\n");
 439                 return (USB_ERR_NOMEM);
 440         }
 441
 442         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 443
 444         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 445
 446         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 447             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 448
 449         temp = XREAD4(sc, oper, XHCI_USBSTS);
 450
 451         /* clear interrupts */
 452         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 453         /* disable all device notifications */
 454         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 455
 456         /* setup device context base address */
 457         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 458         pdctxa = buf_res.buffer;
 459         memset(pdctxa, 0, sizeof(*pdctxa));
 460
 461         addr = buf_res.physaddr;
 462         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 463
 464         /* slot 0 points to the table of scratchpad pointers */
 465         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 466
 467         for (i = 0; i != sc->sc_noscratch; i++) {
 468                 struct usb_page_search buf_scp;
 469                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 470                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 471         }
 472
 473         addr = buf_res.physaddr;
 474
 475         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 476         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 477         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 478         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 479
 480         /* Setup event table size */
 481
 482         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 483
 484         DPRINTF("HCS2=0x%08x\n", temp);
 485
 486         temp = XHCI_HCS2_ERST_MAX(temp);
 487         temp = 1U << temp;
 488         if (temp > XHCI_MAX_RSEG)
 489                 temp = XHCI_MAX_RSEG;
 490
 491         sc->sc_erst_max = temp;
 492
 493         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 494             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 495
 496         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 497
 498         /* Check if we should use the default IMOD value */
 499         if (sc->sc_imod_default == 0)
 500                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 501
 502         /* Setup interrupt rate */
 503         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 504
 505         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 506
 507         phwr = buf_res.buffer;
 508         addr = buf_res.physaddr;
 509         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 510
 511         /* reset hardware root structure */
 512         memset(phwr, 0, sizeof(*phwr));
 513
 514         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 515         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 516
 517         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 518
 519         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 520         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 521
 522         addr = (uint64_t)buf_res.physaddr;
 523
 524         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 525
 526         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 527         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 528
 529         /* Setup interrupter registers */
 530
 531         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 532         temp |= XHCI_IMAN_INTR_ENA;
 533         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 534
 535         /* setup command ring control base address */
 536         addr = buf_res.physaddr;
 537         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 538
 539         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 540
 541         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 542         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 543
 544         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 545
 546         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 547
 548         /* Go! */
 549         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 550             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 551
 552         for (i = 0; i != 100; i++) {
 553                 usb_pause_mtx(NULL, hz / 100);
 554                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 555                 if (!temp)
 556                         break;
 557         }
 558         if (temp) {
 559                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 560                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 561                 return (USB_ERR_IOERROR);
 562         }
 563
 564         /* catch any lost interrupts */
 565         xhci_do_poll(&sc->sc_bus);
 566
 567         if (sc->sc_port_route != NULL) {
 568                 /* Route all ports to the XHCI by default */
 569                 sc->sc_port_route(sc->sc_bus.parent,
 570                     ~xhciroute, xhciroute);
 571         }
 572         return (0);
 573 }
 574
 575 usb_error_t
 576 xhci_halt_controller(struct xhci_softc *sc)
 577 {
 578         uint32_t temp;
 579         uint16_t i;
 580
 581         DPRINTF("\n");
 582
 583         sc->sc_capa_off = 0;
 584         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 585         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 586         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 587
 588         /* Halt controller */
 589         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 590
 591         for (i = 0; i != 100; i++) {
 592                 usb_pause_mtx(NULL, hz / 100);
 593                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 594                 if (temp)
 595                         break;
 596         }
 597
 598         if (!temp) {
 599                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 600                 return (USB_ERR_IOERROR);
 601         }
 602         return (0);
 603 }
 604
 605 usb_error_t
 606 xhci_init(struct xhci_softc *sc, device_t self)
 607 {
 608         /* initialise some bus fields */
 609         sc->sc_bus.parent = self;
 610
 611         /* set the bus revision */
 612         sc->sc_bus.usbrev = USB_REV_3_0;
 613
 614         /* set up the bus struct */
 615         sc->sc_bus.methods = &xhci_bus_methods;
 616
 617         /* setup devices array */
 618         sc->sc_bus.devices = sc->sc_devices;
 619         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 620
 621         /* setup command queue mutex and condition varible */
 622         cv_init(&sc->sc_cmd_cv, "CMDQ");
 623         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 624
 625         /* get all DMA memory */
 626         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 627             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 628                 return (ENOMEM);
 629         }
 630
 631         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 632         sc->sc_config_msg[0].bus = &sc->sc_bus;
 633         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 634         sc->sc_config_msg[1].bus = &sc->sc_bus;
 635
 636         return (0);
 637 }
 638
 639 void
 640 xhci_uninit(struct xhci_softc *sc)
 641 {
 642         /*
 643          * NOTE: At this point the control transfer process is gone
 644          * and "xhci_configure_msg" is no longer called. Consequently
 645          * waiting for the configuration messages to complete is not
 646          * needed.
 647          */
 648         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 649
 650         cv_destroy(&sc->sc_cmd_cv);
 651         sx_destroy(&sc->sc_cmd_sx);
 652 }
 653
 654 static void
 655 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 656 {
 657         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 658
 659         switch (state) {
 660         case USB_HW_POWER_SUSPEND:
 661                 DPRINTF("Stopping the XHCI\n");
 662                 xhci_halt_controller(sc);
 663                 break;
 664         case USB_HW_POWER_SHUTDOWN:
 665                 DPRINTF("Stopping the XHCI\n");
 666                 xhci_halt_controller(sc);
 667                 break;
 668         case USB_HW_POWER_RESUME:
 669                 DPRINTF("Starting the XHCI\n");
 670                 xhci_start_controller(sc);
 671                 break;
 672         default:
 673                 break;
 674         }
 675 }
 676
 677 static usb_error_t
 678 xhci_generic_done_sub(struct usb_xfer *xfer)
 679 {
 680         struct xhci_td *td;
 681         struct xhci_td *td_alt_next;
 682         uint32_t len;
 683         uint8_t status;
 684
 685         td = xfer->td_transfer_cache;
 686         td_alt_next = td->alt_next;
 687
 688         if (xfer->aframes != xfer->nframes)
 689                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 690
 691         while (1) {
 692
 693                 usb_pc_cpu_invalidate(td->page_cache);
 694
 695                 status = td->status;
 696                 len = td->remainder;
 697
 698                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 699                     xfer, (unsigned int)xfer->aframes,
 700                     (unsigned int)xfer->nframes,
 701                     (unsigned int)len, (unsigned int)td->len,
 702                     (unsigned int)status);
 703
 704                 /*
 705                  * Verify the status length and
 706                  * add the length to "frlengths[]":
 707                  */
 708                 if (len > td->len) {
 709                         /* should not happen */
 710                         DPRINTF("Invalid status length, "
 711                             "0x%04x/0x%04x bytes\n", len, td->len);
 712                         status = XHCI_TRB_ERROR_LENGTH;
 713                 } else if (xfer->aframes != xfer->nframes) {
 714                         xfer->frlengths[xfer->aframes] += td->len - len;
 715                 }
 716                 /* Check for last transfer */
 717                 if (((void *)td) == xfer->td_transfer_last) {
 718                         td = NULL;
 719                         break;
 720                 }
 721                 /* Check for transfer error */
 722                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 723                     status != XHCI_TRB_ERROR_SUCCESS) {
 724                         /* the transfer is finished */
 725                         td = NULL;
 726                         break;
 727                 }
 728                 /* Check for short transfer */
 729                 if (len > 0) {
 730                         if (xfer->flags_int.short_frames_ok ||
 731                             xfer->flags_int.isochronous_xfr ||
 732                             xfer->flags_int.control_xfr) {
 733                                 /* follow alt next */
 734                                 td = td->alt_next;
 735                         } else {
 736                                 /* the transfer is finished */
 737                                 td = NULL;
 738                         }
 739                         break;
 740                 }
 741                 td = td->obj_next;
 742
 743                 if (td->alt_next != td_alt_next) {
 744                         /* this USB frame is complete */
 745                         break;
 746                 }
 747         }
 748
 749         /* update transfer cache */
 750
 751         xfer->td_transfer_cache = td;
 752
 753         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 754             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 755             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 756             USB_ERR_NORMAL_COMPLETION);
 757 }
 758
 759 static void
 760 xhci_generic_done(struct usb_xfer *xfer)
 761 {
 762         usb_error_t err = 0;
 763
 764         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 765             xfer, xfer->endpoint);
 766
 767         /* reset scanner */
 768
 769         xfer->td_transfer_cache = xfer->td_transfer_first;
 770
 771         if (xfer->flags_int.control_xfr) {
 772
 773                 if (xfer->flags_int.control_hdr)
 774                         err = xhci_generic_done_sub(xfer);
 775
 776                 xfer->aframes = 1;
 777
 778                 if (xfer->td_transfer_cache == NULL)
 779                         goto done;
 780         }
 781
 782         while (xfer->aframes != xfer->nframes) {
 783
 784                 err = xhci_generic_done_sub(xfer);
 785                 xfer->aframes++;
 786
 787                 if (xfer->td_transfer_cache == NULL)
 788                         goto done;
 789         }
 790
 791         if (xfer->flags_int.control_xfr &&
 792             !xfer->flags_int.control_act)
 793                 err = xhci_generic_done_sub(xfer);
 794 done:
 795         /* transfer is complete */
 796         xhci_device_done(xfer, err);
 797 }
 798
 799 static void
 800 xhci_activate_transfer(struct usb_xfer *xfer)
 801 {
 802         struct xhci_td *td;
 803
 804         td = xfer->td_transfer_cache;
 805
 806         usb_pc_cpu_invalidate(td->page_cache);
 807
 808         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 809
 810                 /* activate the transfer */
 811
 812                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 813                 usb_pc_cpu_flush(td->page_cache);
 814
 815                 xhci_endpoint_doorbell(xfer);
 816         }
 817 }
 818
 819 static void
 820 xhci_skip_transfer(struct usb_xfer *xfer)
 821 {
 822         struct xhci_td *td;
 823         struct xhci_td *td_last;
 824
 825         td = xfer->td_transfer_cache;
 826         td_last = xfer->td_transfer_last;
 827
 828         td = td->alt_next;
 829
 830         usb_pc_cpu_invalidate(td->page_cache);
 831
 832         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 833
 834                 usb_pc_cpu_invalidate(td_last->page_cache);
 835
 836                 /* copy LINK TRB to current waiting location */
 837
 838                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 839                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 840                 usb_pc_cpu_flush(td->page_cache);
 841
 842                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 843                 usb_pc_cpu_flush(td->page_cache);
 844
 845                 xhci_endpoint_doorbell(xfer);
 846         }
 847 }
 848
 849 /*------------------------------------------------------------------------*
 850  *      xhci_check_transfer
 851  *------------------------------------------------------------------------*/
 852 static void
 853 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 854 {
 855         struct xhci_endpoint_ext *pepext;
 856         int64_t offset;
 857         uint64_t td_event;
 858         uint32_t temp;
 859         uint32_t remainder;
 860         uint16_t stream_id;
 861         uint16_t i;
 862         uint8_t status;
 863         uint8_t halted;
 864         uint8_t epno;
 865         uint8_t index;
 866
 867         /* decode TRB */
 868         td_event = le64toh(trb->qwTrb0);
 869         temp = le32toh(trb->dwTrb2);
 870
 871         remainder = XHCI_TRB_2_REM_GET(temp);
 872         status = XHCI_TRB_2_ERROR_GET(temp);
 873         stream_id = XHCI_TRB_2_STREAM_GET(temp);
 874
 875         temp = le32toh(trb->dwTrb3);
 876         epno = XHCI_TRB_3_EP_GET(temp);
 877         index = XHCI_TRB_3_SLOT_GET(temp);
 878
 879         /* check if error means halted */
 880         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 881             status != XHCI_TRB_ERROR_SUCCESS);
 882
 883         DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
 884             index, epno, stream_id, remainder, status);
 885
 886         if (index > sc->sc_noslot) {
 887                 DPRINTF("Invalid slot.\n");
 888                 return;
 889         }
 890
 891         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 892                 DPRINTF("Invalid endpoint.\n");
 893                 return;
 894         }
 895
 896         pepext = &sc->sc_hw.devs[index].endp[epno];
 897
 898         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
 899                 stream_id = 0;
 900                 DPRINTF("stream_id=0\n");
 901         } else if (stream_id >= XHCI_MAX_STREAMS) {
 902                 DPRINTF("Invalid stream ID.\n");
 903                 return;
 904         }
 905
 906         /* try to find the USB transfer that generated the event */
 907         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 908                 struct usb_xfer *xfer;
 909                 struct xhci_td *td;
 910
 911                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 912                 if (xfer == NULL)
 913                         continue;
 914
 915                 td = xfer->td_transfer_cache;
 916
 917                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 918                         (long long)td_event,
 919                         (long long)td->td_self,
 920                         (long long)td->td_self + sizeof(td->td_trb));
 921
 922                 /*
 923                  * NOTE: Some XHCI implementations might not trigger
 924                  * an event on the last LINK TRB so we need to
 925                  * consider both the last and second last event
 926                  * address as conditions for a successful transfer.
 927                  *
 928                  * NOTE: We assume that the XHCI will only trigger one
 929                  * event per chain of TRBs.
 930                  */
 931
 932                 offset = td_event - td->td_self;
 933
 934                 if (offset >= 0 &&
 935                     offset < (int64_t)sizeof(td->td_trb)) {
 936
 937                         usb_pc_cpu_invalidate(td->page_cache);
 938
 939                         /* compute rest of remainder, if any */
 940                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 941                                 temp = le32toh(td->td_trb[i].dwTrb2);
 942                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 943                         }
 944
 945                         DPRINTFN(5, "New remainder: %u\n", remainder);
 946
 947                         /* clear isochronous transfer errors */
 948                         if (xfer->flags_int.isochronous_xfr) {
 949                                 if (halted) {
 950                                         halted = 0;
 951                                         status = XHCI_TRB_ERROR_SUCCESS;
 952                                         remainder = td->len;
 953                                 }
 954                         }
 955
 956                         /* "td->remainder" is verified later */
 957                         td->remainder = remainder;
 958                         td->status = status;
 959
 960                         usb_pc_cpu_flush(td->page_cache);
 961
 962                         /*
 963                          * 1) Last transfer descriptor makes the
 964                          * transfer done
 965                          */
 966                         if (((void *)td) == xfer->td_transfer_last) {
 967                                 DPRINTF("TD is last\n");
 968                                 xhci_generic_done(xfer);
 969                                 break;
 970                         }
 971
 972                         /*
 973                          * 2) Any kind of error makes the transfer
 974                          * done
 975                          */
 976                         if (halted) {
 977                                 DPRINTF("TD has I/O error\n");
 978                                 xhci_generic_done(xfer);
 979                                 break;
 980                         }
 981
 982                         /*
 983                          * 3) If there is no alternate next transfer,
 984                          * a short packet also makes the transfer done
 985                          */
 986                         if (td->remainder > 0) {
 987                                 if (td->alt_next == NULL) {
 988                                         DPRINTF(
 989                                             "short TD has no alternate next\n");
 990                                         xhci_generic_done(xfer);
 991                                         break;
 992                                 }
 993                                 DPRINTF("TD has short pkt\n");
 994                                 if (xfer->flags_int.short_frames_ok ||
 995                                     xfer->flags_int.isochronous_xfr ||
 996                                     xfer->flags_int.control_xfr) {
 997                                         /* follow the alt next */
 998                                         xfer->td_transfer_cache = td->alt_next;
 999                                         xhci_activate_transfer(xfer);
1000                                         break;
1001                                 }
1002                                 xhci_skip_transfer(xfer);
1003                                 xhci_generic_done(xfer);
1004                                 break;
1005                         }
1006
1007                         /*
1008                          * 4) Transfer complete - go to next TD
1009                          */
1010                         DPRINTF("Following next TD\n");
1011                         xfer->td_transfer_cache = td->obj_next;
1012                         xhci_activate_transfer(xfer);
1013                         break;          /* there should only be one match */
1014                 }
1015         }
1016 }
1017
1018 static int
1019 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1020 {
1021         if (sc->sc_cmd_addr == trb->qwTrb0) {
1022                 DPRINTF("Received command event\n");
1023                 sc->sc_cmd_result[0] = trb->dwTrb2;
1024                 sc->sc_cmd_result[1] = trb->dwTrb3;
1025                 cv_signal(&sc->sc_cmd_cv);
1026                 return (1);     /* command match */
1027         }
1028         return (0);
1029 }
1030
1031 static int
1032 xhci_interrupt_poll(struct xhci_softc *sc)
1033 {
1034         struct usb_page_search buf_res;
1035         struct xhci_hw_root *phwr;
1036         uint64_t addr;
1037         uint32_t temp;
1038         int retval = 0;
1039         uint16_t i;
1040         uint8_t event;
1041         uint8_t j;
1042         uint8_t k;
1043         uint8_t t;
1044
1045         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1046
1047         phwr = buf_res.buffer;
1048
1049         /* Receive any events */
1050
1051         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1052
1053         i = sc->sc_event_idx;
1054         j = sc->sc_event_ccs;
1055         t = 2;
1056
1057         while (1) {
1058
1059                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1060
1061                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1062
1063                 if (j != k)
1064                         break;
1065
1066                 event = XHCI_TRB_3_TYPE_GET(temp);
1067
1068                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1069                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1070                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1071                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1072
1073                 switch (event) {
1074                 case XHCI_TRB_EVENT_TRANSFER:
1075                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1076                         break;
1077                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1078                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1079                         break;
1080                 default:
1081                         DPRINTF("Unhandled event = %u\n", event);
1082                         break;
1083                 }
1084
1085                 i++;
1086
1087                 if (i == XHCI_MAX_EVENTS) {
1088                         i = 0;
1089                         j ^= 1;
1090
1091                         /* check for timeout */
1092                         if (!--t)
1093                                 break;
1094                 }
1095         }
1096
1097         sc->sc_event_idx = i;
1098         sc->sc_event_ccs = j;
1099
1100         /*
1101          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1102          * latched. That means to activate the register we need to
1103          * write both the low and high double word of the 64-bit
1104          * register.
1105          */
1106
1107         addr = (uint32_t)buf_res.physaddr;
1108         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1109
1110         /* try to clear busy bit */
1111         addr |= XHCI_ERDP_LO_BUSY;
1112
1113         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1114         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1115
1116         return (retval);
1117 }
1118
1119 static usb_error_t
1120 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1121     uint16_t timeout_ms)
1122 {
1123         struct usb_page_search buf_res;
1124         struct xhci_hw_root *phwr;
1125         uint64_t addr;
1126         uint32_t temp;
1127         uint8_t i;
1128         uint8_t j;
1129         uint8_t timeout = 0;
1130         int err;
1131
1132         XHCI_CMD_ASSERT_LOCKED(sc);
1133
1134         /* get hardware root structure */
1135
1136         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1137
1138         phwr = buf_res.buffer;
1139
1140         /* Queue command */
1141
1142         USB_BUS_LOCK(&sc->sc_bus);
1143 retry:
1144         i = sc->sc_command_idx;
1145         j = sc->sc_command_ccs;
1146
1147         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1148             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1149             (long long)le64toh(trb->qwTrb0),
1150             (long)le32toh(trb->dwTrb2),
1151             (long)le32toh(trb->dwTrb3));
1152
1153         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1154         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1155
1156         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1157
1158         temp = trb->dwTrb3;
1159
1160         if (j)
1161                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1162         else
1163                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1164
1165         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1166
1167         phwr->hwr_commands[i].dwTrb3 = temp;
1168
1169         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1170
1171         addr = buf_res.physaddr;
1172         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1173
1174         sc->sc_cmd_addr = htole64(addr);
1175
1176         i++;
1177
1178         if (i == (XHCI_MAX_COMMANDS - 1)) {
1179
1180                 if (j) {
1181                         temp = htole32(XHCI_TRB_3_TC_BIT |
1182                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1183                             XHCI_TRB_3_CYCLE_BIT);
1184                 } else {
1185                         temp = htole32(XHCI_TRB_3_TC_BIT |
1186                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1187                 }
1188
1189                 phwr->hwr_commands[i].dwTrb3 = temp;
1190
1191                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1192
1193                 i = 0;
1194                 j ^= 1;
1195         }
1196
1197         sc->sc_command_idx = i;
1198         sc->sc_command_ccs = j;
1199
1200         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1201
1202         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1203             USB_MS_TO_TICKS(timeout_ms));
1204
1205         /*
1206          * In some error cases event interrupts are not generated.
1207          * Poll one time to see if the command has completed.
1208          */
1209         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1210                 DPRINTF("Command was completed when polling\n");
1211                 err = 0;
1212         }
1213         if (err != 0) {
1214                 DPRINTF("Command timeout!\n");
1215                 /*
1216                  * After some weeks of continuous operation, it has
1217                  * been observed that the ASMedia Technology, ASM1042
1218                  * SuperSpeed USB Host Controller can suddenly stop
1219                  * accepting commands via the command queue. Try to
1220                  * first reset the command queue. If that fails do a
1221                  * host controller reset.
1222                  */
1223                 if (timeout == 0 &&
1224                     xhci_reset_command_queue_locked(sc) == 0) {
1225                         temp = le32toh(trb->dwTrb3);
1226
1227                         /*
1228                          * Avoid infinite XHCI reset loops if the set
1229                          * address command fails to respond due to a
1230                          * non-enumerating device:
1231                          */
1232                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1233                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1234                                 DPRINTF("Set address timeout\n");
1235                         } else {
1236                                 timeout = 1;
1237                                 goto retry;
1238                         }
1239                 } else {
1240                         DPRINTF("Controller reset!\n");
1241                         usb_bus_reset_async_locked(&sc->sc_bus);
1242                 }
1243                 err = USB_ERR_TIMEOUT;
1244                 trb->dwTrb2 = 0;
1245                 trb->dwTrb3 = 0;
1246         } else {
1247                 temp = le32toh(sc->sc_cmd_result[0]);
1248                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1249                         err = USB_ERR_IOERROR;
1250
1251                 trb->dwTrb2 = sc->sc_cmd_result[0];
1252                 trb->dwTrb3 = sc->sc_cmd_result[1];
1253         }
1254
1255         USB_BUS_UNLOCK(&sc->sc_bus);
1256
1257         return (err);
1258 }
1259
1260 #if 0
1261 static usb_error_t
1262 xhci_cmd_nop(struct xhci_softc *sc)
1263 {
1264         struct xhci_trb trb;
1265         uint32_t temp;
1266
1267         DPRINTF("\n");
1268
1269         trb.qwTrb0 = 0;
1270         trb.dwTrb2 = 0;
1271         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1272
1273         trb.dwTrb3 = htole32(temp);
1274
1275         return (xhci_do_command(sc, &trb, 100 /* ms */));
1276 }
1277 #endif
1278
1279 static usb_error_t
1280 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1281 {
1282         struct xhci_trb trb;
1283         uint32_t temp;
1284         usb_error_t err;
1285
1286         DPRINTF("\n");
1287
1288         trb.qwTrb0 = 0;
1289         trb.dwTrb2 = 0;
1290         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1291
1292         err = xhci_do_command(sc, &trb, 100 /* ms */);
1293         if (err)
1294                 goto done;
1295
1296         temp = le32toh(trb.dwTrb3);
1297
1298         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1299
1300 done:
1301         return (err);
1302 }
1303
1304 static usb_error_t
1305 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1306 {
1307         struct xhci_trb trb;
1308         uint32_t temp;
1309
1310         DPRINTF("\n");
1311
1312         trb.qwTrb0 = 0;
1313         trb.dwTrb2 = 0;
1314         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1315             XHCI_TRB_3_SLOT_SET(slot_id);
1316
1317         trb.dwTrb3 = htole32(temp);
1318
1319         return (xhci_do_command(sc, &trb, 100 /* ms */));
1320 }
1321
1322 static usb_error_t
1323 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1324     uint8_t bsr, uint8_t slot_id)
1325 {
1326         struct xhci_trb trb;
1327         uint32_t temp;
1328
1329         DPRINTF("\n");
1330
1331         trb.qwTrb0 = htole64(input_ctx);
1332         trb.dwTrb2 = 0;
1333         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1334             XHCI_TRB_3_SLOT_SET(slot_id);
1335
1336         if (bsr)
1337                 temp |= XHCI_TRB_3_BSR_BIT;
1338
1339         trb.dwTrb3 = htole32(temp);
1340
1341         return (xhci_do_command(sc, &trb, 500 /* ms */));
1342 }
1343
1344 static usb_error_t
1345 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1346 {
1347         struct usb_page_search buf_inp;
1348         struct usb_page_search buf_dev;
1349         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1350         struct xhci_hw_dev *hdev;
1351         struct xhci_dev_ctx *pdev;
1352         struct xhci_endpoint_ext *pepext;
1353         uint32_t temp;
1354         uint16_t mps;
1355         usb_error_t err;
1356         uint8_t index;
1357
1358         /* the root HUB case is not handled here */
1359         if (udev->parent_hub == NULL)
1360                 return (USB_ERR_INVAL);
1361
1362         index = udev->controller_slot_id;
1363
1364         hdev =  &sc->sc_hw.devs[index];
1365
1366         if (mtx != NULL)
1367                 mtx_unlock(mtx);
1368
1369         XHCI_CMD_LOCK(sc);
1370
1371         switch (hdev->state) {
1372         case XHCI_ST_DEFAULT:
1373         case XHCI_ST_ENABLED:
1374
1375                 hdev->state = XHCI_ST_ENABLED;
1376
1377                 /* set configure mask to slot and EP0 */
1378                 xhci_configure_mask(udev, 3, 0);
1379
1380                 /* configure input slot context structure */
1381                 err = xhci_configure_device(udev);
1382
1383                 if (err != 0) {
1384                         DPRINTF("Could not configure device\n");
1385                         break;
1386                 }
1387
1388                 /* configure input endpoint context structure */
1389                 switch (udev->speed) {
1390                 case USB_SPEED_LOW:
1391                 case USB_SPEED_FULL:
1392                         mps = 8;
1393                         break;
1394                 case USB_SPEED_HIGH:
1395                         mps = 64;
1396                         break;
1397                 default:
1398                         mps = 512;
1399                         break;
1400                 }
1401
1402                 pepext = xhci_get_endpoint_ext(udev,
1403                     &udev->ctrl_ep_desc);
1404                 err = xhci_configure_endpoint(udev,
1405                     &udev->ctrl_ep_desc, pepext,
1406                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1407
1408                 if (err != 0) {
1409                         DPRINTF("Could not configure default endpoint\n");
1410                         break;
1411                 }
1412
1413                 /* execute set address command */
1414                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1415
1416                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1417                     (address == 0), index);
1418
1419                 if (err != 0) {
1420                         temp = le32toh(sc->sc_cmd_result[0]);
1421                         if (address == 0 && sc->sc_port_route != NULL &&
1422                             XHCI_TRB_2_ERROR_GET(temp) ==
1423                             XHCI_TRB_ERROR_PARAMETER) {
1424                                 /* LynxPoint XHCI - ports are not switchable */
1425                                 /* Un-route all ports from the XHCI */
1426                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1427                         }
1428                         DPRINTF("Could not set address "
1429                             "for slot %u.\n", index);
1430                         if (address != 0)
1431                                 break;
1432                 }
1433
1434                 /* update device address to new value */
1435
1436                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1437                 pdev = buf_dev.buffer;
1438                 usb_pc_cpu_invalidate(&hdev->device_pc);
1439
1440                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1441                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1442
1443                 /* update device state to new value */
1444
1445                 if (address != 0)
1446                         hdev->state = XHCI_ST_ADDRESSED;
1447                 else
1448                         hdev->state = XHCI_ST_DEFAULT;
1449                 break;
1450
1451         default:
1452                 DPRINTF("Wrong state for set address.\n");
1453                 err = USB_ERR_IOERROR;
1454                 break;
1455         }
1456         XHCI_CMD_UNLOCK(sc);
1457
1458         if (mtx != NULL)
1459                 mtx_lock(mtx);
1460
1461         return (err);
1462 }
1463
1464 static usb_error_t
1465 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1466     uint8_t deconfigure, uint8_t slot_id)
1467 {
1468         struct xhci_trb trb;
1469         uint32_t temp;
1470
1471         DPRINTF("\n");
1472
1473         trb.qwTrb0 = htole64(input_ctx);
1474         trb.dwTrb2 = 0;
1475         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1476             XHCI_TRB_3_SLOT_SET(slot_id);
1477
1478         if (deconfigure)
1479                 temp |= XHCI_TRB_3_DCEP_BIT;
1480
1481         trb.dwTrb3 = htole32(temp);
1482
1483         return (xhci_do_command(sc, &trb, 100 /* ms */));
1484 }
1485
1486 static usb_error_t
1487 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1488     uint8_t slot_id)
1489 {
1490         struct xhci_trb trb;
1491         uint32_t temp;
1492
1493         DPRINTF("\n");
1494
1495         trb.qwTrb0 = htole64(input_ctx);
1496         trb.dwTrb2 = 0;
1497         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1498             XHCI_TRB_3_SLOT_SET(slot_id);
1499         trb.dwTrb3 = htole32(temp);
1500
1501         return (xhci_do_command(sc, &trb, 100 /* ms */));
1502 }
1503
1504 static usb_error_t
1505 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1506     uint8_t ep_id, uint8_t slot_id)
1507 {
1508         struct xhci_trb trb;
1509         uint32_t temp;
1510
1511         DPRINTF("\n");
1512
1513         trb.qwTrb0 = 0;
1514         trb.dwTrb2 = 0;
1515         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1516             XHCI_TRB_3_SLOT_SET(slot_id) |
1517             XHCI_TRB_3_EP_SET(ep_id);
1518
1519         if (preserve)
1520                 temp |= XHCI_TRB_3_PRSV_BIT;
1521
1522         trb.dwTrb3 = htole32(temp);
1523
1524         return (xhci_do_command(sc, &trb, 100 /* ms */));
1525 }
1526
1527 static usb_error_t
1528 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1529     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1530 {
1531         struct xhci_trb trb;
1532         uint32_t temp;
1533
1534         DPRINTF("\n");
1535
1536         trb.qwTrb0 = htole64(dequeue_ptr);
1537
1538         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1539         trb.dwTrb2 = htole32(temp);
1540
1541         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1542             XHCI_TRB_3_SLOT_SET(slot_id) |
1543             XHCI_TRB_3_EP_SET(ep_id);
1544         trb.dwTrb3 = htole32(temp);
1545
1546         return (xhci_do_command(sc, &trb, 100 /* ms */));
1547 }
1548
1549 static usb_error_t
1550 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1551     uint8_t ep_id, uint8_t slot_id)
1552 {
1553         struct xhci_trb trb;
1554         uint32_t temp;
1555
1556         DPRINTF("\n");
1557
1558         trb.qwTrb0 = 0;
1559         trb.dwTrb2 = 0;
1560         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1561             XHCI_TRB_3_SLOT_SET(slot_id) |
1562             XHCI_TRB_3_EP_SET(ep_id);
1563
1564         if (suspend)
1565                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1566
1567         trb.dwTrb3 = htole32(temp);
1568
1569         return (xhci_do_command(sc, &trb, 100 /* ms */));
1570 }
1571
1572 static usb_error_t
1573 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1574 {
1575         struct xhci_trb trb;
1576         uint32_t temp;
1577
1578         DPRINTF("\n");
1579
1580         trb.qwTrb0 = 0;
1581         trb.dwTrb2 = 0;
1582         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1583             XHCI_TRB_3_SLOT_SET(slot_id);
1584
1585         trb.dwTrb3 = htole32(temp);
1586
1587         return (xhci_do_command(sc, &trb, 100 /* ms */));
1588 }
1589
1590 /*------------------------------------------------------------------------*
1591  *      xhci_interrupt - XHCI interrupt handler
1592  *------------------------------------------------------------------------*/
1593 void
1594 xhci_interrupt(struct xhci_softc *sc)
1595 {
1596         uint32_t status;
1597         uint32_t temp;
1598
1599         USB_BUS_LOCK(&sc->sc_bus);
1600
1601         status = XREAD4(sc, oper, XHCI_USBSTS);
1602
1603         /* acknowledge interrupts, if any */
1604         if (status != 0) {
1605                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1606                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1607         }
1608
1609         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1610
1611         /* force clearing of pending interrupts */
1612         if (temp & XHCI_IMAN_INTR_PEND)
1613                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1614
1615         /* check for event(s) */
1616         xhci_interrupt_poll(sc);
1617
1618         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1619             XHCI_STS_HSE | XHCI_STS_HCE)) {
1620
1621                 if (status & XHCI_STS_PCD) {
1622                         xhci_root_intr(sc);
1623                 }
1624
1625                 if (status & XHCI_STS_HCH) {
1626                         printf("%s: host controller halted\n",
1627                             __FUNCTION__);
1628                 }
1629
1630                 if (status & XHCI_STS_HSE) {
1631                         printf("%s: host system error\n",
1632                             __FUNCTION__);
1633                 }
1634
1635                 if (status & XHCI_STS_HCE) {
1636                         printf("%s: host controller error\n",
1637                            __FUNCTION__);
1638                 }
1639         }
1640         USB_BUS_UNLOCK(&sc->sc_bus);
1641 }
1642
1643 /*------------------------------------------------------------------------*
1644  *      xhci_timeout - XHCI timeout handler
1645  *------------------------------------------------------------------------*/
1646 static void
1647 xhci_timeout(void *arg)
1648 {
1649         struct usb_xfer *xfer = arg;
1650
1651         DPRINTF("xfer=%p\n", xfer);
1652
1653         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1654
1655         /* transfer is transferred */
1656         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1657 }
1658
1659 static void
1660 xhci_do_poll(struct usb_bus *bus)
1661 {
1662         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1663
1664         USB_BUS_LOCK(&sc->sc_bus);
1665         xhci_interrupt_poll(sc);
1666         USB_BUS_UNLOCK(&sc->sc_bus);
1667 }
1668
1669 static void
1670 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1671 {
1672         struct usb_page_search buf_res;
1673         struct xhci_td *td;
1674         struct xhci_td *td_next;
1675         struct xhci_td *td_alt_next;
1676         struct xhci_td *td_first;
1677         uint32_t buf_offset;
1678         uint32_t average;
1679         uint32_t len_old;
1680         uint32_t npkt_off;
1681         uint32_t dword;
1682         uint8_t shortpkt_old;
1683         uint8_t precompute;
1684         uint8_t x;
1685
1686         td_alt_next = NULL;
1687         buf_offset = 0;
1688         shortpkt_old = temp->shortpkt;
1689         len_old = temp->len;
1690         npkt_off = 0;
1691         precompute = 1;
1692
1693 restart:
1694
1695         td = temp->td;
1696         td_next = td_first = temp->td_next;
1697
1698         while (1) {
1699
1700                 if (temp->len == 0) {
1701
1702                         if (temp->shortpkt)
1703                                 break;
1704
1705                         /* send a Zero Length Packet, ZLP, last */
1706
1707                         temp->shortpkt = 1;
1708                         average = 0;
1709
1710                 } else {
1711
1712                         average = temp->average;
1713
1714                         if (temp->len < average) {
1715                                 if (temp->len % temp->max_packet_size) {
1716                                         temp->shortpkt = 1;
1717                                 }
1718                                 average = temp->len;
1719                         }
1720                 }
1721
1722                 if (td_next == NULL)
1723                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1724
1725                 /* get next TD */
1726
1727                 td = td_next;
1728                 td_next = td->obj_next;
1729
1730                 /* check if we are pre-computing */
1731
1732                 if (precompute) {
1733
1734                         /* update remaining length */
1735
1736                         temp->len -= average;
1737
1738                         continue;
1739                 }
1740                 /* fill out current TD */
1741
1742                 td->len = average;
1743                 td->remainder = 0;
1744                 td->status = 0;
1745
1746                 /* update remaining length */
1747
1748                 temp->len -= average;
1749
1750                 /* reset TRB index */
1751
1752                 x = 0;
1753
1754                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1755                         /* immediate data */
1756
1757                         if (average > 8)
1758                                 average = 8;
1759
1760                         td->td_trb[0].qwTrb0 = 0;
1761
1762                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1763                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1764                            average);
1765
1766                         dword = XHCI_TRB_2_BYTES_SET(8) |
1767                             XHCI_TRB_2_TDSZ_SET(0) |
1768                             XHCI_TRB_2_IRQ_SET(0);
1769
1770                         td->td_trb[0].dwTrb2 = htole32(dword);
1771
1772                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1773                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1774
1775                         /* check wLength */
1776                         if (td->td_trb[0].qwTrb0 &
1777                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1778                                 if (td->td_trb[0].qwTrb0 &
1779                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1780                                         dword |= XHCI_TRB_3_TRT_IN;
1781                                 else
1782                                         dword |= XHCI_TRB_3_TRT_OUT;
1783                         }
1784
1785                         td->td_trb[0].dwTrb3 = htole32(dword);
1786 #ifdef USB_DEBUG
1787                         xhci_dump_trb(&td->td_trb[x]);
1788 #endif
1789                         x++;
1790
1791                 } else do {
1792
1793                         uint32_t npkt;
1794
1795                         /* fill out buffer pointers */
1796
1797                         if (average == 0) {
1798                                 memset(&buf_res, 0, sizeof(buf_res));
1799                         } else {
1800                                 usbd_get_page(temp->pc, temp->offset +
1801                                     buf_offset, &buf_res);
1802
1803                                 /* get length to end of page */
1804                                 if (buf_res.length > average)
1805                                         buf_res.length = average;
1806
1807                                 /* check for maximum length */
1808                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1809                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1810
1811                                 npkt_off += buf_res.length;
1812                         }
1813
1814                         /* setup npkt */
1815                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1816                             temp->max_packet_size;
1817
1818                         if (npkt == 0)
1819                                 npkt = 1;
1820                         else if (npkt > 31)
1821                                 npkt = 31;
1822
1823                         /* fill out TRB's */
1824                         td->td_trb[x].qwTrb0 =
1825                             htole64((uint64_t)buf_res.physaddr);
1826
1827                         dword =
1828                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1829                           XHCI_TRB_2_TDSZ_SET(npkt) |
1830                           XHCI_TRB_2_IRQ_SET(0);
1831
1832                         td->td_trb[x].dwTrb2 = htole32(dword);
1833
1834                         switch (temp->trb_type) {
1835                         case XHCI_TRB_TYPE_ISOCH:
1836                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1837                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1838                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1839                                 if (td != td_first) {
1840                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1841                                 } else if (temp->do_isoc_sync != 0) {
1842                                         temp->do_isoc_sync = 0;
1843                                         /* wait until "isoc_frame" */
1844                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1845                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1846                                 } else {
1847                                         /* start data transfer at next interval */
1848                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1849                                             XHCI_TRB_3_ISO_SIA_BIT;
1850                                 }
1851                                 if (temp->direction == UE_DIR_IN)
1852                                         dword |= XHCI_TRB_3_ISP_BIT;
1853                                 break;
1854                         case XHCI_TRB_TYPE_DATA_STAGE:
1855                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1856                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1857                                 if (temp->direction == UE_DIR_IN)
1858                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1859                                 break;
1860                         case XHCI_TRB_TYPE_STATUS_STAGE:
1861                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1862                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1863                                 if (temp->direction == UE_DIR_IN)
1864                                         dword |= XHCI_TRB_3_DIR_IN;
1865                                 break;
1866                         default:        /* XHCI_TRB_TYPE_NORMAL */
1867                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1868                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1869                                 if (temp->direction == UE_DIR_IN)
1870                                         dword |= XHCI_TRB_3_ISP_BIT;
1871                                 break;
1872                         }
1873                         td->td_trb[x].dwTrb3 = htole32(dword);
1874
1875                         average -= buf_res.length;
1876                         buf_offset += buf_res.length;
1877 #ifdef USB_DEBUG
1878                         xhci_dump_trb(&td->td_trb[x]);
1879 #endif
1880                         x++;
1881
1882                 } while (average != 0);
1883
1884                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1885
1886                 /* store number of data TRB's */
1887
1888                 td->ntrb = x;
1889
1890                 DPRINTF("NTRB=%u\n", x);
1891
1892                 /* fill out link TRB */
1893
1894                 if (td_next != NULL) {
1895                         /* link the current TD with the next one */
1896                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1897                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1898                 } else {
1899                         /* this field will get updated later */
1900                         DPRINTF("NOLINK\n");
1901                 }
1902
1903                 dword = XHCI_TRB_2_IRQ_SET(0);
1904
1905                 td->td_trb[x].dwTrb2 = htole32(dword);
1906
1907                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1908                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1909                     /*
1910                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1911                      * frame only receives a single short packet event
1912                      * by setting the CHAIN bit in the LINK field. In
1913                      * addition some XHCI controllers have problems
1914                      * sending a ZLP unless the CHAIN-BIT is set in
1915                      * the LINK TRB.
1916                      */
1917                     XHCI_TRB_3_CHAIN_BIT;
1918
1919                 td->td_trb[x].dwTrb3 = htole32(dword);
1920
1921                 td->alt_next = td_alt_next;
1922 #ifdef USB_DEBUG
1923                 xhci_dump_trb(&td->td_trb[x]);
1924 #endif
1925                 usb_pc_cpu_flush(td->page_cache);
1926         }
1927
1928         if (precompute) {
1929                 precompute = 0;
1930
1931                 /* setup alt next pointer, if any */
1932                 if (temp->last_frame) {
1933                         td_alt_next = NULL;
1934                 } else {
1935                         /* we use this field internally */
1936                         td_alt_next = td_next;
1937                 }
1938
1939                 /* restore */
1940                 temp->shortpkt = shortpkt_old;
1941                 temp->len = len_old;
1942                 goto restart;
1943         }
1944
1945         /*
1946          * Remove cycle bit from the first TRB if we are
1947          * stepping them:
1948          */
1949         if (temp->step_td != 0) {
1950                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1951                 usb_pc_cpu_flush(td_first->page_cache);
1952         }
1953
1954         /* clear TD SIZE to zero, hence this is the last TRB */
1955         /* remove chain bit because this is the last data TRB in the chain */
1956         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1957         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1958         /* remove CHAIN-BIT from last LINK TRB */
1959         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1960
1961         usb_pc_cpu_flush(td->page_cache);
1962
1963         temp->td = td;
1964         temp->td_next = td_next;
1965 }
1966
1967 static void
1968 xhci_setup_generic_chain(struct usb_xfer *xfer)
1969 {
1970         struct xhci_std_temp temp;
1971         struct xhci_td *td;
1972         uint32_t x;
1973         uint32_t y;
1974         uint8_t mult;
1975
1976         temp.do_isoc_sync = 0;
1977         temp.step_td = 0;
1978         temp.tbc = 0;
1979         temp.tlbpc = 0;
1980         temp.average = xfer->max_hc_frame_size;
1981         temp.max_packet_size = xfer->max_packet_size;
1982         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1983         temp.pc = NULL;
1984         temp.last_frame = 0;
1985         temp.offset = 0;
1986         temp.multishort = xfer->flags_int.isochronous_xfr ||
1987             xfer->flags_int.control_xfr ||
1988             xfer->flags_int.short_frames_ok;
1989
1990         /* toggle the DMA set we are using */
1991         xfer->flags_int.curr_dma_set ^= 1;
1992
1993         /* get next DMA set */
1994         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1995
1996         temp.td = NULL;
1997         temp.td_next = td;
1998
1999         xfer->td_transfer_first = td;
2000         xfer->td_transfer_cache = td;
2001
2002         if (xfer->flags_int.isochronous_xfr) {
2003                 uint8_t shift;
2004
2005                 /* compute multiplier for ISOCHRONOUS transfers */
2006                 mult = xfer->endpoint->ecomp ?
2007                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2008                     : 0;
2009                 /* check for USB 2.0 multiplier */
2010                 if (mult == 0) {
2011                         mult = (xfer->endpoint->edesc->
2012                             wMaxPacketSize[1] >> 3) & 3;
2013                 }
2014                 /* range check */
2015                 if (mult > 2)
2016                         mult = 3;
2017                 else
2018                         mult++;
2019
2020                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2021
2022                 DPRINTF("MFINDEX=0x%08x\n", x);
2023
2024                 switch (usbd_get_speed(xfer->xroot->udev)) {
2025                 case USB_SPEED_FULL:
2026                         shift = 3;
2027                         temp.isoc_delta = 8;    /* 1ms */
2028                         x += temp.isoc_delta - 1;
2029                         x &= ~(temp.isoc_delta - 1);
2030                         break;
2031                 default:
2032                         shift = usbd_xfer_get_fps_shift(xfer);
2033                         temp.isoc_delta = 1U << shift;
2034                         x += temp.isoc_delta - 1;
2035                         x &= ~(temp.isoc_delta - 1);
2036                         /* simple frame load balancing */
2037                         x += xfer->endpoint->usb_uframe;
2038                         break;
2039                 }
2040
2041                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2042
2043                 if ((xfer->endpoint->is_synced == 0) ||
2044                     (y < (xfer->nframes << shift)) ||
2045                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2046                         /*
2047                          * If there is data underflow or the pipe
2048                          * queue is empty we schedule the transfer a
2049                          * few frames ahead of the current frame
2050                          * position. Else two isochronous transfers
2051                          * might overlap.
2052                          */
2053                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2054                         xfer->endpoint->is_synced = 1;
2055                         temp.do_isoc_sync = 1;
2056
2057                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2058                 }
2059
2060                 /* compute isochronous completion time */
2061
2062                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2063
2064                 xfer->isoc_time_complete =
2065                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2066                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2067
2068                 x = 0;
2069                 temp.isoc_frame = xfer->endpoint->isoc_next;
2070                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2071
2072                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2073
2074         } else if (xfer->flags_int.control_xfr) {
2075
2076                 /* check if we should prepend a setup message */
2077
2078                 if (xfer->flags_int.control_hdr) {
2079
2080                         temp.len = xfer->frlengths[0];
2081                         temp.pc = xfer->frbuffers + 0;
2082                         temp.shortpkt = temp.len ? 1 : 0;
2083                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2084                         temp.direction = 0;
2085
2086                         /* check for last frame */
2087                         if (xfer->nframes == 1) {
2088                                 /* no STATUS stage yet, SETUP is last */
2089                                 if (xfer->flags_int.control_act)
2090                                         temp.last_frame = 1;
2091                         }
2092
2093                         xhci_setup_generic_chain_sub(&temp);
2094                 }
2095                 x = 1;
2096                 mult = 1;
2097                 temp.isoc_delta = 0;
2098                 temp.isoc_frame = 0;
2099                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2100         } else {
2101                 x = 0;
2102                 mult = 1;
2103                 temp.isoc_delta = 0;
2104                 temp.isoc_frame = 0;
2105                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2106         }
2107
2108         if (x != xfer->nframes) {
2109                 /* setup page_cache pointer */
2110                 temp.pc = xfer->frbuffers + x;
2111                 /* set endpoint direction */
2112                 temp.direction = UE_GET_DIR(xfer->endpointno);
2113         }
2114
2115         while (x != xfer->nframes) {
2116
2117                 /* DATA0 / DATA1 message */
2118
2119                 temp.len = xfer->frlengths[x];
2120                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2121                     x != 0 && temp.multishort == 0);
2122
2123                 x++;
2124
2125                 if (x == xfer->nframes) {
2126                         if (xfer->flags_int.control_xfr) {
2127                                 /* no STATUS stage yet, DATA is last */
2128                                 if (xfer->flags_int.control_act)
2129                                         temp.last_frame = 1;
2130                         } else {
2131                                 temp.last_frame = 1;
2132                         }
2133                 }
2134                 if (temp.len == 0) {
2135
2136                         /* make sure that we send an USB packet */
2137
2138                         temp.shortpkt = 0;
2139
2140                         temp.tbc = 0;
2141                         temp.tlbpc = mult - 1;
2142
2143                 } else if (xfer->flags_int.isochronous_xfr) {
2144
2145                         uint8_t tdpc;
2146
2147                         /*
2148                          * Isochronous transfers don't have short
2149                          * packet termination:
2150                          */
2151
2152                         temp.shortpkt = 1;
2153
2154                         /* isochronous transfers have a transfer limit */
2155
2156                         if (temp.len > xfer->max_frame_size)
2157                                 temp.len = xfer->max_frame_size;
2158
2159                         /* compute TD packet count */
2160                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2161                             xfer->max_packet_size;
2162
2163                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2164                         temp.tlbpc = (tdpc % mult);
2165
2166                         if (temp.tlbpc == 0)
2167                                 temp.tlbpc = mult - 1;
2168                         else
2169                                 temp.tlbpc--;
2170                 } else {
2171
2172                         /* regular data transfer */
2173
2174                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2175                 }
2176
2177                 xhci_setup_generic_chain_sub(&temp);
2178
2179                 if (xfer->flags_int.isochronous_xfr) {
2180                         temp.offset += xfer->frlengths[x - 1];
2181                         temp.isoc_frame += temp.isoc_delta;
2182                 } else {
2183                         /* get next Page Cache pointer */
2184                         temp.pc = xfer->frbuffers + x;
2185                 }
2186         }
2187
2188         /* check if we should append a status stage */
2189
2190         if (xfer->flags_int.control_xfr &&
2191             !xfer->flags_int.control_act) {
2192
2193                 /*
2194                  * Send a DATA1 message and invert the current
2195                  * endpoint direction.
2196                  */
2197                 temp.step_td = (xfer->nframes != 0);
2198                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2199                 temp.len = 0;
2200                 temp.pc = NULL;
2201                 temp.shortpkt = 0;
2202                 temp.last_frame = 1;
2203                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2204
2205                 xhci_setup_generic_chain_sub(&temp);
2206         }
2207
2208         td = temp.td;
2209
2210         /* must have at least one frame! */
2211
2212         xfer->td_transfer_last = td;
2213
2214         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2215 }
2216
2217 static void
2218 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2219 {
2220         struct usb_page_search buf_res;
2221         struct xhci_dev_ctx_addr *pdctxa;
2222
2223         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2224
2225         pdctxa = buf_res.buffer;
2226
2227         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2228
2229         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2230
2231         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2232 }
2233
2234 static usb_error_t
2235 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2236 {
2237         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2238         struct usb_page_search buf_inp;
2239         struct xhci_input_dev_ctx *pinp;
2240         uint32_t temp;
2241         uint8_t index;
2242         uint8_t x;
2243
2244         index = udev->controller_slot_id;
2245
2246         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2247
2248         pinp = buf_inp.buffer;
2249
2250         if (drop) {
2251                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2252                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2253                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2254         } else {
2255                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2256                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2257
2258                 /* find most significant set bit */
2259                 for (x = 31; x != 1; x--) {
2260                         if (mask & (1 << x))
2261                                 break;
2262                 }
2263
2264                 /* adjust */
2265                 x--;
2266
2267                 /* figure out maximum */
2268                 if (x > sc->sc_hw.devs[index].context_num) {
2269                         sc->sc_hw.devs[index].context_num = x;
2270                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2271                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2272                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2273                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2274                 }
2275         }
2276         return (0);
2277 }
2278
2279 static usb_error_t
2280 xhci_configure_endpoint(struct usb_device *udev,
2281     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2282     uint16_t interval, uint8_t max_packet_count,
2283     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2284     uint16_t max_frame_size, uint8_t ep_mode)
2285 {
2286         struct usb_page_search buf_inp;
2287         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2288         struct xhci_input_dev_ctx *pinp;
2289         uint64_t ring_addr = pepext->physaddr;
2290         uint32_t temp;
2291         uint8_t index;
2292         uint8_t epno;
2293         uint8_t type;
2294
2295         index = udev->controller_slot_id;
2296
2297         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2298
2299         pinp = buf_inp.buffer;
2300
2301         epno = edesc->bEndpointAddress;
2302         type = edesc->bmAttributes & UE_XFERTYPE;
2303
2304         if (type == UE_CONTROL)
2305                 epno |= UE_DIR_IN;
2306
2307         epno = XHCI_EPNO2EPID(epno);
2308
2309         if (epno == 0)
2310                 return (USB_ERR_NO_PIPE);               /* invalid */
2311
2312         if (max_packet_count == 0)
2313                 return (USB_ERR_BAD_BUFSIZE);
2314
2315         max_packet_count--;
2316
2317         if (mult == 0)
2318                 return (USB_ERR_BAD_BUFSIZE);
2319
2320         /* store endpoint mode */
2321         pepext->trb_ep_mode = ep_mode;
2322         usb_pc_cpu_flush(pepext->page_cache);
2323
2324         if (ep_mode == USB_EP_MODE_STREAMS) {
2325                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2326                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2327                     XHCI_EPCTX_0_LSA_SET(1);
2328
2329                 ring_addr += sizeof(struct xhci_trb) *
2330                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2331         } else {
2332                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2333                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2334                     XHCI_EPCTX_0_LSA_SET(0);
2335
2336                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2337         }
2338
2339         switch (udev->speed) {
2340         case USB_SPEED_FULL:
2341         case USB_SPEED_LOW:
2342                 /* 1ms -> 125us */
2343                 fps_shift += 3;
2344                 break;
2345         default:
2346                 break;
2347         }
2348
2349         switch (type) {
2350         case UE_INTERRUPT:
2351                 if (fps_shift > 3)
2352                         fps_shift--;
2353                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2354                 break;
2355         case UE_ISOCHRONOUS:
2356                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2357
2358                 switch (udev->speed) {
2359                 case USB_SPEED_SUPER:
2360                         if (mult > 3)
2361                                 mult = 3;
2362                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2363                         max_packet_count /= mult;
2364                         break;
2365                 default:
2366                         break;
2367                 }
2368                 break;
2369         default:
2370                 break;
2371         }
2372
2373         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2374
2375         temp =
2376             XHCI_EPCTX_1_HID_SET(0) |
2377             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2378             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2379
2380         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2381                 if (type != UE_ISOCHRONOUS)
2382                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2383         }
2384
2385         switch (type) {
2386         case UE_CONTROL:
2387                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2388                 break;
2389         case UE_ISOCHRONOUS:
2390                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2391                 break;
2392         case UE_BULK:
2393                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2394                 break;
2395         default:
2396                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2397                 break;
2398         }
2399
2400         /* check for IN direction */
2401         if (epno & 1)
2402                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2403
2404         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2405         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2406
2407         switch (edesc->bmAttributes & UE_XFERTYPE) {
2408         case UE_INTERRUPT:
2409         case UE_ISOCHRONOUS:
2410                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2411                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2412                     max_frame_size));
2413                 break;
2414         case UE_CONTROL:
2415                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2416                 break;
2417         default:
2418                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2419                 break;
2420         }
2421
2422         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2423
2424 #ifdef USB_DEBUG
2425         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2426 #endif
2427         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2428
2429         return (0);             /* success */
2430 }
2431
2432 static usb_error_t
2433 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2434 {
2435         struct xhci_endpoint_ext *pepext;
2436         struct usb_endpoint_ss_comp_descriptor *ecomp;
2437         usb_stream_t x;
2438
2439         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2440             xfer->endpoint->edesc);
2441
2442         ecomp = xfer->endpoint->ecomp;
2443
2444         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2445                 uint64_t temp;
2446
2447                 /* halt any transfers */
2448                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2449
2450                 /* compute start of TRB ring for stream "x" */
2451                 temp = pepext->physaddr +
2452                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2453                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2454
2455                 /* make tree structure */
2456                 pepext->trb[(XHCI_MAX_TRANSFERS *
2457                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2458
2459                 /* reserved fields */
2460                 pepext->trb[(XHCI_MAX_TRANSFERS *
2461                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2462                 pepext->trb[(XHCI_MAX_TRANSFERS *
2463                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2464         }
2465         usb_pc_cpu_flush(pepext->page_cache);
2466
2467         return (xhci_configure_endpoint(xfer->xroot->udev,
2468             xfer->endpoint->edesc, pepext,
2469             xfer->interval, xfer->max_packet_count,
2470             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2471             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2472             xfer->max_frame_size, xfer->endpoint->ep_mode));
2473 }
2474
2475 static usb_error_t
2476 xhci_configure_device(struct usb_device *udev)
2477 {
2478         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2479         struct usb_page_search buf_inp;
2480         struct usb_page_cache *pcinp;
2481         struct xhci_input_dev_ctx *pinp;
2482         struct usb_device *hubdev;
2483         uint32_t temp;
2484         uint32_t route;
2485         uint32_t rh_port;
2486         uint8_t is_hub;
2487         uint8_t index;
2488         uint8_t depth;
2489
2490         index = udev->controller_slot_id;
2491
2492         DPRINTF("index=%u\n", index);
2493
2494         pcinp = &sc->sc_hw.devs[index].input_pc;
2495
2496         usbd_get_page(pcinp, 0, &buf_inp);
2497
2498         pinp = buf_inp.buffer;
2499
2500         rh_port = 0;
2501         route = 0;
2502
2503         /* figure out route string and root HUB port number */
2504
2505         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2506
2507                 if (hubdev->parent_hub == NULL)
2508                         break;
2509
2510                 depth = hubdev->parent_hub->depth;
2511
2512                 /*
2513                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2514                  * more than 15 ports
2515                  */
2516
2517                 rh_port = hubdev->port_no;
2518
2519                 if (depth == 0)
2520                         break;
2521
2522                 if (rh_port > 15)
2523                         rh_port = 15;
2524
2525                 if (depth < 6)
2526                         route |= rh_port << (4 * (depth - 1));
2527         }
2528
2529         DPRINTF("Route=0x%08x\n", route);
2530
2531         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2532             XHCI_SCTX_0_CTX_NUM_SET(
2533             sc->sc_hw.devs[index].context_num + 1);
2534
2535         switch (udev->speed) {
2536         case USB_SPEED_LOW:
2537                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2538                 if (udev->parent_hs_hub != NULL &&
2539                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2540                     UDPROTO_HSHUBMTT) {
2541                         DPRINTF("Device inherits MTT\n");
2542                         temp |= XHCI_SCTX_0_MTT_SET(1);
2543                 }
2544                 break;
2545         case USB_SPEED_HIGH:
2546                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2547                 if (sc->sc_hw.devs[index].nports != 0 &&
2548                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2549                         DPRINTF("HUB supports MTT\n");
2550                         temp |= XHCI_SCTX_0_MTT_SET(1);
2551                 }
2552                 break;
2553         case USB_SPEED_FULL:
2554                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2555                 if (udev->parent_hs_hub != NULL &&
2556                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2557                     UDPROTO_HSHUBMTT) {
2558                         DPRINTF("Device inherits MTT\n");
2559                         temp |= XHCI_SCTX_0_MTT_SET(1);
2560                 }
2561                 break;
2562         default:
2563                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2564                 break;
2565         }
2566
2567         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2568             (udev->speed == USB_SPEED_SUPER ||
2569             udev->speed == USB_SPEED_HIGH);
2570
2571         if (is_hub)
2572                 temp |= XHCI_SCTX_0_HUB_SET(1);
2573
2574         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2575
2576         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2577
2578         if (is_hub) {
2579                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2580                     sc->sc_hw.devs[index].nports);
2581         }
2582
2583         switch (udev->speed) {
2584         case USB_SPEED_SUPER:
2585                 switch (sc->sc_hw.devs[index].state) {
2586                 case XHCI_ST_ADDRESSED:
2587                 case XHCI_ST_CONFIGURED:
2588                         /* enable power save */
2589                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2590                         break;
2591                 default:
2592                         /* disable power save */
2593                         break;
2594                 }
2595                 break;
2596         default:
2597                 break;
2598         }
2599
2600         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2601
2602         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2603
2604         if (is_hub) {
2605                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2606                     sc->sc_hw.devs[index].tt);
2607         }
2608
2609         hubdev = udev->parent_hs_hub;
2610
2611         /* check if we should activate the transaction translator */
2612         switch (udev->speed) {
2613         case USB_SPEED_FULL:
2614         case USB_SPEED_LOW:
2615                 if (hubdev != NULL) {
2616                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2617                             hubdev->controller_slot_id);
2618                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2619                             udev->hs_port_no);
2620                 }
2621                 break;
2622         default:
2623                 break;
2624         }
2625
2626         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2627
2628         /*
2629          * These fields should be initialized to zero, according to
2630          * XHCI section 6.2.2 - slot context:
2631          */
2632         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2633             XHCI_SCTX_3_SLOT_STATE_SET(0);
2634
2635         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2636
2637 #ifdef USB_DEBUG
2638         xhci_dump_device(sc, &pinp->ctx_slot);
2639 #endif
2640         usb_pc_cpu_flush(pcinp);
2641
2642         return (0);             /* success */
2643 }
2644
2645 static usb_error_t
2646 xhci_alloc_device_ext(struct usb_device *udev)
2647 {
2648         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2649         struct usb_page_search buf_dev;
2650         struct usb_page_search buf_ep;
2651         struct xhci_trb *trb;
2652         struct usb_page_cache *pc;
2653         struct usb_page *pg;
2654         uint64_t addr;
2655         uint8_t index;
2656         uint8_t i;
2657
2658         index = udev->controller_slot_id;
2659
2660         pc = &sc->sc_hw.devs[index].device_pc;
2661         pg = &sc->sc_hw.devs[index].device_pg;
2662
2663         /* need to initialize the page cache */
2664         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2665
2666         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2667             (2 * sizeof(struct xhci_dev_ctx)) :
2668             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2669                 goto error;
2670
2671         usbd_get_page(pc, 0, &buf_dev);
2672
2673         pc = &sc->sc_hw.devs[index].input_pc;
2674         pg = &sc->sc_hw.devs[index].input_pg;
2675
2676         /* need to initialize the page cache */
2677         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2678
2679         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2680             (2 * sizeof(struct xhci_input_dev_ctx)) :
2681             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2682                 goto error;
2683         }
2684
2685         pc = &sc->sc_hw.devs[index].endpoint_pc;
2686         pg = &sc->sc_hw.devs[index].endpoint_pg;
2687
2688         /* need to initialize the page cache */
2689         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2690
2691         if (usb_pc_alloc_mem(pc, pg,
2692             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2693                 goto error;
2694         }
2695
2696         /* initialise all endpoint LINK TRBs */
2697
2698         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2699
2700                 /* lookup endpoint TRB ring */
2701                 usbd_get_page(pc, (uintptr_t)&
2702                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2703
2704                 /* get TRB pointer */
2705                 trb = buf_ep.buffer;
2706                 trb += XHCI_MAX_TRANSFERS - 1;
2707
2708                 /* get TRB start address */
2709                 addr = buf_ep.physaddr;
2710
2711                 /* create LINK TRB */
2712                 trb->qwTrb0 = htole64(addr);
2713                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2714                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2715                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2716         }
2717
2718         usb_pc_cpu_flush(pc);
2719
2720         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2721
2722         return (0);
2723
2724 error:
2725         xhci_free_device_ext(udev);
2726
2727         return (USB_ERR_NOMEM);
2728 }
2729
2730 static void
2731 xhci_free_device_ext(struct usb_device *udev)
2732 {
2733         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2734         uint8_t index;
2735
2736         index = udev->controller_slot_id;
2737         xhci_set_slot_pointer(sc, index, 0);
2738
2739         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2740         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2741         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2742 }
2743
2744 static struct xhci_endpoint_ext *
2745 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2746 {
2747         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2748         struct xhci_endpoint_ext *pepext;
2749         struct usb_page_cache *pc;
2750         struct usb_page_search buf_ep;
2751         uint8_t epno;
2752         uint8_t index;
2753
2754         epno = edesc->bEndpointAddress;
2755         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2756                 epno |= UE_DIR_IN;
2757
2758         epno = XHCI_EPNO2EPID(epno);
2759
2760         index = udev->controller_slot_id;
2761
2762         pc = &sc->sc_hw.devs[index].endpoint_pc;
2763
2764         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->
2765             trb[epno][0], &buf_ep);
2766
2767         pepext = &sc->sc_hw.devs[index].endp[epno];
2768         pepext->page_cache = pc;
2769         pepext->trb = buf_ep.buffer;
2770         pepext->physaddr = buf_ep.physaddr;
2771
2772         return (pepext);
2773 }
2774
2775 static void
2776 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2777 {
2778         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2779         uint8_t epno;
2780         uint8_t index;
2781
2782         epno = xfer->endpointno;
2783         if (xfer->flags_int.control_xfr)
2784                 epno |= UE_DIR_IN;
2785
2786         epno = XHCI_EPNO2EPID(epno);
2787         index = xfer->xroot->udev->controller_slot_id;
2788
2789         if (xfer->xroot->udev->flags.self_suspended == 0) {
2790                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2791                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2792         }
2793 }
2794
2795 static void
2796 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2797 {
2798         struct xhci_endpoint_ext *pepext;
2799
2800         if (xfer->flags_int.bandwidth_reclaimed) {
2801                 xfer->flags_int.bandwidth_reclaimed = 0;
2802
2803                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2804                     xfer->endpoint->edesc);
2805
2806                 pepext->trb_used[xfer->stream_id]--;
2807
2808                 pepext->xfer[xfer->qh_pos] = NULL;
2809
2810                 if (error && pepext->trb_running != 0) {
2811                         pepext->trb_halted = 1;
2812                         pepext->trb_running = 0;
2813                 }
2814         }
2815 }
2816
2817 static usb_error_t
2818 xhci_transfer_insert(struct usb_xfer *xfer)
2819 {
2820         struct xhci_td *td_first;
2821         struct xhci_td *td_last;
2822         struct xhci_trb *trb_link;
2823         struct xhci_endpoint_ext *pepext;
2824         uint64_t addr;
2825         usb_stream_t id;
2826         uint8_t i;
2827         uint8_t inext;
2828         uint8_t trb_limit;
2829
2830         DPRINTFN(8, "\n");
2831
2832         id = xfer->stream_id;
2833
2834         /* check if already inserted */
2835         if (xfer->flags_int.bandwidth_reclaimed) {
2836                 DPRINTFN(8, "Already in schedule\n");
2837                 return (0);
2838         }
2839
2840         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2841             xfer->endpoint->edesc);
2842
2843         td_first = xfer->td_transfer_first;
2844         td_last = xfer->td_transfer_last;
2845         addr = pepext->physaddr;
2846
2847         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2848         case UE_CONTROL:
2849         case UE_INTERRUPT:
2850                 /* single buffered */
2851                 trb_limit = 1;
2852                 break;
2853         default:
2854                 /* multi buffered */
2855                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2856                 break;
2857         }
2858
2859         if (pepext->trb_used[id] >= trb_limit) {
2860                 DPRINTFN(8, "Too many TDs queued.\n");
2861                 return (USB_ERR_NOMEM);
2862         }
2863
2864         /* check for stopped condition, after putting transfer on interrupt queue */
2865         if (pepext->trb_running == 0) {
2866                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2867
2868                 DPRINTFN(8, "Not running\n");
2869
2870                 /* start configuration */
2871                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2872                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2873                 return (0);
2874         }
2875
2876         pepext->trb_used[id]++;
2877
2878         /* get current TRB index */
2879         i = pepext->trb_index[id];
2880
2881         /* get next TRB index */
2882         inext = (i + 1);
2883
2884         /* the last entry of the ring is a hardcoded link TRB */
2885         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2886                 inext = 0;
2887
2888         /* store next TRB index, before stream ID offset is added */
2889         pepext->trb_index[id] = inext;
2890
2891         /* offset for stream */
2892         i += id * XHCI_MAX_TRANSFERS;
2893         inext += id * XHCI_MAX_TRANSFERS;
2894
2895         /* compute terminating return address */
2896         addr += (inext * sizeof(struct xhci_trb));
2897
2898         /* compute link TRB pointer */
2899         trb_link = td_last->td_trb + td_last->ntrb;
2900
2901         /* update next pointer of last link TRB */
2902         trb_link->qwTrb0 = htole64(addr);
2903         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2904         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2905             XHCI_TRB_3_CYCLE_BIT |
2906             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2907
2908 #ifdef USB_DEBUG
2909         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2910 #endif
2911         usb_pc_cpu_flush(td_last->page_cache);
2912
2913         /* write ahead chain end marker */
2914
2915         pepext->trb[inext].qwTrb0 = 0;
2916         pepext->trb[inext].dwTrb2 = 0;
2917         pepext->trb[inext].dwTrb3 = 0;
2918
2919         /* update next pointer of link TRB */
2920
2921         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2922         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2923
2924 #ifdef USB_DEBUG
2925         xhci_dump_trb(&pepext->trb[i]);
2926 #endif
2927         usb_pc_cpu_flush(pepext->page_cache);
2928
2929         /* toggle cycle bit which activates the transfer chain */
2930
2931         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2932             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2933
2934         usb_pc_cpu_flush(pepext->page_cache);
2935
2936         DPRINTF("qh_pos = %u\n", i);
2937
2938         pepext->xfer[i] = xfer;
2939
2940         xfer->qh_pos = i;
2941
2942         xfer->flags_int.bandwidth_reclaimed = 1;
2943
2944         xhci_endpoint_doorbell(xfer);
2945
2946         return (0);
2947 }
2948
2949 static void
2950 xhci_root_intr(struct xhci_softc *sc)
2951 {
2952         uint16_t i;
2953
2954         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2955
2956         /* clear any old interrupt data */
2957         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2958
2959         for (i = 1; i <= sc->sc_noport; i++) {
2960                 /* pick out CHANGE bits from the status register */
2961                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2962                     XHCI_PS_CSC | XHCI_PS_PEC |
2963                     XHCI_PS_OCC | XHCI_PS_WRC |
2964                     XHCI_PS_PRC | XHCI_PS_PLC |
2965                     XHCI_PS_CEC)) {
2966                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2967                         DPRINTF("port %d changed\n", i);
2968                 }
2969         }
2970         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2971             sizeof(sc->sc_hub_idata));
2972 }
2973
2974 /*------------------------------------------------------------------------*
2975  *      xhci_device_done - XHCI done handler
2976  *
2977  * NOTE: This function can be called two times in a row on
2978  * the same USB transfer. From close and from interrupt.
2979  *------------------------------------------------------------------------*/
2980 static void
2981 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2982 {
2983         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2984             xfer, xfer->endpoint, error);
2985
2986         /* remove transfer from HW queue */
2987         xhci_transfer_remove(xfer, error);
2988
2989         /* dequeue transfer and start next transfer */
2990         usbd_transfer_done(xfer, error);
2991 }
2992
2993 /*------------------------------------------------------------------------*
2994  * XHCI data transfer support (generic type)
2995  *------------------------------------------------------------------------*/
2996 static void
2997 xhci_device_generic_open(struct usb_xfer *xfer)
2998 {
2999         if (xfer->flags_int.isochronous_xfr) {
3000                 switch (xfer->xroot->udev->speed) {
3001                 case USB_SPEED_FULL:
3002                         break;
3003                 default:
3004                         usb_hs_bandwidth_alloc(xfer);
3005                         break;
3006                 }
3007         }
3008 }
3009
3010 static void
3011 xhci_device_generic_close(struct usb_xfer *xfer)
3012 {
3013         DPRINTF("\n");
3014
3015         xhci_device_done(xfer, USB_ERR_CANCELLED);
3016
3017         if (xfer->flags_int.isochronous_xfr) {
3018                 switch (xfer->xroot->udev->speed) {
3019                 case USB_SPEED_FULL:
3020                         break;
3021                 default:
3022                         usb_hs_bandwidth_free(xfer);
3023                         break;
3024                 }
3025         }
3026 }
3027
3028 static void
3029 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3030     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3031 {
3032         struct usb_xfer *xfer;
3033
3034         /* check if there is a current transfer */
3035         xfer = ep->endpoint_q[stream_id].curr;
3036         if (xfer == NULL)
3037                 return;
3038
3039         /*
3040          * Check if the current transfer is started and then pickup
3041          * the next one, if any. Else wait for next start event due to
3042          * block on failure feature.
3043          */
3044         if (!xfer->flags_int.bandwidth_reclaimed)
3045                 return;
3046
3047         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3048         if (xfer == NULL) {
3049                 /*
3050                  * In case of enter we have to consider that the
3051                  * transfer is queued by the USB core after the enter
3052                  * method is called.
3053                  */
3054                 xfer = enter_xfer;
3055
3056                 if (xfer == NULL)
3057                         return;
3058         }
3059
3060         /* try to multi buffer */
3061         xhci_transfer_insert(xfer);
3062 }
3063
3064 static void
3065 xhci_device_generic_enter(struct usb_xfer *xfer)
3066 {
3067         DPRINTF("\n");
3068
3069         /* setup TD's and QH */
3070         xhci_setup_generic_chain(xfer);
3071
3072         xhci_device_generic_multi_enter(xfer->endpoint,
3073             xfer->stream_id, xfer);
3074 }
3075
3076 static void
3077 xhci_device_generic_start(struct usb_xfer *xfer)
3078 {
3079         DPRINTF("\n");
3080
3081         /* try to insert xfer on HW queue */
3082         xhci_transfer_insert(xfer);
3083
3084         /* try to multi buffer */
3085         xhci_device_generic_multi_enter(xfer->endpoint,
3086             xfer->stream_id, NULL);
3087
3088         /* add transfer last on interrupt queue */
3089         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3090
3091         /* start timeout, if any */
3092         if (xfer->timeout != 0)
3093                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3094 }
3095
3096 struct usb_pipe_methods xhci_device_generic_methods =
3097 {
3098         .open = xhci_device_generic_open,
3099         .close = xhci_device_generic_close,
3100         .enter = xhci_device_generic_enter,
3101         .start = xhci_device_generic_start,
3102 };
3103
3104 /*------------------------------------------------------------------------*
3105  * xhci root HUB support
3106  *------------------------------------------------------------------------*
3107  * Simulate a hardware HUB by handling all the necessary requests.
3108  *------------------------------------------------------------------------*/
3109
3110 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3111
3112 static const
3113 struct usb_device_descriptor xhci_devd =
3114 {
3115         .bLength = sizeof(xhci_devd),
3116         .bDescriptorType = UDESC_DEVICE,        /* type */
3117         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3118         .bDeviceClass = UDCLASS_HUB,            /* class */
3119         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3120         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3121         .bMaxPacketSize = 9,                    /* max packet size */
3122         HSETW(.idVendor, 0x0000),               /* vendor */
3123         HSETW(.idProduct, 0x0000),              /* product */
3124         HSETW(.bcdDevice, 0x0100),              /* device version */
3125         .iManufacturer = 1,
3126         .iProduct = 2,
3127         .iSerialNumber = 0,
3128         .bNumConfigurations = 1,                /* # of configurations */
3129 };
3130
3131 static const
3132 struct xhci_bos_desc xhci_bosd = {
3133         .bosd = {
3134                 .bLength = sizeof(xhci_bosd.bosd),
3135                 .bDescriptorType = UDESC_BOS,
3136                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3137                 .bNumDeviceCaps = 3,
3138         },
3139         .usb2extd = {
3140                 .bLength = sizeof(xhci_bosd.usb2extd),
3141                 .bDescriptorType = 1,
3142                 .bDevCapabilityType = 2,
3143                 .bmAttributes[0] = 2,
3144         },
3145         .usbdcd = {
3146                 .bLength = sizeof(xhci_bosd.usbdcd),
3147                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3148                 .bDevCapabilityType = 3,
3149                 .bmAttributes = 0, /* XXX */
3150                 HSETW(.wSpeedsSupported, 0x000C),
3151                 .bFunctionalitySupport = 8,
3152                 .bU1DevExitLat = 255,   /* dummy - not used */
3153                 .wU2DevExitLat = { 0x00, 0x08 },
3154         },
3155         .cidd = {
3156                 .bLength = sizeof(xhci_bosd.cidd),
3157                 .bDescriptorType = 1,
3158                 .bDevCapabilityType = 4,
3159                 .bReserved = 0,
3160                 .bContainerID = 0, /* XXX */
3161         },
3162 };
3163
3164 static const
3165 struct xhci_config_desc xhci_confd = {
3166         .confd = {
3167                 .bLength = sizeof(xhci_confd.confd),
3168                 .bDescriptorType = UDESC_CONFIG,
3169                 .wTotalLength[0] = sizeof(xhci_confd),
3170                 .bNumInterface = 1,
3171                 .bConfigurationValue = 1,
3172                 .iConfiguration = 0,
3173                 .bmAttributes = UC_SELF_POWERED,
3174                 .bMaxPower = 0          /* max power */
3175         },
3176         .ifcd = {
3177                 .bLength = sizeof(xhci_confd.ifcd),
3178                 .bDescriptorType = UDESC_INTERFACE,
3179                 .bNumEndpoints = 1,
3180                 .bInterfaceClass = UICLASS_HUB,
3181                 .bInterfaceSubClass = UISUBCLASS_HUB,
3182                 .bInterfaceProtocol = 0,
3183         },
3184         .endpd = {
3185                 .bLength = sizeof(xhci_confd.endpd),
3186                 .bDescriptorType = UDESC_ENDPOINT,
3187                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3188                 .bmAttributes = UE_INTERRUPT,
3189                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3190                 .bInterval = 255,
3191         },
3192         .endpcd = {
3193                 .bLength = sizeof(xhci_confd.endpcd),
3194                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3195                 .bMaxBurst = 0,
3196                 .bmAttributes = 0,
3197         },
3198 };
3199
3200 static const
3201 struct usb_hub_ss_descriptor xhci_hubd = {
3202         .bLength = sizeof(xhci_hubd),
3203         .bDescriptorType = UDESC_SS_HUB,
3204 };
3205
3206 static usb_error_t
3207 xhci_roothub_exec(struct usb_device *udev,
3208     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3209 {
3210         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3211         const char *str_ptr;
3212         const void *ptr;
3213         uint32_t port;
3214         uint32_t v;
3215         uint16_t len;
3216         uint16_t i;
3217         uint16_t value;
3218         uint16_t index;
3219         uint8_t j;
3220         usb_error_t err;
3221
3222         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3223
3224         /* buffer reset */
3225         ptr = (const void *)&sc->sc_hub_desc;
3226         len = 0;
3227         err = 0;
3228
3229         value = UGETW(req->wValue);
3230         index = UGETW(req->wIndex);
3231
3232         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3233             "wValue=0x%04x wIndex=0x%04x\n",
3234             req->bmRequestType, req->bRequest,
3235             UGETW(req->wLength), value, index);
3236
3237 #define C(x,y) ((x) | ((y) << 8))
3238         switch (C(req->bRequest, req->bmRequestType)) {
3239         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3240         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3241         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3242                 /*
3243                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3244                  * for the integrated root hub.
3245                  */
3246                 break;
3247         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3248                 len = 1;
3249                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3250                 break;
3251         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3252                 switch (value >> 8) {
3253                 case UDESC_DEVICE:
3254                         if ((value & 0xff) != 0) {
3255                                 err = USB_ERR_IOERROR;
3256                                 goto done;
3257                         }
3258                         len = sizeof(xhci_devd);
3259                         ptr = (const void *)&xhci_devd;
3260                         break;
3261
3262                 case UDESC_BOS:
3263                         if ((value & 0xff) != 0) {
3264                                 err = USB_ERR_IOERROR;
3265                                 goto done;
3266                         }
3267                         len = sizeof(xhci_bosd);
3268                         ptr = (const void *)&xhci_bosd;
3269                         break;
3270
3271                 case UDESC_CONFIG:
3272                         if ((value & 0xff) != 0) {
3273                                 err = USB_ERR_IOERROR;
3274                                 goto done;
3275                         }
3276                         len = sizeof(xhci_confd);
3277                         ptr = (const void *)&xhci_confd;
3278                         break;
3279
3280                 case UDESC_STRING:
3281                         switch (value & 0xff) {
3282                         case 0: /* Language table */
3283                                 str_ptr = "\001";
3284                                 break;
3285
3286                         case 1: /* Vendor */
3287                                 str_ptr = sc->sc_vendor;
3288                                 break;
3289
3290                         case 2: /* Product */
3291                                 str_ptr = "XHCI root HUB";
3292                                 break;
3293
3294                         default:
3295                                 str_ptr = "";
3296                                 break;
3297                         }
3298
3299                         len = usb_make_str_desc(
3300                             sc->sc_hub_desc.temp,
3301                             sizeof(sc->sc_hub_desc.temp),
3302                             str_ptr);
3303                         break;
3304
3305                 default:
3306                         err = USB_ERR_IOERROR;
3307                         goto done;
3308                 }
3309                 break;
3310         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3311                 len = 1;
3312                 sc->sc_hub_desc.temp[0] = 0;
3313                 break;
3314         case C(UR_GET_STATUS, UT_READ_DEVICE):
3315                 len = 2;
3316                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3317                 break;
3318         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3319         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3320                 len = 2;
3321                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3322                 break;
3323         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3324                 if (value >= XHCI_MAX_DEVICES) {
3325                         err = USB_ERR_IOERROR;
3326                         goto done;
3327                 }
3328                 break;
3329         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3330                 if (value != 0 && value != 1) {
3331                         err = USB_ERR_IOERROR;
3332                         goto done;
3333                 }
3334                 sc->sc_conf = value;
3335                 break;
3336         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3337                 break;
3338         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3339         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3340         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3341                 err = USB_ERR_IOERROR;
3342                 goto done;
3343         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3344                 break;
3345         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3346                 break;
3347                 /* Hub requests */
3348         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3349                 break;
3350         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3351                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3352
3353                 if ((index < 1) ||
3354                     (index > sc->sc_noport)) {
3355                         err = USB_ERR_IOERROR;
3356                         goto done;
3357                 }
3358                 port = XHCI_PORTSC(index);
3359
3360                 v = XREAD4(sc, oper, port);
3361                 i = XHCI_PS_PLS_GET(v);
3362                 v &= ~XHCI_PS_CLEAR;
3363
3364                 switch (value) {
3365                 case UHF_C_BH_PORT_RESET:
3366                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3367                         break;
3368                 case UHF_C_PORT_CONFIG_ERROR:
3369                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3370                         break;
3371                 case UHF_C_PORT_SUSPEND:
3372                 case UHF_C_PORT_LINK_STATE:
3373                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3374                         break;
3375                 case UHF_C_PORT_CONNECTION:
3376                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3377                         break;
3378                 case UHF_C_PORT_ENABLE:
3379                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3380                         break;
3381                 case UHF_C_PORT_OVER_CURRENT:
3382                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3383                         break;
3384                 case UHF_C_PORT_RESET:
3385                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3386                         break;
3387                 case UHF_PORT_ENABLE:
3388                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3389                         break;
3390                 case UHF_PORT_POWER:
3391                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3392                         break;
3393                 case UHF_PORT_INDICATOR:
3394                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3395                         break;
3396                 case UHF_PORT_SUSPEND:
3397
3398                         /* U3 -> U15 */
3399                         if (i == 3) {
3400                                 XWRITE4(sc, oper, port, v |
3401                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3402                         }
3403
3404                         /* wait 20ms for resume sequence to complete */
3405                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3406
3407                         /* U0 */
3408                         XWRITE4(sc, oper, port, v |
3409                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3410                         break;
3411                 default:
3412                         err = USB_ERR_IOERROR;
3413                         goto done;
3414                 }
3415                 break;
3416
3417         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3418                 if ((value & 0xff) != 0) {
3419                         err = USB_ERR_IOERROR;
3420                         goto done;
3421                 }
3422
3423                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3424
3425                 sc->sc_hub_desc.hubd = xhci_hubd;
3426
3427                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3428
3429                 if (XHCI_HCS0_PPC(v))
3430                         i = UHD_PWR_INDIVIDUAL;
3431                 else
3432                         i = UHD_PWR_GANGED;
3433
3434                 if (XHCI_HCS0_PIND(v))
3435                         i |= UHD_PORT_IND;
3436
3437                 i |= UHD_OC_INDIVIDUAL;
3438
3439                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3440
3441                 /* see XHCI section 5.4.9: */
3442                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3443
3444                 for (j = 1; j <= sc->sc_noport; j++) {
3445
3446                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3447                         if (v & XHCI_PS_DR) {
3448                                 sc->sc_hub_desc.hubd.
3449                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3450                         }
3451                 }
3452                 len = sc->sc_hub_desc.hubd.bLength;
3453                 break;
3454
3455         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3456                 len = 16;
3457                 memset(sc->sc_hub_desc.temp, 0, 16);
3458                 break;
3459
3460         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3461                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3462
3463                 if ((index < 1) ||
3464                     (index > sc->sc_noport)) {
3465                         err = USB_ERR_IOERROR;
3466                         goto done;
3467                 }
3468
3469                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3470
3471                 DPRINTFN(9, "port status=0x%08x\n", v);
3472
3473                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3474
3475                 switch (XHCI_PS_SPEED_GET(v)) {
3476                 case 3:
3477                         i |= UPS_HIGH_SPEED;
3478                         break;
3479                 case 2:
3480                         i |= UPS_LOW_SPEED;
3481                         break;
3482                 case 1:
3483                         /* FULL speed */
3484                         break;
3485                 default:
3486                         i |= UPS_OTHER_SPEED;
3487                         break;
3488                 }
3489
3490                 if (v & XHCI_PS_CCS)
3491                         i |= UPS_CURRENT_CONNECT_STATUS;
3492                 if (v & XHCI_PS_PED)
3493                         i |= UPS_PORT_ENABLED;
3494                 if (v & XHCI_PS_OCA)
3495                         i |= UPS_OVERCURRENT_INDICATOR;
3496                 if (v & XHCI_PS_PR)
3497                         i |= UPS_RESET;
3498                 if (v & XHCI_PS_PP) {
3499                         /*
3500                          * The USB 3.0 RH is using the
3501                          * USB 2.0's power bit
3502                          */
3503                         i |= UPS_PORT_POWER;
3504                 }
3505                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3506
3507                 i = 0;
3508                 if (v & XHCI_PS_CSC)
3509                         i |= UPS_C_CONNECT_STATUS;
3510                 if (v & XHCI_PS_PEC)
3511                         i |= UPS_C_PORT_ENABLED;
3512                 if (v & XHCI_PS_OCC)
3513                         i |= UPS_C_OVERCURRENT_INDICATOR;
3514                 if (v & XHCI_PS_WRC)
3515                         i |= UPS_C_BH_PORT_RESET;
3516                 if (v & XHCI_PS_PRC)
3517                         i |= UPS_C_PORT_RESET;
3518                 if (v & XHCI_PS_PLC)
3519                         i |= UPS_C_PORT_LINK_STATE;
3520                 if (v & XHCI_PS_CEC)
3521                         i |= UPS_C_PORT_CONFIG_ERROR;
3522
3523                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3524                 len = sizeof(sc->sc_hub_desc.ps);
3525                 break;
3526
3527         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3528                 err = USB_ERR_IOERROR;
3529                 goto done;
3530
3531         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3532                 break;
3533
3534         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3535
3536                 i = index >> 8;
3537                 index &= 0x00FF;
3538
3539                 if ((index < 1) ||
3540                     (index > sc->sc_noport)) {
3541                         err = USB_ERR_IOERROR;
3542                         goto done;
3543                 }
3544
3545                 port = XHCI_PORTSC(index);
3546                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3547
3548                 switch (value) {
3549                 case UHF_PORT_U1_TIMEOUT:
3550                         if (XHCI_PS_SPEED_GET(v) != 4) {
3551                                 err = USB_ERR_IOERROR;
3552                                 goto done;
3553                         }
3554                         port = XHCI_PORTPMSC(index);
3555                         v = XREAD4(sc, oper, port);
3556                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3557                         v |= XHCI_PM3_U1TO_SET(i);
3558                         XWRITE4(sc, oper, port, v);
3559                         break;
3560                 case UHF_PORT_U2_TIMEOUT:
3561                         if (XHCI_PS_SPEED_GET(v) != 4) {
3562                                 err = USB_ERR_IOERROR;
3563                                 goto done;
3564                         }
3565                         port = XHCI_PORTPMSC(index);
3566                         v = XREAD4(sc, oper, port);
3567                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3568                         v |= XHCI_PM3_U2TO_SET(i);
3569                         XWRITE4(sc, oper, port, v);
3570                         break;
3571                 case UHF_BH_PORT_RESET:
3572                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3573                         break;
3574                 case UHF_PORT_LINK_STATE:
3575                         XWRITE4(sc, oper, port, v |
3576                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3577                         /* 4ms settle time */
3578                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3579                         break;
3580                 case UHF_PORT_ENABLE:
3581                         DPRINTFN(3, "set port enable %d\n", index);
3582                         break;
3583                 case UHF_PORT_SUSPEND:
3584                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3585                         j = XHCI_PS_SPEED_GET(v);
3586                         if ((j < 1) || (j > 3)) {
3587                                 /* non-supported speed */
3588                                 err = USB_ERR_IOERROR;
3589                                 goto done;
3590                         }
3591                         XWRITE4(sc, oper, port, v |
3592                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3593                         break;
3594                 case UHF_PORT_RESET:
3595                         DPRINTFN(6, "reset port %d\n", index);
3596                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3597                         break;
3598                 case UHF_PORT_POWER:
3599                         DPRINTFN(3, "set port power %d\n", index);
3600                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3601                         break;
3602                 case UHF_PORT_TEST:
3603                         DPRINTFN(3, "set port test %d\n", index);
3604                         break;
3605                 case UHF_PORT_INDICATOR:
3606                         DPRINTFN(3, "set port indicator %d\n", index);
3607
3608                         v &= ~XHCI_PS_PIC_SET(3);
3609                         v |= XHCI_PS_PIC_SET(1);
3610
3611                         XWRITE4(sc, oper, port, v);
3612                         break;
3613                 default:
3614                         err = USB_ERR_IOERROR;
3615                         goto done;
3616                 }
3617                 break;
3618
3619         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3620         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3621         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3622         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3623                 break;
3624         default:
3625                 err = USB_ERR_IOERROR;
3626                 goto done;
3627         }
3628 done:
3629         *plength = len;
3630         *pptr = ptr;
3631         return (err);
3632 }
3633
3634 static void
3635 xhci_xfer_setup(struct usb_setup_params *parm)
3636 {
3637         struct usb_page_search page_info;
3638         struct usb_page_cache *pc;
3639         struct xhci_softc *sc;
3640         struct usb_xfer *xfer;
3641         void *last_obj;
3642         uint32_t ntd;
3643         uint32_t n;
3644
3645         sc = XHCI_BUS2SC(parm->udev->bus);
3646         xfer = parm->curr_xfer;
3647
3648         /*
3649          * The proof for the "ntd" formula is illustrated like this:
3650          *
3651          * +------------------------------------+
3652          * |                                    |
3653          * |         |remainder ->              |
3654          * |   +-----+---+                      |
3655          * |   | xxx | x | frm 0                |
3656          * |   +-----+---++                     |
3657          * |   | xxx | xx | frm 1               |
3658          * |   +-----+----+                     |
3659          * |            ...                     |
3660          * +------------------------------------+
3661          *
3662          * "xxx" means a completely full USB transfer descriptor
3663          *
3664          * "x" and "xx" means a short USB packet
3665          *
3666          * For the remainder of an USB transfer modulo
3667          * "max_data_length" we need two USB transfer descriptors.
3668          * One to transfer the remaining data and one to finalise with
3669          * a zero length packet in case the "force_short_xfer" flag is
3670          * set. We only need two USB transfer descriptors in the case
3671          * where the transfer length of the first one is a factor of
3672          * "max_frame_size". The rest of the needed USB transfer
3673          * descriptors is given by the buffer size divided by the
3674          * maximum data payload.
3675          */
3676         parm->hc_max_packet_size = 0x400;
3677         parm->hc_max_packet_count = 16 * 3;
3678         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3679
3680         xfer->flags_int.bdma_enable = 1;
3681
3682         usbd_transfer_setup_sub(parm);
3683
3684         if (xfer->flags_int.isochronous_xfr) {
3685                 ntd = ((1 * xfer->nframes)
3686                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3687         } else if (xfer->flags_int.control_xfr) {
3688                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3689                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3690         } else {
3691                 ntd = ((2 * xfer->nframes)
3692                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3693         }
3694
3695 alloc_dma_set:
3696
3697         if (parm->err)
3698                 return;
3699
3700         /*
3701          * Allocate queue heads and transfer descriptors
3702          */
3703         last_obj = NULL;
3704
3705         if (usbd_transfer_setup_sub_malloc(
3706             parm, &pc, sizeof(struct xhci_td),
3707             XHCI_TD_ALIGN, ntd)) {
3708                 parm->err = USB_ERR_NOMEM;
3709                 return;
3710         }
3711         if (parm->buf) {
3712                 for (n = 0; n != ntd; n++) {
3713                         struct xhci_td *td;
3714
3715                         usbd_get_page(pc + n, 0, &page_info);
3716
3717                         td = page_info.buffer;
3718
3719                         /* init TD */
3720                         td->td_self = page_info.physaddr;
3721                         td->obj_next = last_obj;
3722                         td->page_cache = pc + n;
3723
3724                         last_obj = td;
3725
3726                         usb_pc_cpu_flush(pc + n);
3727                 }
3728         }
3729         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3730
3731         if (!xfer->flags_int.curr_dma_set) {
3732                 xfer->flags_int.curr_dma_set = 1;
3733                 goto alloc_dma_set;
3734         }
3735 }
3736
3737 static usb_error_t
3738 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3739 {
3740         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3741         struct usb_page_search buf_inp;
3742         struct usb_device *udev;
3743         struct xhci_endpoint_ext *pepext;
3744         struct usb_endpoint_descriptor *edesc;
3745         struct usb_page_cache *pcinp;
3746         usb_error_t err;
3747         usb_stream_t stream_id;
3748         uint8_t index;
3749         uint8_t epno;
3750
3751         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3752             xfer->endpoint->edesc);
3753
3754         udev = xfer->xroot->udev;
3755         index = udev->controller_slot_id;
3756
3757         pcinp = &sc->sc_hw.devs[index].input_pc;
3758
3759         usbd_get_page(pcinp, 0, &buf_inp);
3760
3761         edesc = xfer->endpoint->edesc;
3762
3763         epno = edesc->bEndpointAddress;
3764         stream_id = xfer->stream_id;
3765
3766         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3767                 epno |= UE_DIR_IN;
3768
3769         epno = XHCI_EPNO2EPID(epno);
3770
3771         if (epno == 0)
3772                 return (USB_ERR_NO_PIPE);               /* invalid */
3773
3774         XHCI_CMD_LOCK(sc);
3775
3776         /* configure endpoint */
3777
3778         err = xhci_configure_endpoint_by_xfer(xfer);
3779
3780         if (err != 0) {
3781                 XHCI_CMD_UNLOCK(sc);
3782                 return (err);
3783         }
3784
3785         /*
3786          * Get the endpoint into the stopped state according to the
3787          * endpoint context state diagram in the XHCI specification:
3788          */
3789
3790         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3791
3792         if (err != 0)
3793                 DPRINTF("Could not stop endpoint %u\n", epno);
3794
3795         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3796
3797         if (err != 0)
3798                 DPRINTF("Could not reset endpoint %u\n", epno);
3799
3800         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3801             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3802             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3803             stream_id, epno, index);
3804
3805         if (err != 0)
3806                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3807
3808         /*
3809          * Get the endpoint into the running state according to the
3810          * endpoint context state diagram in the XHCI specification:
3811          */
3812
3813         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3814
3815         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3816
3817         if (err != 0)
3818                 DPRINTF("Could not configure endpoint %u\n", epno);
3819
3820         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3821
3822         if (err != 0)
3823                 DPRINTF("Could not configure endpoint %u\n", epno);
3824
3825         XHCI_CMD_UNLOCK(sc);
3826
3827         return (0);
3828 }
3829
3830 static void
3831 xhci_xfer_unsetup(struct usb_xfer *xfer)
3832 {
3833         return;
3834 }
3835
3836 static void
3837 xhci_start_dma_delay(struct usb_xfer *xfer)
3838 {
3839         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3840
3841         /* put transfer on interrupt queue (again) */
3842         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3843
3844         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3845             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3846 }
3847
3848 static void
3849 xhci_configure_msg(struct usb_proc_msg *pm)
3850 {
3851         struct xhci_softc *sc;
3852         struct xhci_endpoint_ext *pepext;
3853         struct usb_xfer *xfer;
3854
3855         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3856
3857 restart:
3858         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3859
3860                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3861                     xfer->endpoint->edesc);
3862
3863                 if ((pepext->trb_halted != 0) ||
3864                     (pepext->trb_running == 0)) {
3865
3866                         uint16_t i;
3867
3868                         /* clear halted and running */
3869                         pepext->trb_halted = 0;
3870                         pepext->trb_running = 0;
3871
3872                         /* nuke remaining buffered transfers */
3873
3874                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3875                             XHCI_MAX_STREAMS); i++) {
3876                                 /*
3877                                  * NOTE: We need to use the timeout
3878                                  * error code here else existing
3879                                  * isochronous clients can get
3880                                  * confused:
3881                                  */
3882                                 if (pepext->xfer[i] != NULL) {
3883                                         xhci_device_done(pepext->xfer[i],
3884                                             USB_ERR_TIMEOUT);
3885                                 }
3886                         }
3887
3888                         /*
3889                          * NOTE: The USB transfer cannot vanish in
3890                          * this state!
3891                          */
3892
3893                         USB_BUS_UNLOCK(&sc->sc_bus);
3894
3895                         xhci_configure_reset_endpoint(xfer);
3896
3897                         USB_BUS_LOCK(&sc->sc_bus);
3898
3899                         /* check if halted is still cleared */
3900                         if (pepext->trb_halted == 0) {
3901                                 pepext->trb_running = 1;
3902                                 memset(pepext->trb_index, 0,
3903                                     sizeof(pepext->trb_index));
3904                         }
3905                         goto restart;
3906                 }
3907
3908                 if (xfer->flags_int.did_dma_delay) {
3909
3910                         /* remove transfer from interrupt queue (again) */
3911                         usbd_transfer_dequeue(xfer);
3912
3913                         /* we are finally done */
3914                         usb_dma_delay_done_cb(xfer);
3915
3916                         /* queue changed - restart */
3917                         goto restart;
3918                 }
3919         }
3920
3921         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3922
3923                 /* try to insert xfer on HW queue */
3924                 xhci_transfer_insert(xfer);
3925
3926                 /* try to multi buffer */
3927                 xhci_device_generic_multi_enter(xfer->endpoint,
3928                     xfer->stream_id, NULL);
3929         }
3930 }
3931
3932 static void
3933 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3934     struct usb_endpoint *ep)
3935 {
3936         struct xhci_endpoint_ext *pepext;
3937
3938         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3939             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3940
3941         if (udev->parent_hub == NULL) {
3942                 /* root HUB has special endpoint handling */
3943                 return;
3944         }
3945
3946         ep->methods = &xhci_device_generic_methods;
3947
3948         pepext = xhci_get_endpoint_ext(udev, edesc);
3949
3950         USB_BUS_LOCK(udev->bus);
3951         pepext->trb_halted = 1;
3952         pepext->trb_running = 0;
3953         USB_BUS_UNLOCK(udev->bus);
3954 }
3955
3956 static void
3957 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3958 {
3959
3960 }
3961
3962 static void
3963 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3964 {
3965         struct xhci_endpoint_ext *pepext;
3966
3967         DPRINTF("\n");
3968
3969         if (udev->flags.usb_mode != USB_MODE_HOST) {
3970                 /* not supported */
3971                 return;
3972         }
3973         if (udev->parent_hub == NULL) {
3974                 /* root HUB has special endpoint handling */
3975                 return;
3976         }
3977
3978         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3979
3980         USB_BUS_LOCK(udev->bus);
3981         pepext->trb_halted = 1;
3982         pepext->trb_running = 0;
3983         USB_BUS_UNLOCK(udev->bus);
3984 }
3985
3986 static usb_error_t
3987 xhci_device_init(struct usb_device *udev)
3988 {
3989         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3990         usb_error_t err;
3991         uint8_t temp;
3992
3993         /* no init for root HUB */
3994         if (udev->parent_hub == NULL)
3995                 return (0);
3996
3997         XHCI_CMD_LOCK(sc);
3998
3999         /* set invalid default */
4000
4001         udev->controller_slot_id = sc->sc_noslot + 1;
4002
4003         /* try to get a new slot ID from the XHCI */
4004
4005         err = xhci_cmd_enable_slot(sc, &temp);
4006
4007         if (err) {
4008                 XHCI_CMD_UNLOCK(sc);
4009                 return (err);
4010         }
4011
4012         if (temp > sc->sc_noslot) {
4013                 XHCI_CMD_UNLOCK(sc);
4014                 return (USB_ERR_BAD_ADDRESS);
4015         }
4016
4017         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4018                 DPRINTF("slot %u already allocated.\n", temp);
4019                 XHCI_CMD_UNLOCK(sc);
4020                 return (USB_ERR_BAD_ADDRESS);
4021         }
4022
4023         /* store slot ID for later reference */
4024
4025         udev->controller_slot_id = temp;
4026
4027         /* reset data structure */
4028
4029         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4030
4031         /* set mark slot allocated */
4032
4033         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4034
4035         err = xhci_alloc_device_ext(udev);
4036
4037         XHCI_CMD_UNLOCK(sc);
4038
4039         /* get device into default state */
4040
4041         if (err == 0)
4042                 err = xhci_set_address(udev, NULL, 0);
4043
4044         return (err);
4045 }
4046
4047 static void
4048 xhci_device_uninit(struct usb_device *udev)
4049 {
4050         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4051         uint8_t index;
4052
4053         /* no init for root HUB */
4054         if (udev->parent_hub == NULL)
4055                 return;
4056
4057         XHCI_CMD_LOCK(sc);
4058
4059         index = udev->controller_slot_id;
4060
4061         if (index <= sc->sc_noslot) {
4062                 xhci_cmd_disable_slot(sc, index);
4063                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4064
4065                 /* free device extension */
4066                 xhci_free_device_ext(udev);
4067         }
4068
4069         XHCI_CMD_UNLOCK(sc);
4070 }
4071
4072 static void
4073 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4074 {
4075         /*
4076          * Wait until the hardware has finished any possible use of
4077          * the transfer descriptor(s)
4078          */
4079         *pus = 2048;                    /* microseconds */
4080 }
4081
4082 static void
4083 xhci_device_resume(struct usb_device *udev)
4084 {
4085         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4086         uint8_t index;
4087         uint8_t n;
4088         uint8_t p;
4089
4090         DPRINTF("\n");
4091
4092         /* check for root HUB */
4093         if (udev->parent_hub == NULL)
4094                 return;
4095
4096         index = udev->controller_slot_id;
4097
4098         XHCI_CMD_LOCK(sc);
4099
4100         /* blindly resume all endpoints */
4101
4102         USB_BUS_LOCK(udev->bus);
4103
4104         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4105                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4106                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4107                             n | XHCI_DB_SID_SET(p));
4108                 }
4109         }
4110
4111         USB_BUS_UNLOCK(udev->bus);
4112
4113         XHCI_CMD_UNLOCK(sc);
4114 }
4115
4116 static void
4117 xhci_device_suspend(struct usb_device *udev)
4118 {
4119         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4120         uint8_t index;
4121         uint8_t n;
4122         usb_error_t err;
4123
4124         DPRINTF("\n");
4125
4126         /* check for root HUB */
4127         if (udev->parent_hub == NULL)
4128                 return;
4129
4130         index = udev->controller_slot_id;
4131
4132         XHCI_CMD_LOCK(sc);
4133
4134         /* blindly suspend all endpoints */
4135
4136         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4137                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4138                 if (err != 0) {
4139                         DPRINTF("Failed to suspend endpoint "
4140                             "%u on slot %u (ignored).\n", n, index);
4141                 }
4142         }
4143
4144         XHCI_CMD_UNLOCK(sc);
4145 }
4146
4147 static void
4148 xhci_set_hw_power(struct usb_bus *bus)
4149 {
4150         DPRINTF("\n");
4151 }
4152
4153 static void
4154 xhci_device_state_change(struct usb_device *udev)
4155 {
4156         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4157         struct usb_page_search buf_inp;
4158         usb_error_t err;
4159         uint8_t index;
4160
4161         /* check for root HUB */
4162         if (udev->parent_hub == NULL)
4163                 return;
4164
4165         index = udev->controller_slot_id;
4166
4167         DPRINTF("\n");
4168
4169         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4170                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4171                     &sc->sc_hw.devs[index].tt);
4172                 if (err != 0)
4173                         sc->sc_hw.devs[index].nports = 0;
4174         }
4175
4176         XHCI_CMD_LOCK(sc);
4177
4178         switch (usb_get_device_state(udev)) {
4179         case USB_STATE_POWERED:
4180                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4181                         break;
4182
4183                 /* set default state */
4184                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4185
4186                 /* reset number of contexts */
4187                 sc->sc_hw.devs[index].context_num = 0;
4188
4189                 err = xhci_cmd_reset_dev(sc, index);
4190
4191                 if (err != 0) {
4192                         DPRINTF("Device reset failed "
4193                             "for slot %u.\n", index);
4194                 }
4195                 break;
4196
4197         case USB_STATE_ADDRESSED:
4198                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4199                         break;
4200
4201                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4202
4203                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4204
4205                 if (err) {
4206                         DPRINTF("Failed to deconfigure "
4207                             "slot %u.\n", index);
4208                 }
4209                 break;
4210
4211         case USB_STATE_CONFIGURED:
4212                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4213                         break;
4214
4215                 /* set configured state */
4216                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4217
4218                 /* reset number of contexts */
4219                 sc->sc_hw.devs[index].context_num = 0;
4220
4221                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4222
4223                 xhci_configure_mask(udev, 3, 0);
4224
4225                 err = xhci_configure_device(udev);
4226                 if (err != 0) {
4227                         DPRINTF("Could not configure device "
4228                             "at slot %u.\n", index);
4229                 }
4230
4231                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4232                 if (err != 0) {
4233                         DPRINTF("Could not evaluate device "
4234                             "context at slot %u.\n", index);
4235                 }
4236                 break;
4237
4238         default:
4239                 break;
4240         }
4241         XHCI_CMD_UNLOCK(sc);
4242 }
4243
4244 static usb_error_t
4245 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4246     uint8_t ep_mode)
4247 {
4248         switch (ep_mode) {
4249         case USB_EP_MODE_DEFAULT:
4250                 return (0);
4251         case USB_EP_MODE_STREAMS:
4252                 if (xhcistreams == 0 ||
4253                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4254                     udev->speed != USB_SPEED_SUPER)
4255                         return (USB_ERR_INVAL);
4256                 return (0);
4257         default:
4258                 return (USB_ERR_INVAL);
4259         }
4260 }
4261
4262 struct usb_bus_methods xhci_bus_methods = {
4263         .endpoint_init = xhci_ep_init,
4264         .endpoint_uninit = xhci_ep_uninit,
4265         .xfer_setup = xhci_xfer_setup,
4266         .xfer_unsetup = xhci_xfer_unsetup,
4267         .get_dma_delay = xhci_get_dma_delay,
4268         .device_init = xhci_device_init,
4269         .device_uninit = xhci_device_uninit,
4270         .device_resume = xhci_device_resume,
4271         .device_suspend = xhci_device_suspend,
4272         .set_hw_power = xhci_set_hw_power,
4273         .roothub_exec = xhci_roothub_exec,
4274         .xfer_poll = xhci_do_poll,
4275         .start_dma_delay = xhci_start_dma_delay,
4276         .set_address = xhci_set_address,
4277         .clear_stall = xhci_ep_clear_stall,
4278         .device_state_change = xhci_device_state_change,
4279         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4280         .set_endpoint_mode = xhci_set_endpoint_mode,
4281 };