sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  29  *
  30  * The XHCI 1.0 spec can be found at
  31  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  32  * and the USB 3.0 spec at
  33  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  34  */
  35
  36 /*
  37  * A few words about the design implementation: This driver emulates
  38  * the concept about TDs which is found in EHCI specification. This
  39  * way we achieve that the USB controller drivers look similar to
  40  * eachother which makes it easier to understand the code.
  41  */
  42
  43 #ifdef USB_GLOBAL_INCLUDE_FILE
  44 #include USB_GLOBAL_INCLUDE_FILE
  45 #else
  46 #include <sys/stdint.h>
  47 #include <sys/stddef.h>
  48 #include <sys/param.h>
  49 #include <sys/queue.h>
  50 #include <sys/types.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/bus.h>
  54 #include <sys/module.h>
  55 #include <sys/lock.h>
  56 #include <sys/mutex.h>
  57 #include <sys/condvar.h>
  58 #include <sys/sysctl.h>
  59 #include <sys/sx.h>
  60 #include <sys/unistd.h>
  61 #include <sys/callout.h>
  62 #include <sys/malloc.h>
  63 #include <sys/priv.h>
  64
  65 #include <dev/usb/usb.h>
  66 #include <dev/usb/usbdi.h>
  67
  68 #define USB_DEBUG_VAR xhcidebug
  69
  70 #include <dev/usb/usb_core.h>
  71 #include <dev/usb/usb_debug.h>
  72 #include <dev/usb/usb_busdma.h>
  73 #include <dev/usb/usb_process.h>
  74 #include <dev/usb/usb_transfer.h>
  75 #include <dev/usb/usb_device.h>
  76 #include <dev/usb/usb_hub.h>
  77 #include <dev/usb/usb_util.h>
  78
  79 #include <dev/usb/usb_controller.h>
  80 #include <dev/usb/usb_bus.h>
  81 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  82
  83 #include <dev/usb/controller/xhci.h>
  84 #include <dev/usb/controller/xhcireg.h>
  85
  86 #define XHCI_BUS2SC(bus) \
  87    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  88     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  89
  90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91
  92 static int xhcistreams;
  93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
  94     &xhcistreams, 0, "Set to enable streams mode support");
  95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
  96
  97 #ifdef USB_DEBUG
  98 static int xhcidebug;
  99 static int xhciroute;
 100 static int xhcipolling;
 101
 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
 103     &xhcidebug, 0, "Debug level");
 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
 106     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
 109     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 111 #else
 112 #define xhciroute 0
 113 #endif
 114
 115 #define XHCI_INTR_ENDPT 1
 116
 117 struct xhci_std_temp {
 118         struct xhci_softc       *sc;
 119         struct usb_page_cache   *pc;
 120         struct xhci_td          *td;
 121         struct xhci_td          *td_next;
 122         uint32_t                len;
 123         uint32_t                offset;
 124         uint32_t                max_packet_size;
 125         uint32_t                average;
 126         uint16_t                isoc_delta;
 127         uint16_t                isoc_frame;
 128         uint8_t                 shortpkt;
 129         uint8_t                 multishort;
 130         uint8_t                 last_frame;
 131         uint8_t                 trb_type;
 132         uint8_t                 direction;
 133         uint8_t                 tbc;
 134         uint8_t                 tlbpc;
 135         uint8_t                 step_td;
 136         uint8_t                 do_isoc_sync;
 137 };
 138
 139 static void     xhci_do_poll(struct usb_bus *);
 140 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 141 static void     xhci_root_intr(struct xhci_softc *);
 142 static void     xhci_free_device_ext(struct usb_device *);
 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 144                     struct usb_endpoint_descriptor *);
 145 static usb_proc_callback_t xhci_configure_msg;
 146 static usb_error_t xhci_configure_device(struct usb_device *);
 147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 148                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 149                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 150                    uint8_t);
 151 static usb_error_t xhci_configure_mask(struct usb_device *,
 152                     uint32_t, uint8_t);
 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 154                     uint64_t, uint8_t);
 155 static void xhci_endpoint_doorbell(struct usb_xfer *);
 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 159 #ifdef USB_DEBUG
 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 161 #endif
 162
 163 extern struct usb_bus_methods xhci_bus_methods;
 164
 165 #ifdef USB_DEBUG
 166 static void
 167 xhci_dump_trb(struct xhci_trb *trb)
 168 {
 169         DPRINTFN(5, "trb = %p\n", trb);
 170         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 171         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 172         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 173 }
 174
 175 static void
 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 177 {
 178         DPRINTFN(5, "pep = %p\n", pep);
 179         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 180         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 181         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 182         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 183         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 184         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 185         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 186 }
 187
 188 static void
 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 190 {
 191         DPRINTFN(5, "psl = %p\n", psl);
 192         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 193         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 194         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 195         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 196 }
 197 #endif
 198
 199 uint8_t
 200 xhci_use_polling(void)
 201 {
 202 #ifdef USB_DEBUG
 203         return (xhcipolling != 0);
 204 #else
 205         return (0);
 206 #endif
 207 }
 208
 209 static void
 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 211 {
 212         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 213         uint8_t i;
 214
 215         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 216            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 217
 218         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 219            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 220
 221         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 222                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 223                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 224         }
 225 }
 226
 227 static void
 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 229 {
 230         if (sc->sc_ctx_is_64_byte) {
 231                 uint32_t offset;
 232                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 233                 /* all contexts are initially 32-bytes */
 234                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 235                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 236         }
 237         *ptr = htole32(val);
 238 }
 239
 240 static uint32_t
 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 242 {
 243         if (sc->sc_ctx_is_64_byte) {
 244                 uint32_t offset;
 245                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 246                 /* all contexts are initially 32-bytes */
 247                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 248                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 249         }
 250         return (le32toh(*ptr));
 251 }
 252
 253 static void
 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 255 {
 256         if (sc->sc_ctx_is_64_byte) {
 257                 uint32_t offset;
 258                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 259                 /* all contexts are initially 32-bytes */
 260                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 261                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 262         }
 263         *ptr = htole64(val);
 264 }
 265
 266 #ifdef USB_DEBUG
 267 static uint64_t
 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 269 {
 270         if (sc->sc_ctx_is_64_byte) {
 271                 uint32_t offset;
 272                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 273                 /* all contexts are initially 32-bytes */
 274                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 275                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 276         }
 277         return (le64toh(*ptr));
 278 }
 279 #endif
 280
 281 static int
 282 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 283 {
 284         struct usb_page_search buf_res;
 285         struct xhci_hw_root *phwr;
 286         uint64_t addr;
 287         uint32_t temp;
 288
 289         DPRINTF("\n");
 290
 291         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 292         if (temp & XHCI_CRCR_LO_CRR) {
 293                 DPRINTF("Command ring running\n");
 294                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 295
 296                 /*
 297                  * Try to abort the last command as per section
 298                  * 4.6.1.2 "Aborting a Command" of the XHCI
 299                  * specification:
 300                  */
 301
 302                 /* stop and cancel */
 303                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 304                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 305
 306                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 307                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 308
 309                 /* wait 250ms */
 310                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 311
 312                 /* check if command ring is still running */
 313                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 314                 if (temp & XHCI_CRCR_LO_CRR) {
 315                         DPRINTF("Comand ring still running\n");
 316                         return (USB_ERR_IOERROR);
 317                 }
 318         }
 319
 320         /* reset command ring */
 321         sc->sc_command_ccs = 1;
 322         sc->sc_command_idx = 0;
 323
 324         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 325
 326         /* set up command ring control base address */
 327         addr = buf_res.physaddr;
 328         phwr = buf_res.buffer;
 329         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 330
 331         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 332
 333         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 334         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 335
 336         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 337
 338         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 339         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 340
 341         return (0);
 342 }
 343
 344 usb_error_t
 345 xhci_start_controller(struct xhci_softc *sc)
 346 {
 347         struct usb_page_search buf_res;
 348         struct xhci_hw_root *phwr;
 349         struct xhci_dev_ctx_addr *pdctxa;
 350         uint64_t addr;
 351         uint32_t temp;
 352         uint16_t i;
 353
 354         DPRINTF("\n");
 355
 356         sc->sc_event_ccs = 1;
 357         sc->sc_event_idx = 0;
 358         sc->sc_command_ccs = 1;
 359         sc->sc_command_idx = 0;
 360
 361         /* Reset controller */
 362         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 363
 364         for (i = 0; i != 100; i++) {
 365                 usb_pause_mtx(NULL, hz / 100);
 366                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 367                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 368                 if (!temp)
 369                         break;
 370         }
 371
 372         if (temp) {
 373                 device_printf(sc->sc_bus.parent, "Controller "
 374                     "reset timeout.\n");
 375                 return (USB_ERR_IOERROR);
 376         }
 377
 378         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 379                 device_printf(sc->sc_bus.parent, "Controller does "
 380                     "not support 4K page size.\n");
 381                 return (USB_ERR_IOERROR);
 382         }
 383
 384         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 385
 386         i = XHCI_HCS1_N_PORTS(temp);
 387
 388         if (i == 0) {
 389                 device_printf(sc->sc_bus.parent, "Invalid number "
 390                     "of ports: %u\n", i);
 391                 return (USB_ERR_IOERROR);
 392         }
 393
 394         sc->sc_noport = i;
 395         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 396
 397         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 398                 sc->sc_noslot = XHCI_MAX_DEVICES;
 399
 400         /* set up number of device slots */
 401
 402         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 403             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 404
 405         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 406
 407         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 408
 409         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 410
 411         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 412
 413         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 414                 device_printf(sc->sc_bus.parent, "XHCI request "
 415                     "too many scratchpads\n");
 416                 return (USB_ERR_NOMEM);
 417         }
 418
 419         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 420
 421         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 422
 423         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 424             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 425
 426         temp = XREAD4(sc, oper, XHCI_USBSTS);
 427
 428         /* clear interrupts */
 429         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 430         /* disable all device notifications */
 431         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 432
 433         /* set up device context base address */
 434         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 435         pdctxa = buf_res.buffer;
 436         memset(pdctxa, 0, sizeof(*pdctxa));
 437
 438         addr = buf_res.physaddr;
 439         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 440
 441         /* slot 0 points to the table of scratchpad pointers */
 442         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 443
 444         for (i = 0; i != sc->sc_noscratch; i++) {
 445                 struct usb_page_search buf_scp;
 446                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 447                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 448         }
 449
 450         addr = buf_res.physaddr;
 451
 452         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 453         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 454         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 455         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 456
 457         /* Setup event table size */
 458
 459         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 460
 461         DPRINTF("HCS2=0x%08x\n", temp);
 462
 463         temp = XHCI_HCS2_ERST_MAX(temp);
 464         temp = 1U << temp;
 465         if (temp > XHCI_MAX_RSEG)
 466                 temp = XHCI_MAX_RSEG;
 467
 468         sc->sc_erst_max = temp;
 469
 470         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 471             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 472
 473         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 474
 475         /* Check if we should use the default IMOD value */
 476         if (sc->sc_imod_default == 0)
 477                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 478
 479         /* Setup interrupt rate */
 480         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 481
 482         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 483
 484         phwr = buf_res.buffer;
 485         addr = buf_res.physaddr;
 486         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 487
 488         /* reset hardware root structure */
 489         memset(phwr, 0, sizeof(*phwr));
 490
 491         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 492         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 493
 494         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 495
 496         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 497         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 498
 499         addr = buf_res.physaddr;
 500
 501         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 502
 503         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 504         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 505
 506         /* Setup interrupter registers */
 507
 508         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 509         temp |= XHCI_IMAN_INTR_ENA;
 510         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 511
 512         /* set up command ring control base address */
 513         addr = buf_res.physaddr;
 514         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 515
 516         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 517
 518         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 519         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 520
 521         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 522
 523         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 524
 525         /* Go! */
 526         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 527             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 528
 529         for (i = 0; i != 100; i++) {
 530                 usb_pause_mtx(NULL, hz / 100);
 531                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 532                 if (!temp)
 533                         break;
 534         }
 535         if (temp) {
 536                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 537                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 538                 return (USB_ERR_IOERROR);
 539         }
 540
 541         /* catch any lost interrupts */
 542         xhci_do_poll(&sc->sc_bus);
 543
 544         if (sc->sc_port_route != NULL) {
 545                 /* Route all ports to the XHCI by default */
 546                 sc->sc_port_route(sc->sc_bus.parent,
 547                     ~xhciroute, xhciroute);
 548         }
 549         return (0);
 550 }
 551
 552 usb_error_t
 553 xhci_halt_controller(struct xhci_softc *sc)
 554 {
 555         uint32_t temp;
 556         uint16_t i;
 557
 558         DPRINTF("\n");
 559
 560         sc->sc_capa_off = 0;
 561         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 562         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 563         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 564
 565         /* Halt controller */
 566         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 567
 568         for (i = 0; i != 100; i++) {
 569                 usb_pause_mtx(NULL, hz / 100);
 570                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 571                 if (temp)
 572                         break;
 573         }
 574
 575         if (!temp) {
 576                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 577                 return (USB_ERR_IOERROR);
 578         }
 579         return (0);
 580 }
 581
 582 usb_error_t
 583 xhci_init(struct xhci_softc *sc, device_t self)
 584 {
 585         uint32_t temp;
 586
 587         DPRINTF("\n");
 588
 589         /* initialize some bus fields */
 590         sc->sc_bus.parent = self;
 591
 592         /* set the bus revision */
 593         sc->sc_bus.usbrev = USB_REV_3_0;
 594
 595         /* set up the bus struct */
 596         sc->sc_bus.methods = &xhci_bus_methods;
 597
 598         /* set up devices array */
 599         sc->sc_bus.devices = sc->sc_devices;
 600         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 601
 602         /* set default cycle state in case of early interrupts */
 603         sc->sc_event_ccs = 1;
 604         sc->sc_command_ccs = 1;
 605
 606         /* set up bus space offsets */
 607         sc->sc_capa_off = 0;
 608         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 609         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 610         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 611
 612         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 613         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 614         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 615
 616         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 617
 618         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 619
 620         DPRINTF("HCS0 = 0x%08x\n", temp);
 621
 622         /* set up context size */
 623         if (XHCI_HCS0_CSZ(temp)) {
 624                 sc->sc_ctx_is_64_byte = 1;
 625         } else {
 626                 sc->sc_ctx_is_64_byte = 0;
 627         }
 628
 629         /* get DMA bits */
 630         sc->sc_bus.dma_bits = XHCI_HCS0_AC64(temp) ? 64 : 32;
 631
 632         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 633             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 634
 635         /* get all DMA memory */
 636         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 637             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 638                 return (ENOMEM);
 639         }
 640
 641         /* set up command queue mutex and condition varible */
 642         cv_init(&sc->sc_cmd_cv, "CMDQ");
 643         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 644
 645         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 646         sc->sc_config_msg[0].bus = &sc->sc_bus;
 647         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 648         sc->sc_config_msg[1].bus = &sc->sc_bus;
 649
 650         return (0);
 651 }
 652
 653 void
 654 xhci_uninit(struct xhci_softc *sc)
 655 {
 656         /*
 657          * NOTE: At this point the control transfer process is gone
 658          * and "xhci_configure_msg" is no longer called. Consequently
 659          * waiting for the configuration messages to complete is not
 660          * needed.
 661          */
 662         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 663
 664         cv_destroy(&sc->sc_cmd_cv);
 665         sx_destroy(&sc->sc_cmd_sx);
 666 }
 667
 668 static void
 669 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 670 {
 671         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 672
 673         switch (state) {
 674         case USB_HW_POWER_SUSPEND:
 675                 DPRINTF("Stopping the XHCI\n");
 676                 xhci_halt_controller(sc);
 677                 break;
 678         case USB_HW_POWER_SHUTDOWN:
 679                 DPRINTF("Stopping the XHCI\n");
 680                 xhci_halt_controller(sc);
 681                 break;
 682         case USB_HW_POWER_RESUME:
 683                 DPRINTF("Starting the XHCI\n");
 684                 xhci_start_controller(sc);
 685                 break;
 686         default:
 687                 break;
 688         }
 689 }
 690
 691 static usb_error_t
 692 xhci_generic_done_sub(struct usb_xfer *xfer)
 693 {
 694         struct xhci_td *td;
 695         struct xhci_td *td_alt_next;
 696         uint32_t len;
 697         uint8_t status;
 698
 699         td = xfer->td_transfer_cache;
 700         td_alt_next = td->alt_next;
 701
 702         if (xfer->aframes != xfer->nframes)
 703                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 704
 705         while (1) {
 706
 707                 usb_pc_cpu_invalidate(td->page_cache);
 708
 709                 status = td->status;
 710                 len = td->remainder;
 711
 712                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 713                     xfer, (unsigned int)xfer->aframes,
 714                     (unsigned int)xfer->nframes,
 715                     (unsigned int)len, (unsigned int)td->len,
 716                     (unsigned int)status);
 717
 718                 /*
 719                  * Verify the status length and
 720                  * add the length to "frlengths[]":
 721                  */
 722                 if (len > td->len) {
 723                         /* should not happen */
 724                         DPRINTF("Invalid status length, "
 725                             "0x%04x/0x%04x bytes\n", len, td->len);
 726                         status = XHCI_TRB_ERROR_LENGTH;
 727                 } else if (xfer->aframes != xfer->nframes) {
 728                         xfer->frlengths[xfer->aframes] += td->len - len;
 729                 }
 730                 /* Check for last transfer */
 731                 if (((void *)td) == xfer->td_transfer_last) {
 732                         td = NULL;
 733                         break;
 734                 }
 735                 /* Check for transfer error */
 736                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 737                     status != XHCI_TRB_ERROR_SUCCESS) {
 738                         /* the transfer is finished */
 739                         td = NULL;
 740                         break;
 741                 }
 742                 /* Check for short transfer */
 743                 if (len > 0) {
 744                         if (xfer->flags_int.short_frames_ok ||
 745                             xfer->flags_int.isochronous_xfr ||
 746                             xfer->flags_int.control_xfr) {
 747                                 /* follow alt next */
 748                                 td = td->alt_next;
 749                         } else {
 750                                 /* the transfer is finished */
 751                                 td = NULL;
 752                         }
 753                         break;
 754                 }
 755                 td = td->obj_next;
 756
 757                 if (td->alt_next != td_alt_next) {
 758                         /* this USB frame is complete */
 759                         break;
 760                 }
 761         }
 762
 763         /* update transfer cache */
 764
 765         xfer->td_transfer_cache = td;
 766
 767         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 768             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 769             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 770             USB_ERR_NORMAL_COMPLETION);
 771 }
 772
 773 static void
 774 xhci_generic_done(struct usb_xfer *xfer)
 775 {
 776         usb_error_t err = 0;
 777
 778         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 779             xfer, xfer->endpoint);
 780
 781         /* reset scanner */
 782
 783         xfer->td_transfer_cache = xfer->td_transfer_first;
 784
 785         if (xfer->flags_int.control_xfr) {
 786
 787                 if (xfer->flags_int.control_hdr)
 788                         err = xhci_generic_done_sub(xfer);
 789
 790                 xfer->aframes = 1;
 791
 792                 if (xfer->td_transfer_cache == NULL)
 793                         goto done;
 794         }
 795
 796         while (xfer->aframes != xfer->nframes) {
 797
 798                 err = xhci_generic_done_sub(xfer);
 799                 xfer->aframes++;
 800
 801                 if (xfer->td_transfer_cache == NULL)
 802                         goto done;
 803         }
 804
 805         if (xfer->flags_int.control_xfr &&
 806             !xfer->flags_int.control_act)
 807                 err = xhci_generic_done_sub(xfer);
 808 done:
 809         /* transfer is complete */
 810         xhci_device_done(xfer, err);
 811 }
 812
 813 static void
 814 xhci_activate_transfer(struct usb_xfer *xfer)
 815 {
 816         struct xhci_td *td;
 817
 818         td = xfer->td_transfer_cache;
 819
 820         usb_pc_cpu_invalidate(td->page_cache);
 821
 822         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 823
 824                 /* activate the transfer */
 825
 826                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 827                 usb_pc_cpu_flush(td->page_cache);
 828
 829                 xhci_endpoint_doorbell(xfer);
 830         }
 831 }
 832
 833 static void
 834 xhci_skip_transfer(struct usb_xfer *xfer)
 835 {
 836         struct xhci_td *td;
 837         struct xhci_td *td_last;
 838
 839         td = xfer->td_transfer_cache;
 840         td_last = xfer->td_transfer_last;
 841
 842         td = td->alt_next;
 843
 844         usb_pc_cpu_invalidate(td->page_cache);
 845
 846         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 847
 848                 usb_pc_cpu_invalidate(td_last->page_cache);
 849
 850                 /* copy LINK TRB to current waiting location */
 851
 852                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 853                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 854                 usb_pc_cpu_flush(td->page_cache);
 855
 856                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 857                 usb_pc_cpu_flush(td->page_cache);
 858
 859                 xhci_endpoint_doorbell(xfer);
 860         }
 861 }
 862
 863 /*------------------------------------------------------------------------*
 864  *      xhci_check_transfer
 865  *------------------------------------------------------------------------*/
 866 static void
 867 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 868 {
 869         struct xhci_endpoint_ext *pepext;
 870         int64_t offset;
 871         uint64_t td_event;
 872         uint32_t temp;
 873         uint32_t remainder;
 874         uint16_t stream_id;
 875         uint16_t i;
 876         uint8_t status;
 877         uint8_t halted;
 878         uint8_t epno;
 879         uint8_t index;
 880
 881         /* decode TRB */
 882         td_event = le64toh(trb->qwTrb0);
 883         temp = le32toh(trb->dwTrb2);
 884
 885         remainder = XHCI_TRB_2_REM_GET(temp);
 886         status = XHCI_TRB_2_ERROR_GET(temp);
 887         stream_id = XHCI_TRB_2_STREAM_GET(temp);
 888
 889         temp = le32toh(trb->dwTrb3);
 890         epno = XHCI_TRB_3_EP_GET(temp);
 891         index = XHCI_TRB_3_SLOT_GET(temp);
 892
 893         /* check if error means halted */
 894         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 895             status != XHCI_TRB_ERROR_SUCCESS);
 896
 897         DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
 898             index, epno, stream_id, remainder, status);
 899
 900         if (index > sc->sc_noslot) {
 901                 DPRINTF("Invalid slot.\n");
 902                 return;
 903         }
 904
 905         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 906                 DPRINTF("Invalid endpoint.\n");
 907                 return;
 908         }
 909
 910         pepext = &sc->sc_hw.devs[index].endp[epno];
 911
 912         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
 913                 stream_id = 0;
 914                 DPRINTF("stream_id=0\n");
 915         } else if (stream_id >= XHCI_MAX_STREAMS) {
 916                 DPRINTF("Invalid stream ID.\n");
 917                 return;
 918         }
 919
 920         /* try to find the USB transfer that generated the event */
 921         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 922                 struct usb_xfer *xfer;
 923                 struct xhci_td *td;
 924
 925                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 926                 if (xfer == NULL)
 927                         continue;
 928
 929                 td = xfer->td_transfer_cache;
 930
 931                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 932                         (long long)td_event,
 933                         (long long)td->td_self,
 934                         (long long)td->td_self + sizeof(td->td_trb));
 935
 936                 /*
 937                  * NOTE: Some XHCI implementations might not trigger
 938                  * an event on the last LINK TRB so we need to
 939                  * consider both the last and second last event
 940                  * address as conditions for a successful transfer.
 941                  *
 942                  * NOTE: We assume that the XHCI will only trigger one
 943                  * event per chain of TRBs.
 944                  */
 945
 946                 offset = td_event - td->td_self;
 947
 948                 if (offset >= 0 &&
 949                     offset < (int64_t)sizeof(td->td_trb)) {
 950
 951                         usb_pc_cpu_invalidate(td->page_cache);
 952
 953                         /* compute rest of remainder, if any */
 954                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 955                                 temp = le32toh(td->td_trb[i].dwTrb2);
 956                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 957                         }
 958
 959                         DPRINTFN(5, "New remainder: %u\n", remainder);
 960
 961                         /* clear isochronous transfer errors */
 962                         if (xfer->flags_int.isochronous_xfr) {
 963                                 if (halted) {
 964                                         halted = 0;
 965                                         status = XHCI_TRB_ERROR_SUCCESS;
 966                                         remainder = td->len;
 967                                 }
 968                         }
 969
 970                         /* "td->remainder" is verified later */
 971                         td->remainder = remainder;
 972                         td->status = status;
 973
 974                         usb_pc_cpu_flush(td->page_cache);
 975
 976                         /*
 977                          * 1) Last transfer descriptor makes the
 978                          * transfer done
 979                          */
 980                         if (((void *)td) == xfer->td_transfer_last) {
 981                                 DPRINTF("TD is last\n");
 982                                 xhci_generic_done(xfer);
 983                                 break;
 984                         }
 985
 986                         /*
 987                          * 2) Any kind of error makes the transfer
 988                          * done
 989                          */
 990                         if (halted) {
 991                                 DPRINTF("TD has I/O error\n");
 992                                 xhci_generic_done(xfer);
 993                                 break;
 994                         }
 995
 996                         /*
 997                          * 3) If there is no alternate next transfer,
 998                          * a short packet also makes the transfer done
 999                          */
1000                         if (td->remainder > 0) {
1001                                 if (td->alt_next == NULL) {
1002                                         DPRINTF(
1003                                             "short TD has no alternate next\n");
1004                                         xhci_generic_done(xfer);
1005                                         break;
1006                                 }
1007                                 DPRINTF("TD has short pkt\n");
1008                                 if (xfer->flags_int.short_frames_ok ||
1009                                     xfer->flags_int.isochronous_xfr ||
1010                                     xfer->flags_int.control_xfr) {
1011                                         /* follow the alt next */
1012                                         xfer->td_transfer_cache = td->alt_next;
1013                                         xhci_activate_transfer(xfer);
1014                                         break;
1015                                 }
1016                                 xhci_skip_transfer(xfer);
1017                                 xhci_generic_done(xfer);
1018                                 break;
1019                         }
1020
1021                         /*
1022                          * 4) Transfer complete - go to next TD
1023                          */
1024                         DPRINTF("Following next TD\n");
1025                         xfer->td_transfer_cache = td->obj_next;
1026                         xhci_activate_transfer(xfer);
1027                         break;          /* there should only be one match */
1028                 }
1029         }
1030 }
1031
1032 static int
1033 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1034 {
1035         if (sc->sc_cmd_addr == trb->qwTrb0) {
1036                 DPRINTF("Received command event\n");
1037                 sc->sc_cmd_result[0] = trb->dwTrb2;
1038                 sc->sc_cmd_result[1] = trb->dwTrb3;
1039                 cv_signal(&sc->sc_cmd_cv);
1040                 return (1);     /* command match */
1041         }
1042         return (0);
1043 }
1044
1045 static int
1046 xhci_interrupt_poll(struct xhci_softc *sc)
1047 {
1048         struct usb_page_search buf_res;
1049         struct xhci_hw_root *phwr;
1050         uint64_t addr;
1051         uint32_t temp;
1052         int retval = 0;
1053         uint16_t i;
1054         uint8_t event;
1055         uint8_t j;
1056         uint8_t k;
1057         uint8_t t;
1058
1059         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1060
1061         phwr = buf_res.buffer;
1062
1063         /* Receive any events */
1064
1065         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1066
1067         i = sc->sc_event_idx;
1068         j = sc->sc_event_ccs;
1069         t = 2;
1070
1071         while (1) {
1072
1073                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1074
1075                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1076
1077                 if (j != k)
1078                         break;
1079
1080                 event = XHCI_TRB_3_TYPE_GET(temp);
1081
1082                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1083                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1084                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1085                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1086
1087                 switch (event) {
1088                 case XHCI_TRB_EVENT_TRANSFER:
1089                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1090                         break;
1091                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1092                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1093                         break;
1094                 default:
1095                         DPRINTF("Unhandled event = %u\n", event);
1096                         break;
1097                 }
1098
1099                 i++;
1100
1101                 if (i == XHCI_MAX_EVENTS) {
1102                         i = 0;
1103                         j ^= 1;
1104
1105                         /* check for timeout */
1106                         if (!--t)
1107                                 break;
1108                 }
1109         }
1110
1111         sc->sc_event_idx = i;
1112         sc->sc_event_ccs = j;
1113
1114         /*
1115          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1116          * latched. That means to activate the register we need to
1117          * write both the low and high double word of the 64-bit
1118          * register.
1119          */
1120
1121         addr = buf_res.physaddr;
1122         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1123
1124         /* try to clear busy bit */
1125         addr |= XHCI_ERDP_LO_BUSY;
1126
1127         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1128         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1129
1130         return (retval);
1131 }
1132
1133 static usb_error_t
1134 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1135     uint16_t timeout_ms)
1136 {
1137         struct usb_page_search buf_res;
1138         struct xhci_hw_root *phwr;
1139         uint64_t addr;
1140         uint32_t temp;
1141         uint8_t i;
1142         uint8_t j;
1143         uint8_t timeout = 0;
1144         int err;
1145
1146         XHCI_CMD_ASSERT_LOCKED(sc);
1147
1148         /* get hardware root structure */
1149
1150         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1151
1152         phwr = buf_res.buffer;
1153
1154         /* Queue command */
1155
1156         USB_BUS_LOCK(&sc->sc_bus);
1157 retry:
1158         i = sc->sc_command_idx;
1159         j = sc->sc_command_ccs;
1160
1161         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1162             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1163             (long long)le64toh(trb->qwTrb0),
1164             (long)le32toh(trb->dwTrb2),
1165             (long)le32toh(trb->dwTrb3));
1166
1167         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1168         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1169
1170         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1171
1172         temp = trb->dwTrb3;
1173
1174         if (j)
1175                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1176         else
1177                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1178
1179         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1180
1181         phwr->hwr_commands[i].dwTrb3 = temp;
1182
1183         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1184
1185         addr = buf_res.physaddr;
1186         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1187
1188         sc->sc_cmd_addr = htole64(addr);
1189
1190         i++;
1191
1192         if (i == (XHCI_MAX_COMMANDS - 1)) {
1193
1194                 if (j) {
1195                         temp = htole32(XHCI_TRB_3_TC_BIT |
1196                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1197                             XHCI_TRB_3_CYCLE_BIT);
1198                 } else {
1199                         temp = htole32(XHCI_TRB_3_TC_BIT |
1200                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1201                 }
1202
1203                 phwr->hwr_commands[i].dwTrb3 = temp;
1204
1205                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1206
1207                 i = 0;
1208                 j ^= 1;
1209         }
1210
1211         sc->sc_command_idx = i;
1212         sc->sc_command_ccs = j;
1213
1214         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1215
1216         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1217             USB_MS_TO_TICKS(timeout_ms));
1218
1219         /*
1220          * In some error cases event interrupts are not generated.
1221          * Poll one time to see if the command has completed.
1222          */
1223         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1224                 DPRINTF("Command was completed when polling\n");
1225                 err = 0;
1226         }
1227         if (err != 0) {
1228                 DPRINTF("Command timeout!\n");
1229                 /*
1230                  * After some weeks of continuous operation, it has
1231                  * been observed that the ASMedia Technology, ASM1042
1232                  * SuperSpeed USB Host Controller can suddenly stop
1233                  * accepting commands via the command queue. Try to
1234                  * first reset the command queue. If that fails do a
1235                  * host controller reset.
1236                  */
1237                 if (timeout == 0 &&
1238                     xhci_reset_command_queue_locked(sc) == 0) {
1239                         temp = le32toh(trb->dwTrb3);
1240
1241                         /*
1242                          * Avoid infinite XHCI reset loops if the set
1243                          * address command fails to respond due to a
1244                          * non-enumerating device:
1245                          */
1246                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1247                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1248                                 DPRINTF("Set address timeout\n");
1249                         } else {
1250                                 timeout = 1;
1251                                 goto retry;
1252                         }
1253                 } else {
1254                         DPRINTF("Controller reset!\n");
1255                         usb_bus_reset_async_locked(&sc->sc_bus);
1256                 }
1257                 err = USB_ERR_TIMEOUT;
1258                 trb->dwTrb2 = 0;
1259                 trb->dwTrb3 = 0;
1260         } else {
1261                 temp = le32toh(sc->sc_cmd_result[0]);
1262                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1263                         err = USB_ERR_IOERROR;
1264
1265                 trb->dwTrb2 = sc->sc_cmd_result[0];
1266                 trb->dwTrb3 = sc->sc_cmd_result[1];
1267         }
1268
1269         USB_BUS_UNLOCK(&sc->sc_bus);
1270
1271         return (err);
1272 }
1273
1274 #if 0
1275 static usb_error_t
1276 xhci_cmd_nop(struct xhci_softc *sc)
1277 {
1278         struct xhci_trb trb;
1279         uint32_t temp;
1280
1281         DPRINTF("\n");
1282
1283         trb.qwTrb0 = 0;
1284         trb.dwTrb2 = 0;
1285         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1286
1287         trb.dwTrb3 = htole32(temp);
1288
1289         return (xhci_do_command(sc, &trb, 100 /* ms */));
1290 }
1291 #endif
1292
1293 static usb_error_t
1294 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1295 {
1296         struct xhci_trb trb;
1297         uint32_t temp;
1298         usb_error_t err;
1299
1300         DPRINTF("\n");
1301
1302         trb.qwTrb0 = 0;
1303         trb.dwTrb2 = 0;
1304         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1305
1306         err = xhci_do_command(sc, &trb, 100 /* ms */);
1307         if (err)
1308                 goto done;
1309
1310         temp = le32toh(trb.dwTrb3);
1311
1312         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1313
1314 done:
1315         return (err);
1316 }
1317
1318 static usb_error_t
1319 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1320 {
1321         struct xhci_trb trb;
1322         uint32_t temp;
1323
1324         DPRINTF("\n");
1325
1326         trb.qwTrb0 = 0;
1327         trb.dwTrb2 = 0;
1328         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1329             XHCI_TRB_3_SLOT_SET(slot_id);
1330
1331         trb.dwTrb3 = htole32(temp);
1332
1333         return (xhci_do_command(sc, &trb, 100 /* ms */));
1334 }
1335
1336 static usb_error_t
1337 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1338     uint8_t bsr, uint8_t slot_id)
1339 {
1340         struct xhci_trb trb;
1341         uint32_t temp;
1342
1343         DPRINTF("\n");
1344
1345         trb.qwTrb0 = htole64(input_ctx);
1346         trb.dwTrb2 = 0;
1347         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1348             XHCI_TRB_3_SLOT_SET(slot_id);
1349
1350         if (bsr)
1351                 temp |= XHCI_TRB_3_BSR_BIT;
1352
1353         trb.dwTrb3 = htole32(temp);
1354
1355         return (xhci_do_command(sc, &trb, 500 /* ms */));
1356 }
1357
1358 static usb_error_t
1359 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1360 {
1361         struct usb_page_search buf_inp;
1362         struct usb_page_search buf_dev;
1363         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1364         struct xhci_hw_dev *hdev;
1365         struct xhci_dev_ctx *pdev;
1366         struct xhci_endpoint_ext *pepext;
1367         uint32_t temp;
1368         uint16_t mps;
1369         usb_error_t err;
1370         uint8_t index;
1371
1372         /* the root HUB case is not handled here */
1373         if (udev->parent_hub == NULL)
1374                 return (USB_ERR_INVAL);
1375
1376         index = udev->controller_slot_id;
1377
1378         hdev =  &sc->sc_hw.devs[index];
1379
1380         if (mtx != NULL)
1381                 mtx_unlock(mtx);
1382
1383         XHCI_CMD_LOCK(sc);
1384
1385         switch (hdev->state) {
1386         case XHCI_ST_DEFAULT:
1387         case XHCI_ST_ENABLED:
1388
1389                 hdev->state = XHCI_ST_ENABLED;
1390
1391                 /* set configure mask to slot and EP0 */
1392                 xhci_configure_mask(udev, 3, 0);
1393
1394                 /* configure input slot context structure */
1395                 err = xhci_configure_device(udev);
1396
1397                 if (err != 0) {
1398                         DPRINTF("Could not configure device\n");
1399                         break;
1400                 }
1401
1402                 /* configure input endpoint context structure */
1403                 switch (udev->speed) {
1404                 case USB_SPEED_LOW:
1405                 case USB_SPEED_FULL:
1406                         mps = 8;
1407                         break;
1408                 case USB_SPEED_HIGH:
1409                         mps = 64;
1410                         break;
1411                 default:
1412                         mps = 512;
1413                         break;
1414                 }
1415
1416                 pepext = xhci_get_endpoint_ext(udev,
1417                     &udev->ctrl_ep_desc);
1418
1419                 /* ensure the control endpoint is setup again */
1420                 USB_BUS_LOCK(udev->bus);
1421                 pepext->trb_halted = 1;
1422                 pepext->trb_running = 0;
1423                 USB_BUS_UNLOCK(udev->bus);
1424
1425                 err = xhci_configure_endpoint(udev,
1426                     &udev->ctrl_ep_desc, pepext,
1427                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1428
1429                 if (err != 0) {
1430                         DPRINTF("Could not configure default endpoint\n");
1431                         break;
1432                 }
1433
1434                 /* execute set address command */
1435                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1436
1437                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1438                     (address == 0), index);
1439
1440                 if (err != 0) {
1441                         temp = le32toh(sc->sc_cmd_result[0]);
1442                         if (address == 0 && sc->sc_port_route != NULL &&
1443                             XHCI_TRB_2_ERROR_GET(temp) ==
1444                             XHCI_TRB_ERROR_PARAMETER) {
1445                                 /* LynxPoint XHCI - ports are not switchable */
1446                                 /* Un-route all ports from the XHCI */
1447                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1448                         }
1449                         DPRINTF("Could not set address "
1450                             "for slot %u.\n", index);
1451                         if (address != 0)
1452                                 break;
1453                 }
1454
1455                 /* update device address to new value */
1456
1457                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1458                 pdev = buf_dev.buffer;
1459                 usb_pc_cpu_invalidate(&hdev->device_pc);
1460
1461                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1462                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1463
1464                 /* update device state to new value */
1465
1466                 if (address != 0)
1467                         hdev->state = XHCI_ST_ADDRESSED;
1468                 else
1469                         hdev->state = XHCI_ST_DEFAULT;
1470                 break;
1471
1472         default:
1473                 DPRINTF("Wrong state for set address.\n");
1474                 err = USB_ERR_IOERROR;
1475                 break;
1476         }
1477         XHCI_CMD_UNLOCK(sc);
1478
1479         if (mtx != NULL)
1480                 mtx_lock(mtx);
1481
1482         return (err);
1483 }
1484
1485 static usb_error_t
1486 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1487     uint8_t deconfigure, uint8_t slot_id)
1488 {
1489         struct xhci_trb trb;
1490         uint32_t temp;
1491
1492         DPRINTF("\n");
1493
1494         trb.qwTrb0 = htole64(input_ctx);
1495         trb.dwTrb2 = 0;
1496         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1497             XHCI_TRB_3_SLOT_SET(slot_id);
1498
1499         if (deconfigure)
1500                 temp |= XHCI_TRB_3_DCEP_BIT;
1501
1502         trb.dwTrb3 = htole32(temp);
1503
1504         return (xhci_do_command(sc, &trb, 100 /* ms */));
1505 }
1506
1507 static usb_error_t
1508 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1509     uint8_t slot_id)
1510 {
1511         struct xhci_trb trb;
1512         uint32_t temp;
1513
1514         DPRINTF("\n");
1515
1516         trb.qwTrb0 = htole64(input_ctx);
1517         trb.dwTrb2 = 0;
1518         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1519             XHCI_TRB_3_SLOT_SET(slot_id);
1520         trb.dwTrb3 = htole32(temp);
1521
1522         return (xhci_do_command(sc, &trb, 100 /* ms */));
1523 }
1524
1525 static usb_error_t
1526 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1527     uint8_t ep_id, uint8_t slot_id)
1528 {
1529         struct xhci_trb trb;
1530         uint32_t temp;
1531
1532         DPRINTF("\n");
1533
1534         trb.qwTrb0 = 0;
1535         trb.dwTrb2 = 0;
1536         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1537             XHCI_TRB_3_SLOT_SET(slot_id) |
1538             XHCI_TRB_3_EP_SET(ep_id);
1539
1540         if (preserve)
1541                 temp |= XHCI_TRB_3_PRSV_BIT;
1542
1543         trb.dwTrb3 = htole32(temp);
1544
1545         return (xhci_do_command(sc, &trb, 100 /* ms */));
1546 }
1547
1548 static usb_error_t
1549 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1550     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1551 {
1552         struct xhci_trb trb;
1553         uint32_t temp;
1554
1555         DPRINTF("\n");
1556
1557         trb.qwTrb0 = htole64(dequeue_ptr);
1558
1559         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1560         trb.dwTrb2 = htole32(temp);
1561
1562         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1563             XHCI_TRB_3_SLOT_SET(slot_id) |
1564             XHCI_TRB_3_EP_SET(ep_id);
1565         trb.dwTrb3 = htole32(temp);
1566
1567         return (xhci_do_command(sc, &trb, 100 /* ms */));
1568 }
1569
1570 static usb_error_t
1571 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1572     uint8_t ep_id, uint8_t slot_id)
1573 {
1574         struct xhci_trb trb;
1575         uint32_t temp;
1576
1577         DPRINTF("\n");
1578
1579         trb.qwTrb0 = 0;
1580         trb.dwTrb2 = 0;
1581         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1582             XHCI_TRB_3_SLOT_SET(slot_id) |
1583             XHCI_TRB_3_EP_SET(ep_id);
1584
1585         if (suspend)
1586                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1587
1588         trb.dwTrb3 = htole32(temp);
1589
1590         return (xhci_do_command(sc, &trb, 100 /* ms */));
1591 }
1592
1593 static usb_error_t
1594 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1595 {
1596         struct xhci_trb trb;
1597         uint32_t temp;
1598
1599         DPRINTF("\n");
1600
1601         trb.qwTrb0 = 0;
1602         trb.dwTrb2 = 0;
1603         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1604             XHCI_TRB_3_SLOT_SET(slot_id);
1605
1606         trb.dwTrb3 = htole32(temp);
1607
1608         return (xhci_do_command(sc, &trb, 100 /* ms */));
1609 }
1610
1611 /*------------------------------------------------------------------------*
1612  *      xhci_interrupt - XHCI interrupt handler
1613  *------------------------------------------------------------------------*/
1614 void
1615 xhci_interrupt(struct xhci_softc *sc)
1616 {
1617         uint32_t status;
1618         uint32_t temp;
1619
1620         USB_BUS_LOCK(&sc->sc_bus);
1621
1622         status = XREAD4(sc, oper, XHCI_USBSTS);
1623
1624         /* acknowledge interrupts, if any */
1625         if (status != 0) {
1626                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1627                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1628         }
1629
1630         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1631
1632         /* force clearing of pending interrupts */
1633         if (temp & XHCI_IMAN_INTR_PEND)
1634                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1635
1636         /* check for event(s) */
1637         xhci_interrupt_poll(sc);
1638
1639         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1640             XHCI_STS_HSE | XHCI_STS_HCE)) {
1641
1642                 if (status & XHCI_STS_PCD) {
1643                         xhci_root_intr(sc);
1644                 }
1645
1646                 if (status & XHCI_STS_HCH) {
1647                         printf("%s: host controller halted\n",
1648                             __FUNCTION__);
1649                 }
1650
1651                 if (status & XHCI_STS_HSE) {
1652                         printf("%s: host system error\n",
1653                             __FUNCTION__);
1654                 }
1655
1656                 if (status & XHCI_STS_HCE) {
1657                         printf("%s: host controller error\n",
1658                            __FUNCTION__);
1659                 }
1660         }
1661         USB_BUS_UNLOCK(&sc->sc_bus);
1662 }
1663
1664 /*------------------------------------------------------------------------*
1665  *      xhci_timeout - XHCI timeout handler
1666  *------------------------------------------------------------------------*/
1667 static void
1668 xhci_timeout(void *arg)
1669 {
1670         struct usb_xfer *xfer = arg;
1671
1672         DPRINTF("xfer=%p\n", xfer);
1673
1674         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1675
1676         /* transfer is transferred */
1677         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1678 }
1679
1680 static void
1681 xhci_do_poll(struct usb_bus *bus)
1682 {
1683         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1684
1685         USB_BUS_LOCK(&sc->sc_bus);
1686         xhci_interrupt_poll(sc);
1687         USB_BUS_UNLOCK(&sc->sc_bus);
1688 }
1689
1690 static void
1691 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1692 {
1693         struct usb_page_search buf_res;
1694         struct xhci_td *td;
1695         struct xhci_td *td_next;
1696         struct xhci_td *td_alt_next;
1697         struct xhci_td *td_first;
1698         uint32_t buf_offset;
1699         uint32_t average;
1700         uint32_t len_old;
1701         uint32_t npkt_off;
1702         uint32_t dword;
1703         uint8_t shortpkt_old;
1704         uint8_t precompute;
1705         uint8_t x;
1706
1707         td_alt_next = NULL;
1708         buf_offset = 0;
1709         shortpkt_old = temp->shortpkt;
1710         len_old = temp->len;
1711         npkt_off = 0;
1712         precompute = 1;
1713
1714 restart:
1715
1716         td = temp->td;
1717         td_next = td_first = temp->td_next;
1718
1719         while (1) {
1720
1721                 if (temp->len == 0) {
1722
1723                         if (temp->shortpkt)
1724                                 break;
1725
1726                         /* send a Zero Length Packet, ZLP, last */
1727
1728                         temp->shortpkt = 1;
1729                         average = 0;
1730
1731                 } else {
1732
1733                         average = temp->average;
1734
1735                         if (temp->len < average) {
1736                                 if (temp->len % temp->max_packet_size) {
1737                                         temp->shortpkt = 1;
1738                                 }
1739                                 average = temp->len;
1740                         }
1741                 }
1742
1743                 if (td_next == NULL)
1744                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1745
1746                 /* get next TD */
1747
1748                 td = td_next;
1749                 td_next = td->obj_next;
1750
1751                 /* check if we are pre-computing */
1752
1753                 if (precompute) {
1754
1755                         /* update remaining length */
1756
1757                         temp->len -= average;
1758
1759                         continue;
1760                 }
1761                 /* fill out current TD */
1762
1763                 td->len = average;
1764                 td->remainder = 0;
1765                 td->status = 0;
1766
1767                 /* update remaining length */
1768
1769                 temp->len -= average;
1770
1771                 /* reset TRB index */
1772
1773                 x = 0;
1774
1775                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1776                         /* immediate data */
1777
1778                         if (average > 8)
1779                                 average = 8;
1780
1781                         td->td_trb[0].qwTrb0 = 0;
1782
1783                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1784                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1785                            average);
1786
1787                         dword = XHCI_TRB_2_BYTES_SET(8) |
1788                             XHCI_TRB_2_TDSZ_SET(0) |
1789                             XHCI_TRB_2_IRQ_SET(0);
1790
1791                         td->td_trb[0].dwTrb2 = htole32(dword);
1792
1793                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1794                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1795
1796                         /* check wLength */
1797                         if (td->td_trb[0].qwTrb0 &
1798                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1799                                 if (td->td_trb[0].qwTrb0 &
1800                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1801                                         dword |= XHCI_TRB_3_TRT_IN;
1802                                 else
1803                                         dword |= XHCI_TRB_3_TRT_OUT;
1804                         }
1805
1806                         td->td_trb[0].dwTrb3 = htole32(dword);
1807 #ifdef USB_DEBUG
1808                         xhci_dump_trb(&td->td_trb[x]);
1809 #endif
1810                         x++;
1811
1812                 } else do {
1813
1814                         uint32_t npkt;
1815
1816                         /* fill out buffer pointers */
1817
1818                         if (average == 0) {
1819                                 memset(&buf_res, 0, sizeof(buf_res));
1820                         } else {
1821                                 usbd_get_page(temp->pc, temp->offset +
1822                                     buf_offset, &buf_res);
1823
1824                                 /* get length to end of page */
1825                                 if (buf_res.length > average)
1826                                         buf_res.length = average;
1827
1828                                 /* check for maximum length */
1829                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1830                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1831
1832                                 npkt_off += buf_res.length;
1833                         }
1834
1835                         /* set up npkt */
1836                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1837                             temp->max_packet_size;
1838
1839                         if (npkt == 0)
1840                                 npkt = 1;
1841                         else if (npkt > 31)
1842                                 npkt = 31;
1843
1844                         /* fill out TRB's */
1845                         td->td_trb[x].qwTrb0 =
1846                             htole64((uint64_t)buf_res.physaddr);
1847
1848                         dword =
1849                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1850                           XHCI_TRB_2_TDSZ_SET(npkt) |
1851                           XHCI_TRB_2_IRQ_SET(0);
1852
1853                         td->td_trb[x].dwTrb2 = htole32(dword);
1854
1855                         switch (temp->trb_type) {
1856                         case XHCI_TRB_TYPE_ISOCH:
1857                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1858                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1859                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1860                                 if (td != td_first) {
1861                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1862                                 } else if (temp->do_isoc_sync != 0) {
1863                                         temp->do_isoc_sync = 0;
1864                                         /* wait until "isoc_frame" */
1865                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1866                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1867                                 } else {
1868                                         /* start data transfer at next interval */
1869                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1870                                             XHCI_TRB_3_ISO_SIA_BIT;
1871                                 }
1872                                 if (temp->direction == UE_DIR_IN)
1873                                         dword |= XHCI_TRB_3_ISP_BIT;
1874                                 break;
1875                         case XHCI_TRB_TYPE_DATA_STAGE:
1876                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1877                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1878                                 if (temp->direction == UE_DIR_IN)
1879                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1880                                 /*
1881                                  * Section 3.2.9 in the XHCI
1882                                  * specification about control
1883                                  * transfers says that we should use a
1884                                  * normal-TRB if there are more TRBs
1885                                  * extending the data-stage
1886                                  * TRB. Update the "trb_type".
1887                                  */
1888                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1889                                 break;
1890                         case XHCI_TRB_TYPE_STATUS_STAGE:
1891                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1892                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1893                                 if (temp->direction == UE_DIR_IN)
1894                                         dword |= XHCI_TRB_3_DIR_IN;
1895                                 break;
1896                         default:        /* XHCI_TRB_TYPE_NORMAL */
1897                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1898                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1899                                 if (temp->direction == UE_DIR_IN)
1900                                         dword |= XHCI_TRB_3_ISP_BIT;
1901                                 break;
1902                         }
1903                         td->td_trb[x].dwTrb3 = htole32(dword);
1904
1905                         average -= buf_res.length;
1906                         buf_offset += buf_res.length;
1907 #ifdef USB_DEBUG
1908                         xhci_dump_trb(&td->td_trb[x]);
1909 #endif
1910                         x++;
1911
1912                 } while (average != 0);
1913
1914                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1915
1916                 /* store number of data TRB's */
1917
1918                 td->ntrb = x;
1919
1920                 DPRINTF("NTRB=%u\n", x);
1921
1922                 /* fill out link TRB */
1923
1924                 if (td_next != NULL) {
1925                         /* link the current TD with the next one */
1926                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1927                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1928                 } else {
1929                         /* this field will get updated later */
1930                         DPRINTF("NOLINK\n");
1931                 }
1932
1933                 dword = XHCI_TRB_2_IRQ_SET(0);
1934
1935                 td->td_trb[x].dwTrb2 = htole32(dword);
1936
1937                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1938                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1939                     /*
1940                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1941                      * frame only receives a single short packet event
1942                      * by setting the CHAIN bit in the LINK field. In
1943                      * addition some XHCI controllers have problems
1944                      * sending a ZLP unless the CHAIN-BIT is set in
1945                      * the LINK TRB.
1946                      */
1947                     XHCI_TRB_3_CHAIN_BIT;
1948
1949                 td->td_trb[x].dwTrb3 = htole32(dword);
1950
1951                 td->alt_next = td_alt_next;
1952 #ifdef USB_DEBUG
1953                 xhci_dump_trb(&td->td_trb[x]);
1954 #endif
1955                 usb_pc_cpu_flush(td->page_cache);
1956         }
1957
1958         if (precompute) {
1959                 precompute = 0;
1960
1961                 /* set up alt next pointer, if any */
1962                 if (temp->last_frame) {
1963                         td_alt_next = NULL;
1964                 } else {
1965                         /* we use this field internally */
1966                         td_alt_next = td_next;
1967                 }
1968
1969                 /* restore */
1970                 temp->shortpkt = shortpkt_old;
1971                 temp->len = len_old;
1972                 goto restart;
1973         }
1974
1975         /*
1976          * Remove cycle bit from the first TRB if we are
1977          * stepping them:
1978          */
1979         if (temp->step_td != 0) {
1980                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1981                 usb_pc_cpu_flush(td_first->page_cache);
1982         }
1983
1984         /* clear TD SIZE to zero, hence this is the last TRB */
1985         /* remove chain bit because this is the last data TRB in the chain */
1986         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1987         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1988         /* remove CHAIN-BIT from last LINK TRB */
1989         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1990
1991         usb_pc_cpu_flush(td->page_cache);
1992
1993         temp->td = td;
1994         temp->td_next = td_next;
1995 }
1996
1997 static void
1998 xhci_setup_generic_chain(struct usb_xfer *xfer)
1999 {
2000         struct xhci_std_temp temp;
2001         struct xhci_td *td;
2002         uint32_t x;
2003         uint32_t y;
2004         uint8_t mult;
2005
2006         temp.do_isoc_sync = 0;
2007         temp.step_td = 0;
2008         temp.tbc = 0;
2009         temp.tlbpc = 0;
2010         temp.average = xfer->max_hc_frame_size;
2011         temp.max_packet_size = xfer->max_packet_size;
2012         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2013         temp.pc = NULL;
2014         temp.last_frame = 0;
2015         temp.offset = 0;
2016         temp.multishort = xfer->flags_int.isochronous_xfr ||
2017             xfer->flags_int.control_xfr ||
2018             xfer->flags_int.short_frames_ok;
2019
2020         /* toggle the DMA set we are using */
2021         xfer->flags_int.curr_dma_set ^= 1;
2022
2023         /* get next DMA set */
2024         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2025
2026         temp.td = NULL;
2027         temp.td_next = td;
2028
2029         xfer->td_transfer_first = td;
2030         xfer->td_transfer_cache = td;
2031
2032         if (xfer->flags_int.isochronous_xfr) {
2033                 uint8_t shift;
2034
2035                 /* compute multiplier for ISOCHRONOUS transfers */
2036                 mult = xfer->endpoint->ecomp ?
2037                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2038                     : 0;
2039                 /* check for USB 2.0 multiplier */
2040                 if (mult == 0) {
2041                         mult = (xfer->endpoint->edesc->
2042                             wMaxPacketSize[1] >> 3) & 3;
2043                 }
2044                 /* range check */
2045                 if (mult > 2)
2046                         mult = 3;
2047                 else
2048                         mult++;
2049
2050                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2051
2052                 DPRINTF("MFINDEX=0x%08x\n", x);
2053
2054                 switch (usbd_get_speed(xfer->xroot->udev)) {
2055                 case USB_SPEED_FULL:
2056                         shift = 3;
2057                         temp.isoc_delta = 8;    /* 1ms */
2058                         x += temp.isoc_delta - 1;
2059                         x &= ~(temp.isoc_delta - 1);
2060                         break;
2061                 default:
2062                         shift = usbd_xfer_get_fps_shift(xfer);
2063                         temp.isoc_delta = 1U << shift;
2064                         x += temp.isoc_delta - 1;
2065                         x &= ~(temp.isoc_delta - 1);
2066                         /* simple frame load balancing */
2067                         x += xfer->endpoint->usb_uframe;
2068                         break;
2069                 }
2070
2071                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2072
2073                 if ((xfer->endpoint->is_synced == 0) ||
2074                     (y < (xfer->nframes << shift)) ||
2075                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2076                         /*
2077                          * If there is data underflow or the pipe
2078                          * queue is empty we schedule the transfer a
2079                          * few frames ahead of the current frame
2080                          * position. Else two isochronous transfers
2081                          * might overlap.
2082                          */
2083                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2084                         xfer->endpoint->is_synced = 1;
2085                         temp.do_isoc_sync = 1;
2086
2087                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2088                 }
2089
2090                 /* compute isochronous completion time */
2091
2092                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2093
2094                 xfer->isoc_time_complete =
2095                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2096                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2097
2098                 x = 0;
2099                 temp.isoc_frame = xfer->endpoint->isoc_next;
2100                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2101
2102                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2103
2104         } else if (xfer->flags_int.control_xfr) {
2105
2106                 /* check if we should prepend a setup message */
2107
2108                 if (xfer->flags_int.control_hdr) {
2109
2110                         temp.len = xfer->frlengths[0];
2111                         temp.pc = xfer->frbuffers + 0;
2112                         temp.shortpkt = temp.len ? 1 : 0;
2113                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2114                         temp.direction = 0;
2115
2116                         /* check for last frame */
2117                         if (xfer->nframes == 1) {
2118                                 /* no STATUS stage yet, SETUP is last */
2119                                 if (xfer->flags_int.control_act)
2120                                         temp.last_frame = 1;
2121                         }
2122
2123                         xhci_setup_generic_chain_sub(&temp);
2124                 }
2125                 x = 1;
2126                 mult = 1;
2127                 temp.isoc_delta = 0;
2128                 temp.isoc_frame = 0;
2129                 temp.trb_type = xfer->flags_int.control_did_data ?
2130                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2131         } else {
2132                 x = 0;
2133                 mult = 1;
2134                 temp.isoc_delta = 0;
2135                 temp.isoc_frame = 0;
2136                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2137         }
2138
2139         if (x != xfer->nframes) {
2140                 /* set up page_cache pointer */
2141                 temp.pc = xfer->frbuffers + x;
2142                 /* set endpoint direction */
2143                 temp.direction = UE_GET_DIR(xfer->endpointno);
2144         }
2145
2146         while (x != xfer->nframes) {
2147
2148                 /* DATA0 / DATA1 message */
2149
2150                 temp.len = xfer->frlengths[x];
2151                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2152                     x != 0 && temp.multishort == 0);
2153
2154                 x++;
2155
2156                 if (x == xfer->nframes) {
2157                         if (xfer->flags_int.control_xfr) {
2158                                 /* no STATUS stage yet, DATA is last */
2159                                 if (xfer->flags_int.control_act)
2160                                         temp.last_frame = 1;
2161                         } else {
2162                                 temp.last_frame = 1;
2163                         }
2164                 }
2165                 if (temp.len == 0) {
2166
2167                         /* make sure that we send an USB packet */
2168
2169                         temp.shortpkt = 0;
2170
2171                         temp.tbc = 0;
2172                         temp.tlbpc = mult - 1;
2173
2174                 } else if (xfer->flags_int.isochronous_xfr) {
2175
2176                         uint8_t tdpc;
2177
2178                         /*
2179                          * Isochronous transfers don't have short
2180                          * packet termination:
2181                          */
2182
2183                         temp.shortpkt = 1;
2184
2185                         /* isochronous transfers have a transfer limit */
2186
2187                         if (temp.len > xfer->max_frame_size)
2188                                 temp.len = xfer->max_frame_size;
2189
2190                         /* compute TD packet count */
2191                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2192                             xfer->max_packet_size;
2193
2194                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2195                         temp.tlbpc = (tdpc % mult);
2196
2197                         if (temp.tlbpc == 0)
2198                                 temp.tlbpc = mult - 1;
2199                         else
2200                                 temp.tlbpc--;
2201                 } else {
2202
2203                         /* regular data transfer */
2204
2205                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2206                 }
2207
2208                 xhci_setup_generic_chain_sub(&temp);
2209
2210                 if (xfer->flags_int.isochronous_xfr) {
2211                         temp.offset += xfer->frlengths[x - 1];
2212                         temp.isoc_frame += temp.isoc_delta;
2213                 } else {
2214                         /* get next Page Cache pointer */
2215                         temp.pc = xfer->frbuffers + x;
2216                 }
2217         }
2218
2219         /* check if we should append a status stage */
2220
2221         if (xfer->flags_int.control_xfr &&
2222             !xfer->flags_int.control_act) {
2223
2224                 /*
2225                  * Send a DATA1 message and invert the current
2226                  * endpoint direction.
2227                  */
2228                 temp.step_td = (xfer->nframes != 0);
2229                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2230                 temp.len = 0;
2231                 temp.pc = NULL;
2232                 temp.shortpkt = 0;
2233                 temp.last_frame = 1;
2234                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2235
2236                 xhci_setup_generic_chain_sub(&temp);
2237         }
2238
2239         td = temp.td;
2240
2241         /* must have at least one frame! */
2242
2243         xfer->td_transfer_last = td;
2244
2245         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2246 }
2247
2248 static void
2249 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2250 {
2251         struct usb_page_search buf_res;
2252         struct xhci_dev_ctx_addr *pdctxa;
2253
2254         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2255
2256         pdctxa = buf_res.buffer;
2257
2258         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2259
2260         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2261
2262         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2263 }
2264
2265 static usb_error_t
2266 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2267 {
2268         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2269         struct usb_page_search buf_inp;
2270         struct xhci_input_dev_ctx *pinp;
2271         uint32_t temp;
2272         uint8_t index;
2273         uint8_t x;
2274
2275         index = udev->controller_slot_id;
2276
2277         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2278
2279         pinp = buf_inp.buffer;
2280
2281         if (drop) {
2282                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2283                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2284                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2285         } else {
2286                 /*
2287                  * Some hardware requires that we drop the endpoint
2288                  * context before adding it again:
2289                  */
2290                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2291                     mask & XHCI_INCTX_NON_CTRL_MASK);
2292
2293                 /* Add new endpoint context */
2294                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2295
2296                 /* find most significant set bit */
2297                 for (x = 31; x != 1; x--) {
2298                         if (mask & (1 << x))
2299                                 break;
2300                 }
2301
2302                 /* adjust */
2303                 x--;
2304
2305                 /* figure out the maximum number of contexts */
2306                 if (x > sc->sc_hw.devs[index].context_num)
2307                         sc->sc_hw.devs[index].context_num = x;
2308                 else
2309                         x = sc->sc_hw.devs[index].context_num;
2310
2311                 /* update number of contexts */
2312                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2313                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2314                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2315                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2316         }
2317         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2318         return (0);
2319 }
2320
2321 static usb_error_t
2322 xhci_configure_endpoint(struct usb_device *udev,
2323     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2324     uint16_t interval, uint8_t max_packet_count,
2325     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2326     uint16_t max_frame_size, uint8_t ep_mode)
2327 {
2328         struct usb_page_search buf_inp;
2329         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2330         struct xhci_input_dev_ctx *pinp;
2331         uint64_t ring_addr = pepext->physaddr;
2332         uint32_t temp;
2333         uint8_t index;
2334         uint8_t epno;
2335         uint8_t type;
2336
2337         index = udev->controller_slot_id;
2338
2339         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2340
2341         pinp = buf_inp.buffer;
2342
2343         epno = edesc->bEndpointAddress;
2344         type = edesc->bmAttributes & UE_XFERTYPE;
2345
2346         if (type == UE_CONTROL)
2347                 epno |= UE_DIR_IN;
2348
2349         epno = XHCI_EPNO2EPID(epno);
2350
2351         if (epno == 0)
2352                 return (USB_ERR_NO_PIPE);               /* invalid */
2353
2354         if (max_packet_count == 0)
2355                 return (USB_ERR_BAD_BUFSIZE);
2356
2357         max_packet_count--;
2358
2359         if (mult == 0)
2360                 return (USB_ERR_BAD_BUFSIZE);
2361
2362         /* store endpoint mode */
2363         pepext->trb_ep_mode = ep_mode;
2364         usb_pc_cpu_flush(pepext->page_cache);
2365
2366         if (ep_mode == USB_EP_MODE_STREAMS) {
2367                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2368                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2369                     XHCI_EPCTX_0_LSA_SET(1);
2370
2371                 ring_addr += sizeof(struct xhci_trb) *
2372                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2373         } else {
2374                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2375                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2376                     XHCI_EPCTX_0_LSA_SET(0);
2377
2378                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2379         }
2380
2381         switch (udev->speed) {
2382         case USB_SPEED_FULL:
2383         case USB_SPEED_LOW:
2384                 /* 1ms -> 125us */
2385                 fps_shift += 3;
2386                 break;
2387         default:
2388                 break;
2389         }
2390
2391         switch (type) {
2392         case UE_INTERRUPT:
2393                 if (fps_shift > 3)
2394                         fps_shift--;
2395                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2396                 break;
2397         case UE_ISOCHRONOUS:
2398                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2399
2400                 switch (udev->speed) {
2401                 case USB_SPEED_SUPER:
2402                         if (mult > 3)
2403                                 mult = 3;
2404                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2405                         max_packet_count /= mult;
2406                         break;
2407                 default:
2408                         break;
2409                 }
2410                 break;
2411         default:
2412                 break;
2413         }
2414
2415         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2416
2417         temp =
2418             XHCI_EPCTX_1_HID_SET(0) |
2419             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2420             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2421
2422         /*
2423          * Always enable the "three strikes and you are gone" feature
2424          * except for ISOCHRONOUS endpoints. This is suggested by
2425          * section 4.3.3 in the XHCI specification about device slot
2426          * initialisation.
2427          */
2428         if (type != UE_ISOCHRONOUS)
2429                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2430
2431         switch (type) {
2432         case UE_CONTROL:
2433                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2434                 break;
2435         case UE_ISOCHRONOUS:
2436                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2437                 break;
2438         case UE_BULK:
2439                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2440                 break;
2441         default:
2442                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2443                 break;
2444         }
2445
2446         /* check for IN direction */
2447         if (epno & 1)
2448                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2449
2450         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2451         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2452
2453         switch (edesc->bmAttributes & UE_XFERTYPE) {
2454         case UE_INTERRUPT:
2455         case UE_ISOCHRONOUS:
2456                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2457                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2458                     max_frame_size));
2459                 break;
2460         case UE_CONTROL:
2461                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2462                 break;
2463         default:
2464                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2465                 break;
2466         }
2467
2468         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2469
2470 #ifdef USB_DEBUG
2471         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2472 #endif
2473         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2474
2475         return (0);             /* success */
2476 }
2477
2478 static usb_error_t
2479 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2480 {
2481         struct xhci_endpoint_ext *pepext;
2482         struct usb_endpoint_ss_comp_descriptor *ecomp;
2483         usb_stream_t x;
2484
2485         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2486             xfer->endpoint->edesc);
2487
2488         ecomp = xfer->endpoint->ecomp;
2489
2490         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2491                 uint64_t temp;
2492
2493                 /* halt any transfers */
2494                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2495
2496                 /* compute start of TRB ring for stream "x" */
2497                 temp = pepext->physaddr +
2498                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2499                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2500
2501                 /* make tree structure */
2502                 pepext->trb[(XHCI_MAX_TRANSFERS *
2503                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2504
2505                 /* reserved fields */
2506                 pepext->trb[(XHCI_MAX_TRANSFERS *
2507                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2508                 pepext->trb[(XHCI_MAX_TRANSFERS *
2509                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2510         }
2511         usb_pc_cpu_flush(pepext->page_cache);
2512
2513         return (xhci_configure_endpoint(xfer->xroot->udev,
2514             xfer->endpoint->edesc, pepext,
2515             xfer->interval, xfer->max_packet_count,
2516             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2517             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2518             xfer->max_frame_size, xfer->endpoint->ep_mode));
2519 }
2520
2521 static usb_error_t
2522 xhci_configure_device(struct usb_device *udev)
2523 {
2524         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2525         struct usb_page_search buf_inp;
2526         struct usb_page_cache *pcinp;
2527         struct xhci_input_dev_ctx *pinp;
2528         struct usb_device *hubdev;
2529         uint32_t temp;
2530         uint32_t route;
2531         uint32_t rh_port;
2532         uint8_t is_hub;
2533         uint8_t index;
2534         uint8_t depth;
2535
2536         index = udev->controller_slot_id;
2537
2538         DPRINTF("index=%u\n", index);
2539
2540         pcinp = &sc->sc_hw.devs[index].input_pc;
2541
2542         usbd_get_page(pcinp, 0, &buf_inp);
2543
2544         pinp = buf_inp.buffer;
2545
2546         rh_port = 0;
2547         route = 0;
2548
2549         /* figure out route string and root HUB port number */
2550
2551         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2552
2553                 if (hubdev->parent_hub == NULL)
2554                         break;
2555
2556                 depth = hubdev->parent_hub->depth;
2557
2558                 /*
2559                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2560                  * more than 15 ports
2561                  */
2562
2563                 rh_port = hubdev->port_no;
2564
2565                 if (depth == 0)
2566                         break;
2567
2568                 if (rh_port > 15)
2569                         rh_port = 15;
2570
2571                 if (depth < 6)
2572                         route |= rh_port << (4 * (depth - 1));
2573         }
2574
2575         DPRINTF("Route=0x%08x\n", route);
2576
2577         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2578             XHCI_SCTX_0_CTX_NUM_SET(
2579             sc->sc_hw.devs[index].context_num + 1);
2580
2581         switch (udev->speed) {
2582         case USB_SPEED_LOW:
2583                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2584                 if (udev->parent_hs_hub != NULL &&
2585                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2586                     UDPROTO_HSHUBMTT) {
2587                         DPRINTF("Device inherits MTT\n");
2588                         temp |= XHCI_SCTX_0_MTT_SET(1);
2589                 }
2590                 break;
2591         case USB_SPEED_HIGH:
2592                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2593                 if (sc->sc_hw.devs[index].nports != 0 &&
2594                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2595                         DPRINTF("HUB supports MTT\n");
2596                         temp |= XHCI_SCTX_0_MTT_SET(1);
2597                 }
2598                 break;
2599         case USB_SPEED_FULL:
2600                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2601                 if (udev->parent_hs_hub != NULL &&
2602                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2603                     UDPROTO_HSHUBMTT) {
2604                         DPRINTF("Device inherits MTT\n");
2605                         temp |= XHCI_SCTX_0_MTT_SET(1);
2606                 }
2607                 break;
2608         default:
2609                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2610                 break;
2611         }
2612
2613         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2614             (udev->speed == USB_SPEED_SUPER ||
2615             udev->speed == USB_SPEED_HIGH);
2616
2617         if (is_hub)
2618                 temp |= XHCI_SCTX_0_HUB_SET(1);
2619
2620         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2621
2622         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2623
2624         if (is_hub) {
2625                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2626                     sc->sc_hw.devs[index].nports);
2627         }
2628
2629         switch (udev->speed) {
2630         case USB_SPEED_SUPER:
2631                 switch (sc->sc_hw.devs[index].state) {
2632                 case XHCI_ST_ADDRESSED:
2633                 case XHCI_ST_CONFIGURED:
2634                         /* enable power save */
2635                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2636                         break;
2637                 default:
2638                         /* disable power save */
2639                         break;
2640                 }
2641                 break;
2642         default:
2643                 break;
2644         }
2645
2646         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2647
2648         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2649
2650         if (is_hub) {
2651                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2652                     sc->sc_hw.devs[index].tt);
2653         }
2654
2655         hubdev = udev->parent_hs_hub;
2656
2657         /* check if we should activate the transaction translator */
2658         switch (udev->speed) {
2659         case USB_SPEED_FULL:
2660         case USB_SPEED_LOW:
2661                 if (hubdev != NULL) {
2662                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2663                             hubdev->controller_slot_id);
2664                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2665                             udev->hs_port_no);
2666                 }
2667                 break;
2668         default:
2669                 break;
2670         }
2671
2672         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2673
2674         /*
2675          * These fields should be initialized to zero, according to
2676          * XHCI section 6.2.2 - slot context:
2677          */
2678         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2679             XHCI_SCTX_3_SLOT_STATE_SET(0);
2680
2681         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2682
2683 #ifdef USB_DEBUG
2684         xhci_dump_device(sc, &pinp->ctx_slot);
2685 #endif
2686         usb_pc_cpu_flush(pcinp);
2687
2688         return (0);             /* success */
2689 }
2690
2691 static usb_error_t
2692 xhci_alloc_device_ext(struct usb_device *udev)
2693 {
2694         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2695         struct usb_page_search buf_dev;
2696         struct usb_page_search buf_ep;
2697         struct xhci_trb *trb;
2698         struct usb_page_cache *pc;
2699         struct usb_page *pg;
2700         uint64_t addr;
2701         uint8_t index;
2702         uint8_t i;
2703
2704         index = udev->controller_slot_id;
2705
2706         pc = &sc->sc_hw.devs[index].device_pc;
2707         pg = &sc->sc_hw.devs[index].device_pg;
2708
2709         /* need to initialize the page cache */
2710         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2711
2712         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2713             (2 * sizeof(struct xhci_dev_ctx)) :
2714             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2715                 goto error;
2716
2717         usbd_get_page(pc, 0, &buf_dev);
2718
2719         pc = &sc->sc_hw.devs[index].input_pc;
2720         pg = &sc->sc_hw.devs[index].input_pg;
2721
2722         /* need to initialize the page cache */
2723         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2724
2725         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2726             (2 * sizeof(struct xhci_input_dev_ctx)) :
2727             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2728                 goto error;
2729         }
2730
2731         /* initialize all endpoint LINK TRBs */
2732
2733         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2734
2735                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2736                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2737
2738                 /* need to initialize the page cache */
2739                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2740
2741                 if (usb_pc_alloc_mem(pc, pg,
2742                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2743                         goto error;
2744                 }
2745
2746                 /* lookup endpoint TRB ring */
2747                 usbd_get_page(pc, 0, &buf_ep);
2748
2749                 /* get TRB pointer */
2750                 trb = buf_ep.buffer;
2751                 trb += XHCI_MAX_TRANSFERS - 1;
2752
2753                 /* get TRB start address */
2754                 addr = buf_ep.physaddr;
2755
2756                 /* create LINK TRB */
2757                 trb->qwTrb0 = htole64(addr);
2758                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2759                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2760                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2761
2762                 usb_pc_cpu_flush(pc);
2763         }
2764
2765         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2766
2767         return (0);
2768
2769 error:
2770         xhci_free_device_ext(udev);
2771
2772         return (USB_ERR_NOMEM);
2773 }
2774
2775 static void
2776 xhci_free_device_ext(struct usb_device *udev)
2777 {
2778         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2779         uint8_t index;
2780         uint8_t i;
2781
2782         index = udev->controller_slot_id;
2783         xhci_set_slot_pointer(sc, index, 0);
2784
2785         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2786         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2787         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2788                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2789 }
2790
2791 static struct xhci_endpoint_ext *
2792 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2793 {
2794         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2795         struct xhci_endpoint_ext *pepext;
2796         struct usb_page_cache *pc;
2797         struct usb_page_search buf_ep;
2798         uint8_t epno;
2799         uint8_t index;
2800
2801         epno = edesc->bEndpointAddress;
2802         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2803                 epno |= UE_DIR_IN;
2804
2805         epno = XHCI_EPNO2EPID(epno);
2806
2807         index = udev->controller_slot_id;
2808
2809         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2810
2811         usbd_get_page(pc, 0, &buf_ep);
2812
2813         pepext = &sc->sc_hw.devs[index].endp[epno];
2814         pepext->page_cache = pc;
2815         pepext->trb = buf_ep.buffer;
2816         pepext->physaddr = buf_ep.physaddr;
2817
2818         return (pepext);
2819 }
2820
2821 static void
2822 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2823 {
2824         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2825         uint8_t epno;
2826         uint8_t index;
2827
2828         epno = xfer->endpointno;
2829         if (xfer->flags_int.control_xfr)
2830                 epno |= UE_DIR_IN;
2831
2832         epno = XHCI_EPNO2EPID(epno);
2833         index = xfer->xroot->udev->controller_slot_id;
2834
2835         if (xfer->xroot->udev->flags.self_suspended == 0) {
2836                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2837                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2838         }
2839 }
2840
2841 static void
2842 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2843 {
2844         struct xhci_endpoint_ext *pepext;
2845
2846         if (xfer->flags_int.bandwidth_reclaimed) {
2847                 xfer->flags_int.bandwidth_reclaimed = 0;
2848
2849                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2850                     xfer->endpoint->edesc);
2851
2852                 pepext->trb_used[xfer->stream_id]--;
2853
2854                 pepext->xfer[xfer->qh_pos] = NULL;
2855
2856                 if (error && pepext->trb_running != 0) {
2857                         pepext->trb_halted = 1;
2858                         pepext->trb_running = 0;
2859                 }
2860         }
2861 }
2862
2863 static usb_error_t
2864 xhci_transfer_insert(struct usb_xfer *xfer)
2865 {
2866         struct xhci_td *td_first;
2867         struct xhci_td *td_last;
2868         struct xhci_trb *trb_link;
2869         struct xhci_endpoint_ext *pepext;
2870         uint64_t addr;
2871         usb_stream_t id;
2872         uint8_t i;
2873         uint8_t inext;
2874         uint8_t trb_limit;
2875
2876         DPRINTFN(8, "\n");
2877
2878         id = xfer->stream_id;
2879
2880         /* check if already inserted */
2881         if (xfer->flags_int.bandwidth_reclaimed) {
2882                 DPRINTFN(8, "Already in schedule\n");
2883                 return (0);
2884         }
2885
2886         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2887             xfer->endpoint->edesc);
2888
2889         td_first = xfer->td_transfer_first;
2890         td_last = xfer->td_transfer_last;
2891         addr = pepext->physaddr;
2892
2893         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2894         case UE_CONTROL:
2895         case UE_INTERRUPT:
2896                 /* single buffered */
2897                 trb_limit = 1;
2898                 break;
2899         default:
2900                 /* multi buffered */
2901                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2902                 break;
2903         }
2904
2905         if (pepext->trb_used[id] >= trb_limit) {
2906                 DPRINTFN(8, "Too many TDs queued.\n");
2907                 return (USB_ERR_NOMEM);
2908         }
2909
2910         /* check for stopped condition, after putting transfer on interrupt queue */
2911         if (pepext->trb_running == 0) {
2912                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2913
2914                 DPRINTFN(8, "Not running\n");
2915
2916                 /* start configuration */
2917                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2918                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2919                 return (0);
2920         }
2921
2922         pepext->trb_used[id]++;
2923
2924         /* get current TRB index */
2925         i = pepext->trb_index[id];
2926
2927         /* get next TRB index */
2928         inext = (i + 1);
2929
2930         /* the last entry of the ring is a hardcoded link TRB */
2931         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2932                 inext = 0;
2933
2934         /* store next TRB index, before stream ID offset is added */
2935         pepext->trb_index[id] = inext;
2936
2937         /* offset for stream */
2938         i += id * XHCI_MAX_TRANSFERS;
2939         inext += id * XHCI_MAX_TRANSFERS;
2940
2941         /* compute terminating return address */
2942         addr += (inext * sizeof(struct xhci_trb));
2943
2944         /* compute link TRB pointer */
2945         trb_link = td_last->td_trb + td_last->ntrb;
2946
2947         /* update next pointer of last link TRB */
2948         trb_link->qwTrb0 = htole64(addr);
2949         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2950         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2951             XHCI_TRB_3_CYCLE_BIT |
2952             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2953
2954 #ifdef USB_DEBUG
2955         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2956 #endif
2957         usb_pc_cpu_flush(td_last->page_cache);
2958
2959         /* write ahead chain end marker */
2960
2961         pepext->trb[inext].qwTrb0 = 0;
2962         pepext->trb[inext].dwTrb2 = 0;
2963         pepext->trb[inext].dwTrb3 = 0;
2964
2965         /* update next pointer of link TRB */
2966
2967         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2968         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2969
2970 #ifdef USB_DEBUG
2971         xhci_dump_trb(&pepext->trb[i]);
2972 #endif
2973         usb_pc_cpu_flush(pepext->page_cache);
2974
2975         /* toggle cycle bit which activates the transfer chain */
2976
2977         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2978             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2979
2980         usb_pc_cpu_flush(pepext->page_cache);
2981
2982         DPRINTF("qh_pos = %u\n", i);
2983
2984         pepext->xfer[i] = xfer;
2985
2986         xfer->qh_pos = i;
2987
2988         xfer->flags_int.bandwidth_reclaimed = 1;
2989
2990         xhci_endpoint_doorbell(xfer);
2991
2992         return (0);
2993 }
2994
2995 static void
2996 xhci_root_intr(struct xhci_softc *sc)
2997 {
2998         uint16_t i;
2999
3000         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3001
3002         /* clear any old interrupt data */
3003         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3004
3005         for (i = 1; i <= sc->sc_noport; i++) {
3006                 /* pick out CHANGE bits from the status register */
3007                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3008                     XHCI_PS_CSC | XHCI_PS_PEC |
3009                     XHCI_PS_OCC | XHCI_PS_WRC |
3010                     XHCI_PS_PRC | XHCI_PS_PLC |
3011                     XHCI_PS_CEC)) {
3012                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3013                         DPRINTF("port %d changed\n", i);
3014                 }
3015         }
3016         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3017             sizeof(sc->sc_hub_idata));
3018 }
3019
3020 /*------------------------------------------------------------------------*
3021  *      xhci_device_done - XHCI done handler
3022  *
3023  * NOTE: This function can be called two times in a row on
3024  * the same USB transfer. From close and from interrupt.
3025  *------------------------------------------------------------------------*/
3026 static void
3027 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3028 {
3029         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3030             xfer, xfer->endpoint, error);
3031
3032         /* remove transfer from HW queue */
3033         xhci_transfer_remove(xfer, error);
3034
3035         /* dequeue transfer and start next transfer */
3036         usbd_transfer_done(xfer, error);
3037 }
3038
3039 /*------------------------------------------------------------------------*
3040  * XHCI data transfer support (generic type)
3041  *------------------------------------------------------------------------*/
3042 static void
3043 xhci_device_generic_open(struct usb_xfer *xfer)
3044 {
3045         if (xfer->flags_int.isochronous_xfr) {
3046                 switch (xfer->xroot->udev->speed) {
3047                 case USB_SPEED_FULL:
3048                         break;
3049                 default:
3050                         usb_hs_bandwidth_alloc(xfer);
3051                         break;
3052                 }
3053         }
3054 }
3055
3056 static void
3057 xhci_device_generic_close(struct usb_xfer *xfer)
3058 {
3059         DPRINTF("\n");
3060
3061         xhci_device_done(xfer, USB_ERR_CANCELLED);
3062
3063         if (xfer->flags_int.isochronous_xfr) {
3064                 switch (xfer->xroot->udev->speed) {
3065                 case USB_SPEED_FULL:
3066                         break;
3067                 default:
3068                         usb_hs_bandwidth_free(xfer);
3069                         break;
3070                 }
3071         }
3072 }
3073
3074 static void
3075 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3076     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3077 {
3078         struct usb_xfer *xfer;
3079
3080         /* check if there is a current transfer */
3081         xfer = ep->endpoint_q[stream_id].curr;
3082         if (xfer == NULL)
3083                 return;
3084
3085         /*
3086          * Check if the current transfer is started and then pickup
3087          * the next one, if any. Else wait for next start event due to
3088          * block on failure feature.
3089          */
3090         if (!xfer->flags_int.bandwidth_reclaimed)
3091                 return;
3092
3093         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3094         if (xfer == NULL) {
3095                 /*
3096                  * In case of enter we have to consider that the
3097                  * transfer is queued by the USB core after the enter
3098                  * method is called.
3099                  */
3100                 xfer = enter_xfer;
3101
3102                 if (xfer == NULL)
3103                         return;
3104         }
3105
3106         /* try to multi buffer */
3107         xhci_transfer_insert(xfer);
3108 }
3109
3110 static void
3111 xhci_device_generic_enter(struct usb_xfer *xfer)
3112 {
3113         DPRINTF("\n");
3114
3115         /* set up TD's and QH */
3116         xhci_setup_generic_chain(xfer);
3117
3118         xhci_device_generic_multi_enter(xfer->endpoint,
3119             xfer->stream_id, xfer);
3120 }
3121
3122 static void
3123 xhci_device_generic_start(struct usb_xfer *xfer)
3124 {
3125         DPRINTF("\n");
3126
3127         /* try to insert xfer on HW queue */
3128         xhci_transfer_insert(xfer);
3129
3130         /* try to multi buffer */
3131         xhci_device_generic_multi_enter(xfer->endpoint,
3132             xfer->stream_id, NULL);
3133
3134         /* add transfer last on interrupt queue */
3135         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3136
3137         /* start timeout, if any */
3138         if (xfer->timeout != 0)
3139                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3140 }
3141
3142 struct usb_pipe_methods xhci_device_generic_methods =
3143 {
3144         .open = xhci_device_generic_open,
3145         .close = xhci_device_generic_close,
3146         .enter = xhci_device_generic_enter,
3147         .start = xhci_device_generic_start,
3148 };
3149
3150 /*------------------------------------------------------------------------*
3151  * xhci root HUB support
3152  *------------------------------------------------------------------------*
3153  * Simulate a hardware HUB by handling all the necessary requests.
3154  *------------------------------------------------------------------------*/
3155
3156 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3157
3158 static const
3159 struct usb_device_descriptor xhci_devd =
3160 {
3161         .bLength = sizeof(xhci_devd),
3162         .bDescriptorType = UDESC_DEVICE,        /* type */
3163         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3164         .bDeviceClass = UDCLASS_HUB,            /* class */
3165         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3166         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3167         .bMaxPacketSize = 9,                    /* max packet size */
3168         HSETW(.idVendor, 0x0000),               /* vendor */
3169         HSETW(.idProduct, 0x0000),              /* product */
3170         HSETW(.bcdDevice, 0x0100),              /* device version */
3171         .iManufacturer = 1,
3172         .iProduct = 2,
3173         .iSerialNumber = 0,
3174         .bNumConfigurations = 1,                /* # of configurations */
3175 };
3176
3177 static const
3178 struct xhci_bos_desc xhci_bosd = {
3179         .bosd = {
3180                 .bLength = sizeof(xhci_bosd.bosd),
3181                 .bDescriptorType = UDESC_BOS,
3182                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3183                 .bNumDeviceCaps = 3,
3184         },
3185         .usb2extd = {
3186                 .bLength = sizeof(xhci_bosd.usb2extd),
3187                 .bDescriptorType = 1,
3188                 .bDevCapabilityType = 2,
3189                 .bmAttributes[0] = 2,
3190         },
3191         .usbdcd = {
3192                 .bLength = sizeof(xhci_bosd.usbdcd),
3193                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3194                 .bDevCapabilityType = 3,
3195                 .bmAttributes = 0, /* XXX */
3196                 HSETW(.wSpeedsSupported, 0x000C),
3197                 .bFunctionalitySupport = 8,
3198                 .bU1DevExitLat = 255,   /* dummy - not used */
3199                 .wU2DevExitLat = { 0x00, 0x08 },
3200         },
3201         .cidd = {
3202                 .bLength = sizeof(xhci_bosd.cidd),
3203                 .bDescriptorType = 1,
3204                 .bDevCapabilityType = 4,
3205                 .bReserved = 0,
3206                 .bContainerID = 0, /* XXX */
3207         },
3208 };
3209
3210 static const
3211 struct xhci_config_desc xhci_confd = {
3212         .confd = {
3213                 .bLength = sizeof(xhci_confd.confd),
3214                 .bDescriptorType = UDESC_CONFIG,
3215                 .wTotalLength[0] = sizeof(xhci_confd),
3216                 .bNumInterface = 1,
3217                 .bConfigurationValue = 1,
3218                 .iConfiguration = 0,
3219                 .bmAttributes = UC_SELF_POWERED,
3220                 .bMaxPower = 0          /* max power */
3221         },
3222         .ifcd = {
3223                 .bLength = sizeof(xhci_confd.ifcd),
3224                 .bDescriptorType = UDESC_INTERFACE,
3225                 .bNumEndpoints = 1,
3226                 .bInterfaceClass = UICLASS_HUB,
3227                 .bInterfaceSubClass = UISUBCLASS_HUB,
3228                 .bInterfaceProtocol = 0,
3229         },
3230         .endpd = {
3231                 .bLength = sizeof(xhci_confd.endpd),
3232                 .bDescriptorType = UDESC_ENDPOINT,
3233                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3234                 .bmAttributes = UE_INTERRUPT,
3235                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3236                 .bInterval = 255,
3237         },
3238         .endpcd = {
3239                 .bLength = sizeof(xhci_confd.endpcd),
3240                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3241                 .bMaxBurst = 0,
3242                 .bmAttributes = 0,
3243         },
3244 };
3245
3246 static const
3247 struct usb_hub_ss_descriptor xhci_hubd = {
3248         .bLength = sizeof(xhci_hubd),
3249         .bDescriptorType = UDESC_SS_HUB,
3250 };
3251
3252 static usb_error_t
3253 xhci_roothub_exec(struct usb_device *udev,
3254     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3255 {
3256         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3257         const char *str_ptr;
3258         const void *ptr;
3259         uint32_t port;
3260         uint32_t v;
3261         uint16_t len;
3262         uint16_t i;
3263         uint16_t value;
3264         uint16_t index;
3265         uint8_t j;
3266         usb_error_t err;
3267
3268         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3269
3270         /* buffer reset */
3271         ptr = (const void *)&sc->sc_hub_desc;
3272         len = 0;
3273         err = 0;
3274
3275         value = UGETW(req->wValue);
3276         index = UGETW(req->wIndex);
3277
3278         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3279             "wValue=0x%04x wIndex=0x%04x\n",
3280             req->bmRequestType, req->bRequest,
3281             UGETW(req->wLength), value, index);
3282
3283 #define C(x,y) ((x) | ((y) << 8))
3284         switch (C(req->bRequest, req->bmRequestType)) {
3285         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3286         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3287         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3288                 /*
3289                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3290                  * for the integrated root hub.
3291                  */
3292                 break;
3293         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3294                 len = 1;
3295                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3296                 break;
3297         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3298                 switch (value >> 8) {
3299                 case UDESC_DEVICE:
3300                         if ((value & 0xff) != 0) {
3301                                 err = USB_ERR_IOERROR;
3302                                 goto done;
3303                         }
3304                         len = sizeof(xhci_devd);
3305                         ptr = (const void *)&xhci_devd;
3306                         break;
3307
3308                 case UDESC_BOS:
3309                         if ((value & 0xff) != 0) {
3310                                 err = USB_ERR_IOERROR;
3311                                 goto done;
3312                         }
3313                         len = sizeof(xhci_bosd);
3314                         ptr = (const void *)&xhci_bosd;
3315                         break;
3316
3317                 case UDESC_CONFIG:
3318                         if ((value & 0xff) != 0) {
3319                                 err = USB_ERR_IOERROR;
3320                                 goto done;
3321                         }
3322                         len = sizeof(xhci_confd);
3323                         ptr = (const void *)&xhci_confd;
3324                         break;
3325
3326                 case UDESC_STRING:
3327                         switch (value & 0xff) {
3328                         case 0: /* Language table */
3329                                 str_ptr = "\001";
3330                                 break;
3331
3332                         case 1: /* Vendor */
3333                                 str_ptr = sc->sc_vendor;
3334                                 break;
3335
3336                         case 2: /* Product */
3337                                 str_ptr = "XHCI root HUB";
3338                                 break;
3339
3340                         default:
3341                                 str_ptr = "";
3342                                 break;
3343                         }
3344
3345                         len = usb_make_str_desc(
3346                             sc->sc_hub_desc.temp,
3347                             sizeof(sc->sc_hub_desc.temp),
3348                             str_ptr);
3349                         break;
3350
3351                 default:
3352                         err = USB_ERR_IOERROR;
3353                         goto done;
3354                 }
3355                 break;
3356         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3357                 len = 1;
3358                 sc->sc_hub_desc.temp[0] = 0;
3359                 break;
3360         case C(UR_GET_STATUS, UT_READ_DEVICE):
3361                 len = 2;
3362                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3363                 break;
3364         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3365         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3366                 len = 2;
3367                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3368                 break;
3369         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3370                 if (value >= XHCI_MAX_DEVICES) {
3371                         err = USB_ERR_IOERROR;
3372                         goto done;
3373                 }
3374                 break;
3375         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3376                 if (value != 0 && value != 1) {
3377                         err = USB_ERR_IOERROR;
3378                         goto done;
3379                 }
3380                 sc->sc_conf = value;
3381                 break;
3382         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3383                 break;
3384         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3385         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3386         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3387                 err = USB_ERR_IOERROR;
3388                 goto done;
3389         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3390                 break;
3391         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3392                 break;
3393                 /* Hub requests */
3394         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3395                 break;
3396         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3397                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3398
3399                 if ((index < 1) ||
3400                     (index > sc->sc_noport)) {
3401                         err = USB_ERR_IOERROR;
3402                         goto done;
3403                 }
3404                 port = XHCI_PORTSC(index);
3405
3406                 v = XREAD4(sc, oper, port);
3407                 i = XHCI_PS_PLS_GET(v);
3408                 v &= ~XHCI_PS_CLEAR;
3409
3410                 switch (value) {
3411                 case UHF_C_BH_PORT_RESET:
3412                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3413                         break;
3414                 case UHF_C_PORT_CONFIG_ERROR:
3415                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3416                         break;
3417                 case UHF_C_PORT_SUSPEND:
3418                 case UHF_C_PORT_LINK_STATE:
3419                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3420                         break;
3421                 case UHF_C_PORT_CONNECTION:
3422                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3423                         break;
3424                 case UHF_C_PORT_ENABLE:
3425                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3426                         break;
3427                 case UHF_C_PORT_OVER_CURRENT:
3428                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3429                         break;
3430                 case UHF_C_PORT_RESET:
3431                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3432                         break;
3433                 case UHF_PORT_ENABLE:
3434                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3435                         break;
3436                 case UHF_PORT_POWER:
3437                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3438                         break;
3439                 case UHF_PORT_INDICATOR:
3440                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3441                         break;
3442                 case UHF_PORT_SUSPEND:
3443
3444                         /* U3 -> U15 */
3445                         if (i == 3) {
3446                                 XWRITE4(sc, oper, port, v |
3447                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3448                         }
3449
3450                         /* wait 20ms for resume sequence to complete */
3451                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3452
3453                         /* U0 */
3454                         XWRITE4(sc, oper, port, v |
3455                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3456                         break;
3457                 default:
3458                         err = USB_ERR_IOERROR;
3459                         goto done;
3460                 }
3461                 break;
3462
3463         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3464                 if ((value & 0xff) != 0) {
3465                         err = USB_ERR_IOERROR;
3466                         goto done;
3467                 }
3468
3469                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3470
3471                 sc->sc_hub_desc.hubd = xhci_hubd;
3472
3473                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3474
3475                 if (XHCI_HCS0_PPC(v))
3476                         i = UHD_PWR_INDIVIDUAL;
3477                 else
3478                         i = UHD_PWR_GANGED;
3479
3480                 if (XHCI_HCS0_PIND(v))
3481                         i |= UHD_PORT_IND;
3482
3483                 i |= UHD_OC_INDIVIDUAL;
3484
3485                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3486
3487                 /* see XHCI section 5.4.9: */
3488                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3489
3490                 for (j = 1; j <= sc->sc_noport; j++) {
3491
3492                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3493                         if (v & XHCI_PS_DR) {
3494                                 sc->sc_hub_desc.hubd.
3495                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3496                         }
3497                 }
3498                 len = sc->sc_hub_desc.hubd.bLength;
3499                 break;
3500
3501         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3502                 len = 16;
3503                 memset(sc->sc_hub_desc.temp, 0, 16);
3504                 break;
3505
3506         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3507                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3508
3509                 if ((index < 1) ||
3510                     (index > sc->sc_noport)) {
3511                         err = USB_ERR_IOERROR;
3512                         goto done;
3513                 }
3514
3515                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3516
3517                 DPRINTFN(9, "port status=0x%08x\n", v);
3518
3519                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3520
3521                 switch (XHCI_PS_SPEED_GET(v)) {
3522                 case 3:
3523                         i |= UPS_HIGH_SPEED;
3524                         break;
3525                 case 2:
3526                         i |= UPS_LOW_SPEED;
3527                         break;
3528                 case 1:
3529                         /* FULL speed */
3530                         break;
3531                 default:
3532                         i |= UPS_OTHER_SPEED;
3533                         break;
3534                 }
3535
3536                 if (v & XHCI_PS_CCS)
3537                         i |= UPS_CURRENT_CONNECT_STATUS;
3538                 if (v & XHCI_PS_PED)
3539                         i |= UPS_PORT_ENABLED;
3540                 if (v & XHCI_PS_OCA)
3541                         i |= UPS_OVERCURRENT_INDICATOR;
3542                 if (v & XHCI_PS_PR)
3543                         i |= UPS_RESET;
3544                 if (v & XHCI_PS_PP) {
3545                         /*
3546                          * The USB 3.0 RH is using the
3547                          * USB 2.0's power bit
3548                          */
3549                         i |= UPS_PORT_POWER;
3550                 }
3551                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3552
3553                 i = 0;
3554                 if (v & XHCI_PS_CSC)
3555                         i |= UPS_C_CONNECT_STATUS;
3556                 if (v & XHCI_PS_PEC)
3557                         i |= UPS_C_PORT_ENABLED;
3558                 if (v & XHCI_PS_OCC)
3559                         i |= UPS_C_OVERCURRENT_INDICATOR;
3560                 if (v & XHCI_PS_WRC)
3561                         i |= UPS_C_BH_PORT_RESET;
3562                 if (v & XHCI_PS_PRC)
3563                         i |= UPS_C_PORT_RESET;
3564                 if (v & XHCI_PS_PLC)
3565                         i |= UPS_C_PORT_LINK_STATE;
3566                 if (v & XHCI_PS_CEC)
3567                         i |= UPS_C_PORT_CONFIG_ERROR;
3568
3569                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3570                 len = sizeof(sc->sc_hub_desc.ps);
3571                 break;
3572
3573         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3574                 err = USB_ERR_IOERROR;
3575                 goto done;
3576
3577         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3578                 break;
3579
3580         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3581
3582                 i = index >> 8;
3583                 index &= 0x00FF;
3584
3585                 if ((index < 1) ||
3586                     (index > sc->sc_noport)) {
3587                         err = USB_ERR_IOERROR;
3588                         goto done;
3589                 }
3590
3591                 port = XHCI_PORTSC(index);
3592                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3593
3594                 switch (value) {
3595                 case UHF_PORT_U1_TIMEOUT:
3596                         if (XHCI_PS_SPEED_GET(v) != 4) {
3597                                 err = USB_ERR_IOERROR;
3598                                 goto done;
3599                         }
3600                         port = XHCI_PORTPMSC(index);
3601                         v = XREAD4(sc, oper, port);
3602                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3603                         v |= XHCI_PM3_U1TO_SET(i);
3604                         XWRITE4(sc, oper, port, v);
3605                         break;
3606                 case UHF_PORT_U2_TIMEOUT:
3607                         if (XHCI_PS_SPEED_GET(v) != 4) {
3608                                 err = USB_ERR_IOERROR;
3609                                 goto done;
3610                         }
3611                         port = XHCI_PORTPMSC(index);
3612                         v = XREAD4(sc, oper, port);
3613                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3614                         v |= XHCI_PM3_U2TO_SET(i);
3615                         XWRITE4(sc, oper, port, v);
3616                         break;
3617                 case UHF_BH_PORT_RESET:
3618                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3619                         break;
3620                 case UHF_PORT_LINK_STATE:
3621                         XWRITE4(sc, oper, port, v |
3622                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3623                         /* 4ms settle time */
3624                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3625                         break;
3626                 case UHF_PORT_ENABLE:
3627                         DPRINTFN(3, "set port enable %d\n", index);
3628                         break;
3629                 case UHF_PORT_SUSPEND:
3630                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3631                         j = XHCI_PS_SPEED_GET(v);
3632                         if ((j < 1) || (j > 3)) {
3633                                 /* non-supported speed */
3634                                 err = USB_ERR_IOERROR;
3635                                 goto done;
3636                         }
3637                         XWRITE4(sc, oper, port, v |
3638                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3639                         break;
3640                 case UHF_PORT_RESET:
3641                         DPRINTFN(6, "reset port %d\n", index);
3642                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3643                         break;
3644                 case UHF_PORT_POWER:
3645                         DPRINTFN(3, "set port power %d\n", index);
3646                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3647                         break;
3648                 case UHF_PORT_TEST:
3649                         DPRINTFN(3, "set port test %d\n", index);
3650                         break;
3651                 case UHF_PORT_INDICATOR:
3652                         DPRINTFN(3, "set port indicator %d\n", index);
3653
3654                         v &= ~XHCI_PS_PIC_SET(3);
3655                         v |= XHCI_PS_PIC_SET(1);
3656
3657                         XWRITE4(sc, oper, port, v);
3658                         break;
3659                 default:
3660                         err = USB_ERR_IOERROR;
3661                         goto done;
3662                 }
3663                 break;
3664
3665         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3666         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3667         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3668         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3669                 break;
3670         default:
3671                 err = USB_ERR_IOERROR;
3672                 goto done;
3673         }
3674 done:
3675         *plength = len;
3676         *pptr = ptr;
3677         return (err);
3678 }
3679
3680 static void
3681 xhci_xfer_setup(struct usb_setup_params *parm)
3682 {
3683         struct usb_page_search page_info;
3684         struct usb_page_cache *pc;
3685         struct xhci_softc *sc;
3686         struct usb_xfer *xfer;
3687         void *last_obj;
3688         uint32_t ntd;
3689         uint32_t n;
3690
3691         sc = XHCI_BUS2SC(parm->udev->bus);
3692         xfer = parm->curr_xfer;
3693
3694         /*
3695          * The proof for the "ntd" formula is illustrated like this:
3696          *
3697          * +------------------------------------+
3698          * |                                    |
3699          * |         |remainder ->              |
3700          * |   +-----+---+                      |
3701          * |   | xxx | x | frm 0                |
3702          * |   +-----+---++                     |
3703          * |   | xxx | xx | frm 1               |
3704          * |   +-----+----+                     |
3705          * |            ...                     |
3706          * +------------------------------------+
3707          *
3708          * "xxx" means a completely full USB transfer descriptor
3709          *
3710          * "x" and "xx" means a short USB packet
3711          *
3712          * For the remainder of an USB transfer modulo
3713          * "max_data_length" we need two USB transfer descriptors.
3714          * One to transfer the remaining data and one to finalise with
3715          * a zero length packet in case the "force_short_xfer" flag is
3716          * set. We only need two USB transfer descriptors in the case
3717          * where the transfer length of the first one is a factor of
3718          * "max_frame_size". The rest of the needed USB transfer
3719          * descriptors is given by the buffer size divided by the
3720          * maximum data payload.
3721          */
3722         parm->hc_max_packet_size = 0x400;
3723         parm->hc_max_packet_count = 16 * 3;
3724         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3725
3726         xfer->flags_int.bdma_enable = 1;
3727
3728         usbd_transfer_setup_sub(parm);
3729
3730         if (xfer->flags_int.isochronous_xfr) {
3731                 ntd = ((1 * xfer->nframes)
3732                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3733         } else if (xfer->flags_int.control_xfr) {
3734                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3735                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3736         } else {
3737                 ntd = ((2 * xfer->nframes)
3738                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3739         }
3740
3741 alloc_dma_set:
3742
3743         if (parm->err)
3744                 return;
3745
3746         /*
3747          * Allocate queue heads and transfer descriptors
3748          */
3749         last_obj = NULL;
3750
3751         if (usbd_transfer_setup_sub_malloc(
3752             parm, &pc, sizeof(struct xhci_td),
3753             XHCI_TD_ALIGN, ntd)) {
3754                 parm->err = USB_ERR_NOMEM;
3755                 return;
3756         }
3757         if (parm->buf) {
3758                 for (n = 0; n != ntd; n++) {
3759                         struct xhci_td *td;
3760
3761                         usbd_get_page(pc + n, 0, &page_info);
3762
3763                         td = page_info.buffer;
3764
3765                         /* init TD */
3766                         td->td_self = page_info.physaddr;
3767                         td->obj_next = last_obj;
3768                         td->page_cache = pc + n;
3769
3770                         last_obj = td;
3771
3772                         usb_pc_cpu_flush(pc + n);
3773                 }
3774         }
3775         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3776
3777         if (!xfer->flags_int.curr_dma_set) {
3778                 xfer->flags_int.curr_dma_set = 1;
3779                 goto alloc_dma_set;
3780         }
3781 }
3782
3783 static usb_error_t
3784 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3785 {
3786         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3787         struct usb_page_search buf_inp;
3788         struct usb_device *udev;
3789         struct xhci_endpoint_ext *pepext;
3790         struct usb_endpoint_descriptor *edesc;
3791         struct usb_page_cache *pcinp;
3792         usb_error_t err;
3793         usb_stream_t stream_id;
3794         uint8_t index;
3795         uint8_t epno;
3796
3797         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3798             xfer->endpoint->edesc);
3799
3800         udev = xfer->xroot->udev;
3801         index = udev->controller_slot_id;
3802
3803         pcinp = &sc->sc_hw.devs[index].input_pc;
3804
3805         usbd_get_page(pcinp, 0, &buf_inp);
3806
3807         edesc = xfer->endpoint->edesc;
3808
3809         epno = edesc->bEndpointAddress;
3810         stream_id = xfer->stream_id;
3811
3812         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3813                 epno |= UE_DIR_IN;
3814
3815         epno = XHCI_EPNO2EPID(epno);
3816
3817         if (epno == 0)
3818                 return (USB_ERR_NO_PIPE);               /* invalid */
3819
3820         XHCI_CMD_LOCK(sc);
3821
3822         /* configure endpoint */
3823
3824         err = xhci_configure_endpoint_by_xfer(xfer);
3825
3826         if (err != 0) {
3827                 XHCI_CMD_UNLOCK(sc);
3828                 return (err);
3829         }
3830
3831         /*
3832          * Get the endpoint into the stopped state according to the
3833          * endpoint context state diagram in the XHCI specification:
3834          */
3835
3836         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3837
3838         if (err != 0)
3839                 DPRINTF("Could not stop endpoint %u\n", epno);
3840
3841         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3842
3843         if (err != 0)
3844                 DPRINTF("Could not reset endpoint %u\n", epno);
3845
3846         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3847             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3848             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3849             stream_id, epno, index);
3850
3851         if (err != 0)
3852                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3853
3854         /*
3855          * Get the endpoint into the running state according to the
3856          * endpoint context state diagram in the XHCI specification:
3857          */
3858
3859         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3860
3861         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3862
3863         if (err != 0)
3864                 DPRINTF("Could not configure endpoint %u\n", epno);
3865
3866         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3867
3868         if (err != 0)
3869                 DPRINTF("Could not configure endpoint %u\n", epno);
3870
3871         XHCI_CMD_UNLOCK(sc);
3872
3873         return (0);
3874 }
3875
3876 static void
3877 xhci_xfer_unsetup(struct usb_xfer *xfer)
3878 {
3879         return;
3880 }
3881
3882 static void
3883 xhci_start_dma_delay(struct usb_xfer *xfer)
3884 {
3885         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3886
3887         /* put transfer on interrupt queue (again) */
3888         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3889
3890         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3891             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3892 }
3893
3894 static void
3895 xhci_configure_msg(struct usb_proc_msg *pm)
3896 {
3897         struct xhci_softc *sc;
3898         struct xhci_endpoint_ext *pepext;
3899         struct usb_xfer *xfer;
3900
3901         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3902
3903 restart:
3904         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3905
3906                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3907                     xfer->endpoint->edesc);
3908
3909                 if ((pepext->trb_halted != 0) ||
3910                     (pepext->trb_running == 0)) {
3911
3912                         uint16_t i;
3913
3914                         /* clear halted and running */
3915                         pepext->trb_halted = 0;
3916                         pepext->trb_running = 0;
3917
3918                         /* nuke remaining buffered transfers */
3919
3920                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3921                             XHCI_MAX_STREAMS); i++) {
3922                                 /*
3923                                  * NOTE: We need to use the timeout
3924                                  * error code here else existing
3925                                  * isochronous clients can get
3926                                  * confused:
3927                                  */
3928                                 if (pepext->xfer[i] != NULL) {
3929                                         xhci_device_done(pepext->xfer[i],
3930                                             USB_ERR_TIMEOUT);
3931                                 }
3932                         }
3933
3934                         /*
3935                          * NOTE: The USB transfer cannot vanish in
3936                          * this state!
3937                          */
3938
3939                         USB_BUS_UNLOCK(&sc->sc_bus);
3940
3941                         xhci_configure_reset_endpoint(xfer);
3942
3943                         USB_BUS_LOCK(&sc->sc_bus);
3944
3945                         /* check if halted is still cleared */
3946                         if (pepext->trb_halted == 0) {
3947                                 pepext->trb_running = 1;
3948                                 memset(pepext->trb_index, 0,
3949                                     sizeof(pepext->trb_index));
3950                         }
3951                         goto restart;
3952                 }
3953
3954                 if (xfer->flags_int.did_dma_delay) {
3955
3956                         /* remove transfer from interrupt queue (again) */
3957                         usbd_transfer_dequeue(xfer);
3958
3959                         /* we are finally done */
3960                         usb_dma_delay_done_cb(xfer);
3961
3962                         /* queue changed - restart */
3963                         goto restart;
3964                 }
3965         }
3966
3967         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3968
3969                 /* try to insert xfer on HW queue */
3970                 xhci_transfer_insert(xfer);
3971
3972                 /* try to multi buffer */
3973                 xhci_device_generic_multi_enter(xfer->endpoint,
3974                     xfer->stream_id, NULL);
3975         }
3976 }
3977
3978 static void
3979 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3980     struct usb_endpoint *ep)
3981 {
3982         struct xhci_endpoint_ext *pepext;
3983
3984         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3985             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3986
3987         if (udev->parent_hub == NULL) {
3988                 /* root HUB has special endpoint handling */
3989                 return;
3990         }
3991
3992         ep->methods = &xhci_device_generic_methods;
3993
3994         pepext = xhci_get_endpoint_ext(udev, edesc);
3995
3996         USB_BUS_LOCK(udev->bus);
3997         pepext->trb_halted = 1;
3998         pepext->trb_running = 0;
3999         USB_BUS_UNLOCK(udev->bus);
4000 }
4001
4002 static void
4003 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4004 {
4005
4006 }
4007
4008 static void
4009 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4010 {
4011         struct xhci_endpoint_ext *pepext;
4012
4013         DPRINTF("\n");
4014
4015         if (udev->flags.usb_mode != USB_MODE_HOST) {
4016                 /* not supported */
4017                 return;
4018         }
4019         if (udev->parent_hub == NULL) {
4020                 /* root HUB has special endpoint handling */
4021                 return;
4022         }
4023
4024         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4025
4026         USB_BUS_LOCK(udev->bus);
4027         pepext->trb_halted = 1;
4028         pepext->trb_running = 0;
4029         USB_BUS_UNLOCK(udev->bus);
4030 }
4031
4032 static usb_error_t
4033 xhci_device_init(struct usb_device *udev)
4034 {
4035         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4036         usb_error_t err;
4037         uint8_t temp;
4038
4039         /* no init for root HUB */
4040         if (udev->parent_hub == NULL)
4041                 return (0);
4042
4043         XHCI_CMD_LOCK(sc);
4044
4045         /* set invalid default */
4046
4047         udev->controller_slot_id = sc->sc_noslot + 1;
4048
4049         /* try to get a new slot ID from the XHCI */
4050
4051         err = xhci_cmd_enable_slot(sc, &temp);
4052
4053         if (err) {
4054                 XHCI_CMD_UNLOCK(sc);
4055                 return (err);
4056         }
4057
4058         if (temp > sc->sc_noslot) {
4059                 XHCI_CMD_UNLOCK(sc);
4060                 return (USB_ERR_BAD_ADDRESS);
4061         }
4062
4063         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4064                 DPRINTF("slot %u already allocated.\n", temp);
4065                 XHCI_CMD_UNLOCK(sc);
4066                 return (USB_ERR_BAD_ADDRESS);
4067         }
4068
4069         /* store slot ID for later reference */
4070
4071         udev->controller_slot_id = temp;
4072
4073         /* reset data structure */
4074
4075         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4076
4077         /* set mark slot allocated */
4078
4079         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4080
4081         err = xhci_alloc_device_ext(udev);
4082
4083         XHCI_CMD_UNLOCK(sc);
4084
4085         /* get device into default state */
4086
4087         if (err == 0)
4088                 err = xhci_set_address(udev, NULL, 0);
4089
4090         return (err);
4091 }
4092
4093 static void
4094 xhci_device_uninit(struct usb_device *udev)
4095 {
4096         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4097         uint8_t index;
4098
4099         /* no init for root HUB */
4100         if (udev->parent_hub == NULL)
4101                 return;
4102
4103         XHCI_CMD_LOCK(sc);
4104
4105         index = udev->controller_slot_id;
4106
4107         if (index <= sc->sc_noslot) {
4108                 xhci_cmd_disable_slot(sc, index);
4109                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4110
4111                 /* free device extension */
4112                 xhci_free_device_ext(udev);
4113         }
4114
4115         XHCI_CMD_UNLOCK(sc);
4116 }
4117
4118 static void
4119 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4120 {
4121         /*
4122          * Wait until the hardware has finished any possible use of
4123          * the transfer descriptor(s)
4124          */
4125         *pus = 2048;                    /* microseconds */
4126 }
4127
4128 static void
4129 xhci_device_resume(struct usb_device *udev)
4130 {
4131         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4132         uint8_t index;
4133         uint8_t n;
4134         uint8_t p;
4135
4136         DPRINTF("\n");
4137
4138         /* check for root HUB */
4139         if (udev->parent_hub == NULL)
4140                 return;
4141
4142         index = udev->controller_slot_id;
4143
4144         XHCI_CMD_LOCK(sc);
4145
4146         /* blindly resume all endpoints */
4147
4148         USB_BUS_LOCK(udev->bus);
4149
4150         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4151                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4152                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4153                             n | XHCI_DB_SID_SET(p));
4154                 }
4155         }
4156
4157         USB_BUS_UNLOCK(udev->bus);
4158
4159         XHCI_CMD_UNLOCK(sc);
4160 }
4161
4162 static void
4163 xhci_device_suspend(struct usb_device *udev)
4164 {
4165         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4166         uint8_t index;
4167         uint8_t n;
4168         usb_error_t err;
4169
4170         DPRINTF("\n");
4171
4172         /* check for root HUB */
4173         if (udev->parent_hub == NULL)
4174                 return;
4175
4176         index = udev->controller_slot_id;
4177
4178         XHCI_CMD_LOCK(sc);
4179
4180         /* blindly suspend all endpoints */
4181
4182         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4183                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4184                 if (err != 0) {
4185                         DPRINTF("Failed to suspend endpoint "
4186                             "%u on slot %u (ignored).\n", n, index);
4187                 }
4188         }
4189
4190         XHCI_CMD_UNLOCK(sc);
4191 }
4192
4193 static void
4194 xhci_set_hw_power(struct usb_bus *bus)
4195 {
4196         DPRINTF("\n");
4197 }
4198
4199 static void
4200 xhci_device_state_change(struct usb_device *udev)
4201 {
4202         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4203         struct usb_page_search buf_inp;
4204         usb_error_t err;
4205         uint8_t index;
4206
4207         /* check for root HUB */
4208         if (udev->parent_hub == NULL)
4209                 return;
4210
4211         index = udev->controller_slot_id;
4212
4213         DPRINTF("\n");
4214
4215         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4216                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4217                     &sc->sc_hw.devs[index].tt);
4218                 if (err != 0)
4219                         sc->sc_hw.devs[index].nports = 0;
4220         }
4221
4222         XHCI_CMD_LOCK(sc);
4223
4224         switch (usb_get_device_state(udev)) {
4225         case USB_STATE_POWERED:
4226                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4227                         break;
4228
4229                 /* set default state */
4230                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4231
4232                 /* reset number of contexts */
4233                 sc->sc_hw.devs[index].context_num = 0;
4234
4235                 err = xhci_cmd_reset_dev(sc, index);
4236
4237                 if (err != 0) {
4238                         DPRINTF("Device reset failed "
4239                             "for slot %u.\n", index);
4240                 }
4241                 break;
4242
4243         case USB_STATE_ADDRESSED:
4244                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4245                         break;
4246
4247                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4248
4249                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4250
4251                 if (err) {
4252                         DPRINTF("Failed to deconfigure "
4253                             "slot %u.\n", index);
4254                 }
4255                 break;
4256
4257         case USB_STATE_CONFIGURED:
4258                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4259                         break;
4260
4261                 /* set configured state */
4262                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4263
4264                 /* reset number of contexts */
4265                 sc->sc_hw.devs[index].context_num = 0;
4266
4267                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4268
4269                 xhci_configure_mask(udev, 3, 0);
4270
4271                 err = xhci_configure_device(udev);
4272                 if (err != 0) {
4273                         DPRINTF("Could not configure device "
4274                             "at slot %u.\n", index);
4275                 }
4276
4277                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4278                 if (err != 0) {
4279                         DPRINTF("Could not evaluate device "
4280                             "context at slot %u.\n", index);
4281                 }
4282                 break;
4283
4284         default:
4285                 break;
4286         }
4287         XHCI_CMD_UNLOCK(sc);
4288 }
4289
4290 static usb_error_t
4291 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4292     uint8_t ep_mode)
4293 {
4294         switch (ep_mode) {
4295         case USB_EP_MODE_DEFAULT:
4296                 return (0);
4297         case USB_EP_MODE_STREAMS:
4298                 if (xhcistreams == 0 ||
4299                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4300                     udev->speed != USB_SPEED_SUPER)
4301                         return (USB_ERR_INVAL);
4302                 return (0);
4303         default:
4304                 return (USB_ERR_INVAL);
4305         }
4306 }
4307
4308 struct usb_bus_methods xhci_bus_methods = {
4309         .endpoint_init = xhci_ep_init,
4310         .endpoint_uninit = xhci_ep_uninit,
4311         .xfer_setup = xhci_xfer_setup,
4312         .xfer_unsetup = xhci_xfer_unsetup,
4313         .get_dma_delay = xhci_get_dma_delay,
4314         .device_init = xhci_device_init,
4315         .device_uninit = xhci_device_uninit,
4316         .device_resume = xhci_device_resume,
4317         .device_suspend = xhci_device_suspend,
4318         .set_hw_power = xhci_set_hw_power,
4319         .roothub_exec = xhci_roothub_exec,
4320         .xfer_poll = xhci_do_poll,
4321         .start_dma_delay = xhci_start_dma_delay,
4322         .set_address = xhci_set_address,
4323         .clear_stall = xhci_ep_clear_stall,
4324         .device_state_change = xhci_device_state_change,
4325         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4326         .set_endpoint_mode = xhci_set_endpoint_mode,
4327 };