3 * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
28 * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
30 * The XHCI 1.0 spec can be found at
31 * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
32 * and the USB 3.0 spec at
33 * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
37 * A few words about the design implementation: This driver emulates
38 * the concept about TDs which is found in EHCI specification. This
39 * way we achieve that the USB controller drivers look similar to
40 * eachother which makes it easier to understand the code.
43 #ifdef USB_GLOBAL_INCLUDE_FILE
44 #include USB_GLOBAL_INCLUDE_FILE
46 #include <sys/stdint.h>
47 #include <sys/stddef.h>
48 #include <sys/param.h>
49 #include <sys/queue.h>
50 #include <sys/types.h>
51 #include <sys/systm.h>
52 #include <sys/kernel.h>
54 #include <sys/module.h>
56 #include <sys/mutex.h>
57 #include <sys/condvar.h>
58 #include <sys/sysctl.h>
60 #include <sys/unistd.h>
61 #include <sys/callout.h>
62 #include <sys/malloc.h>
65 #include <dev/usb/usb.h>
66 #include <dev/usb/usbdi.h>
68 #define USB_DEBUG_VAR xhcidebug
70 #include <dev/usb/usb_core.h>
71 #include <dev/usb/usb_debug.h>
72 #include <dev/usb/usb_busdma.h>
73 #include <dev/usb/usb_process.h>
74 #include <dev/usb/usb_transfer.h>
75 #include <dev/usb/usb_device.h>
76 #include <dev/usb/usb_hub.h>
77 #include <dev/usb/usb_util.h>
79 #include <dev/usb/usb_controller.h>
80 #include <dev/usb/usb_bus.h>
81 #endif /* USB_GLOBAL_INCLUDE_FILE */
83 #include <dev/usb/controller/xhci.h>
84 #include <dev/usb/controller/xhcireg.h>
86 #define XHCI_BUS2SC(bus) \
87 ((struct xhci_softc *)(((uint8_t *)(bus)) - \
88 ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
92 static int xhcistreams;
93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
94 &xhcistreams, 0, "Set to enable streams mode support");
95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
100 static int xhcipolling;
101 static int xhcidma32;
102 static int xhcictlstep;
104 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
105 &xhcidebug, 0, "Debug level");
106 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
107 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
108 &xhciroute, 0, "Routing bitmap for switching EHCI ports to the XHCI controller");
109 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
110 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
111 &xhcipolling, 0, "Set to enable software interrupt polling for the XHCI controller");
112 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
113 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, dma32, CTLFLAG_RWTUN,
114 &xhcidma32, 0, "Set to only use 32-bit DMA for the XHCI controller");
115 TUNABLE_INT("hw.usb.xhci.dma32", &xhcidma32);
116 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, ctlstep, CTLFLAG_RWTUN,
117 &xhcictlstep, 0, "Set to enable control endpoint status stage stepping");
118 TUNABLE_INT("hw.usb.xhci.ctlstep", &xhcictlstep);
122 #define xhcictlstep 0
125 #define XHCI_INTR_ENDPT 1
127 struct xhci_std_temp {
128 struct xhci_softc *sc;
129 struct usb_page_cache *pc;
131 struct xhci_td *td_next;
134 uint32_t max_packet_size;
146 uint8_t do_isoc_sync;
149 static void xhci_do_poll(struct usb_bus *);
150 static void xhci_device_done(struct usb_xfer *, usb_error_t);
151 static void xhci_root_intr(struct xhci_softc *);
152 static void xhci_free_device_ext(struct usb_device *);
153 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
154 struct usb_endpoint_descriptor *);
155 static usb_proc_callback_t xhci_configure_msg;
156 static usb_error_t xhci_configure_device(struct usb_device *);
157 static usb_error_t xhci_configure_endpoint(struct usb_device *,
158 struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
159 uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
161 static usb_error_t xhci_configure_mask(struct usb_device *,
163 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
165 static void xhci_endpoint_doorbell(struct usb_xfer *);
166 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
167 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
168 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
170 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
173 extern struct usb_bus_methods xhci_bus_methods;
177 xhci_dump_trb(struct xhci_trb *trb)
179 DPRINTFN(5, "trb = %p\n", trb);
180 DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
181 DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
182 DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
186 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
188 DPRINTFN(5, "pep = %p\n", pep);
189 DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
190 DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
191 DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
192 DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
193 DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
194 DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
195 DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
199 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
201 DPRINTFN(5, "psl = %p\n", psl);
202 DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
203 DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
204 DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
205 DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
210 xhci_use_polling(void)
213 return (xhcipolling != 0);
220 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
222 struct xhci_softc *sc = XHCI_BUS2SC(bus);
225 cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
226 sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
228 cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
229 sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
231 for (i = 0; i != sc->sc_noscratch; i++) {
232 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
233 XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
238 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
240 if (sc->sc_ctx_is_64_byte) {
242 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
243 /* all contexts are initially 32-bytes */
244 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
245 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
251 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
253 if (sc->sc_ctx_is_64_byte) {
255 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
256 /* all contexts are initially 32-bytes */
257 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
258 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
260 return (le32toh(*ptr));
264 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
266 if (sc->sc_ctx_is_64_byte) {
268 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
269 /* all contexts are initially 32-bytes */
270 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
271 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
278 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
280 if (sc->sc_ctx_is_64_byte) {
282 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
283 /* all contexts are initially 32-bytes */
284 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
285 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
287 return (le64toh(*ptr));
292 xhci_reset_command_queue_locked(struct xhci_softc *sc)
294 struct usb_page_search buf_res;
295 struct xhci_hw_root *phwr;
301 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
302 if (temp & XHCI_CRCR_LO_CRR) {
303 DPRINTF("Command ring running\n");
304 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
307 * Try to abort the last command as per section
308 * 4.6.1.2 "Aborting a Command" of the XHCI
312 /* stop and cancel */
313 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
314 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
316 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
317 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
320 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
322 /* check if command ring is still running */
323 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
324 if (temp & XHCI_CRCR_LO_CRR) {
325 DPRINTF("Comand ring still running\n");
326 return (USB_ERR_IOERROR);
330 /* reset command ring */
331 sc->sc_command_ccs = 1;
332 sc->sc_command_idx = 0;
334 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
336 /* set up command ring control base address */
337 addr = buf_res.physaddr;
338 phwr = buf_res.buffer;
339 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
341 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
343 memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
344 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
346 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
348 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
349 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
355 xhci_start_controller(struct xhci_softc *sc)
357 struct usb_page_search buf_res;
358 struct xhci_hw_root *phwr;
359 struct xhci_dev_ctx_addr *pdctxa;
367 sc->sc_event_ccs = 1;
368 sc->sc_event_idx = 0;
369 sc->sc_command_ccs = 1;
370 sc->sc_command_idx = 0;
372 err = xhci_reset_controller(sc);
376 /* set up number of device slots */
377 DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
378 XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
380 XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
382 temp = XREAD4(sc, oper, XHCI_USBSTS);
384 /* clear interrupts */
385 XWRITE4(sc, oper, XHCI_USBSTS, temp);
386 /* disable all device notifications */
387 XWRITE4(sc, oper, XHCI_DNCTRL, 0);
389 /* set up device context base address */
390 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
391 pdctxa = buf_res.buffer;
392 memset(pdctxa, 0, sizeof(*pdctxa));
394 addr = buf_res.physaddr;
395 addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
397 /* slot 0 points to the table of scratchpad pointers */
398 pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
400 for (i = 0; i != sc->sc_noscratch; i++) {
401 struct usb_page_search buf_scp;
402 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
403 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
406 addr = buf_res.physaddr;
408 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
409 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
410 XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
411 XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
413 /* set up event table size */
414 DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
415 XREAD4(sc, runt, XHCI_ERSTSZ(0)), sc->sc_erst_max);
417 XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(sc->sc_erst_max));
419 /* set up interrupt rate */
420 XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
422 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
424 phwr = buf_res.buffer;
425 addr = buf_res.physaddr;
426 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
428 /* reset hardware root structure */
429 memset(phwr, 0, sizeof(*phwr));
431 phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
432 phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
434 DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
436 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
437 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
439 addr = buf_res.physaddr;
441 DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
443 XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
444 XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
446 /* set up interrupter registers */
447 temp = XREAD4(sc, runt, XHCI_IMAN(0));
448 temp |= XHCI_IMAN_INTR_ENA;
449 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
451 /* set up command ring control base address */
452 addr = buf_res.physaddr;
453 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
455 DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
457 XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
458 XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
460 phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
462 usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
465 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
466 XHCI_CMD_INTE | XHCI_CMD_HSEE);
468 for (i = 0; i != 100; i++) {
469 usb_pause_mtx(NULL, hz / 100);
470 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
475 XWRITE4(sc, oper, XHCI_USBCMD, 0);
476 device_printf(sc->sc_bus.parent, "Run timeout.\n");
477 return (USB_ERR_IOERROR);
480 /* catch any lost interrupts */
481 xhci_do_poll(&sc->sc_bus);
483 if (sc->sc_port_route != NULL) {
484 /* Route all ports to the XHCI by default */
485 sc->sc_port_route(sc->sc_bus.parent,
486 ~xhciroute, xhciroute);
492 xhci_halt_controller(struct xhci_softc *sc)
500 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
501 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
502 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
504 /* Halt controller */
505 XWRITE4(sc, oper, XHCI_USBCMD, 0);
507 for (i = 0; i != 100; i++) {
508 usb_pause_mtx(NULL, hz / 100);
509 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
515 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
516 return (USB_ERR_IOERROR);
522 xhci_reset_controller(struct xhci_softc *sc)
529 /* Reset controller */
530 XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
532 for (i = 0; i != 100; i++) {
533 usb_pause_mtx(NULL, hz / 100);
534 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
535 (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
541 device_printf(sc->sc_bus.parent, "Controller "
543 return (USB_ERR_IOERROR);
549 xhci_init(struct xhci_softc *sc, device_t self, uint8_t dma32)
555 /* initialize some bus fields */
556 sc->sc_bus.parent = self;
558 /* set the bus revision */
559 sc->sc_bus.usbrev = USB_REV_3_0;
561 /* set up the bus struct */
562 sc->sc_bus.methods = &xhci_bus_methods;
564 /* set up devices array */
565 sc->sc_bus.devices = sc->sc_devices;
566 sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
568 /* set default cycle state in case of early interrupts */
569 sc->sc_event_ccs = 1;
570 sc->sc_command_ccs = 1;
572 /* set up bus space offsets */
574 sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
575 sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
576 sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
578 DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
579 DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
580 DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
582 DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
584 if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
585 device_printf(sc->sc_bus.parent, "Controller does "
586 "not support 4K page size.\n");
590 temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
592 DPRINTF("HCS0 = 0x%08x\n", temp);
594 /* set up context size */
595 if (XHCI_HCS0_CSZ(temp)) {
596 sc->sc_ctx_is_64_byte = 1;
598 sc->sc_ctx_is_64_byte = 0;
602 sc->sc_bus.dma_bits = (XHCI_HCS0_AC64(temp) &&
603 xhcidma32 == 0 && dma32 == 0) ? 64 : 32;
605 device_printf(self, "%d bytes context size, %d-bit DMA\n",
606 sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
608 temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
610 /* get number of device slots */
611 sc->sc_noport = XHCI_HCS1_N_PORTS(temp);
613 if (sc->sc_noport == 0) {
614 device_printf(sc->sc_bus.parent, "Invalid number "
615 "of ports: %u\n", sc->sc_noport);
619 sc->sc_noport = sc->sc_noport;
620 sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
622 DPRINTF("Max slots: %u\n", sc->sc_noslot);
624 if (sc->sc_noslot > XHCI_MAX_DEVICES)
625 sc->sc_noslot = XHCI_MAX_DEVICES;
627 temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
629 DPRINTF("HCS2=0x%08x\n", temp);
631 /* get number of scratchpads */
632 sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
634 if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
635 device_printf(sc->sc_bus.parent, "XHCI request "
636 "too many scratchpads\n");
640 DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
642 /* get event table size */
643 sc->sc_erst_max = 1U << XHCI_HCS2_ERST_MAX(temp);
644 if (sc->sc_erst_max > XHCI_MAX_RSEG)
645 sc->sc_erst_max = XHCI_MAX_RSEG;
647 temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
649 /* get maximum exit latency */
650 sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
651 XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
653 /* Check if we should use the default IMOD value. */
654 if (sc->sc_imod_default == 0)
655 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
657 /* get all DMA memory */
658 if (usb_bus_mem_alloc_all(&sc->sc_bus,
659 USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
663 /* set up command queue mutex and condition varible */
664 cv_init(&sc->sc_cmd_cv, "CMDQ");
665 sx_init(&sc->sc_cmd_sx, "CMDQ lock");
667 sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
668 sc->sc_config_msg[0].bus = &sc->sc_bus;
669 sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
670 sc->sc_config_msg[1].bus = &sc->sc_bus;
676 xhci_uninit(struct xhci_softc *sc)
679 * NOTE: At this point the control transfer process is gone
680 * and "xhci_configure_msg" is no longer called. Consequently
681 * waiting for the configuration messages to complete is not
684 usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
686 cv_destroy(&sc->sc_cmd_cv);
687 sx_destroy(&sc->sc_cmd_sx);
691 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
693 struct xhci_softc *sc = XHCI_BUS2SC(bus);
696 case USB_HW_POWER_SUSPEND:
697 DPRINTF("Stopping the XHCI\n");
698 xhci_halt_controller(sc);
699 xhci_reset_controller(sc);
701 case USB_HW_POWER_SHUTDOWN:
702 DPRINTF("Stopping the XHCI\n");
703 xhci_halt_controller(sc);
704 xhci_reset_controller(sc);
706 case USB_HW_POWER_RESUME:
707 DPRINTF("Starting the XHCI\n");
708 xhci_start_controller(sc);
716 xhci_generic_done_sub(struct usb_xfer *xfer)
719 struct xhci_td *td_alt_next;
723 td = xfer->td_transfer_cache;
724 td_alt_next = td->alt_next;
726 if (xfer->aframes != xfer->nframes)
727 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
731 usb_pc_cpu_invalidate(td->page_cache);
736 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
737 xfer, (unsigned int)xfer->aframes,
738 (unsigned int)xfer->nframes,
739 (unsigned int)len, (unsigned int)td->len,
740 (unsigned int)status);
743 * Verify the status length and
744 * add the length to "frlengths[]":
747 /* should not happen */
748 DPRINTF("Invalid status length, "
749 "0x%04x/0x%04x bytes\n", len, td->len);
750 status = XHCI_TRB_ERROR_LENGTH;
751 } else if (xfer->aframes != xfer->nframes) {
752 xfer->frlengths[xfer->aframes] += td->len - len;
754 /* Check for last transfer */
755 if (((void *)td) == xfer->td_transfer_last) {
759 /* Check for transfer error */
760 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
761 status != XHCI_TRB_ERROR_SUCCESS) {
762 /* the transfer is finished */
766 /* Check for short transfer */
768 if (xfer->flags_int.short_frames_ok ||
769 xfer->flags_int.isochronous_xfr ||
770 xfer->flags_int.control_xfr) {
771 /* follow alt next */
774 /* the transfer is finished */
781 if (td->alt_next != td_alt_next) {
782 /* this USB frame is complete */
787 /* update transfer cache */
789 xfer->td_transfer_cache = td;
791 return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
792 (status != XHCI_TRB_ERROR_SHORT_PKT &&
793 status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
794 USB_ERR_NORMAL_COMPLETION);
798 xhci_generic_done(struct usb_xfer *xfer)
802 DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
803 xfer, xfer->endpoint);
807 xfer->td_transfer_cache = xfer->td_transfer_first;
809 if (xfer->flags_int.control_xfr) {
811 if (xfer->flags_int.control_hdr)
812 err = xhci_generic_done_sub(xfer);
816 if (xfer->td_transfer_cache == NULL)
820 while (xfer->aframes != xfer->nframes) {
822 err = xhci_generic_done_sub(xfer);
825 if (xfer->td_transfer_cache == NULL)
829 if (xfer->flags_int.control_xfr &&
830 !xfer->flags_int.control_act)
831 err = xhci_generic_done_sub(xfer);
833 /* transfer is complete */
834 xhci_device_done(xfer, err);
838 xhci_activate_transfer(struct usb_xfer *xfer)
842 td = xfer->td_transfer_cache;
844 usb_pc_cpu_invalidate(td->page_cache);
846 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
848 /* activate the transfer */
850 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
851 usb_pc_cpu_flush(td->page_cache);
853 xhci_endpoint_doorbell(xfer);
858 xhci_skip_transfer(struct usb_xfer *xfer)
861 struct xhci_td *td_last;
863 td = xfer->td_transfer_cache;
864 td_last = xfer->td_transfer_last;
868 usb_pc_cpu_invalidate(td->page_cache);
870 if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
872 usb_pc_cpu_invalidate(td_last->page_cache);
874 /* copy LINK TRB to current waiting location */
876 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
877 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
878 usb_pc_cpu_flush(td->page_cache);
880 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
881 usb_pc_cpu_flush(td->page_cache);
883 xhci_endpoint_doorbell(xfer);
887 /*------------------------------------------------------------------------*
888 * xhci_check_transfer
889 *------------------------------------------------------------------------*/
891 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
893 struct xhci_endpoint_ext *pepext;
906 td_event = le64toh(trb->qwTrb0);
907 temp = le32toh(trb->dwTrb2);
909 remainder = XHCI_TRB_2_REM_GET(temp);
910 status = XHCI_TRB_2_ERROR_GET(temp);
911 stream_id = XHCI_TRB_2_STREAM_GET(temp);
913 temp = le32toh(trb->dwTrb3);
914 epno = XHCI_TRB_3_EP_GET(temp);
915 index = XHCI_TRB_3_SLOT_GET(temp);
917 /* check if error means halted */
918 halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
919 status != XHCI_TRB_ERROR_SUCCESS);
921 DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
922 index, epno, stream_id, remainder, status);
924 if (index > sc->sc_noslot) {
925 DPRINTF("Invalid slot.\n");
929 if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
930 DPRINTF("Invalid endpoint.\n");
934 pepext = &sc->sc_hw.devs[index].endp[epno];
936 if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
938 DPRINTF("stream_id=0\n");
939 } else if (stream_id >= XHCI_MAX_STREAMS) {
940 DPRINTF("Invalid stream ID.\n");
944 /* try to find the USB transfer that generated the event */
945 for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
946 struct usb_xfer *xfer;
949 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
953 td = xfer->td_transfer_cache;
955 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
957 (long long)td->td_self,
958 (long long)td->td_self + sizeof(td->td_trb));
961 * NOTE: Some XHCI implementations might not trigger
962 * an event on the last LINK TRB so we need to
963 * consider both the last and second last event
964 * address as conditions for a successful transfer.
966 * NOTE: We assume that the XHCI will only trigger one
967 * event per chain of TRBs.
970 offset = td_event - td->td_self;
973 offset < (int64_t)sizeof(td->td_trb)) {
975 usb_pc_cpu_invalidate(td->page_cache);
977 /* compute rest of remainder, if any */
978 for (i = (offset / 16) + 1; i < td->ntrb; i++) {
979 temp = le32toh(td->td_trb[i].dwTrb2);
980 remainder += XHCI_TRB_2_BYTES_GET(temp);
983 DPRINTFN(5, "New remainder: %u\n", remainder);
985 /* clear isochronous transfer errors */
986 if (xfer->flags_int.isochronous_xfr) {
989 status = XHCI_TRB_ERROR_SUCCESS;
994 /* "td->remainder" is verified later */
995 td->remainder = remainder;
998 usb_pc_cpu_flush(td->page_cache);
1001 * 1) Last transfer descriptor makes the
1004 if (((void *)td) == xfer->td_transfer_last) {
1005 DPRINTF("TD is last\n");
1006 xhci_generic_done(xfer);
1011 * 2) Any kind of error makes the transfer
1015 DPRINTF("TD has I/O error\n");
1016 xhci_generic_done(xfer);
1021 * 3) If there is no alternate next transfer,
1022 * a short packet also makes the transfer done
1024 if (td->remainder > 0) {
1025 if (td->alt_next == NULL) {
1027 "short TD has no alternate next\n");
1028 xhci_generic_done(xfer);
1031 DPRINTF("TD has short pkt\n");
1032 if (xfer->flags_int.short_frames_ok ||
1033 xfer->flags_int.isochronous_xfr ||
1034 xfer->flags_int.control_xfr) {
1035 /* follow the alt next */
1036 xfer->td_transfer_cache = td->alt_next;
1037 xhci_activate_transfer(xfer);
1040 xhci_skip_transfer(xfer);
1041 xhci_generic_done(xfer);
1046 * 4) Transfer complete - go to next TD
1048 DPRINTF("Following next TD\n");
1049 xfer->td_transfer_cache = td->obj_next;
1050 xhci_activate_transfer(xfer);
1051 break; /* there should only be one match */
1057 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1059 if (sc->sc_cmd_addr == trb->qwTrb0) {
1060 DPRINTF("Received command event\n");
1061 sc->sc_cmd_result[0] = trb->dwTrb2;
1062 sc->sc_cmd_result[1] = trb->dwTrb3;
1063 cv_signal(&sc->sc_cmd_cv);
1064 return (1); /* command match */
1070 xhci_interrupt_poll(struct xhci_softc *sc)
1072 struct usb_page_search buf_res;
1073 struct xhci_hw_root *phwr;
1083 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1085 phwr = buf_res.buffer;
1087 /* Receive any events */
1089 usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1091 i = sc->sc_event_idx;
1092 j = sc->sc_event_ccs;
1097 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1099 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1104 event = XHCI_TRB_3_TYPE_GET(temp);
1106 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1107 i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1108 (long)le32toh(phwr->hwr_events[i].dwTrb2),
1109 (long)le32toh(phwr->hwr_events[i].dwTrb3));
1112 case XHCI_TRB_EVENT_TRANSFER:
1113 xhci_check_transfer(sc, &phwr->hwr_events[i]);
1115 case XHCI_TRB_EVENT_CMD_COMPLETE:
1116 retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1119 DPRINTF("Unhandled event = %u\n", event);
1125 if (i == XHCI_MAX_EVENTS) {
1129 /* check for timeout */
1135 sc->sc_event_idx = i;
1136 sc->sc_event_ccs = j;
1139 * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1140 * latched. That means to activate the register we need to
1141 * write both the low and high double word of the 64-bit
1145 addr = buf_res.physaddr;
1146 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1148 /* try to clear busy bit */
1149 addr |= XHCI_ERDP_LO_BUSY;
1151 XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1152 XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1158 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1159 uint16_t timeout_ms)
1161 struct usb_page_search buf_res;
1162 struct xhci_hw_root *phwr;
1167 uint8_t timeout = 0;
1170 XHCI_CMD_ASSERT_LOCKED(sc);
1172 /* get hardware root structure */
1174 usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1176 phwr = buf_res.buffer;
1180 USB_BUS_LOCK(&sc->sc_bus);
1182 i = sc->sc_command_idx;
1183 j = sc->sc_command_ccs;
1185 DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1186 i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1187 (long long)le64toh(trb->qwTrb0),
1188 (long)le32toh(trb->dwTrb2),
1189 (long)le32toh(trb->dwTrb3));
1191 phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1192 phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1194 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1199 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1201 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1203 temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1205 phwr->hwr_commands[i].dwTrb3 = temp;
1207 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1209 addr = buf_res.physaddr;
1210 addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1212 sc->sc_cmd_addr = htole64(addr);
1216 if (i == (XHCI_MAX_COMMANDS - 1)) {
1219 temp = htole32(XHCI_TRB_3_TC_BIT |
1220 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1221 XHCI_TRB_3_CYCLE_BIT);
1223 temp = htole32(XHCI_TRB_3_TC_BIT |
1224 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1227 phwr->hwr_commands[i].dwTrb3 = temp;
1229 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1235 sc->sc_command_idx = i;
1236 sc->sc_command_ccs = j;
1238 XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1240 err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1241 USB_MS_TO_TICKS(timeout_ms));
1244 * In some error cases event interrupts are not generated.
1245 * Poll one time to see if the command has completed.
1247 if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1248 DPRINTF("Command was completed when polling\n");
1252 DPRINTF("Command timeout!\n");
1254 * After some weeks of continuous operation, it has
1255 * been observed that the ASMedia Technology, ASM1042
1256 * SuperSpeed USB Host Controller can suddenly stop
1257 * accepting commands via the command queue. Try to
1258 * first reset the command queue. If that fails do a
1259 * host controller reset.
1262 xhci_reset_command_queue_locked(sc) == 0) {
1263 temp = le32toh(trb->dwTrb3);
1266 * Avoid infinite XHCI reset loops if the set
1267 * address command fails to respond due to a
1268 * non-enumerating device:
1270 if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1271 (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1272 DPRINTF("Set address timeout\n");
1278 DPRINTF("Controller reset!\n");
1279 usb_bus_reset_async_locked(&sc->sc_bus);
1281 err = USB_ERR_TIMEOUT;
1285 temp = le32toh(sc->sc_cmd_result[0]);
1286 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1287 err = USB_ERR_IOERROR;
1289 trb->dwTrb2 = sc->sc_cmd_result[0];
1290 trb->dwTrb3 = sc->sc_cmd_result[1];
1293 USB_BUS_UNLOCK(&sc->sc_bus);
1300 xhci_cmd_nop(struct xhci_softc *sc)
1302 struct xhci_trb trb;
1309 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1311 trb.dwTrb3 = htole32(temp);
1313 return (xhci_do_command(sc, &trb, 100 /* ms */));
1318 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1320 struct xhci_trb trb;
1328 trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1330 err = xhci_do_command(sc, &trb, 100 /* ms */);
1334 temp = le32toh(trb.dwTrb3);
1336 *pslot = XHCI_TRB_3_SLOT_GET(temp);
1343 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1345 struct xhci_trb trb;
1352 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1353 XHCI_TRB_3_SLOT_SET(slot_id);
1355 trb.dwTrb3 = htole32(temp);
1357 return (xhci_do_command(sc, &trb, 100 /* ms */));
1361 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1362 uint8_t bsr, uint8_t slot_id)
1364 struct xhci_trb trb;
1369 trb.qwTrb0 = htole64(input_ctx);
1371 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1372 XHCI_TRB_3_SLOT_SET(slot_id);
1375 temp |= XHCI_TRB_3_BSR_BIT;
1377 trb.dwTrb3 = htole32(temp);
1379 return (xhci_do_command(sc, &trb, 500 /* ms */));
1383 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1385 struct usb_page_search buf_inp;
1386 struct usb_page_search buf_dev;
1387 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1388 struct xhci_hw_dev *hdev;
1389 struct xhci_dev_ctx *pdev;
1390 struct xhci_endpoint_ext *pepext;
1396 /* the root HUB case is not handled here */
1397 if (udev->parent_hub == NULL)
1398 return (USB_ERR_INVAL);
1400 index = udev->controller_slot_id;
1402 hdev = &sc->sc_hw.devs[index];
1409 switch (hdev->state) {
1410 case XHCI_ST_DEFAULT:
1411 case XHCI_ST_ENABLED:
1413 hdev->state = XHCI_ST_ENABLED;
1415 /* set configure mask to slot and EP0 */
1416 xhci_configure_mask(udev, 3, 0);
1418 /* configure input slot context structure */
1419 err = xhci_configure_device(udev);
1422 DPRINTF("Could not configure device\n");
1426 /* configure input endpoint context structure */
1427 switch (udev->speed) {
1429 case USB_SPEED_FULL:
1432 case USB_SPEED_HIGH:
1440 pepext = xhci_get_endpoint_ext(udev,
1441 &udev->ctrl_ep_desc);
1443 /* ensure the control endpoint is setup again */
1444 USB_BUS_LOCK(udev->bus);
1445 pepext->trb_halted = 1;
1446 pepext->trb_running = 0;
1447 USB_BUS_UNLOCK(udev->bus);
1449 err = xhci_configure_endpoint(udev,
1450 &udev->ctrl_ep_desc, pepext,
1451 0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1454 DPRINTF("Could not configure default endpoint\n");
1458 /* execute set address command */
1459 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1461 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1462 (address == 0), index);
1465 temp = le32toh(sc->sc_cmd_result[0]);
1466 if (address == 0 && sc->sc_port_route != NULL &&
1467 XHCI_TRB_2_ERROR_GET(temp) ==
1468 XHCI_TRB_ERROR_PARAMETER) {
1469 /* LynxPoint XHCI - ports are not switchable */
1470 /* Un-route all ports from the XHCI */
1471 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1473 DPRINTF("Could not set address "
1474 "for slot %u.\n", index);
1479 /* update device address to new value */
1481 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1482 pdev = buf_dev.buffer;
1483 usb_pc_cpu_invalidate(&hdev->device_pc);
1485 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1486 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1488 /* update device state to new value */
1491 hdev->state = XHCI_ST_ADDRESSED;
1493 hdev->state = XHCI_ST_DEFAULT;
1497 DPRINTF("Wrong state for set address.\n");
1498 err = USB_ERR_IOERROR;
1501 XHCI_CMD_UNLOCK(sc);
1510 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1511 uint8_t deconfigure, uint8_t slot_id)
1513 struct xhci_trb trb;
1518 trb.qwTrb0 = htole64(input_ctx);
1520 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1521 XHCI_TRB_3_SLOT_SET(slot_id);
1524 temp |= XHCI_TRB_3_DCEP_BIT;
1526 trb.dwTrb3 = htole32(temp);
1528 return (xhci_do_command(sc, &trb, 100 /* ms */));
1532 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1535 struct xhci_trb trb;
1540 trb.qwTrb0 = htole64(input_ctx);
1542 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1543 XHCI_TRB_3_SLOT_SET(slot_id);
1544 trb.dwTrb3 = htole32(temp);
1546 return (xhci_do_command(sc, &trb, 100 /* ms */));
1550 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1551 uint8_t ep_id, uint8_t slot_id)
1553 struct xhci_trb trb;
1560 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1561 XHCI_TRB_3_SLOT_SET(slot_id) |
1562 XHCI_TRB_3_EP_SET(ep_id);
1565 temp |= XHCI_TRB_3_PRSV_BIT;
1567 trb.dwTrb3 = htole32(temp);
1569 return (xhci_do_command(sc, &trb, 100 /* ms */));
1573 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1574 uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1576 struct xhci_trb trb;
1581 trb.qwTrb0 = htole64(dequeue_ptr);
1583 temp = XHCI_TRB_2_STREAM_SET(stream_id);
1584 trb.dwTrb2 = htole32(temp);
1586 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1587 XHCI_TRB_3_SLOT_SET(slot_id) |
1588 XHCI_TRB_3_EP_SET(ep_id);
1589 trb.dwTrb3 = htole32(temp);
1591 return (xhci_do_command(sc, &trb, 100 /* ms */));
1595 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1596 uint8_t ep_id, uint8_t slot_id)
1598 struct xhci_trb trb;
1605 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1606 XHCI_TRB_3_SLOT_SET(slot_id) |
1607 XHCI_TRB_3_EP_SET(ep_id);
1610 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1612 trb.dwTrb3 = htole32(temp);
1614 return (xhci_do_command(sc, &trb, 100 /* ms */));
1618 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1620 struct xhci_trb trb;
1627 temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1628 XHCI_TRB_3_SLOT_SET(slot_id);
1630 trb.dwTrb3 = htole32(temp);
1632 return (xhci_do_command(sc, &trb, 100 /* ms */));
1635 /*------------------------------------------------------------------------*
1636 * xhci_interrupt - XHCI interrupt handler
1637 *------------------------------------------------------------------------*/
1639 xhci_interrupt(struct xhci_softc *sc)
1644 USB_BUS_LOCK(&sc->sc_bus);
1646 status = XREAD4(sc, oper, XHCI_USBSTS);
1648 /* acknowledge interrupts, if any */
1650 XWRITE4(sc, oper, XHCI_USBSTS, status);
1651 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1654 temp = XREAD4(sc, runt, XHCI_IMAN(0));
1656 /* force clearing of pending interrupts */
1657 if (temp & XHCI_IMAN_INTR_PEND)
1658 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1660 /* check for event(s) */
1661 xhci_interrupt_poll(sc);
1663 if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1664 XHCI_STS_HSE | XHCI_STS_HCE)) {
1666 if (status & XHCI_STS_PCD) {
1670 if (status & XHCI_STS_HCH) {
1671 printf("%s: host controller halted\n",
1675 if (status & XHCI_STS_HSE) {
1676 printf("%s: host system error\n",
1680 if (status & XHCI_STS_HCE) {
1681 printf("%s: host controller error\n",
1685 USB_BUS_UNLOCK(&sc->sc_bus);
1688 /*------------------------------------------------------------------------*
1689 * xhci_timeout - XHCI timeout handler
1690 *------------------------------------------------------------------------*/
1692 xhci_timeout(void *arg)
1694 struct usb_xfer *xfer = arg;
1696 DPRINTF("xfer=%p\n", xfer);
1698 USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1700 /* transfer is transferred */
1701 xhci_device_done(xfer, USB_ERR_TIMEOUT);
1705 xhci_do_poll(struct usb_bus *bus)
1707 struct xhci_softc *sc = XHCI_BUS2SC(bus);
1709 USB_BUS_LOCK(&sc->sc_bus);
1710 xhci_interrupt_poll(sc);
1711 USB_BUS_UNLOCK(&sc->sc_bus);
1715 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1717 struct usb_page_search buf_res;
1719 struct xhci_td *td_next;
1720 struct xhci_td *td_alt_next;
1721 struct xhci_td *td_first;
1722 uint32_t buf_offset;
1727 uint8_t shortpkt_old;
1733 shortpkt_old = temp->shortpkt;
1734 len_old = temp->len;
1741 td_next = td_first = temp->td_next;
1745 if (temp->len == 0) {
1750 /* send a Zero Length Packet, ZLP, last */
1757 average = temp->average;
1759 if (temp->len < average) {
1760 if (temp->len % temp->max_packet_size) {
1763 average = temp->len;
1767 if (td_next == NULL)
1768 panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1773 td_next = td->obj_next;
1775 /* check if we are pre-computing */
1779 /* update remaining length */
1781 temp->len -= average;
1785 /* fill out current TD */
1791 /* update remaining length */
1793 temp->len -= average;
1795 /* reset TRB index */
1799 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1800 /* immediate data */
1805 td->td_trb[0].qwTrb0 = 0;
1807 usbd_copy_out(temp->pc, temp->offset + buf_offset,
1808 (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1811 dword = XHCI_TRB_2_BYTES_SET(8) |
1812 XHCI_TRB_2_TDSZ_SET(0) |
1813 XHCI_TRB_2_IRQ_SET(0);
1815 td->td_trb[0].dwTrb2 = htole32(dword);
1817 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1818 XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1821 if (td->td_trb[0].qwTrb0 &
1822 htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1823 if (td->td_trb[0].qwTrb0 &
1824 htole64(XHCI_TRB_0_DIR_IN_MASK))
1825 dword |= XHCI_TRB_3_TRT_IN;
1827 dword |= XHCI_TRB_3_TRT_OUT;
1830 td->td_trb[0].dwTrb3 = htole32(dword);
1832 xhci_dump_trb(&td->td_trb[x]);
1840 /* fill out buffer pointers */
1843 memset(&buf_res, 0, sizeof(buf_res));
1845 usbd_get_page(temp->pc, temp->offset +
1846 buf_offset, &buf_res);
1848 /* get length to end of page */
1849 if (buf_res.length > average)
1850 buf_res.length = average;
1852 /* check for maximum length */
1853 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1854 buf_res.length = XHCI_TD_PAGE_SIZE;
1856 npkt_off += buf_res.length;
1860 npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1861 temp->max_packet_size;
1868 /* fill out TRB's */
1869 td->td_trb[x].qwTrb0 =
1870 htole64((uint64_t)buf_res.physaddr);
1873 XHCI_TRB_2_BYTES_SET(buf_res.length) |
1874 XHCI_TRB_2_TDSZ_SET(npkt) |
1875 XHCI_TRB_2_IRQ_SET(0);
1877 td->td_trb[x].dwTrb2 = htole32(dword);
1879 switch (temp->trb_type) {
1880 case XHCI_TRB_TYPE_ISOCH:
1881 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1882 XHCI_TRB_3_TBC_SET(temp->tbc) |
1883 XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1884 if (td != td_first) {
1885 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1886 } else if (temp->do_isoc_sync != 0) {
1887 temp->do_isoc_sync = 0;
1888 /* wait until "isoc_frame" */
1889 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1890 XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1892 /* start data transfer at next interval */
1893 dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1894 XHCI_TRB_3_ISO_SIA_BIT;
1896 if (temp->direction == UE_DIR_IN)
1897 dword |= XHCI_TRB_3_ISP_BIT;
1899 case XHCI_TRB_TYPE_DATA_STAGE:
1900 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1901 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1902 if (temp->direction == UE_DIR_IN)
1903 dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1905 * Section 3.2.9 in the XHCI
1906 * specification about control
1907 * transfers says that we should use a
1908 * normal-TRB if there are more TRBs
1909 * extending the data-stage
1910 * TRB. Update the "trb_type".
1912 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1914 case XHCI_TRB_TYPE_STATUS_STAGE:
1915 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1916 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1917 if (temp->direction == UE_DIR_IN)
1918 dword |= XHCI_TRB_3_DIR_IN;
1920 default: /* XHCI_TRB_TYPE_NORMAL */
1921 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1922 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1923 if (temp->direction == UE_DIR_IN)
1924 dword |= XHCI_TRB_3_ISP_BIT;
1927 td->td_trb[x].dwTrb3 = htole32(dword);
1929 average -= buf_res.length;
1930 buf_offset += buf_res.length;
1932 xhci_dump_trb(&td->td_trb[x]);
1936 } while (average != 0);
1938 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1940 /* store number of data TRB's */
1944 DPRINTF("NTRB=%u\n", x);
1946 /* fill out link TRB */
1948 if (td_next != NULL) {
1949 /* link the current TD with the next one */
1950 td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1951 DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1953 /* this field will get updated later */
1954 DPRINTF("NOLINK\n");
1957 dword = XHCI_TRB_2_IRQ_SET(0);
1959 td->td_trb[x].dwTrb2 = htole32(dword);
1961 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1962 XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1964 * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1965 * frame only receives a single short packet event
1966 * by setting the CHAIN bit in the LINK field. In
1967 * addition some XHCI controllers have problems
1968 * sending a ZLP unless the CHAIN-BIT is set in
1971 XHCI_TRB_3_CHAIN_BIT;
1973 td->td_trb[x].dwTrb3 = htole32(dword);
1975 td->alt_next = td_alt_next;
1977 xhci_dump_trb(&td->td_trb[x]);
1979 usb_pc_cpu_flush(td->page_cache);
1985 /* set up alt next pointer, if any */
1986 if (temp->last_frame) {
1989 /* we use this field internally */
1990 td_alt_next = td_next;
1994 temp->shortpkt = shortpkt_old;
1995 temp->len = len_old;
2000 * Remove cycle bit from the first TRB if we are
2003 if (temp->step_td != 0) {
2004 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
2005 usb_pc_cpu_flush(td_first->page_cache);
2008 /* clear TD SIZE to zero, hence this is the last TRB */
2009 /* remove chain bit because this is the last data TRB in the chain */
2010 td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
2011 td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2012 /* remove CHAIN-BIT from last LINK TRB */
2013 td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
2015 usb_pc_cpu_flush(td->page_cache);
2018 temp->td_next = td_next;
2022 xhci_setup_generic_chain(struct usb_xfer *xfer)
2024 struct xhci_std_temp temp;
2030 temp.do_isoc_sync = 0;
2034 temp.average = xfer->max_hc_frame_size;
2035 temp.max_packet_size = xfer->max_packet_size;
2036 temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2038 temp.last_frame = 0;
2040 temp.multishort = xfer->flags_int.isochronous_xfr ||
2041 xfer->flags_int.control_xfr ||
2042 xfer->flags_int.short_frames_ok;
2044 /* toggle the DMA set we are using */
2045 xfer->flags_int.curr_dma_set ^= 1;
2047 /* get next DMA set */
2048 td = xfer->td_start[xfer->flags_int.curr_dma_set];
2053 xfer->td_transfer_first = td;
2054 xfer->td_transfer_cache = td;
2056 if (xfer->flags_int.isochronous_xfr) {
2059 /* compute multiplier for ISOCHRONOUS transfers */
2060 mult = xfer->endpoint->ecomp ?
2061 UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2063 /* check for USB 2.0 multiplier */
2065 mult = (xfer->endpoint->edesc->
2066 wMaxPacketSize[1] >> 3) & 3;
2074 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2076 DPRINTF("MFINDEX=0x%08x\n", x);
2078 switch (usbd_get_speed(xfer->xroot->udev)) {
2079 case USB_SPEED_FULL:
2081 temp.isoc_delta = 8; /* 1ms */
2082 x += temp.isoc_delta - 1;
2083 x &= ~(temp.isoc_delta - 1);
2086 shift = usbd_xfer_get_fps_shift(xfer);
2087 temp.isoc_delta = 1U << shift;
2088 x += temp.isoc_delta - 1;
2089 x &= ~(temp.isoc_delta - 1);
2090 /* simple frame load balancing */
2091 x += xfer->endpoint->usb_uframe;
2095 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2097 if ((xfer->endpoint->is_synced == 0) ||
2098 (y < (xfer->nframes << shift)) ||
2099 (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2101 * If there is data underflow or the pipe
2102 * queue is empty we schedule the transfer a
2103 * few frames ahead of the current frame
2104 * position. Else two isochronous transfers
2107 xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2108 xfer->endpoint->is_synced = 1;
2109 temp.do_isoc_sync = 1;
2111 DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2114 /* compute isochronous completion time */
2116 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2118 xfer->isoc_time_complete =
2119 usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2120 (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2123 temp.isoc_frame = xfer->endpoint->isoc_next;
2124 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2126 xfer->endpoint->isoc_next += xfer->nframes << shift;
2128 } else if (xfer->flags_int.control_xfr) {
2130 /* check if we should prepend a setup message */
2132 if (xfer->flags_int.control_hdr) {
2134 temp.len = xfer->frlengths[0];
2135 temp.pc = xfer->frbuffers + 0;
2136 temp.shortpkt = temp.len ? 1 : 0;
2137 temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2140 /* check for last frame */
2141 if (xfer->nframes == 1) {
2142 /* no STATUS stage yet, SETUP is last */
2143 if (xfer->flags_int.control_act)
2144 temp.last_frame = 1;
2147 xhci_setup_generic_chain_sub(&temp);
2151 temp.isoc_delta = 0;
2152 temp.isoc_frame = 0;
2153 temp.trb_type = xfer->flags_int.control_did_data ?
2154 XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2158 temp.isoc_delta = 0;
2159 temp.isoc_frame = 0;
2160 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2163 if (x != xfer->nframes) {
2164 /* set up page_cache pointer */
2165 temp.pc = xfer->frbuffers + x;
2166 /* set endpoint direction */
2167 temp.direction = UE_GET_DIR(xfer->endpointno);
2170 while (x != xfer->nframes) {
2172 /* DATA0 / DATA1 message */
2174 temp.len = xfer->frlengths[x];
2175 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2176 x != 0 && temp.multishort == 0);
2180 if (x == xfer->nframes) {
2181 if (xfer->flags_int.control_xfr) {
2182 /* no STATUS stage yet, DATA is last */
2183 if (xfer->flags_int.control_act)
2184 temp.last_frame = 1;
2186 temp.last_frame = 1;
2189 if (temp.len == 0) {
2191 /* make sure that we send an USB packet */
2196 temp.tlbpc = mult - 1;
2198 } else if (xfer->flags_int.isochronous_xfr) {
2203 * Isochronous transfers don't have short
2204 * packet termination:
2209 /* isochronous transfers have a transfer limit */
2211 if (temp.len > xfer->max_frame_size)
2212 temp.len = xfer->max_frame_size;
2214 /* compute TD packet count */
2215 tdpc = (temp.len + xfer->max_packet_size - 1) /
2216 xfer->max_packet_size;
2218 temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2219 temp.tlbpc = (tdpc % mult);
2221 if (temp.tlbpc == 0)
2222 temp.tlbpc = mult - 1;
2227 /* regular data transfer */
2229 temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2232 xhci_setup_generic_chain_sub(&temp);
2234 if (xfer->flags_int.isochronous_xfr) {
2235 temp.offset += xfer->frlengths[x - 1];
2236 temp.isoc_frame += temp.isoc_delta;
2238 /* get next Page Cache pointer */
2239 temp.pc = xfer->frbuffers + x;
2243 /* check if we should append a status stage */
2245 if (xfer->flags_int.control_xfr &&
2246 !xfer->flags_int.control_act) {
2249 * Send a DATA1 message and invert the current
2250 * endpoint direction.
2252 if (xhcictlstep || temp.sc->sc_ctlstep) {
2254 * Some XHCI controllers will not delay the
2255 * status stage until the next SOF. Force this
2256 * behaviour to avoid failed control
2259 temp.step_td = (xfer->nframes != 0);
2263 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2267 temp.last_frame = 1;
2268 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2270 xhci_setup_generic_chain_sub(&temp);
2275 /* must have at least one frame! */
2277 xfer->td_transfer_last = td;
2279 DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2283 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2285 struct usb_page_search buf_res;
2286 struct xhci_dev_ctx_addr *pdctxa;
2288 usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2290 pdctxa = buf_res.buffer;
2292 DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2294 pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2296 usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2300 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2302 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2303 struct usb_page_search buf_inp;
2304 struct xhci_input_dev_ctx *pinp;
2309 index = udev->controller_slot_id;
2311 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2313 pinp = buf_inp.buffer;
2316 mask &= XHCI_INCTX_NON_CTRL_MASK;
2317 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2318 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2321 * Some hardware requires that we drop the endpoint
2322 * context before adding it again:
2324 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2325 mask & XHCI_INCTX_NON_CTRL_MASK);
2327 /* Add new endpoint context */
2328 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2330 /* find most significant set bit */
2331 for (x = 31; x != 1; x--) {
2332 if (mask & (1 << x))
2339 /* figure out the maximum number of contexts */
2340 if (x > sc->sc_hw.devs[index].context_num)
2341 sc->sc_hw.devs[index].context_num = x;
2343 x = sc->sc_hw.devs[index].context_num;
2345 /* update number of contexts */
2346 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2347 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2348 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2349 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2351 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2356 xhci_configure_endpoint(struct usb_device *udev,
2357 struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2358 uint16_t interval, uint8_t max_packet_count,
2359 uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2360 uint16_t max_frame_size, uint8_t ep_mode)
2362 struct usb_page_search buf_inp;
2363 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2364 struct xhci_input_dev_ctx *pinp;
2365 uint64_t ring_addr = pepext->physaddr;
2371 index = udev->controller_slot_id;
2373 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2375 pinp = buf_inp.buffer;
2377 epno = edesc->bEndpointAddress;
2378 type = edesc->bmAttributes & UE_XFERTYPE;
2380 if (type == UE_CONTROL)
2383 epno = XHCI_EPNO2EPID(epno);
2386 return (USB_ERR_NO_PIPE); /* invalid */
2388 if (max_packet_count == 0)
2389 return (USB_ERR_BAD_BUFSIZE);
2394 return (USB_ERR_BAD_BUFSIZE);
2396 /* store endpoint mode */
2397 pepext->trb_ep_mode = ep_mode;
2398 /* store bMaxPacketSize for control endpoints */
2399 pepext->trb_ep_maxp = edesc->wMaxPacketSize[0];
2400 usb_pc_cpu_flush(pepext->page_cache);
2402 if (ep_mode == USB_EP_MODE_STREAMS) {
2403 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2404 XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2405 XHCI_EPCTX_0_LSA_SET(1);
2407 ring_addr += sizeof(struct xhci_trb) *
2408 XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2410 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2411 XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2412 XHCI_EPCTX_0_LSA_SET(0);
2414 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2417 switch (udev->speed) {
2418 case USB_SPEED_FULL:
2431 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2433 case UE_ISOCHRONOUS:
2434 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2436 switch (udev->speed) {
2437 case USB_SPEED_SUPER:
2440 temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2441 max_packet_count /= mult;
2451 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2454 XHCI_EPCTX_1_HID_SET(0) |
2455 XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2456 XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2459 * Always enable the "three strikes and you are gone" feature
2460 * except for ISOCHRONOUS endpoints. This is suggested by
2461 * section 4.3.3 in the XHCI specification about device slot
2464 if (type != UE_ISOCHRONOUS)
2465 temp |= XHCI_EPCTX_1_CERR_SET(3);
2469 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2471 case UE_ISOCHRONOUS:
2472 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2475 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2478 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2482 /* check for IN direction */
2484 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2486 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2487 xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2489 switch (edesc->bmAttributes & UE_XFERTYPE) {
2491 case UE_ISOCHRONOUS:
2492 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2493 XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2497 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2500 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2504 xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2507 xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2509 usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2511 return (0); /* success */
2515 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2517 struct xhci_endpoint_ext *pepext;
2518 struct usb_endpoint_ss_comp_descriptor *ecomp;
2521 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2522 xfer->endpoint->edesc);
2524 ecomp = xfer->endpoint->ecomp;
2526 for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2529 /* halt any transfers */
2530 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2532 /* compute start of TRB ring for stream "x" */
2533 temp = pepext->physaddr +
2534 (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2535 XHCI_SCTX_0_SCT_SEC_TR_RING;
2537 /* make tree structure */
2538 pepext->trb[(XHCI_MAX_TRANSFERS *
2539 XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2541 /* reserved fields */
2542 pepext->trb[(XHCI_MAX_TRANSFERS *
2543 XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2544 pepext->trb[(XHCI_MAX_TRANSFERS *
2545 XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2547 usb_pc_cpu_flush(pepext->page_cache);
2549 return (xhci_configure_endpoint(xfer->xroot->udev,
2550 xfer->endpoint->edesc, pepext,
2551 xfer->interval, xfer->max_packet_count,
2552 (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2553 usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2554 xfer->max_frame_size, xfer->endpoint->ep_mode));
2558 xhci_configure_device(struct usb_device *udev)
2560 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2561 struct usb_page_search buf_inp;
2562 struct usb_page_cache *pcinp;
2563 struct xhci_input_dev_ctx *pinp;
2564 struct usb_device *hubdev;
2572 index = udev->controller_slot_id;
2574 DPRINTF("index=%u\n", index);
2576 pcinp = &sc->sc_hw.devs[index].input_pc;
2578 usbd_get_page(pcinp, 0, &buf_inp);
2580 pinp = buf_inp.buffer;
2585 /* figure out route string and root HUB port number */
2587 for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2589 if (hubdev->parent_hub == NULL)
2592 depth = hubdev->parent_hub->depth;
2595 * NOTE: HS/FS/LS devices and the SS root HUB can have
2596 * more than 15 ports
2599 rh_port = hubdev->port_no;
2608 route |= rh_port << (4 * (depth - 1));
2611 DPRINTF("Route=0x%08x\n", route);
2613 temp = XHCI_SCTX_0_ROUTE_SET(route) |
2614 XHCI_SCTX_0_CTX_NUM_SET(
2615 sc->sc_hw.devs[index].context_num + 1);
2617 switch (udev->speed) {
2619 temp |= XHCI_SCTX_0_SPEED_SET(2);
2620 if (udev->parent_hs_hub != NULL &&
2621 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2623 DPRINTF("Device inherits MTT\n");
2624 temp |= XHCI_SCTX_0_MTT_SET(1);
2627 case USB_SPEED_HIGH:
2628 temp |= XHCI_SCTX_0_SPEED_SET(3);
2629 if (sc->sc_hw.devs[index].nports != 0 &&
2630 udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2631 DPRINTF("HUB supports MTT\n");
2632 temp |= XHCI_SCTX_0_MTT_SET(1);
2635 case USB_SPEED_FULL:
2636 temp |= XHCI_SCTX_0_SPEED_SET(1);
2637 if (udev->parent_hs_hub != NULL &&
2638 udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2640 DPRINTF("Device inherits MTT\n");
2641 temp |= XHCI_SCTX_0_MTT_SET(1);
2645 temp |= XHCI_SCTX_0_SPEED_SET(4);
2649 is_hub = sc->sc_hw.devs[index].nports != 0 &&
2650 (udev->speed == USB_SPEED_SUPER ||
2651 udev->speed == USB_SPEED_HIGH);
2654 temp |= XHCI_SCTX_0_HUB_SET(1);
2656 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2658 temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2661 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2662 sc->sc_hw.devs[index].nports);
2665 switch (udev->speed) {
2666 case USB_SPEED_SUPER:
2667 switch (sc->sc_hw.devs[index].state) {
2668 case XHCI_ST_ADDRESSED:
2669 case XHCI_ST_CONFIGURED:
2670 /* enable power save */
2671 temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2674 /* disable power save */
2682 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2684 temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2687 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2688 sc->sc_hw.devs[index].tt);
2691 hubdev = udev->parent_hs_hub;
2693 /* check if we should activate the transaction translator */
2694 switch (udev->speed) {
2695 case USB_SPEED_FULL:
2697 if (hubdev != NULL) {
2698 temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2699 hubdev->controller_slot_id);
2700 temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2708 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2711 * These fields should be initialized to zero, according to
2712 * XHCI section 6.2.2 - slot context:
2714 temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2715 XHCI_SCTX_3_SLOT_STATE_SET(0);
2717 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2720 xhci_dump_device(sc, &pinp->ctx_slot);
2722 usb_pc_cpu_flush(pcinp);
2724 return (0); /* success */
2728 xhci_alloc_device_ext(struct usb_device *udev)
2730 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2731 struct usb_page_search buf_dev;
2732 struct usb_page_search buf_ep;
2733 struct xhci_trb *trb;
2734 struct usb_page_cache *pc;
2735 struct usb_page *pg;
2740 index = udev->controller_slot_id;
2742 pc = &sc->sc_hw.devs[index].device_pc;
2743 pg = &sc->sc_hw.devs[index].device_pg;
2745 /* need to initialize the page cache */
2746 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2748 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2749 (2 * sizeof(struct xhci_dev_ctx)) :
2750 sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2753 usbd_get_page(pc, 0, &buf_dev);
2755 pc = &sc->sc_hw.devs[index].input_pc;
2756 pg = &sc->sc_hw.devs[index].input_pg;
2758 /* need to initialize the page cache */
2759 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2761 if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2762 (2 * sizeof(struct xhci_input_dev_ctx)) :
2763 sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2767 /* initialize all endpoint LINK TRBs */
2769 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2771 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2772 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2774 /* need to initialize the page cache */
2775 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2777 if (usb_pc_alloc_mem(pc, pg,
2778 sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2782 /* lookup endpoint TRB ring */
2783 usbd_get_page(pc, 0, &buf_ep);
2785 /* get TRB pointer */
2786 trb = buf_ep.buffer;
2787 trb += XHCI_MAX_TRANSFERS - 1;
2789 /* get TRB start address */
2790 addr = buf_ep.physaddr;
2792 /* create LINK TRB */
2793 trb->qwTrb0 = htole64(addr);
2794 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2795 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2796 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2798 usb_pc_cpu_flush(pc);
2801 xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2806 xhci_free_device_ext(udev);
2808 return (USB_ERR_NOMEM);
2812 xhci_free_device_ext(struct usb_device *udev)
2814 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2818 index = udev->controller_slot_id;
2819 xhci_set_slot_pointer(sc, index, 0);
2821 usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2822 usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2823 for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2824 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2827 static struct xhci_endpoint_ext *
2828 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2830 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2831 struct xhci_endpoint_ext *pepext;
2832 struct usb_page_cache *pc;
2833 struct usb_page_search buf_ep;
2837 epno = edesc->bEndpointAddress;
2838 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2841 epno = XHCI_EPNO2EPID(epno);
2843 index = udev->controller_slot_id;
2845 pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2847 usbd_get_page(pc, 0, &buf_ep);
2849 pepext = &sc->sc_hw.devs[index].endp[epno];
2850 pepext->page_cache = pc;
2851 pepext->trb = buf_ep.buffer;
2852 pepext->physaddr = buf_ep.physaddr;
2858 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2860 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2864 epno = xfer->endpointno;
2865 if (xfer->flags_int.control_xfr)
2868 epno = XHCI_EPNO2EPID(epno);
2869 index = xfer->xroot->udev->controller_slot_id;
2871 if (xfer->xroot->udev->flags.self_suspended == 0) {
2872 XWRITE4(sc, door, XHCI_DOORBELL(index),
2873 epno | XHCI_DB_SID_SET(xfer->stream_id));
2878 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2880 struct xhci_endpoint_ext *pepext;
2882 if (xfer->flags_int.bandwidth_reclaimed) {
2883 xfer->flags_int.bandwidth_reclaimed = 0;
2885 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2886 xfer->endpoint->edesc);
2888 pepext->trb_used[xfer->stream_id]--;
2890 pepext->xfer[xfer->qh_pos] = NULL;
2892 if (error && pepext->trb_running != 0) {
2893 pepext->trb_halted = 1;
2894 pepext->trb_running = 0;
2900 xhci_transfer_insert(struct usb_xfer *xfer)
2902 struct xhci_td *td_first;
2903 struct xhci_td *td_last;
2904 struct xhci_trb *trb_link;
2905 struct xhci_endpoint_ext *pepext;
2914 id = xfer->stream_id;
2916 /* check if already inserted */
2917 if (xfer->flags_int.bandwidth_reclaimed) {
2918 DPRINTFN(8, "Already in schedule\n");
2922 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2923 xfer->endpoint->edesc);
2925 td_first = xfer->td_transfer_first;
2926 td_last = xfer->td_transfer_last;
2927 addr = pepext->physaddr;
2929 switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2932 /* single buffered */
2936 /* multi buffered */
2937 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2941 if (pepext->trb_used[id] >= trb_limit) {
2942 DPRINTFN(8, "Too many TDs queued.\n");
2943 return (USB_ERR_NOMEM);
2946 /* check if bMaxPacketSize changed */
2947 if (xfer->flags_int.control_xfr != 0 &&
2948 pepext->trb_ep_maxp != xfer->endpoint->edesc->wMaxPacketSize[0]) {
2950 DPRINTFN(8, "Reconfigure control endpoint\n");
2952 /* force driver to reconfigure endpoint */
2953 pepext->trb_halted = 1;
2954 pepext->trb_running = 0;
2957 /* check for stopped condition, after putting transfer on interrupt queue */
2958 if (pepext->trb_running == 0) {
2959 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2961 DPRINTFN(8, "Not running\n");
2963 /* start configuration */
2964 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2965 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2969 pepext->trb_used[id]++;
2971 /* get current TRB index */
2972 i = pepext->trb_index[id];
2974 /* get next TRB index */
2977 /* the last entry of the ring is a hardcoded link TRB */
2978 if (inext >= (XHCI_MAX_TRANSFERS - 1))
2981 /* store next TRB index, before stream ID offset is added */
2982 pepext->trb_index[id] = inext;
2984 /* offset for stream */
2985 i += id * XHCI_MAX_TRANSFERS;
2986 inext += id * XHCI_MAX_TRANSFERS;
2988 /* compute terminating return address */
2989 addr += (inext * sizeof(struct xhci_trb));
2991 /* compute link TRB pointer */
2992 trb_link = td_last->td_trb + td_last->ntrb;
2994 /* update next pointer of last link TRB */
2995 trb_link->qwTrb0 = htole64(addr);
2996 trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2997 trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2998 XHCI_TRB_3_CYCLE_BIT |
2999 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3002 xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
3004 usb_pc_cpu_flush(td_last->page_cache);
3006 /* write ahead chain end marker */
3008 pepext->trb[inext].qwTrb0 = 0;
3009 pepext->trb[inext].dwTrb2 = 0;
3010 pepext->trb[inext].dwTrb3 = 0;
3012 /* update next pointer of link TRB */
3014 pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
3015 pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
3018 xhci_dump_trb(&pepext->trb[i]);
3020 usb_pc_cpu_flush(pepext->page_cache);
3022 /* toggle cycle bit which activates the transfer chain */
3024 pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
3025 XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
3027 usb_pc_cpu_flush(pepext->page_cache);
3029 DPRINTF("qh_pos = %u\n", i);
3031 pepext->xfer[i] = xfer;
3035 xfer->flags_int.bandwidth_reclaimed = 1;
3037 xhci_endpoint_doorbell(xfer);
3043 xhci_root_intr(struct xhci_softc *sc)
3047 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3049 /* clear any old interrupt data */
3050 memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
3052 for (i = 1; i <= sc->sc_noport; i++) {
3053 /* pick out CHANGE bits from the status register */
3054 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3055 XHCI_PS_CSC | XHCI_PS_PEC |
3056 XHCI_PS_OCC | XHCI_PS_WRC |
3057 XHCI_PS_PRC | XHCI_PS_PLC |
3059 sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3060 DPRINTF("port %d changed\n", i);
3063 uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3064 sizeof(sc->sc_hub_idata));
3067 /*------------------------------------------------------------------------*
3068 * xhci_device_done - XHCI done handler
3070 * NOTE: This function can be called two times in a row on
3071 * the same USB transfer. From close and from interrupt.
3072 *------------------------------------------------------------------------*/
3074 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3076 DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3077 xfer, xfer->endpoint, error);
3079 /* remove transfer from HW queue */
3080 xhci_transfer_remove(xfer, error);
3082 /* dequeue transfer and start next transfer */
3083 usbd_transfer_done(xfer, error);
3086 /*------------------------------------------------------------------------*
3087 * XHCI data transfer support (generic type)
3088 *------------------------------------------------------------------------*/
3090 xhci_device_generic_open(struct usb_xfer *xfer)
3092 if (xfer->flags_int.isochronous_xfr) {
3093 switch (xfer->xroot->udev->speed) {
3094 case USB_SPEED_FULL:
3097 usb_hs_bandwidth_alloc(xfer);
3104 xhci_device_generic_close(struct usb_xfer *xfer)
3108 xhci_device_done(xfer, USB_ERR_CANCELLED);
3110 if (xfer->flags_int.isochronous_xfr) {
3111 switch (xfer->xroot->udev->speed) {
3112 case USB_SPEED_FULL:
3115 usb_hs_bandwidth_free(xfer);
3122 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3123 usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3125 struct usb_xfer *xfer;
3127 /* check if there is a current transfer */
3128 xfer = ep->endpoint_q[stream_id].curr;
3133 * Check if the current transfer is started and then pickup
3134 * the next one, if any. Else wait for next start event due to
3135 * block on failure feature.
3137 if (!xfer->flags_int.bandwidth_reclaimed)
3140 xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3143 * In case of enter we have to consider that the
3144 * transfer is queued by the USB core after the enter
3153 /* try to multi buffer */
3154 xhci_transfer_insert(xfer);
3158 xhci_device_generic_enter(struct usb_xfer *xfer)
3162 /* set up TD's and QH */
3163 xhci_setup_generic_chain(xfer);
3165 xhci_device_generic_multi_enter(xfer->endpoint,
3166 xfer->stream_id, xfer);
3170 xhci_device_generic_start(struct usb_xfer *xfer)
3174 /* try to insert xfer on HW queue */
3175 xhci_transfer_insert(xfer);
3177 /* try to multi buffer */
3178 xhci_device_generic_multi_enter(xfer->endpoint,
3179 xfer->stream_id, NULL);
3181 /* add transfer last on interrupt queue */
3182 usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3184 /* start timeout, if any */
3185 if (xfer->timeout != 0)
3186 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3189 struct usb_pipe_methods xhci_device_generic_methods =
3191 .open = xhci_device_generic_open,
3192 .close = xhci_device_generic_close,
3193 .enter = xhci_device_generic_enter,
3194 .start = xhci_device_generic_start,
3197 /*------------------------------------------------------------------------*
3198 * xhci root HUB support
3199 *------------------------------------------------------------------------*
3200 * Simulate a hardware HUB by handling all the necessary requests.
3201 *------------------------------------------------------------------------*/
3203 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3206 struct usb_device_descriptor xhci_devd =
3208 .bLength = sizeof(xhci_devd),
3209 .bDescriptorType = UDESC_DEVICE, /* type */
3210 HSETW(.bcdUSB, 0x0300), /* USB version */
3211 .bDeviceClass = UDCLASS_HUB, /* class */
3212 .bDeviceSubClass = UDSUBCLASS_HUB, /* subclass */
3213 .bDeviceProtocol = UDPROTO_SSHUB, /* protocol */
3214 .bMaxPacketSize = 9, /* max packet size */
3215 HSETW(.idVendor, 0x0000), /* vendor */
3216 HSETW(.idProduct, 0x0000), /* product */
3217 HSETW(.bcdDevice, 0x0100), /* device version */
3221 .bNumConfigurations = 1, /* # of configurations */
3225 struct xhci_bos_desc xhci_bosd = {
3227 .bLength = sizeof(xhci_bosd.bosd),
3228 .bDescriptorType = UDESC_BOS,
3229 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3230 .bNumDeviceCaps = 3,
3233 .bLength = sizeof(xhci_bosd.usb2extd),
3234 .bDescriptorType = 1,
3235 .bDevCapabilityType = 2,
3236 .bmAttributes[0] = 2,
3239 .bLength = sizeof(xhci_bosd.usbdcd),
3240 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3241 .bDevCapabilityType = 3,
3242 .bmAttributes = 0, /* XXX */
3243 HSETW(.wSpeedsSupported, 0x000C),
3244 .bFunctionalitySupport = 8,
3245 .bU1DevExitLat = 255, /* dummy - not used */
3246 .wU2DevExitLat = { 0x00, 0x08 },
3249 .bLength = sizeof(xhci_bosd.cidd),
3250 .bDescriptorType = 1,
3251 .bDevCapabilityType = 4,
3253 .bContainerID = 0, /* XXX */
3258 struct xhci_config_desc xhci_confd = {
3260 .bLength = sizeof(xhci_confd.confd),
3261 .bDescriptorType = UDESC_CONFIG,
3262 .wTotalLength[0] = sizeof(xhci_confd),
3264 .bConfigurationValue = 1,
3265 .iConfiguration = 0,
3266 .bmAttributes = UC_SELF_POWERED,
3267 .bMaxPower = 0 /* max power */
3270 .bLength = sizeof(xhci_confd.ifcd),
3271 .bDescriptorType = UDESC_INTERFACE,
3273 .bInterfaceClass = UICLASS_HUB,
3274 .bInterfaceSubClass = UISUBCLASS_HUB,
3275 .bInterfaceProtocol = 0,
3278 .bLength = sizeof(xhci_confd.endpd),
3279 .bDescriptorType = UDESC_ENDPOINT,
3280 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3281 .bmAttributes = UE_INTERRUPT,
3282 .wMaxPacketSize[0] = 2, /* max 15 ports */
3286 .bLength = sizeof(xhci_confd.endpcd),
3287 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3294 struct usb_hub_ss_descriptor xhci_hubd = {
3295 .bLength = sizeof(xhci_hubd),
3296 .bDescriptorType = UDESC_SS_HUB,
3300 xhci_roothub_exec(struct usb_device *udev,
3301 struct usb_device_request *req, const void **pptr, uint16_t *plength)
3303 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3304 const char *str_ptr;
3315 USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3318 ptr = (const void *)&sc->sc_hub_desc;
3322 value = UGETW(req->wValue);
3323 index = UGETW(req->wIndex);
3325 DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3326 "wValue=0x%04x wIndex=0x%04x\n",
3327 req->bmRequestType, req->bRequest,
3328 UGETW(req->wLength), value, index);
3330 #define C(x,y) ((x) | ((y) << 8))
3331 switch (C(req->bRequest, req->bmRequestType)) {
3332 case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3333 case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3334 case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3336 * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3337 * for the integrated root hub.
3340 case C(UR_GET_CONFIG, UT_READ_DEVICE):
3342 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3344 case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3345 switch (value >> 8) {
3347 if ((value & 0xff) != 0) {
3348 err = USB_ERR_IOERROR;
3351 len = sizeof(xhci_devd);
3352 ptr = (const void *)&xhci_devd;
3356 if ((value & 0xff) != 0) {
3357 err = USB_ERR_IOERROR;
3360 len = sizeof(xhci_bosd);
3361 ptr = (const void *)&xhci_bosd;
3365 if ((value & 0xff) != 0) {
3366 err = USB_ERR_IOERROR;
3369 len = sizeof(xhci_confd);
3370 ptr = (const void *)&xhci_confd;
3374 switch (value & 0xff) {
3375 case 0: /* Language table */
3379 case 1: /* Vendor */
3380 str_ptr = sc->sc_vendor;
3383 case 2: /* Product */
3384 str_ptr = "XHCI root HUB";
3392 len = usb_make_str_desc(
3393 sc->sc_hub_desc.temp,
3394 sizeof(sc->sc_hub_desc.temp),
3399 err = USB_ERR_IOERROR;
3403 case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3405 sc->sc_hub_desc.temp[0] = 0;
3407 case C(UR_GET_STATUS, UT_READ_DEVICE):
3409 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3411 case C(UR_GET_STATUS, UT_READ_INTERFACE):
3412 case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3414 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3416 case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3417 if (value >= XHCI_MAX_DEVICES) {
3418 err = USB_ERR_IOERROR;
3422 case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3423 if (value != 0 && value != 1) {
3424 err = USB_ERR_IOERROR;
3427 sc->sc_conf = value;
3429 case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3431 case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3432 case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3433 case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3434 err = USB_ERR_IOERROR;
3436 case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3438 case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3441 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3443 case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3444 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3447 (index > sc->sc_noport)) {
3448 err = USB_ERR_IOERROR;
3451 port = XHCI_PORTSC(index);
3453 v = XREAD4(sc, oper, port);
3454 i = XHCI_PS_PLS_GET(v);
3455 v &= ~XHCI_PS_CLEAR;
3458 case UHF_C_BH_PORT_RESET:
3459 XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3461 case UHF_C_PORT_CONFIG_ERROR:
3462 XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3464 case UHF_C_PORT_SUSPEND:
3465 case UHF_C_PORT_LINK_STATE:
3466 XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3468 case UHF_C_PORT_CONNECTION:
3469 XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3471 case UHF_C_PORT_ENABLE:
3472 XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3474 case UHF_C_PORT_OVER_CURRENT:
3475 XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3477 case UHF_C_PORT_RESET:
3478 XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3480 case UHF_PORT_ENABLE:
3481 XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3483 case UHF_PORT_POWER:
3484 XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3486 case UHF_PORT_INDICATOR:
3487 XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3489 case UHF_PORT_SUSPEND:
3493 XWRITE4(sc, oper, port, v |
3494 XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3497 /* wait 20ms for resume sequence to complete */
3498 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3501 XWRITE4(sc, oper, port, v |
3502 XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3505 err = USB_ERR_IOERROR;
3510 case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3511 if ((value & 0xff) != 0) {
3512 err = USB_ERR_IOERROR;
3516 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3518 sc->sc_hub_desc.hubd = xhci_hubd;
3520 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3522 if (XHCI_HCS0_PPC(v))
3523 i = UHD_PWR_INDIVIDUAL;
3527 if (XHCI_HCS0_PIND(v))
3530 i |= UHD_OC_INDIVIDUAL;
3532 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3534 /* see XHCI section 5.4.9: */
3535 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3537 for (j = 1; j <= sc->sc_noport; j++) {
3539 v = XREAD4(sc, oper, XHCI_PORTSC(j));
3540 if (v & XHCI_PS_DR) {
3541 sc->sc_hub_desc.hubd.
3542 DeviceRemovable[j / 8] |= 1U << (j % 8);
3545 len = sc->sc_hub_desc.hubd.bLength;
3548 case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3550 memset(sc->sc_hub_desc.temp, 0, 16);
3553 case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3554 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3557 (index > sc->sc_noport)) {
3558 err = USB_ERR_IOERROR;
3562 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3564 DPRINTFN(9, "port status=0x%08x\n", v);
3566 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3568 switch (XHCI_PS_SPEED_GET(v)) {
3570 i |= UPS_HIGH_SPEED;
3579 i |= UPS_OTHER_SPEED;
3583 if (v & XHCI_PS_CCS)
3584 i |= UPS_CURRENT_CONNECT_STATUS;
3585 if (v & XHCI_PS_PED)
3586 i |= UPS_PORT_ENABLED;
3587 if (v & XHCI_PS_OCA)
3588 i |= UPS_OVERCURRENT_INDICATOR;
3591 if (v & XHCI_PS_PP) {
3593 * The USB 3.0 RH is using the
3594 * USB 2.0's power bit
3596 i |= UPS_PORT_POWER;
3598 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3601 if (v & XHCI_PS_CSC)
3602 i |= UPS_C_CONNECT_STATUS;
3603 if (v & XHCI_PS_PEC)
3604 i |= UPS_C_PORT_ENABLED;
3605 if (v & XHCI_PS_OCC)
3606 i |= UPS_C_OVERCURRENT_INDICATOR;
3607 if (v & XHCI_PS_WRC)
3608 i |= UPS_C_BH_PORT_RESET;
3609 if (v & XHCI_PS_PRC)
3610 i |= UPS_C_PORT_RESET;
3611 if (v & XHCI_PS_PLC)
3612 i |= UPS_C_PORT_LINK_STATE;
3613 if (v & XHCI_PS_CEC)
3614 i |= UPS_C_PORT_CONFIG_ERROR;
3616 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3617 len = sizeof(sc->sc_hub_desc.ps);
3620 case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3621 err = USB_ERR_IOERROR;
3624 case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3627 case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3633 (index > sc->sc_noport)) {
3634 err = USB_ERR_IOERROR;
3638 port = XHCI_PORTSC(index);
3639 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3642 case UHF_PORT_U1_TIMEOUT:
3643 if (XHCI_PS_SPEED_GET(v) != 4) {
3644 err = USB_ERR_IOERROR;
3647 port = XHCI_PORTPMSC(index);
3648 v = XREAD4(sc, oper, port);
3649 v &= ~XHCI_PM3_U1TO_SET(0xFF);
3650 v |= XHCI_PM3_U1TO_SET(i);
3651 XWRITE4(sc, oper, port, v);
3653 case UHF_PORT_U2_TIMEOUT:
3654 if (XHCI_PS_SPEED_GET(v) != 4) {
3655 err = USB_ERR_IOERROR;
3658 port = XHCI_PORTPMSC(index);
3659 v = XREAD4(sc, oper, port);
3660 v &= ~XHCI_PM3_U2TO_SET(0xFF);
3661 v |= XHCI_PM3_U2TO_SET(i);
3662 XWRITE4(sc, oper, port, v);
3664 case UHF_BH_PORT_RESET:
3665 XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3667 case UHF_PORT_LINK_STATE:
3668 XWRITE4(sc, oper, port, v |
3669 XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3670 /* 4ms settle time */
3671 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3673 case UHF_PORT_ENABLE:
3674 DPRINTFN(3, "set port enable %d\n", index);
3676 case UHF_PORT_SUSPEND:
3677 DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3678 j = XHCI_PS_SPEED_GET(v);
3679 if ((j < 1) || (j > 3)) {
3680 /* non-supported speed */
3681 err = USB_ERR_IOERROR;
3684 XWRITE4(sc, oper, port, v |
3685 XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3687 case UHF_PORT_RESET:
3688 DPRINTFN(6, "reset port %d\n", index);
3689 XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3691 case UHF_PORT_POWER:
3692 DPRINTFN(3, "set port power %d\n", index);
3693 XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3696 DPRINTFN(3, "set port test %d\n", index);
3698 case UHF_PORT_INDICATOR:
3699 DPRINTFN(3, "set port indicator %d\n", index);
3701 v &= ~XHCI_PS_PIC_SET(3);
3702 v |= XHCI_PS_PIC_SET(1);
3704 XWRITE4(sc, oper, port, v);
3707 err = USB_ERR_IOERROR;
3712 case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3713 case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3714 case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3715 case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3718 err = USB_ERR_IOERROR;
3728 xhci_xfer_setup(struct usb_setup_params *parm)
3730 struct usb_page_search page_info;
3731 struct usb_page_cache *pc;
3732 struct xhci_softc *sc;
3733 struct usb_xfer *xfer;
3738 sc = XHCI_BUS2SC(parm->udev->bus);
3739 xfer = parm->curr_xfer;
3742 * The proof for the "ntd" formula is illustrated like this:
3744 * +------------------------------------+
3748 * | | xxx | x | frm 0 |
3750 * | | xxx | xx | frm 1 |
3753 * +------------------------------------+
3755 * "xxx" means a completely full USB transfer descriptor
3757 * "x" and "xx" means a short USB packet
3759 * For the remainder of an USB transfer modulo
3760 * "max_data_length" we need two USB transfer descriptors.
3761 * One to transfer the remaining data and one to finalise with
3762 * a zero length packet in case the "force_short_xfer" flag is
3763 * set. We only need two USB transfer descriptors in the case
3764 * where the transfer length of the first one is a factor of
3765 * "max_frame_size". The rest of the needed USB transfer
3766 * descriptors is given by the buffer size divided by the
3767 * maximum data payload.
3769 parm->hc_max_packet_size = 0x400;
3770 parm->hc_max_packet_count = 16 * 3;
3771 parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3773 xfer->flags_int.bdma_enable = 1;
3775 usbd_transfer_setup_sub(parm);
3777 if (xfer->flags_int.isochronous_xfr) {
3778 ntd = ((1 * xfer->nframes)
3779 + (xfer->max_data_length / xfer->max_hc_frame_size));
3780 } else if (xfer->flags_int.control_xfr) {
3781 ntd = ((2 * xfer->nframes) + 1 /* STATUS */
3782 + (xfer->max_data_length / xfer->max_hc_frame_size));
3784 ntd = ((2 * xfer->nframes)
3785 + (xfer->max_data_length / xfer->max_hc_frame_size));
3794 * Allocate queue heads and transfer descriptors
3798 if (usbd_transfer_setup_sub_malloc(
3799 parm, &pc, sizeof(struct xhci_td),
3800 XHCI_TD_ALIGN, ntd)) {
3801 parm->err = USB_ERR_NOMEM;
3805 for (n = 0; n != ntd; n++) {
3808 usbd_get_page(pc + n, 0, &page_info);
3810 td = page_info.buffer;
3813 td->td_self = page_info.physaddr;
3814 td->obj_next = last_obj;
3815 td->page_cache = pc + n;
3819 usb_pc_cpu_flush(pc + n);
3822 xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3824 if (!xfer->flags_int.curr_dma_set) {
3825 xfer->flags_int.curr_dma_set = 1;
3831 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3833 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3834 struct usb_page_search buf_inp;
3835 struct usb_device *udev;
3836 struct xhci_endpoint_ext *pepext;
3837 struct usb_endpoint_descriptor *edesc;
3838 struct usb_page_cache *pcinp;
3840 usb_stream_t stream_id;
3844 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3845 xfer->endpoint->edesc);
3847 udev = xfer->xroot->udev;
3848 index = udev->controller_slot_id;
3850 pcinp = &sc->sc_hw.devs[index].input_pc;
3852 usbd_get_page(pcinp, 0, &buf_inp);
3854 edesc = xfer->endpoint->edesc;
3856 epno = edesc->bEndpointAddress;
3857 stream_id = xfer->stream_id;
3859 if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3862 epno = XHCI_EPNO2EPID(epno);
3865 return (USB_ERR_NO_PIPE); /* invalid */
3869 /* configure endpoint */
3871 err = xhci_configure_endpoint_by_xfer(xfer);
3874 XHCI_CMD_UNLOCK(sc);
3879 * Get the endpoint into the stopped state according to the
3880 * endpoint context state diagram in the XHCI specification:
3883 err = xhci_cmd_stop_ep(sc, 0, epno, index);
3886 DPRINTF("Could not stop endpoint %u\n", epno);
3888 err = xhci_cmd_reset_ep(sc, 0, epno, index);
3891 DPRINTF("Could not reset endpoint %u\n", epno);
3893 err = xhci_cmd_set_tr_dequeue_ptr(sc,
3894 (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3895 XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3896 stream_id, epno, index);
3899 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3902 * Get the endpoint into the running state according to the
3903 * endpoint context state diagram in the XHCI specification:
3906 xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3909 err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3911 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3914 DPRINTF("Could not configure endpoint %u\n", epno);
3916 XHCI_CMD_UNLOCK(sc);
3922 xhci_xfer_unsetup(struct usb_xfer *xfer)
3928 xhci_start_dma_delay(struct usb_xfer *xfer)
3930 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3932 /* put transfer on interrupt queue (again) */
3933 usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3935 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3936 &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3940 xhci_configure_msg(struct usb_proc_msg *pm)
3942 struct xhci_softc *sc;
3943 struct xhci_endpoint_ext *pepext;
3944 struct usb_xfer *xfer;
3946 sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3949 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3951 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3952 xfer->endpoint->edesc);
3954 if ((pepext->trb_halted != 0) ||
3955 (pepext->trb_running == 0)) {
3959 /* clear halted and running */
3960 pepext->trb_halted = 0;
3961 pepext->trb_running = 0;
3963 /* nuke remaining buffered transfers */
3965 for (i = 0; i != (XHCI_MAX_TRANSFERS *
3966 XHCI_MAX_STREAMS); i++) {
3968 * NOTE: We need to use the timeout
3969 * error code here else existing
3970 * isochronous clients can get
3973 if (pepext->xfer[i] != NULL) {
3974 xhci_device_done(pepext->xfer[i],
3980 * NOTE: The USB transfer cannot vanish in
3984 USB_BUS_UNLOCK(&sc->sc_bus);
3986 xhci_configure_reset_endpoint(xfer);
3988 USB_BUS_LOCK(&sc->sc_bus);
3990 /* check if halted is still cleared */
3991 if (pepext->trb_halted == 0) {
3992 pepext->trb_running = 1;
3993 memset(pepext->trb_index, 0,
3994 sizeof(pepext->trb_index));
3999 if (xfer->flags_int.did_dma_delay) {
4001 /* remove transfer from interrupt queue (again) */
4002 usbd_transfer_dequeue(xfer);
4004 /* we are finally done */
4005 usb_dma_delay_done_cb(xfer);
4007 /* queue changed - restart */
4012 TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
4014 /* try to insert xfer on HW queue */
4015 xhci_transfer_insert(xfer);
4017 /* try to multi buffer */
4018 xhci_device_generic_multi_enter(xfer->endpoint,
4019 xfer->stream_id, NULL);
4024 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
4025 struct usb_endpoint *ep)
4027 struct xhci_endpoint_ext *pepext;
4029 DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
4030 ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
4032 if (udev->parent_hub == NULL) {
4033 /* root HUB has special endpoint handling */
4037 ep->methods = &xhci_device_generic_methods;
4039 pepext = xhci_get_endpoint_ext(udev, edesc);
4041 USB_BUS_LOCK(udev->bus);
4042 pepext->trb_halted = 1;
4043 pepext->trb_running = 0;
4044 USB_BUS_UNLOCK(udev->bus);
4048 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
4054 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4056 struct xhci_endpoint_ext *pepext;
4060 if (udev->flags.usb_mode != USB_MODE_HOST) {
4064 if (udev->parent_hub == NULL) {
4065 /* root HUB has special endpoint handling */
4069 pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4071 USB_BUS_LOCK(udev->bus);
4072 pepext->trb_halted = 1;
4073 pepext->trb_running = 0;
4074 USB_BUS_UNLOCK(udev->bus);
4078 xhci_device_init(struct usb_device *udev)
4080 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4084 /* no init for root HUB */
4085 if (udev->parent_hub == NULL)
4090 /* set invalid default */
4092 udev->controller_slot_id = sc->sc_noslot + 1;
4094 /* try to get a new slot ID from the XHCI */
4096 err = xhci_cmd_enable_slot(sc, &temp);
4099 XHCI_CMD_UNLOCK(sc);
4103 if (temp > sc->sc_noslot) {
4104 XHCI_CMD_UNLOCK(sc);
4105 return (USB_ERR_BAD_ADDRESS);
4108 if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4109 DPRINTF("slot %u already allocated.\n", temp);
4110 XHCI_CMD_UNLOCK(sc);
4111 return (USB_ERR_BAD_ADDRESS);
4114 /* store slot ID for later reference */
4116 udev->controller_slot_id = temp;
4118 /* reset data structure */
4120 memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4122 /* set mark slot allocated */
4124 sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4126 err = xhci_alloc_device_ext(udev);
4128 XHCI_CMD_UNLOCK(sc);
4130 /* get device into default state */
4133 err = xhci_set_address(udev, NULL, 0);
4139 xhci_device_uninit(struct usb_device *udev)
4141 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4144 /* no init for root HUB */
4145 if (udev->parent_hub == NULL)
4150 index = udev->controller_slot_id;
4152 if (index <= sc->sc_noslot) {
4153 xhci_cmd_disable_slot(sc, index);
4154 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4156 /* free device extension */
4157 xhci_free_device_ext(udev);
4160 XHCI_CMD_UNLOCK(sc);
4164 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4167 * Wait until the hardware has finished any possible use of
4168 * the transfer descriptor(s)
4170 *pus = 2048; /* microseconds */
4174 xhci_device_resume(struct usb_device *udev)
4176 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4183 /* check for root HUB */
4184 if (udev->parent_hub == NULL)
4187 index = udev->controller_slot_id;
4191 /* blindly resume all endpoints */
4193 USB_BUS_LOCK(udev->bus);
4195 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4196 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4197 XWRITE4(sc, door, XHCI_DOORBELL(index),
4198 n | XHCI_DB_SID_SET(p));
4202 USB_BUS_UNLOCK(udev->bus);
4204 XHCI_CMD_UNLOCK(sc);
4208 xhci_device_suspend(struct usb_device *udev)
4210 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4217 /* check for root HUB */
4218 if (udev->parent_hub == NULL)
4221 index = udev->controller_slot_id;
4225 /* blindly suspend all endpoints */
4227 for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4228 err = xhci_cmd_stop_ep(sc, 1, n, index);
4230 DPRINTF("Failed to suspend endpoint "
4231 "%u on slot %u (ignored).\n", n, index);
4235 XHCI_CMD_UNLOCK(sc);
4239 xhci_set_hw_power(struct usb_bus *bus)
4245 xhci_device_state_change(struct usb_device *udev)
4247 struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4248 struct usb_page_search buf_inp;
4252 /* check for root HUB */
4253 if (udev->parent_hub == NULL)
4256 index = udev->controller_slot_id;
4260 if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4261 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4262 &sc->sc_hw.devs[index].tt);
4264 sc->sc_hw.devs[index].nports = 0;
4269 switch (usb_get_device_state(udev)) {
4270 case USB_STATE_POWERED:
4271 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4274 /* set default state */
4275 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4277 /* reset number of contexts */
4278 sc->sc_hw.devs[index].context_num = 0;
4280 err = xhci_cmd_reset_dev(sc, index);
4283 DPRINTF("Device reset failed "
4284 "for slot %u.\n", index);
4288 case USB_STATE_ADDRESSED:
4289 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4292 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4294 /* set configure mask to slot only */
4295 xhci_configure_mask(udev, 1, 0);
4297 /* deconfigure all endpoints, except EP0 */
4298 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4301 DPRINTF("Failed to deconfigure "
4302 "slot %u.\n", index);
4306 case USB_STATE_CONFIGURED:
4307 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4310 /* set configured state */
4311 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4313 /* reset number of contexts */
4314 sc->sc_hw.devs[index].context_num = 0;
4316 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4318 xhci_configure_mask(udev, 3, 0);
4320 err = xhci_configure_device(udev);
4322 DPRINTF("Could not configure device "
4323 "at slot %u.\n", index);
4326 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4328 DPRINTF("Could not evaluate device "
4329 "context at slot %u.\n", index);
4336 XHCI_CMD_UNLOCK(sc);
4340 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4344 case USB_EP_MODE_DEFAULT:
4346 case USB_EP_MODE_STREAMS:
4347 if (xhcistreams == 0 ||
4348 (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4349 udev->speed != USB_SPEED_SUPER)
4350 return (USB_ERR_INVAL);
4353 return (USB_ERR_INVAL);
4357 struct usb_bus_methods xhci_bus_methods = {
4358 .endpoint_init = xhci_ep_init,
4359 .endpoint_uninit = xhci_ep_uninit,
4360 .xfer_setup = xhci_xfer_setup,
4361 .xfer_unsetup = xhci_xfer_unsetup,
4362 .get_dma_delay = xhci_get_dma_delay,
4363 .device_init = xhci_device_init,
4364 .device_uninit = xhci_device_uninit,
4365 .device_resume = xhci_device_resume,
4366 .device_suspend = xhci_device_suspend,
4367 .set_hw_power = xhci_set_hw_power,
4368 .roothub_exec = xhci_roothub_exec,
4369 .xfer_poll = xhci_do_poll,
4370 .start_dma_delay = xhci_start_dma_delay,
4371 .set_address = xhci_set_address,
4372 .clear_stall = xhci_ep_clear_stall,
4373 .device_state_change = xhci_device_state_change,
4374 .set_hw_power_sleep = xhci_set_hw_power_sleep,
4375 .set_endpoint_mode = xhci_set_endpoint_mode,