sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  29  *
  30  * The XHCI 1.0 spec can be found at
  31  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  32  * and the USB 3.0 spec at
  33  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  34  */
  35
  36 /*
  37  * A few words about the design implementation: This driver emulates
  38  * the concept about TDs which is found in EHCI specification. This
  39  * way we achieve that the USB controller drivers look similar to
  40  * eachother which makes it easier to understand the code.
  41  */
  42
  43 #ifdef USB_GLOBAL_INCLUDE_FILE
  44 #include USB_GLOBAL_INCLUDE_FILE
  45 #else
  46 #include <sys/stdint.h>
  47 #include <sys/stddef.h>
  48 #include <sys/param.h>
  49 #include <sys/queue.h>
  50 #include <sys/types.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/bus.h>
  54 #include <sys/module.h>
  55 #include <sys/lock.h>
  56 #include <sys/mutex.h>
  57 #include <sys/condvar.h>
  58 #include <sys/sysctl.h>
  59 #include <sys/sx.h>
  60 #include <sys/unistd.h>
  61 #include <sys/callout.h>
  62 #include <sys/malloc.h>
  63 #include <sys/priv.h>
  64
  65 #include <dev/usb/usb.h>
  66 #include <dev/usb/usbdi.h>
  67
  68 #define USB_DEBUG_VAR xhcidebug
  69
  70 #include <dev/usb/usb_core.h>
  71 #include <dev/usb/usb_debug.h>
  72 #include <dev/usb/usb_busdma.h>
  73 #include <dev/usb/usb_process.h>
  74 #include <dev/usb/usb_transfer.h>
  75 #include <dev/usb/usb_device.h>
  76 #include <dev/usb/usb_hub.h>
  77 #include <dev/usb/usb_util.h>
  78
  79 #include <dev/usb/usb_controller.h>
  80 #include <dev/usb/usb_bus.h>
  81 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  82
  83 #include <dev/usb/controller/xhci.h>
  84 #include <dev/usb/controller/xhcireg.h>
  85
  86 #define XHCI_BUS2SC(bus) \
  87    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  88     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  89
  90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91
  92 static int xhcistreams;
  93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
  94     &xhcistreams, 0, "Set to enable streams mode support");
  95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
  96
  97 #ifdef USB_DEBUG
  98 static int xhcidebug;
  99 static int xhciroute;
 100 static int xhcipolling;
 101
 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
 103     &xhcidebug, 0, "Debug level");
 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
 106     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
 109     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 111 #else
 112 #define xhciroute 0
 113 #endif
 114
 115 #define XHCI_INTR_ENDPT 1
 116
 117 struct xhci_std_temp {
 118         struct xhci_softc       *sc;
 119         struct usb_page_cache   *pc;
 120         struct xhci_td          *td;
 121         struct xhci_td          *td_next;
 122         uint32_t                len;
 123         uint32_t                offset;
 124         uint32_t                max_packet_size;
 125         uint32_t                average;
 126         uint16_t                isoc_delta;
 127         uint16_t                isoc_frame;
 128         uint8_t                 shortpkt;
 129         uint8_t                 multishort;
 130         uint8_t                 last_frame;
 131         uint8_t                 trb_type;
 132         uint8_t                 direction;
 133         uint8_t                 tbc;
 134         uint8_t                 tlbpc;
 135         uint8_t                 step_td;
 136         uint8_t                 do_isoc_sync;
 137 };
 138
 139 static void     xhci_do_poll(struct usb_bus *);
 140 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 141 static void     xhci_root_intr(struct xhci_softc *);
 142 static void     xhci_free_device_ext(struct usb_device *);
 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 144                     struct usb_endpoint_descriptor *);
 145 static usb_proc_callback_t xhci_configure_msg;
 146 static usb_error_t xhci_configure_device(struct usb_device *);
 147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 148                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 149                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 150                    uint8_t);
 151 static usb_error_t xhci_configure_mask(struct usb_device *,
 152                     uint32_t, uint8_t);
 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 154                     uint64_t, uint8_t);
 155 static void xhci_endpoint_doorbell(struct usb_xfer *);
 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 159 #ifdef USB_DEBUG
 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 161 #endif
 162
 163 extern struct usb_bus_methods xhci_bus_methods;
 164
 165 #ifdef USB_DEBUG
 166 static void
 167 xhci_dump_trb(struct xhci_trb *trb)
 168 {
 169         DPRINTFN(5, "trb = %p\n", trb);
 170         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 171         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 172         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 173 }
 174
 175 static void
 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 177 {
 178         DPRINTFN(5, "pep = %p\n", pep);
 179         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 180         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 181         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 182         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 183         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 184         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 185         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 186 }
 187
 188 static void
 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 190 {
 191         DPRINTFN(5, "psl = %p\n", psl);
 192         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 193         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 194         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 195         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 196 }
 197 #endif
 198
 199 uint8_t
 200 xhci_use_polling(void)
 201 {
 202 #ifdef USB_DEBUG
 203         return (xhcipolling != 0);
 204 #else
 205         return (0);
 206 #endif
 207 }
 208
 209 static void
 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 211 {
 212         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 213         uint8_t i;
 214
 215         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 216            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 217
 218         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 219            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 220
 221         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 222                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 223                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 224         }
 225 }
 226
 227 static void
 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 229 {
 230         if (sc->sc_ctx_is_64_byte) {
 231                 uint32_t offset;
 232                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 233                 /* all contexts are initially 32-bytes */
 234                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 235                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 236         }
 237         *ptr = htole32(val);
 238 }
 239
 240 static uint32_t
 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 242 {
 243         if (sc->sc_ctx_is_64_byte) {
 244                 uint32_t offset;
 245                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 246                 /* all contexts are initially 32-bytes */
 247                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 248                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 249         }
 250         return (le32toh(*ptr));
 251 }
 252
 253 static void
 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 255 {
 256         if (sc->sc_ctx_is_64_byte) {
 257                 uint32_t offset;
 258                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 259                 /* all contexts are initially 32-bytes */
 260                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 261                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 262         }
 263         *ptr = htole64(val);
 264 }
 265
 266 #ifdef USB_DEBUG
 267 static uint64_t
 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 269 {
 270         if (sc->sc_ctx_is_64_byte) {
 271                 uint32_t offset;
 272                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 273                 /* all contexts are initially 32-bytes */
 274                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 275                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 276         }
 277         return (le64toh(*ptr));
 278 }
 279 #endif
 280
 281 static int
 282 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 283 {
 284         struct usb_page_search buf_res;
 285         struct xhci_hw_root *phwr;
 286         uint64_t addr;
 287         uint32_t temp;
 288
 289         DPRINTF("\n");
 290
 291         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 292         if (temp & XHCI_CRCR_LO_CRR) {
 293                 DPRINTF("Command ring running\n");
 294                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 295
 296                 /*
 297                  * Try to abort the last command as per section
 298                  * 4.6.1.2 "Aborting a Command" of the XHCI
 299                  * specification:
 300                  */
 301
 302                 /* stop and cancel */
 303                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 304                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 305
 306                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 307                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 308
 309                 /* wait 250ms */
 310                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 311
 312                 /* check if command ring is still running */
 313                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 314                 if (temp & XHCI_CRCR_LO_CRR) {
 315                         DPRINTF("Comand ring still running\n");
 316                         return (USB_ERR_IOERROR);
 317                 }
 318         }
 319
 320         /* reset command ring */
 321         sc->sc_command_ccs = 1;
 322         sc->sc_command_idx = 0;
 323
 324         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 325
 326         /* setup command ring control base address */
 327         addr = buf_res.physaddr;
 328         phwr = buf_res.buffer;
 329         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 330
 331         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 332
 333         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 334         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 335
 336         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 337
 338         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 339         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 340
 341         return (0);
 342 }
 343
 344 usb_error_t
 345 xhci_start_controller(struct xhci_softc *sc)
 346 {
 347         struct usb_page_search buf_res;
 348         struct xhci_hw_root *phwr;
 349         struct xhci_dev_ctx_addr *pdctxa;
 350         uint64_t addr;
 351         uint32_t temp;
 352         uint16_t i;
 353
 354         DPRINTF("\n");
 355
 356         sc->sc_capa_off = 0;
 357         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 358         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 359         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 360
 361         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 362         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 363         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 364
 365         sc->sc_event_ccs = 1;
 366         sc->sc_event_idx = 0;
 367         sc->sc_command_ccs = 1;
 368         sc->sc_command_idx = 0;
 369
 370         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 371
 372         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 373
 374         DPRINTF("HCS0 = 0x%08x\n", temp);
 375
 376         if (XHCI_HCS0_CSZ(temp)) {
 377                 sc->sc_ctx_is_64_byte = 1;
 378                 device_printf(sc->sc_bus.parent, "64 byte context size.\n");
 379         } else {
 380                 sc->sc_ctx_is_64_byte = 0;
 381                 device_printf(sc->sc_bus.parent, "32 byte context size.\n");
 382         }
 383
 384         /* Reset controller */
 385         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 386
 387         for (i = 0; i != 100; i++) {
 388                 usb_pause_mtx(NULL, hz / 100);
 389                 temp = XREAD4(sc, oper, XHCI_USBCMD) &
 390                     (XHCI_CMD_HCRST | XHCI_STS_CNR);
 391                 if (!temp)
 392                         break;
 393         }
 394
 395         if (temp) {
 396                 device_printf(sc->sc_bus.parent, "Controller "
 397                     "reset timeout.\n");
 398                 return (USB_ERR_IOERROR);
 399         }
 400
 401         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 402                 device_printf(sc->sc_bus.parent, "Controller does "
 403                     "not support 4K page size.\n");
 404                 return (USB_ERR_IOERROR);
 405         }
 406
 407         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 408
 409         i = XHCI_HCS1_N_PORTS(temp);
 410
 411         if (i == 0) {
 412                 device_printf(sc->sc_bus.parent, "Invalid number "
 413                     "of ports: %u\n", i);
 414                 return (USB_ERR_IOERROR);
 415         }
 416
 417         sc->sc_noport = i;
 418         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 419
 420         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 421                 sc->sc_noslot = XHCI_MAX_DEVICES;
 422
 423         /* setup number of device slots */
 424
 425         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 426             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 427
 428         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 429
 430         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 431
 432         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 433
 434         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 435
 436         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 437                 device_printf(sc->sc_bus.parent, "XHCI request "
 438                     "too many scratchpads\n");
 439                 return (USB_ERR_NOMEM);
 440         }
 441
 442         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 443
 444         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 445
 446         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 447             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 448
 449         temp = XREAD4(sc, oper, XHCI_USBSTS);
 450
 451         /* clear interrupts */
 452         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 453         /* disable all device notifications */
 454         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 455
 456         /* setup device context base address */
 457         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 458         pdctxa = buf_res.buffer;
 459         memset(pdctxa, 0, sizeof(*pdctxa));
 460
 461         addr = buf_res.physaddr;
 462         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 463
 464         /* slot 0 points to the table of scratchpad pointers */
 465         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 466
 467         for (i = 0; i != sc->sc_noscratch; i++) {
 468                 struct usb_page_search buf_scp;
 469                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 470                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 471         }
 472
 473         addr = buf_res.physaddr;
 474
 475         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 476         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 477         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 478         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 479
 480         /* Setup event table size */
 481
 482         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 483
 484         DPRINTF("HCS2=0x%08x\n", temp);
 485
 486         temp = XHCI_HCS2_ERST_MAX(temp);
 487         temp = 1U << temp;
 488         if (temp > XHCI_MAX_RSEG)
 489                 temp = XHCI_MAX_RSEG;
 490
 491         sc->sc_erst_max = temp;
 492
 493         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 494             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 495
 496         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 497
 498         /* Setup interrupt rate */
 499         XWRITE4(sc, runt, XHCI_IMOD(0), XHCI_IMOD_DEFAULT);
 500
 501         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 502
 503         phwr = buf_res.buffer;
 504         addr = buf_res.physaddr;
 505         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 506
 507         /* reset hardware root structure */
 508         memset(phwr, 0, sizeof(*phwr));
 509
 510         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 511         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 512
 513         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 514
 515         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 516         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 517
 518         addr = (uint64_t)buf_res.physaddr;
 519
 520         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 521
 522         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 523         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 524
 525         /* Setup interrupter registers */
 526
 527         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 528         temp |= XHCI_IMAN_INTR_ENA;
 529         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 530
 531         /* setup command ring control base address */
 532         addr = buf_res.physaddr;
 533         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 534
 535         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 536
 537         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 538         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 539
 540         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 541
 542         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 543
 544         /* Go! */
 545         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 546             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 547
 548         for (i = 0; i != 100; i++) {
 549                 usb_pause_mtx(NULL, hz / 100);
 550                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 551                 if (!temp)
 552                         break;
 553         }
 554         if (temp) {
 555                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 556                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 557                 return (USB_ERR_IOERROR);
 558         }
 559
 560         /* catch any lost interrupts */
 561         xhci_do_poll(&sc->sc_bus);
 562
 563         if (sc->sc_port_route != NULL) {
 564                 /* Route all ports to the XHCI by default */
 565                 sc->sc_port_route(sc->sc_bus.parent,
 566                     ~xhciroute, xhciroute);
 567         }
 568         return (0);
 569 }
 570
 571 usb_error_t
 572 xhci_halt_controller(struct xhci_softc *sc)
 573 {
 574         uint32_t temp;
 575         uint16_t i;
 576
 577         DPRINTF("\n");
 578
 579         sc->sc_capa_off = 0;
 580         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 581         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 582         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 583
 584         /* Halt controller */
 585         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 586
 587         for (i = 0; i != 100; i++) {
 588                 usb_pause_mtx(NULL, hz / 100);
 589                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 590                 if (temp)
 591                         break;
 592         }
 593
 594         if (!temp) {
 595                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 596                 return (USB_ERR_IOERROR);
 597         }
 598         return (0);
 599 }
 600
 601 usb_error_t
 602 xhci_init(struct xhci_softc *sc, device_t self)
 603 {
 604         /* initialise some bus fields */
 605         sc->sc_bus.parent = self;
 606
 607         /* set the bus revision */
 608         sc->sc_bus.usbrev = USB_REV_3_0;
 609
 610         /* set up the bus struct */
 611         sc->sc_bus.methods = &xhci_bus_methods;
 612
 613         /* setup devices array */
 614         sc->sc_bus.devices = sc->sc_devices;
 615         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 616
 617         /* setup command queue mutex and condition varible */
 618         cv_init(&sc->sc_cmd_cv, "CMDQ");
 619         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 620
 621         /* get all DMA memory */
 622         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 623             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 624                 return (ENOMEM);
 625         }
 626
 627         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 628         sc->sc_config_msg[0].bus = &sc->sc_bus;
 629         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 630         sc->sc_config_msg[1].bus = &sc->sc_bus;
 631
 632         return (0);
 633 }
 634
 635 void
 636 xhci_uninit(struct xhci_softc *sc)
 637 {
 638         /*
 639          * NOTE: At this point the control transfer process is gone
 640          * and "xhci_configure_msg" is no longer called. Consequently
 641          * waiting for the configuration messages to complete is not
 642          * needed.
 643          */
 644         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 645
 646         cv_destroy(&sc->sc_cmd_cv);
 647         sx_destroy(&sc->sc_cmd_sx);
 648 }
 649
 650 static void
 651 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 652 {
 653         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 654
 655         switch (state) {
 656         case USB_HW_POWER_SUSPEND:
 657                 DPRINTF("Stopping the XHCI\n");
 658                 xhci_halt_controller(sc);
 659                 break;
 660         case USB_HW_POWER_SHUTDOWN:
 661                 DPRINTF("Stopping the XHCI\n");
 662                 xhci_halt_controller(sc);
 663                 break;
 664         case USB_HW_POWER_RESUME:
 665                 DPRINTF("Starting the XHCI\n");
 666                 xhci_start_controller(sc);
 667                 break;
 668         default:
 669                 break;
 670         }
 671 }
 672
 673 static usb_error_t
 674 xhci_generic_done_sub(struct usb_xfer *xfer)
 675 {
 676         struct xhci_td *td;
 677         struct xhci_td *td_alt_next;
 678         uint32_t len;
 679         uint8_t status;
 680
 681         td = xfer->td_transfer_cache;
 682         td_alt_next = td->alt_next;
 683
 684         if (xfer->aframes != xfer->nframes)
 685                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 686
 687         while (1) {
 688
 689                 usb_pc_cpu_invalidate(td->page_cache);
 690
 691                 status = td->status;
 692                 len = td->remainder;
 693
 694                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 695                     xfer, (unsigned int)xfer->aframes,
 696                     (unsigned int)xfer->nframes,
 697                     (unsigned int)len, (unsigned int)td->len,
 698                     (unsigned int)status);
 699
 700                 /*
 701                  * Verify the status length and
 702                  * add the length to "frlengths[]":
 703                  */
 704                 if (len > td->len) {
 705                         /* should not happen */
 706                         DPRINTF("Invalid status length, "
 707                             "0x%04x/0x%04x bytes\n", len, td->len);
 708                         status = XHCI_TRB_ERROR_LENGTH;
 709                 } else if (xfer->aframes != xfer->nframes) {
 710                         xfer->frlengths[xfer->aframes] += td->len - len;
 711                 }
 712                 /* Check for last transfer */
 713                 if (((void *)td) == xfer->td_transfer_last) {
 714                         td = NULL;
 715                         break;
 716                 }
 717                 /* Check for transfer error */
 718                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 719                     status != XHCI_TRB_ERROR_SUCCESS) {
 720                         /* the transfer is finished */
 721                         td = NULL;
 722                         break;
 723                 }
 724                 /* Check for short transfer */
 725                 if (len > 0) {
 726                         if (xfer->flags_int.short_frames_ok ||
 727                             xfer->flags_int.isochronous_xfr ||
 728                             xfer->flags_int.control_xfr) {
 729                                 /* follow alt next */
 730                                 td = td->alt_next;
 731                         } else {
 732                                 /* the transfer is finished */
 733                                 td = NULL;
 734                         }
 735                         break;
 736                 }
 737                 td = td->obj_next;
 738
 739                 if (td->alt_next != td_alt_next) {
 740                         /* this USB frame is complete */
 741                         break;
 742                 }
 743         }
 744
 745         /* update transfer cache */
 746
 747         xfer->td_transfer_cache = td;
 748
 749         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 750             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 751             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 752             USB_ERR_NORMAL_COMPLETION);
 753 }
 754
 755 static void
 756 xhci_generic_done(struct usb_xfer *xfer)
 757 {
 758         usb_error_t err = 0;
 759
 760         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 761             xfer, xfer->endpoint);
 762
 763         /* reset scanner */
 764
 765         xfer->td_transfer_cache = xfer->td_transfer_first;
 766
 767         if (xfer->flags_int.control_xfr) {
 768
 769                 if (xfer->flags_int.control_hdr)
 770                         err = xhci_generic_done_sub(xfer);
 771
 772                 xfer->aframes = 1;
 773
 774                 if (xfer->td_transfer_cache == NULL)
 775                         goto done;
 776         }
 777
 778         while (xfer->aframes != xfer->nframes) {
 779
 780                 err = xhci_generic_done_sub(xfer);
 781                 xfer->aframes++;
 782
 783                 if (xfer->td_transfer_cache == NULL)
 784                         goto done;
 785         }
 786
 787         if (xfer->flags_int.control_xfr &&
 788             !xfer->flags_int.control_act)
 789                 err = xhci_generic_done_sub(xfer);
 790 done:
 791         /* transfer is complete */
 792         xhci_device_done(xfer, err);
 793 }
 794
 795 static void
 796 xhci_activate_transfer(struct usb_xfer *xfer)
 797 {
 798         struct xhci_td *td;
 799
 800         td = xfer->td_transfer_cache;
 801
 802         usb_pc_cpu_invalidate(td->page_cache);
 803
 804         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 805
 806                 /* activate the transfer */
 807
 808                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 809                 usb_pc_cpu_flush(td->page_cache);
 810
 811                 xhci_endpoint_doorbell(xfer);
 812         }
 813 }
 814
 815 static void
 816 xhci_skip_transfer(struct usb_xfer *xfer)
 817 {
 818         struct xhci_td *td;
 819         struct xhci_td *td_last;
 820
 821         td = xfer->td_transfer_cache;
 822         td_last = xfer->td_transfer_last;
 823
 824         td = td->alt_next;
 825
 826         usb_pc_cpu_invalidate(td->page_cache);
 827
 828         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 829
 830                 usb_pc_cpu_invalidate(td_last->page_cache);
 831
 832                 /* copy LINK TRB to current waiting location */
 833
 834                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 835                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 836                 usb_pc_cpu_flush(td->page_cache);
 837
 838                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 839                 usb_pc_cpu_flush(td->page_cache);
 840
 841                 xhci_endpoint_doorbell(xfer);
 842         }
 843 }
 844
 845 /*------------------------------------------------------------------------*
 846  *      xhci_check_transfer
 847  *------------------------------------------------------------------------*/
 848 static void
 849 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 850 {
 851         struct xhci_endpoint_ext *pepext;
 852         int64_t offset;
 853         uint64_t td_event;
 854         uint32_t temp;
 855         uint32_t remainder;
 856         uint16_t stream_id;
 857         uint16_t i;
 858         uint8_t status;
 859         uint8_t halted;
 860         uint8_t epno;
 861         uint8_t index;
 862
 863         /* decode TRB */
 864         td_event = le64toh(trb->qwTrb0);
 865         temp = le32toh(trb->dwTrb2);
 866
 867         remainder = XHCI_TRB_2_REM_GET(temp);
 868         status = XHCI_TRB_2_ERROR_GET(temp);
 869         stream_id = XHCI_TRB_2_STREAM_GET(temp);
 870
 871         temp = le32toh(trb->dwTrb3);
 872         epno = XHCI_TRB_3_EP_GET(temp);
 873         index = XHCI_TRB_3_SLOT_GET(temp);
 874
 875         /* check if error means halted */
 876         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 877             status != XHCI_TRB_ERROR_SUCCESS);
 878
 879         DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
 880             index, epno, stream_id, remainder, status);
 881
 882         if (index > sc->sc_noslot) {
 883                 DPRINTF("Invalid slot.\n");
 884                 return;
 885         }
 886
 887         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 888                 DPRINTF("Invalid endpoint.\n");
 889                 return;
 890         }
 891
 892         pepext = &sc->sc_hw.devs[index].endp[epno];
 893
 894         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
 895                 stream_id = 0;
 896                 DPRINTF("stream_id=0\n");
 897         } else if (stream_id >= XHCI_MAX_STREAMS) {
 898                 DPRINTF("Invalid stream ID.\n");
 899                 return;
 900         }
 901
 902         /* try to find the USB transfer that generated the event */
 903         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 904                 struct usb_xfer *xfer;
 905                 struct xhci_td *td;
 906
 907                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 908                 if (xfer == NULL)
 909                         continue;
 910
 911                 td = xfer->td_transfer_cache;
 912
 913                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 914                         (long long)td_event,
 915                         (long long)td->td_self,
 916                         (long long)td->td_self + sizeof(td->td_trb));
 917
 918                 /*
 919                  * NOTE: Some XHCI implementations might not trigger
 920                  * an event on the last LINK TRB so we need to
 921                  * consider both the last and second last event
 922                  * address as conditions for a successful transfer.
 923                  *
 924                  * NOTE: We assume that the XHCI will only trigger one
 925                  * event per chain of TRBs.
 926                  */
 927
 928                 offset = td_event - td->td_self;
 929
 930                 if (offset >= 0 &&
 931                     offset < (int64_t)sizeof(td->td_trb)) {
 932
 933                         usb_pc_cpu_invalidate(td->page_cache);
 934
 935                         /* compute rest of remainder, if any */
 936                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 937                                 temp = le32toh(td->td_trb[i].dwTrb2);
 938                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 939                         }
 940
 941                         DPRINTFN(5, "New remainder: %u\n", remainder);
 942
 943                         /* clear isochronous transfer errors */
 944                         if (xfer->flags_int.isochronous_xfr) {
 945                                 if (halted) {
 946                                         halted = 0;
 947                                         status = XHCI_TRB_ERROR_SUCCESS;
 948                                         remainder = td->len;
 949                                 }
 950                         }
 951
 952                         /* "td->remainder" is verified later */
 953                         td->remainder = remainder;
 954                         td->status = status;
 955
 956                         usb_pc_cpu_flush(td->page_cache);
 957
 958                         /*
 959                          * 1) Last transfer descriptor makes the
 960                          * transfer done
 961                          */
 962                         if (((void *)td) == xfer->td_transfer_last) {
 963                                 DPRINTF("TD is last\n");
 964                                 xhci_generic_done(xfer);
 965                                 break;
 966                         }
 967
 968                         /*
 969                          * 2) Any kind of error makes the transfer
 970                          * done
 971                          */
 972                         if (halted) {
 973                                 DPRINTF("TD has I/O error\n");
 974                                 xhci_generic_done(xfer);
 975                                 break;
 976                         }
 977
 978                         /*
 979                          * 3) If there is no alternate next transfer,
 980                          * a short packet also makes the transfer done
 981                          */
 982                         if (td->remainder > 0) {
 983                                 if (td->alt_next == NULL) {
 984                                         DPRINTF(
 985                                             "short TD has no alternate next\n");
 986                                         xhci_generic_done(xfer);
 987                                         break;
 988                                 }
 989                                 DPRINTF("TD has short pkt\n");
 990                                 if (xfer->flags_int.short_frames_ok ||
 991                                     xfer->flags_int.isochronous_xfr ||
 992                                     xfer->flags_int.control_xfr) {
 993                                         /* follow the alt next */
 994                                         xfer->td_transfer_cache = td->alt_next;
 995                                         xhci_activate_transfer(xfer);
 996                                         break;
 997                                 }
 998                                 xhci_skip_transfer(xfer);
 999                                 xhci_generic_done(xfer);
1000                                 break;
1001                         }
1002
1003                         /*
1004                          * 4) Transfer complete - go to next TD
1005                          */
1006                         DPRINTF("Following next TD\n");
1007                         xfer->td_transfer_cache = td->obj_next;
1008                         xhci_activate_transfer(xfer);
1009                         break;          /* there should only be one match */
1010                 }
1011         }
1012 }
1013
1014 static int
1015 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1016 {
1017         if (sc->sc_cmd_addr == trb->qwTrb0) {
1018                 DPRINTF("Received command event\n");
1019                 sc->sc_cmd_result[0] = trb->dwTrb2;
1020                 sc->sc_cmd_result[1] = trb->dwTrb3;
1021                 cv_signal(&sc->sc_cmd_cv);
1022                 return (1);     /* command match */
1023         }
1024         return (0);
1025 }
1026
1027 static int
1028 xhci_interrupt_poll(struct xhci_softc *sc)
1029 {
1030         struct usb_page_search buf_res;
1031         struct xhci_hw_root *phwr;
1032         uint64_t addr;
1033         uint32_t temp;
1034         int retval = 0;
1035         uint16_t i;
1036         uint8_t event;
1037         uint8_t j;
1038         uint8_t k;
1039         uint8_t t;
1040
1041         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1042
1043         phwr = buf_res.buffer;
1044
1045         /* Receive any events */
1046
1047         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1048
1049         i = sc->sc_event_idx;
1050         j = sc->sc_event_ccs;
1051         t = 2;
1052
1053         while (1) {
1054
1055                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1056
1057                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1058
1059                 if (j != k)
1060                         break;
1061
1062                 event = XHCI_TRB_3_TYPE_GET(temp);
1063
1064                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1065                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1066                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1067                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1068
1069                 switch (event) {
1070                 case XHCI_TRB_EVENT_TRANSFER:
1071                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1072                         break;
1073                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1074                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1075                         break;
1076                 default:
1077                         DPRINTF("Unhandled event = %u\n", event);
1078                         break;
1079                 }
1080
1081                 i++;
1082
1083                 if (i == XHCI_MAX_EVENTS) {
1084                         i = 0;
1085                         j ^= 1;
1086
1087                         /* check for timeout */
1088                         if (!--t)
1089                                 break;
1090                 }
1091         }
1092
1093         sc->sc_event_idx = i;
1094         sc->sc_event_ccs = j;
1095
1096         /*
1097          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1098          * latched. That means to activate the register we need to
1099          * write both the low and high double word of the 64-bit
1100          * register.
1101          */
1102
1103         addr = (uint32_t)buf_res.physaddr;
1104         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1105
1106         /* try to clear busy bit */
1107         addr |= XHCI_ERDP_LO_BUSY;
1108
1109         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1110         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1111
1112         return (retval);
1113 }
1114
1115 static usb_error_t
1116 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1117     uint16_t timeout_ms)
1118 {
1119         struct usb_page_search buf_res;
1120         struct xhci_hw_root *phwr;
1121         uint64_t addr;
1122         uint32_t temp;
1123         uint8_t i;
1124         uint8_t j;
1125         uint8_t timeout = 0;
1126         int err;
1127
1128         XHCI_CMD_ASSERT_LOCKED(sc);
1129
1130         /* get hardware root structure */
1131
1132         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1133
1134         phwr = buf_res.buffer;
1135
1136         /* Queue command */
1137
1138         USB_BUS_LOCK(&sc->sc_bus);
1139 retry:
1140         i = sc->sc_command_idx;
1141         j = sc->sc_command_ccs;
1142
1143         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1144             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1145             (long long)le64toh(trb->qwTrb0),
1146             (long)le32toh(trb->dwTrb2),
1147             (long)le32toh(trb->dwTrb3));
1148
1149         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1150         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1151
1152         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1153
1154         temp = trb->dwTrb3;
1155
1156         if (j)
1157                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1158         else
1159                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1160
1161         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1162
1163         phwr->hwr_commands[i].dwTrb3 = temp;
1164
1165         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1166
1167         addr = buf_res.physaddr;
1168         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1169
1170         sc->sc_cmd_addr = htole64(addr);
1171
1172         i++;
1173
1174         if (i == (XHCI_MAX_COMMANDS - 1)) {
1175
1176                 if (j) {
1177                         temp = htole32(XHCI_TRB_3_TC_BIT |
1178                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1179                             XHCI_TRB_3_CYCLE_BIT);
1180                 } else {
1181                         temp = htole32(XHCI_TRB_3_TC_BIT |
1182                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1183                 }
1184
1185                 phwr->hwr_commands[i].dwTrb3 = temp;
1186
1187                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1188
1189                 i = 0;
1190                 j ^= 1;
1191         }
1192
1193         sc->sc_command_idx = i;
1194         sc->sc_command_ccs = j;
1195
1196         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1197
1198         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1199             USB_MS_TO_TICKS(timeout_ms));
1200
1201         /*
1202          * In some error cases event interrupts are not generated.
1203          * Poll one time to see if the command has completed.
1204          */
1205         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1206                 DPRINTF("Command was completed when polling\n");
1207                 err = 0;
1208         }
1209         if (err != 0) {
1210                 DPRINTF("Command timeout!\n");
1211                 /*
1212                  * After some weeks of continuous operation, it has
1213                  * been observed that the ASMedia Technology, ASM1042
1214                  * SuperSpeed USB Host Controller can suddenly stop
1215                  * accepting commands via the command queue. Try to
1216                  * first reset the command queue. If that fails do a
1217                  * host controller reset.
1218                  */
1219                 if (timeout == 0 &&
1220                     xhci_reset_command_queue_locked(sc) == 0) {
1221                         timeout = 1;
1222                         goto retry;
1223                 } else {
1224                         DPRINTF("Controller reset!\n");
1225                         usb_bus_reset_async_locked(&sc->sc_bus);
1226                 }
1227                 err = USB_ERR_TIMEOUT;
1228                 trb->dwTrb2 = 0;
1229                 trb->dwTrb3 = 0;
1230         } else {
1231                 temp = le32toh(sc->sc_cmd_result[0]);
1232                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1233                         err = USB_ERR_IOERROR;
1234
1235                 trb->dwTrb2 = sc->sc_cmd_result[0];
1236                 trb->dwTrb3 = sc->sc_cmd_result[1];
1237         }
1238
1239         USB_BUS_UNLOCK(&sc->sc_bus);
1240
1241         return (err);
1242 }
1243
1244 #if 0
1245 static usb_error_t
1246 xhci_cmd_nop(struct xhci_softc *sc)
1247 {
1248         struct xhci_trb trb;
1249         uint32_t temp;
1250
1251         DPRINTF("\n");
1252
1253         trb.qwTrb0 = 0;
1254         trb.dwTrb2 = 0;
1255         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1256
1257         trb.dwTrb3 = htole32(temp);
1258
1259         return (xhci_do_command(sc, &trb, 100 /* ms */));
1260 }
1261 #endif
1262
1263 static usb_error_t
1264 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1265 {
1266         struct xhci_trb trb;
1267         uint32_t temp;
1268         usb_error_t err;
1269
1270         DPRINTF("\n");
1271
1272         trb.qwTrb0 = 0;
1273         trb.dwTrb2 = 0;
1274         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1275
1276         err = xhci_do_command(sc, &trb, 100 /* ms */);
1277         if (err)
1278                 goto done;
1279
1280         temp = le32toh(trb.dwTrb3);
1281
1282         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1283
1284 done:
1285         return (err);
1286 }
1287
1288 static usb_error_t
1289 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1290 {
1291         struct xhci_trb trb;
1292         uint32_t temp;
1293
1294         DPRINTF("\n");
1295
1296         trb.qwTrb0 = 0;
1297         trb.dwTrb2 = 0;
1298         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1299             XHCI_TRB_3_SLOT_SET(slot_id);
1300
1301         trb.dwTrb3 = htole32(temp);
1302
1303         return (xhci_do_command(sc, &trb, 100 /* ms */));
1304 }
1305
1306 static usb_error_t
1307 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1308     uint8_t bsr, uint8_t slot_id)
1309 {
1310         struct xhci_trb trb;
1311         uint32_t temp;
1312
1313         DPRINTF("\n");
1314
1315         trb.qwTrb0 = htole64(input_ctx);
1316         trb.dwTrb2 = 0;
1317         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1318             XHCI_TRB_3_SLOT_SET(slot_id);
1319
1320         if (bsr)
1321                 temp |= XHCI_TRB_3_BSR_BIT;
1322
1323         trb.dwTrb3 = htole32(temp);
1324
1325         return (xhci_do_command(sc, &trb, 500 /* ms */));
1326 }
1327
1328 static usb_error_t
1329 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1330 {
1331         struct usb_page_search buf_inp;
1332         struct usb_page_search buf_dev;
1333         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1334         struct xhci_hw_dev *hdev;
1335         struct xhci_dev_ctx *pdev;
1336         struct xhci_endpoint_ext *pepext;
1337         uint32_t temp;
1338         uint16_t mps;
1339         usb_error_t err;
1340         uint8_t index;
1341
1342         /* the root HUB case is not handled here */
1343         if (udev->parent_hub == NULL)
1344                 return (USB_ERR_INVAL);
1345
1346         index = udev->controller_slot_id;
1347
1348         hdev =  &sc->sc_hw.devs[index];
1349
1350         if (mtx != NULL)
1351                 mtx_unlock(mtx);
1352
1353         XHCI_CMD_LOCK(sc);
1354
1355         switch (hdev->state) {
1356         case XHCI_ST_DEFAULT:
1357         case XHCI_ST_ENABLED:
1358
1359                 hdev->state = XHCI_ST_ENABLED;
1360
1361                 /* set configure mask to slot and EP0 */
1362                 xhci_configure_mask(udev, 3, 0);
1363
1364                 /* configure input slot context structure */
1365                 err = xhci_configure_device(udev);
1366
1367                 if (err != 0) {
1368                         DPRINTF("Could not configure device\n");
1369                         break;
1370                 }
1371
1372                 /* configure input endpoint context structure */
1373                 switch (udev->speed) {
1374                 case USB_SPEED_LOW:
1375                 case USB_SPEED_FULL:
1376                         mps = 8;
1377                         break;
1378                 case USB_SPEED_HIGH:
1379                         mps = 64;
1380                         break;
1381                 default:
1382                         mps = 512;
1383                         break;
1384                 }
1385
1386                 pepext = xhci_get_endpoint_ext(udev,
1387                     &udev->ctrl_ep_desc);
1388                 err = xhci_configure_endpoint(udev,
1389                     &udev->ctrl_ep_desc, pepext,
1390                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1391
1392                 if (err != 0) {
1393                         DPRINTF("Could not configure default endpoint\n");
1394                         break;
1395                 }
1396
1397                 /* execute set address command */
1398                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1399
1400                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1401                     (address == 0), index);
1402
1403                 if (err != 0) {
1404                         temp = le32toh(sc->sc_cmd_result[0]);
1405                         if (address == 0 && sc->sc_port_route != NULL &&
1406                             XHCI_TRB_2_ERROR_GET(temp) ==
1407                             XHCI_TRB_ERROR_PARAMETER) {
1408                                 /* LynxPoint XHCI - ports are not switchable */
1409                                 /* Un-route all ports from the XHCI */
1410                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1411                         }
1412                         DPRINTF("Could not set address "
1413                             "for slot %u.\n", index);
1414                         if (address != 0)
1415                                 break;
1416                 }
1417
1418                 /* update device address to new value */
1419
1420                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1421                 pdev = buf_dev.buffer;
1422                 usb_pc_cpu_invalidate(&hdev->device_pc);
1423
1424                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1425                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1426
1427                 /* update device state to new value */
1428
1429                 if (address != 0)
1430                         hdev->state = XHCI_ST_ADDRESSED;
1431                 else
1432                         hdev->state = XHCI_ST_DEFAULT;
1433                 break;
1434
1435         default:
1436                 DPRINTF("Wrong state for set address.\n");
1437                 err = USB_ERR_IOERROR;
1438                 break;
1439         }
1440         XHCI_CMD_UNLOCK(sc);
1441
1442         if (mtx != NULL)
1443                 mtx_lock(mtx);
1444
1445         return (err);
1446 }
1447
1448 static usb_error_t
1449 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1450     uint8_t deconfigure, uint8_t slot_id)
1451 {
1452         struct xhci_trb trb;
1453         uint32_t temp;
1454
1455         DPRINTF("\n");
1456
1457         trb.qwTrb0 = htole64(input_ctx);
1458         trb.dwTrb2 = 0;
1459         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1460             XHCI_TRB_3_SLOT_SET(slot_id);
1461
1462         if (deconfigure)
1463                 temp |= XHCI_TRB_3_DCEP_BIT;
1464
1465         trb.dwTrb3 = htole32(temp);
1466
1467         return (xhci_do_command(sc, &trb, 100 /* ms */));
1468 }
1469
1470 static usb_error_t
1471 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1472     uint8_t slot_id)
1473 {
1474         struct xhci_trb trb;
1475         uint32_t temp;
1476
1477         DPRINTF("\n");
1478
1479         trb.qwTrb0 = htole64(input_ctx);
1480         trb.dwTrb2 = 0;
1481         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1482             XHCI_TRB_3_SLOT_SET(slot_id);
1483         trb.dwTrb3 = htole32(temp);
1484
1485         return (xhci_do_command(sc, &trb, 100 /* ms */));
1486 }
1487
1488 static usb_error_t
1489 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1490     uint8_t ep_id, uint8_t slot_id)
1491 {
1492         struct xhci_trb trb;
1493         uint32_t temp;
1494
1495         DPRINTF("\n");
1496
1497         trb.qwTrb0 = 0;
1498         trb.dwTrb2 = 0;
1499         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1500             XHCI_TRB_3_SLOT_SET(slot_id) |
1501             XHCI_TRB_3_EP_SET(ep_id);
1502
1503         if (preserve)
1504                 temp |= XHCI_TRB_3_PRSV_BIT;
1505
1506         trb.dwTrb3 = htole32(temp);
1507
1508         return (xhci_do_command(sc, &trb, 100 /* ms */));
1509 }
1510
1511 static usb_error_t
1512 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1513     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1514 {
1515         struct xhci_trb trb;
1516         uint32_t temp;
1517
1518         DPRINTF("\n");
1519
1520         trb.qwTrb0 = htole64(dequeue_ptr);
1521
1522         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1523         trb.dwTrb2 = htole32(temp);
1524
1525         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1526             XHCI_TRB_3_SLOT_SET(slot_id) |
1527             XHCI_TRB_3_EP_SET(ep_id);
1528         trb.dwTrb3 = htole32(temp);
1529
1530         return (xhci_do_command(sc, &trb, 100 /* ms */));
1531 }
1532
1533 static usb_error_t
1534 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1535     uint8_t ep_id, uint8_t slot_id)
1536 {
1537         struct xhci_trb trb;
1538         uint32_t temp;
1539
1540         DPRINTF("\n");
1541
1542         trb.qwTrb0 = 0;
1543         trb.dwTrb2 = 0;
1544         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1545             XHCI_TRB_3_SLOT_SET(slot_id) |
1546             XHCI_TRB_3_EP_SET(ep_id);
1547
1548         if (suspend)
1549                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1550
1551         trb.dwTrb3 = htole32(temp);
1552
1553         return (xhci_do_command(sc, &trb, 100 /* ms */));
1554 }
1555
1556 static usb_error_t
1557 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1558 {
1559         struct xhci_trb trb;
1560         uint32_t temp;
1561
1562         DPRINTF("\n");
1563
1564         trb.qwTrb0 = 0;
1565         trb.dwTrb2 = 0;
1566         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1567             XHCI_TRB_3_SLOT_SET(slot_id);
1568
1569         trb.dwTrb3 = htole32(temp);
1570
1571         return (xhci_do_command(sc, &trb, 100 /* ms */));
1572 }
1573
1574 /*------------------------------------------------------------------------*
1575  *      xhci_interrupt - XHCI interrupt handler
1576  *------------------------------------------------------------------------*/
1577 void
1578 xhci_interrupt(struct xhci_softc *sc)
1579 {
1580         uint32_t status;
1581
1582         USB_BUS_LOCK(&sc->sc_bus);
1583
1584         status = XREAD4(sc, oper, XHCI_USBSTS);
1585         if (status == 0)
1586                 goto done;
1587
1588         /* acknowledge interrupts */
1589
1590         XWRITE4(sc, oper, XHCI_USBSTS, status);
1591
1592         DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1593
1594         if (status & XHCI_STS_EINT) {
1595                 /* check for event(s) */
1596                 xhci_interrupt_poll(sc);
1597         }
1598
1599         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1600             XHCI_STS_HSE | XHCI_STS_HCE)) {
1601
1602                 if (status & XHCI_STS_PCD) {
1603                         xhci_root_intr(sc);
1604                 }
1605
1606                 if (status & XHCI_STS_HCH) {
1607                         printf("%s: host controller halted\n",
1608                             __FUNCTION__);
1609                 }
1610
1611                 if (status & XHCI_STS_HSE) {
1612                         printf("%s: host system error\n",
1613                             __FUNCTION__);
1614                 }
1615
1616                 if (status & XHCI_STS_HCE) {
1617                         printf("%s: host controller error\n",
1618                            __FUNCTION__);
1619                 }
1620         }
1621 done:
1622         USB_BUS_UNLOCK(&sc->sc_bus);
1623 }
1624
1625 /*------------------------------------------------------------------------*
1626  *      xhci_timeout - XHCI timeout handler
1627  *------------------------------------------------------------------------*/
1628 static void
1629 xhci_timeout(void *arg)
1630 {
1631         struct usb_xfer *xfer = arg;
1632
1633         DPRINTF("xfer=%p\n", xfer);
1634
1635         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1636
1637         /* transfer is transferred */
1638         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1639 }
1640
1641 static void
1642 xhci_do_poll(struct usb_bus *bus)
1643 {
1644         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1645
1646         USB_BUS_LOCK(&sc->sc_bus);
1647         xhci_interrupt_poll(sc);
1648         USB_BUS_UNLOCK(&sc->sc_bus);
1649 }
1650
1651 static void
1652 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1653 {
1654         struct usb_page_search buf_res;
1655         struct xhci_td *td;
1656         struct xhci_td *td_next;
1657         struct xhci_td *td_alt_next;
1658         struct xhci_td *td_first;
1659         uint32_t buf_offset;
1660         uint32_t average;
1661         uint32_t len_old;
1662         uint32_t npkt_off;
1663         uint32_t dword;
1664         uint8_t shortpkt_old;
1665         uint8_t precompute;
1666         uint8_t x;
1667
1668         td_alt_next = NULL;
1669         buf_offset = 0;
1670         shortpkt_old = temp->shortpkt;
1671         len_old = temp->len;
1672         npkt_off = 0;
1673         precompute = 1;
1674
1675 restart:
1676
1677         td = temp->td;
1678         td_next = td_first = temp->td_next;
1679
1680         while (1) {
1681
1682                 if (temp->len == 0) {
1683
1684                         if (temp->shortpkt)
1685                                 break;
1686
1687                         /* send a Zero Length Packet, ZLP, last */
1688
1689                         temp->shortpkt = 1;
1690                         average = 0;
1691
1692                 } else {
1693
1694                         average = temp->average;
1695
1696                         if (temp->len < average) {
1697                                 if (temp->len % temp->max_packet_size) {
1698                                         temp->shortpkt = 1;
1699                                 }
1700                                 average = temp->len;
1701                         }
1702                 }
1703
1704                 if (td_next == NULL)
1705                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1706
1707                 /* get next TD */
1708
1709                 td = td_next;
1710                 td_next = td->obj_next;
1711
1712                 /* check if we are pre-computing */
1713
1714                 if (precompute) {
1715
1716                         /* update remaining length */
1717
1718                         temp->len -= average;
1719
1720                         continue;
1721                 }
1722                 /* fill out current TD */
1723
1724                 td->len = average;
1725                 td->remainder = 0;
1726                 td->status = 0;
1727
1728                 /* update remaining length */
1729
1730                 temp->len -= average;
1731
1732                 /* reset TRB index */
1733
1734                 x = 0;
1735
1736                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1737                         /* immediate data */
1738
1739                         if (average > 8)
1740                                 average = 8;
1741
1742                         td->td_trb[0].qwTrb0 = 0;
1743
1744                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1745                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1746                            average);
1747
1748                         dword = XHCI_TRB_2_BYTES_SET(8) |
1749                             XHCI_TRB_2_TDSZ_SET(0) |
1750                             XHCI_TRB_2_IRQ_SET(0);
1751
1752                         td->td_trb[0].dwTrb2 = htole32(dword);
1753
1754                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1755                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1756
1757                         /* check wLength */
1758                         if (td->td_trb[0].qwTrb0 &
1759                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1760                                 if (td->td_trb[0].qwTrb0 & htole64(1))
1761                                         dword |= XHCI_TRB_3_TRT_IN;
1762                                 else
1763                                         dword |= XHCI_TRB_3_TRT_OUT;
1764                         }
1765
1766                         td->td_trb[0].dwTrb3 = htole32(dword);
1767 #ifdef USB_DEBUG
1768                         xhci_dump_trb(&td->td_trb[x]);
1769 #endif
1770                         x++;
1771
1772                 } else do {
1773
1774                         uint32_t npkt;
1775
1776                         /* fill out buffer pointers */
1777
1778                         if (average == 0) {
1779                                 memset(&buf_res, 0, sizeof(buf_res));
1780                         } else {
1781                                 usbd_get_page(temp->pc, temp->offset +
1782                                     buf_offset, &buf_res);
1783
1784                                 /* get length to end of page */
1785                                 if (buf_res.length > average)
1786                                         buf_res.length = average;
1787
1788                                 /* check for maximum length */
1789                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1790                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1791
1792                                 npkt_off += buf_res.length;
1793                         }
1794
1795                         /* setup npkt */
1796                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1797                             temp->max_packet_size;
1798
1799                         if (npkt == 0)
1800                                 npkt = 1;
1801                         else if (npkt > 31)
1802                                 npkt = 31;
1803
1804                         /* fill out TRB's */
1805                         td->td_trb[x].qwTrb0 =
1806                             htole64((uint64_t)buf_res.physaddr);
1807
1808                         dword =
1809                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1810                           XHCI_TRB_2_TDSZ_SET(npkt) |
1811                           XHCI_TRB_2_IRQ_SET(0);
1812
1813                         td->td_trb[x].dwTrb2 = htole32(dword);
1814
1815                         switch (temp->trb_type) {
1816                         case XHCI_TRB_TYPE_ISOCH:
1817                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1818                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1819                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1820                                 if (td != td_first) {
1821                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1822                                 } else if (temp->do_isoc_sync != 0) {
1823                                         temp->do_isoc_sync = 0;
1824                                         /* wait until "isoc_frame" */
1825                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1826                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1827                                 } else {
1828                                         /* start data transfer at next interval */
1829                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1830                                             XHCI_TRB_3_ISO_SIA_BIT;
1831                                 }
1832                                 if (temp->direction == UE_DIR_IN)
1833                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1834                                 break;
1835                         case XHCI_TRB_TYPE_DATA_STAGE:
1836                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1837                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE) |
1838                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1839                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1840                                 if (temp->direction == UE_DIR_IN)
1841                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1842                                 break;
1843                         case XHCI_TRB_TYPE_STATUS_STAGE:
1844                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1845                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE) |
1846                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1847                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1848                                 if (temp->direction == UE_DIR_IN)
1849                                         dword |= XHCI_TRB_3_DIR_IN;
1850                                 break;
1851                         default:        /* XHCI_TRB_TYPE_NORMAL */
1852                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1853                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL) |
1854                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1855                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1856                                 if (temp->direction == UE_DIR_IN)
1857                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1858                                 break;
1859                         }
1860                         td->td_trb[x].dwTrb3 = htole32(dword);
1861
1862                         average -= buf_res.length;
1863                         buf_offset += buf_res.length;
1864 #ifdef USB_DEBUG
1865                         xhci_dump_trb(&td->td_trb[x]);
1866 #endif
1867                         x++;
1868
1869                 } while (average != 0);
1870
1871                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1872
1873                 /* store number of data TRB's */
1874
1875                 td->ntrb = x;
1876
1877                 DPRINTF("NTRB=%u\n", x);
1878
1879                 /* fill out link TRB */
1880
1881                 if (td_next != NULL) {
1882                         /* link the current TD with the next one */
1883                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1884                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1885                 } else {
1886                         /* this field will get updated later */
1887                         DPRINTF("NOLINK\n");
1888                 }
1889
1890                 dword = XHCI_TRB_2_IRQ_SET(0);
1891
1892                 td->td_trb[x].dwTrb2 = htole32(dword);
1893
1894                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1895                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT;
1896
1897                 td->td_trb[x].dwTrb3 = htole32(dword);
1898
1899                 td->alt_next = td_alt_next;
1900 #ifdef USB_DEBUG
1901                 xhci_dump_trb(&td->td_trb[x]);
1902 #endif
1903                 usb_pc_cpu_flush(td->page_cache);
1904         }
1905
1906         if (precompute) {
1907                 precompute = 0;
1908
1909                 /* setup alt next pointer, if any */
1910                 if (temp->last_frame) {
1911                         td_alt_next = NULL;
1912                 } else {
1913                         /* we use this field internally */
1914                         td_alt_next = td_next;
1915                 }
1916
1917                 /* restore */
1918                 temp->shortpkt = shortpkt_old;
1919                 temp->len = len_old;
1920                 goto restart;
1921         }
1922
1923         /*
1924          * Remove cycle bit from the first TRB if we are
1925          * stepping them:
1926          */
1927         if (temp->step_td != 0) {
1928                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1929                 usb_pc_cpu_flush(td_first->page_cache);
1930         }
1931
1932         /* clear TD SIZE to zero, hence this is the last TRB */
1933         /* remove chain bit because this is the last TRB in the chain */
1934         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1935         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1936
1937         usb_pc_cpu_flush(td->page_cache);
1938
1939         temp->td = td;
1940         temp->td_next = td_next;
1941 }
1942
1943 static void
1944 xhci_setup_generic_chain(struct usb_xfer *xfer)
1945 {
1946         struct xhci_std_temp temp;
1947         struct xhci_td *td;
1948         uint32_t x;
1949         uint32_t y;
1950         uint8_t mult;
1951
1952         temp.do_isoc_sync = 0;
1953         temp.step_td = 0;
1954         temp.tbc = 0;
1955         temp.tlbpc = 0;
1956         temp.average = xfer->max_hc_frame_size;
1957         temp.max_packet_size = xfer->max_packet_size;
1958         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
1959         temp.pc = NULL;
1960         temp.last_frame = 0;
1961         temp.offset = 0;
1962         temp.multishort = xfer->flags_int.isochronous_xfr ||
1963             xfer->flags_int.control_xfr ||
1964             xfer->flags_int.short_frames_ok;
1965
1966         /* toggle the DMA set we are using */
1967         xfer->flags_int.curr_dma_set ^= 1;
1968
1969         /* get next DMA set */
1970         td = xfer->td_start[xfer->flags_int.curr_dma_set];
1971
1972         temp.td = NULL;
1973         temp.td_next = td;
1974
1975         xfer->td_transfer_first = td;
1976         xfer->td_transfer_cache = td;
1977
1978         if (xfer->flags_int.isochronous_xfr) {
1979                 uint8_t shift;
1980
1981                 /* compute multiplier for ISOCHRONOUS transfers */
1982                 mult = xfer->endpoint->ecomp ?
1983                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
1984                     : 0;
1985                 /* check for USB 2.0 multiplier */
1986                 if (mult == 0) {
1987                         mult = (xfer->endpoint->edesc->
1988                             wMaxPacketSize[1] >> 3) & 3;
1989                 }
1990                 /* range check */
1991                 if (mult > 2)
1992                         mult = 3;
1993                 else
1994                         mult++;
1995
1996                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
1997
1998                 DPRINTF("MFINDEX=0x%08x\n", x);
1999
2000                 switch (usbd_get_speed(xfer->xroot->udev)) {
2001                 case USB_SPEED_FULL:
2002                         shift = 3;
2003                         temp.isoc_delta = 8;    /* 1ms */
2004                         x += temp.isoc_delta - 1;
2005                         x &= ~(temp.isoc_delta - 1);
2006                         break;
2007                 default:
2008                         shift = usbd_xfer_get_fps_shift(xfer);
2009                         temp.isoc_delta = 1U << shift;
2010                         x += temp.isoc_delta - 1;
2011                         x &= ~(temp.isoc_delta - 1);
2012                         /* simple frame load balancing */
2013                         x += xfer->endpoint->usb_uframe;
2014                         break;
2015                 }
2016
2017                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2018
2019                 if ((xfer->endpoint->is_synced == 0) ||
2020                     (y < (xfer->nframes << shift)) ||
2021                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2022                         /*
2023                          * If there is data underflow or the pipe
2024                          * queue is empty we schedule the transfer a
2025                          * few frames ahead of the current frame
2026                          * position. Else two isochronous transfers
2027                          * might overlap.
2028                          */
2029                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2030                         xfer->endpoint->is_synced = 1;
2031                         temp.do_isoc_sync = 1;
2032
2033                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2034                 }
2035
2036                 /* compute isochronous completion time */
2037
2038                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2039
2040                 xfer->isoc_time_complete =
2041                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2042                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2043
2044                 x = 0;
2045                 temp.isoc_frame = xfer->endpoint->isoc_next;
2046                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2047
2048                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2049
2050         } else if (xfer->flags_int.control_xfr) {
2051
2052                 /* check if we should prepend a setup message */
2053
2054                 if (xfer->flags_int.control_hdr) {
2055
2056                         temp.len = xfer->frlengths[0];
2057                         temp.pc = xfer->frbuffers + 0;
2058                         temp.shortpkt = temp.len ? 1 : 0;
2059                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2060                         temp.direction = 0;
2061
2062                         /* check for last frame */
2063                         if (xfer->nframes == 1) {
2064                                 /* no STATUS stage yet, SETUP is last */
2065                                 if (xfer->flags_int.control_act)
2066                                         temp.last_frame = 1;
2067                         }
2068
2069                         xhci_setup_generic_chain_sub(&temp);
2070                 }
2071                 x = 1;
2072                 mult = 1;
2073                 temp.isoc_delta = 0;
2074                 temp.isoc_frame = 0;
2075                 temp.trb_type = XHCI_TRB_TYPE_DATA_STAGE;
2076         } else {
2077                 x = 0;
2078                 mult = 1;
2079                 temp.isoc_delta = 0;
2080                 temp.isoc_frame = 0;
2081                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2082         }
2083
2084         if (x != xfer->nframes) {
2085                 /* setup page_cache pointer */
2086                 temp.pc = xfer->frbuffers + x;
2087                 /* set endpoint direction */
2088                 temp.direction = UE_GET_DIR(xfer->endpointno);
2089         }
2090
2091         while (x != xfer->nframes) {
2092
2093                 /* DATA0 / DATA1 message */
2094
2095                 temp.len = xfer->frlengths[x];
2096                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2097                     x != 0 && temp.multishort == 0);
2098
2099                 x++;
2100
2101                 if (x == xfer->nframes) {
2102                         if (xfer->flags_int.control_xfr) {
2103                                 /* no STATUS stage yet, DATA is last */
2104                                 if (xfer->flags_int.control_act)
2105                                         temp.last_frame = 1;
2106                         } else {
2107                                 temp.last_frame = 1;
2108                         }
2109                 }
2110                 if (temp.len == 0) {
2111
2112                         /* make sure that we send an USB packet */
2113
2114                         temp.shortpkt = 0;
2115
2116                         temp.tbc = 0;
2117                         temp.tlbpc = mult - 1;
2118
2119                 } else if (xfer->flags_int.isochronous_xfr) {
2120
2121                         uint8_t tdpc;
2122
2123                         /*
2124                          * Isochronous transfers don't have short
2125                          * packet termination:
2126                          */
2127
2128                         temp.shortpkt = 1;
2129
2130                         /* isochronous transfers have a transfer limit */
2131
2132                         if (temp.len > xfer->max_frame_size)
2133                                 temp.len = xfer->max_frame_size;
2134
2135                         /* compute TD packet count */
2136                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2137                             xfer->max_packet_size;
2138
2139                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2140                         temp.tlbpc = (tdpc % mult);
2141
2142                         if (temp.tlbpc == 0)
2143                                 temp.tlbpc = mult - 1;
2144                         else
2145                                 temp.tlbpc--;
2146                 } else {
2147
2148                         /* regular data transfer */
2149
2150                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2151                 }
2152
2153                 xhci_setup_generic_chain_sub(&temp);
2154
2155                 if (xfer->flags_int.isochronous_xfr) {
2156                         temp.offset += xfer->frlengths[x - 1];
2157                         temp.isoc_frame += temp.isoc_delta;
2158                 } else {
2159                         /* get next Page Cache pointer */
2160                         temp.pc = xfer->frbuffers + x;
2161                 }
2162         }
2163
2164         /* check if we should append a status stage */
2165
2166         if (xfer->flags_int.control_xfr &&
2167             !xfer->flags_int.control_act) {
2168
2169                 /*
2170                  * Send a DATA1 message and invert the current
2171                  * endpoint direction.
2172                  */
2173                 temp.step_td = (xfer->nframes != 0);
2174                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2175                 temp.len = 0;
2176                 temp.pc = NULL;
2177                 temp.shortpkt = 0;
2178                 temp.last_frame = 1;
2179                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2180
2181                 xhci_setup_generic_chain_sub(&temp);
2182         }
2183
2184         td = temp.td;
2185
2186         /* must have at least one frame! */
2187
2188         xfer->td_transfer_last = td;
2189
2190         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2191 }
2192
2193 static void
2194 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2195 {
2196         struct usb_page_search buf_res;
2197         struct xhci_dev_ctx_addr *pdctxa;
2198
2199         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2200
2201         pdctxa = buf_res.buffer;
2202
2203         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2204
2205         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2206
2207         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2208 }
2209
2210 static usb_error_t
2211 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2212 {
2213         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2214         struct usb_page_search buf_inp;
2215         struct xhci_input_dev_ctx *pinp;
2216         uint32_t temp;
2217         uint8_t index;
2218         uint8_t x;
2219
2220         index = udev->controller_slot_id;
2221
2222         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2223
2224         pinp = buf_inp.buffer;
2225
2226         if (drop) {
2227                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2228                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2229                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2230         } else {
2231                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, 0);
2232                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2233
2234                 /* find most significant set bit */
2235                 for (x = 31; x != 1; x--) {
2236                         if (mask & (1 << x))
2237                                 break;
2238                 }
2239
2240                 /* adjust */
2241                 x--;
2242
2243                 /* figure out maximum */
2244                 if (x > sc->sc_hw.devs[index].context_num) {
2245                         sc->sc_hw.devs[index].context_num = x;
2246                         temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2247                         temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2248                         temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2249                         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2250                 }
2251         }
2252         return (0);
2253 }
2254
2255 static usb_error_t
2256 xhci_configure_endpoint(struct usb_device *udev,
2257     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2258     uint16_t interval, uint8_t max_packet_count,
2259     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2260     uint16_t max_frame_size, uint8_t ep_mode)
2261 {
2262         struct usb_page_search buf_inp;
2263         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2264         struct xhci_input_dev_ctx *pinp;
2265         uint64_t ring_addr = pepext->physaddr;
2266         uint32_t temp;
2267         uint8_t index;
2268         uint8_t epno;
2269         uint8_t type;
2270
2271         index = udev->controller_slot_id;
2272
2273         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2274
2275         pinp = buf_inp.buffer;
2276
2277         epno = edesc->bEndpointAddress;
2278         type = edesc->bmAttributes & UE_XFERTYPE;
2279
2280         if (type == UE_CONTROL)
2281                 epno |= UE_DIR_IN;
2282
2283         epno = XHCI_EPNO2EPID(epno);
2284
2285         if (epno == 0)
2286                 return (USB_ERR_NO_PIPE);               /* invalid */
2287
2288         if (max_packet_count == 0)
2289                 return (USB_ERR_BAD_BUFSIZE);
2290
2291         max_packet_count--;
2292
2293         if (mult == 0)
2294                 return (USB_ERR_BAD_BUFSIZE);
2295
2296         /* store endpoint mode */
2297         pepext->trb_ep_mode = ep_mode;
2298         usb_pc_cpu_flush(pepext->page_cache);
2299
2300         if (ep_mode == USB_EP_MODE_STREAMS) {
2301                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2302                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2303                     XHCI_EPCTX_0_LSA_SET(1);
2304
2305                 ring_addr += sizeof(struct xhci_trb) *
2306                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2307         } else {
2308                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2309                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2310                     XHCI_EPCTX_0_LSA_SET(0);
2311
2312                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2313         }
2314
2315         switch (udev->speed) {
2316         case USB_SPEED_FULL:
2317         case USB_SPEED_LOW:
2318                 /* 1ms -> 125us */
2319                 fps_shift += 3;
2320                 break;
2321         default:
2322                 break;
2323         }
2324
2325         switch (type) {
2326         case UE_INTERRUPT:
2327                 if (fps_shift > 3)
2328                         fps_shift--;
2329                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2330                 break;
2331         case UE_ISOCHRONOUS:
2332                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2333
2334                 switch (udev->speed) {
2335                 case USB_SPEED_SUPER:
2336                         if (mult > 3)
2337                                 mult = 3;
2338                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2339                         max_packet_count /= mult;
2340                         break;
2341                 default:
2342                         break;
2343                 }
2344                 break;
2345         default:
2346                 break;
2347         }
2348
2349         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2350
2351         temp =
2352             XHCI_EPCTX_1_HID_SET(0) |
2353             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2354             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2355
2356         if ((udev->parent_hs_hub != NULL) || (udev->address != 0)) {
2357                 if (type != UE_ISOCHRONOUS)
2358                         temp |= XHCI_EPCTX_1_CERR_SET(3);
2359         }
2360
2361         switch (type) {
2362         case UE_CONTROL:
2363                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2364                 break;
2365         case UE_ISOCHRONOUS:
2366                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2367                 break;
2368         case UE_BULK:
2369                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2370                 break;
2371         default:
2372                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2373                 break;
2374         }
2375
2376         /* check for IN direction */
2377         if (epno & 1)
2378                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2379
2380         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2381         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2382
2383         switch (edesc->bmAttributes & UE_XFERTYPE) {
2384         case UE_INTERRUPT:
2385         case UE_ISOCHRONOUS:
2386                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2387                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2388                     max_frame_size));
2389                 break;
2390         case UE_CONTROL:
2391                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2392                 break;
2393         default:
2394                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2395                 break;
2396         }
2397
2398         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2399
2400 #ifdef USB_DEBUG
2401         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2402 #endif
2403         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2404
2405         return (0);             /* success */
2406 }
2407
2408 static usb_error_t
2409 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2410 {
2411         struct xhci_endpoint_ext *pepext;
2412         struct usb_endpoint_ss_comp_descriptor *ecomp;
2413         usb_stream_t x;
2414
2415         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2416             xfer->endpoint->edesc);
2417
2418         ecomp = xfer->endpoint->ecomp;
2419
2420         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2421                 uint64_t temp;
2422
2423                 /* halt any transfers */
2424                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2425
2426                 /* compute start of TRB ring for stream "x" */
2427                 temp = pepext->physaddr +
2428                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2429                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2430
2431                 /* make tree structure */
2432                 pepext->trb[(XHCI_MAX_TRANSFERS *
2433                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2434
2435                 /* reserved fields */
2436                 pepext->trb[(XHCI_MAX_TRANSFERS *
2437                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2438                 pepext->trb[(XHCI_MAX_TRANSFERS *
2439                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2440         }
2441         usb_pc_cpu_flush(pepext->page_cache);
2442
2443         return (xhci_configure_endpoint(xfer->xroot->udev,
2444             xfer->endpoint->edesc, pepext,
2445             xfer->interval, xfer->max_packet_count,
2446             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2447             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2448             xfer->max_frame_size, xfer->endpoint->ep_mode));
2449 }
2450
2451 static usb_error_t
2452 xhci_configure_device(struct usb_device *udev)
2453 {
2454         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2455         struct usb_page_search buf_inp;
2456         struct usb_page_cache *pcinp;
2457         struct xhci_input_dev_ctx *pinp;
2458         struct usb_device *hubdev;
2459         uint32_t temp;
2460         uint32_t route;
2461         uint32_t rh_port;
2462         uint8_t is_hub;
2463         uint8_t index;
2464         uint8_t depth;
2465
2466         index = udev->controller_slot_id;
2467
2468         DPRINTF("index=%u\n", index);
2469
2470         pcinp = &sc->sc_hw.devs[index].input_pc;
2471
2472         usbd_get_page(pcinp, 0, &buf_inp);
2473
2474         pinp = buf_inp.buffer;
2475
2476         rh_port = 0;
2477         route = 0;
2478
2479         /* figure out route string and root HUB port number */
2480
2481         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2482
2483                 if (hubdev->parent_hub == NULL)
2484                         break;
2485
2486                 depth = hubdev->parent_hub->depth;
2487
2488                 /*
2489                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2490                  * more than 15 ports
2491                  */
2492
2493                 rh_port = hubdev->port_no;
2494
2495                 if (depth == 0)
2496                         break;
2497
2498                 if (rh_port > 15)
2499                         rh_port = 15;
2500
2501                 if (depth < 6)
2502                         route |= rh_port << (4 * (depth - 1));
2503         }
2504
2505         DPRINTF("Route=0x%08x\n", route);
2506
2507         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2508             XHCI_SCTX_0_CTX_NUM_SET(
2509             sc->sc_hw.devs[index].context_num + 1);
2510
2511         switch (udev->speed) {
2512         case USB_SPEED_LOW:
2513                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2514                 if (udev->parent_hs_hub != NULL &&
2515                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2516                     UDPROTO_HSHUBMTT) {
2517                         DPRINTF("Device inherits MTT\n");
2518                         temp |= XHCI_SCTX_0_MTT_SET(1);
2519                 }
2520                 break;
2521         case USB_SPEED_HIGH:
2522                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2523                 if (sc->sc_hw.devs[index].nports != 0 &&
2524                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2525                         DPRINTF("HUB supports MTT\n");
2526                         temp |= XHCI_SCTX_0_MTT_SET(1);
2527                 }
2528                 break;
2529         case USB_SPEED_FULL:
2530                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2531                 if (udev->parent_hs_hub != NULL &&
2532                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2533                     UDPROTO_HSHUBMTT) {
2534                         DPRINTF("Device inherits MTT\n");
2535                         temp |= XHCI_SCTX_0_MTT_SET(1);
2536                 }
2537                 break;
2538         default:
2539                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2540                 break;
2541         }
2542
2543         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2544             (udev->speed == USB_SPEED_SUPER ||
2545             udev->speed == USB_SPEED_HIGH);
2546
2547         if (is_hub)
2548                 temp |= XHCI_SCTX_0_HUB_SET(1);
2549
2550         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2551
2552         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2553
2554         if (is_hub) {
2555                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2556                     sc->sc_hw.devs[index].nports);
2557         }
2558
2559         switch (udev->speed) {
2560         case USB_SPEED_SUPER:
2561                 switch (sc->sc_hw.devs[index].state) {
2562                 case XHCI_ST_ADDRESSED:
2563                 case XHCI_ST_CONFIGURED:
2564                         /* enable power save */
2565                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2566                         break;
2567                 default:
2568                         /* disable power save */
2569                         break;
2570                 }
2571                 break;
2572         default:
2573                 break;
2574         }
2575
2576         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2577
2578         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2579
2580         if (is_hub) {
2581                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2582                     sc->sc_hw.devs[index].tt);
2583         }
2584
2585         hubdev = udev->parent_hs_hub;
2586
2587         /* check if we should activate the transaction translator */
2588         switch (udev->speed) {
2589         case USB_SPEED_FULL:
2590         case USB_SPEED_LOW:
2591                 if (hubdev != NULL) {
2592                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2593                             hubdev->controller_slot_id);
2594                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2595                             udev->hs_port_no);
2596                 }
2597                 break;
2598         default:
2599                 break;
2600         }
2601
2602         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2603
2604         temp = XHCI_SCTX_3_DEV_ADDR_SET(udev->address) |
2605             XHCI_SCTX_3_SLOT_STATE_SET(0);
2606
2607         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2608
2609 #ifdef USB_DEBUG
2610         xhci_dump_device(sc, &pinp->ctx_slot);
2611 #endif
2612         usb_pc_cpu_flush(pcinp);
2613
2614         return (0);             /* success */
2615 }
2616
2617 static usb_error_t
2618 xhci_alloc_device_ext(struct usb_device *udev)
2619 {
2620         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2621         struct usb_page_search buf_dev;
2622         struct usb_page_search buf_ep;
2623         struct xhci_trb *trb;
2624         struct usb_page_cache *pc;
2625         struct usb_page *pg;
2626         uint64_t addr;
2627         uint8_t index;
2628         uint8_t i;
2629
2630         index = udev->controller_slot_id;
2631
2632         pc = &sc->sc_hw.devs[index].device_pc;
2633         pg = &sc->sc_hw.devs[index].device_pg;
2634
2635         /* need to initialize the page cache */
2636         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2637
2638         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2639             (2 * sizeof(struct xhci_dev_ctx)) :
2640             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2641                 goto error;
2642
2643         usbd_get_page(pc, 0, &buf_dev);
2644
2645         pc = &sc->sc_hw.devs[index].input_pc;
2646         pg = &sc->sc_hw.devs[index].input_pg;
2647
2648         /* need to initialize the page cache */
2649         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2650
2651         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2652             (2 * sizeof(struct xhci_input_dev_ctx)) :
2653             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2654                 goto error;
2655         }
2656
2657         pc = &sc->sc_hw.devs[index].endpoint_pc;
2658         pg = &sc->sc_hw.devs[index].endpoint_pg;
2659
2660         /* need to initialize the page cache */
2661         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2662
2663         if (usb_pc_alloc_mem(pc, pg,
2664             sizeof(struct xhci_dev_endpoint_trbs), XHCI_PAGE_SIZE)) {
2665                 goto error;
2666         }
2667
2668         /* initialise all endpoint LINK TRBs */
2669
2670         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2671
2672                 /* lookup endpoint TRB ring */
2673                 usbd_get_page(pc, (uintptr_t)&
2674                     ((struct xhci_dev_endpoint_trbs *)0)->trb[i][0], &buf_ep);
2675
2676                 /* get TRB pointer */
2677                 trb = buf_ep.buffer;
2678                 trb += XHCI_MAX_TRANSFERS - 1;
2679
2680                 /* get TRB start address */
2681                 addr = buf_ep.physaddr;
2682
2683                 /* create LINK TRB */
2684                 trb->qwTrb0 = htole64(addr);
2685                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2686                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2687                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2688         }
2689
2690         usb_pc_cpu_flush(pc);
2691
2692         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2693
2694         return (0);
2695
2696 error:
2697         xhci_free_device_ext(udev);
2698
2699         return (USB_ERR_NOMEM);
2700 }
2701
2702 static void
2703 xhci_free_device_ext(struct usb_device *udev)
2704 {
2705         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2706         uint8_t index;
2707
2708         index = udev->controller_slot_id;
2709         xhci_set_slot_pointer(sc, index, 0);
2710
2711         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2712         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2713         usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc);
2714 }
2715
2716 static struct xhci_endpoint_ext *
2717 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2718 {
2719         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2720         struct xhci_endpoint_ext *pepext;
2721         struct usb_page_cache *pc;
2722         struct usb_page_search buf_ep;
2723         uint8_t epno;
2724         uint8_t index;
2725
2726         epno = edesc->bEndpointAddress;
2727         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2728                 epno |= UE_DIR_IN;
2729
2730         epno = XHCI_EPNO2EPID(epno);
2731
2732         index = udev->controller_slot_id;
2733
2734         pc = &sc->sc_hw.devs[index].endpoint_pc;
2735
2736         usbd_get_page(pc, (uintptr_t)&((struct xhci_dev_endpoint_trbs *)0)->
2737             trb[epno][0], &buf_ep);
2738
2739         pepext = &sc->sc_hw.devs[index].endp[epno];
2740         pepext->page_cache = pc;
2741         pepext->trb = buf_ep.buffer;
2742         pepext->physaddr = buf_ep.physaddr;
2743
2744         return (pepext);
2745 }
2746
2747 static void
2748 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2749 {
2750         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2751         uint8_t epno;
2752         uint8_t index;
2753
2754         epno = xfer->endpointno;
2755         if (xfer->flags_int.control_xfr)
2756                 epno |= UE_DIR_IN;
2757
2758         epno = XHCI_EPNO2EPID(epno);
2759         index = xfer->xroot->udev->controller_slot_id;
2760
2761         if (xfer->xroot->udev->flags.self_suspended == 0) {
2762                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2763                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2764         }
2765 }
2766
2767 static void
2768 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2769 {
2770         struct xhci_endpoint_ext *pepext;
2771
2772         if (xfer->flags_int.bandwidth_reclaimed) {
2773                 xfer->flags_int.bandwidth_reclaimed = 0;
2774
2775                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2776                     xfer->endpoint->edesc);
2777
2778                 pepext->trb_used[xfer->stream_id]--;
2779
2780                 pepext->xfer[xfer->qh_pos] = NULL;
2781
2782                 if (error && pepext->trb_running != 0) {
2783                         pepext->trb_halted = 1;
2784                         pepext->trb_running = 0;
2785                 }
2786         }
2787 }
2788
2789 static usb_error_t
2790 xhci_transfer_insert(struct usb_xfer *xfer)
2791 {
2792         struct xhci_td *td_first;
2793         struct xhci_td *td_last;
2794         struct xhci_trb *trb_link;
2795         struct xhci_endpoint_ext *pepext;
2796         uint64_t addr;
2797         usb_stream_t id;
2798         uint8_t i;
2799         uint8_t inext;
2800         uint8_t trb_limit;
2801
2802         DPRINTFN(8, "\n");
2803
2804         id = xfer->stream_id;
2805
2806         /* check if already inserted */
2807         if (xfer->flags_int.bandwidth_reclaimed) {
2808                 DPRINTFN(8, "Already in schedule\n");
2809                 return (0);
2810         }
2811
2812         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2813             xfer->endpoint->edesc);
2814
2815         td_first = xfer->td_transfer_first;
2816         td_last = xfer->td_transfer_last;
2817         addr = pepext->physaddr;
2818
2819         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2820         case UE_CONTROL:
2821         case UE_INTERRUPT:
2822                 /* single buffered */
2823                 trb_limit = 1;
2824                 break;
2825         default:
2826                 /* multi buffered */
2827                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2828                 break;
2829         }
2830
2831         if (pepext->trb_used[id] >= trb_limit) {
2832                 DPRINTFN(8, "Too many TDs queued.\n");
2833                 return (USB_ERR_NOMEM);
2834         }
2835
2836         /* check for stopped condition, after putting transfer on interrupt queue */
2837         if (pepext->trb_running == 0) {
2838                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2839
2840                 DPRINTFN(8, "Not running\n");
2841
2842                 /* start configuration */
2843                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2844                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2845                 return (0);
2846         }
2847
2848         pepext->trb_used[id]++;
2849
2850         /* get current TRB index */
2851         i = pepext->trb_index[id];
2852
2853         /* get next TRB index */
2854         inext = (i + 1);
2855
2856         /* the last entry of the ring is a hardcoded link TRB */
2857         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2858                 inext = 0;
2859
2860         /* store next TRB index, before stream ID offset is added */
2861         pepext->trb_index[id] = inext;
2862
2863         /* offset for stream */
2864         i += id * XHCI_MAX_TRANSFERS;
2865         inext += id * XHCI_MAX_TRANSFERS;
2866
2867         /* compute terminating return address */
2868         addr += (inext * sizeof(struct xhci_trb));
2869
2870         /* compute link TRB pointer */
2871         trb_link = td_last->td_trb + td_last->ntrb;
2872
2873         /* update next pointer of last link TRB */
2874         trb_link->qwTrb0 = htole64(addr);
2875         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2876         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2877             XHCI_TRB_3_CYCLE_BIT |
2878             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2879
2880 #ifdef USB_DEBUG
2881         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2882 #endif
2883         usb_pc_cpu_flush(td_last->page_cache);
2884
2885         /* write ahead chain end marker */
2886
2887         pepext->trb[inext].qwTrb0 = 0;
2888         pepext->trb[inext].dwTrb2 = 0;
2889         pepext->trb[inext].dwTrb3 = 0;
2890
2891         /* update next pointer of link TRB */
2892
2893         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2894         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2895
2896 #ifdef USB_DEBUG
2897         xhci_dump_trb(&pepext->trb[i]);
2898 #endif
2899         usb_pc_cpu_flush(pepext->page_cache);
2900
2901         /* toggle cycle bit which activates the transfer chain */
2902
2903         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2904             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2905
2906         usb_pc_cpu_flush(pepext->page_cache);
2907
2908         DPRINTF("qh_pos = %u\n", i);
2909
2910         pepext->xfer[i] = xfer;
2911
2912         xfer->qh_pos = i;
2913
2914         xfer->flags_int.bandwidth_reclaimed = 1;
2915
2916         xhci_endpoint_doorbell(xfer);
2917
2918         return (0);
2919 }
2920
2921 static void
2922 xhci_root_intr(struct xhci_softc *sc)
2923 {
2924         uint16_t i;
2925
2926         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2927
2928         /* clear any old interrupt data */
2929         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2930
2931         for (i = 1; i <= sc->sc_noport; i++) {
2932                 /* pick out CHANGE bits from the status register */
2933                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
2934                     XHCI_PS_CSC | XHCI_PS_PEC |
2935                     XHCI_PS_OCC | XHCI_PS_WRC |
2936                     XHCI_PS_PRC | XHCI_PS_PLC |
2937                     XHCI_PS_CEC)) {
2938                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
2939                         DPRINTF("port %d changed\n", i);
2940                 }
2941         }
2942         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
2943             sizeof(sc->sc_hub_idata));
2944 }
2945
2946 /*------------------------------------------------------------------------*
2947  *      xhci_device_done - XHCI done handler
2948  *
2949  * NOTE: This function can be called two times in a row on
2950  * the same USB transfer. From close and from interrupt.
2951  *------------------------------------------------------------------------*/
2952 static void
2953 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
2954 {
2955         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
2956             xfer, xfer->endpoint, error);
2957
2958         /* remove transfer from HW queue */
2959         xhci_transfer_remove(xfer, error);
2960
2961         /* dequeue transfer and start next transfer */
2962         usbd_transfer_done(xfer, error);
2963 }
2964
2965 /*------------------------------------------------------------------------*
2966  * XHCI data transfer support (generic type)
2967  *------------------------------------------------------------------------*/
2968 static void
2969 xhci_device_generic_open(struct usb_xfer *xfer)
2970 {
2971         if (xfer->flags_int.isochronous_xfr) {
2972                 switch (xfer->xroot->udev->speed) {
2973                 case USB_SPEED_FULL:
2974                         break;
2975                 default:
2976                         usb_hs_bandwidth_alloc(xfer);
2977                         break;
2978                 }
2979         }
2980 }
2981
2982 static void
2983 xhci_device_generic_close(struct usb_xfer *xfer)
2984 {
2985         DPRINTF("\n");
2986
2987         xhci_device_done(xfer, USB_ERR_CANCELLED);
2988
2989         if (xfer->flags_int.isochronous_xfr) {
2990                 switch (xfer->xroot->udev->speed) {
2991                 case USB_SPEED_FULL:
2992                         break;
2993                 default:
2994                         usb_hs_bandwidth_free(xfer);
2995                         break;
2996                 }
2997         }
2998 }
2999
3000 static void
3001 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3002     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3003 {
3004         struct usb_xfer *xfer;
3005
3006         /* check if there is a current transfer */
3007         xfer = ep->endpoint_q[stream_id].curr;
3008         if (xfer == NULL)
3009                 return;
3010
3011         /*
3012          * Check if the current transfer is started and then pickup
3013          * the next one, if any. Else wait for next start event due to
3014          * block on failure feature.
3015          */
3016         if (!xfer->flags_int.bandwidth_reclaimed)
3017                 return;
3018
3019         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3020         if (xfer == NULL) {
3021                 /*
3022                  * In case of enter we have to consider that the
3023                  * transfer is queued by the USB core after the enter
3024                  * method is called.
3025                  */
3026                 xfer = enter_xfer;
3027
3028                 if (xfer == NULL)
3029                         return;
3030         }
3031
3032         /* try to multi buffer */
3033         xhci_transfer_insert(xfer);
3034 }
3035
3036 static void
3037 xhci_device_generic_enter(struct usb_xfer *xfer)
3038 {
3039         DPRINTF("\n");
3040
3041         /* setup TD's and QH */
3042         xhci_setup_generic_chain(xfer);
3043
3044         xhci_device_generic_multi_enter(xfer->endpoint,
3045             xfer->stream_id, xfer);
3046 }
3047
3048 static void
3049 xhci_device_generic_start(struct usb_xfer *xfer)
3050 {
3051         DPRINTF("\n");
3052
3053         /* try to insert xfer on HW queue */
3054         xhci_transfer_insert(xfer);
3055
3056         /* try to multi buffer */
3057         xhci_device_generic_multi_enter(xfer->endpoint,
3058             xfer->stream_id, NULL);
3059
3060         /* add transfer last on interrupt queue */
3061         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3062
3063         /* start timeout, if any */
3064         if (xfer->timeout != 0)
3065                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3066 }
3067
3068 struct usb_pipe_methods xhci_device_generic_methods =
3069 {
3070         .open = xhci_device_generic_open,
3071         .close = xhci_device_generic_close,
3072         .enter = xhci_device_generic_enter,
3073         .start = xhci_device_generic_start,
3074 };
3075
3076 /*------------------------------------------------------------------------*
3077  * xhci root HUB support
3078  *------------------------------------------------------------------------*
3079  * Simulate a hardware HUB by handling all the necessary requests.
3080  *------------------------------------------------------------------------*/
3081
3082 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3083
3084 static const
3085 struct usb_device_descriptor xhci_devd =
3086 {
3087         .bLength = sizeof(xhci_devd),
3088         .bDescriptorType = UDESC_DEVICE,        /* type */
3089         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3090         .bDeviceClass = UDCLASS_HUB,            /* class */
3091         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3092         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3093         .bMaxPacketSize = 9,                    /* max packet size */
3094         HSETW(.idVendor, 0x0000),               /* vendor */
3095         HSETW(.idProduct, 0x0000),              /* product */
3096         HSETW(.bcdDevice, 0x0100),              /* device version */
3097         .iManufacturer = 1,
3098         .iProduct = 2,
3099         .iSerialNumber = 0,
3100         .bNumConfigurations = 1,                /* # of configurations */
3101 };
3102
3103 static const
3104 struct xhci_bos_desc xhci_bosd = {
3105         .bosd = {
3106                 .bLength = sizeof(xhci_bosd.bosd),
3107                 .bDescriptorType = UDESC_BOS,
3108                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3109                 .bNumDeviceCaps = 3,
3110         },
3111         .usb2extd = {
3112                 .bLength = sizeof(xhci_bosd.usb2extd),
3113                 .bDescriptorType = 1,
3114                 .bDevCapabilityType = 2,
3115                 .bmAttributes[0] = 2,
3116         },
3117         .usbdcd = {
3118                 .bLength = sizeof(xhci_bosd.usbdcd),
3119                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3120                 .bDevCapabilityType = 3,
3121                 .bmAttributes = 0, /* XXX */
3122                 HSETW(.wSpeedsSupported, 0x000C),
3123                 .bFunctionalitySupport = 8,
3124                 .bU1DevExitLat = 255,   /* dummy - not used */
3125                 .wU2DevExitLat = { 0x00, 0x08 },
3126         },
3127         .cidd = {
3128                 .bLength = sizeof(xhci_bosd.cidd),
3129                 .bDescriptorType = 1,
3130                 .bDevCapabilityType = 4,
3131                 .bReserved = 0,
3132                 .bContainerID = 0, /* XXX */
3133         },
3134 };
3135
3136 static const
3137 struct xhci_config_desc xhci_confd = {
3138         .confd = {
3139                 .bLength = sizeof(xhci_confd.confd),
3140                 .bDescriptorType = UDESC_CONFIG,
3141                 .wTotalLength[0] = sizeof(xhci_confd),
3142                 .bNumInterface = 1,
3143                 .bConfigurationValue = 1,
3144                 .iConfiguration = 0,
3145                 .bmAttributes = UC_SELF_POWERED,
3146                 .bMaxPower = 0          /* max power */
3147         },
3148         .ifcd = {
3149                 .bLength = sizeof(xhci_confd.ifcd),
3150                 .bDescriptorType = UDESC_INTERFACE,
3151                 .bNumEndpoints = 1,
3152                 .bInterfaceClass = UICLASS_HUB,
3153                 .bInterfaceSubClass = UISUBCLASS_HUB,
3154                 .bInterfaceProtocol = 0,
3155         },
3156         .endpd = {
3157                 .bLength = sizeof(xhci_confd.endpd),
3158                 .bDescriptorType = UDESC_ENDPOINT,
3159                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3160                 .bmAttributes = UE_INTERRUPT,
3161                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3162                 .bInterval = 255,
3163         },
3164         .endpcd = {
3165                 .bLength = sizeof(xhci_confd.endpcd),
3166                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3167                 .bMaxBurst = 0,
3168                 .bmAttributes = 0,
3169         },
3170 };
3171
3172 static const
3173 struct usb_hub_ss_descriptor xhci_hubd = {
3174         .bLength = sizeof(xhci_hubd),
3175         .bDescriptorType = UDESC_SS_HUB,
3176 };
3177
3178 static usb_error_t
3179 xhci_roothub_exec(struct usb_device *udev,
3180     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3181 {
3182         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3183         const char *str_ptr;
3184         const void *ptr;
3185         uint32_t port;
3186         uint32_t v;
3187         uint16_t len;
3188         uint16_t i;
3189         uint16_t value;
3190         uint16_t index;
3191         uint8_t j;
3192         usb_error_t err;
3193
3194         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3195
3196         /* buffer reset */
3197         ptr = (const void *)&sc->sc_hub_desc;
3198         len = 0;
3199         err = 0;
3200
3201         value = UGETW(req->wValue);
3202         index = UGETW(req->wIndex);
3203
3204         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3205             "wValue=0x%04x wIndex=0x%04x\n",
3206             req->bmRequestType, req->bRequest,
3207             UGETW(req->wLength), value, index);
3208
3209 #define C(x,y) ((x) | ((y) << 8))
3210         switch (C(req->bRequest, req->bmRequestType)) {
3211         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3212         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3213         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3214                 /*
3215                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3216                  * for the integrated root hub.
3217                  */
3218                 break;
3219         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3220                 len = 1;
3221                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3222                 break;
3223         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3224                 switch (value >> 8) {
3225                 case UDESC_DEVICE:
3226                         if ((value & 0xff) != 0) {
3227                                 err = USB_ERR_IOERROR;
3228                                 goto done;
3229                         }
3230                         len = sizeof(xhci_devd);
3231                         ptr = (const void *)&xhci_devd;
3232                         break;
3233
3234                 case UDESC_BOS:
3235                         if ((value & 0xff) != 0) {
3236                                 err = USB_ERR_IOERROR;
3237                                 goto done;
3238                         }
3239                         len = sizeof(xhci_bosd);
3240                         ptr = (const void *)&xhci_bosd;
3241                         break;
3242
3243                 case UDESC_CONFIG:
3244                         if ((value & 0xff) != 0) {
3245                                 err = USB_ERR_IOERROR;
3246                                 goto done;
3247                         }
3248                         len = sizeof(xhci_confd);
3249                         ptr = (const void *)&xhci_confd;
3250                         break;
3251
3252                 case UDESC_STRING:
3253                         switch (value & 0xff) {
3254                         case 0: /* Language table */
3255                                 str_ptr = "\001";
3256                                 break;
3257
3258                         case 1: /* Vendor */
3259                                 str_ptr = sc->sc_vendor;
3260                                 break;
3261
3262                         case 2: /* Product */
3263                                 str_ptr = "XHCI root HUB";
3264                                 break;
3265
3266                         default:
3267                                 str_ptr = "";
3268                                 break;
3269                         }
3270
3271                         len = usb_make_str_desc(
3272                             sc->sc_hub_desc.temp,
3273                             sizeof(sc->sc_hub_desc.temp),
3274                             str_ptr);
3275                         break;
3276
3277                 default:
3278                         err = USB_ERR_IOERROR;
3279                         goto done;
3280                 }
3281                 break;
3282         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3283                 len = 1;
3284                 sc->sc_hub_desc.temp[0] = 0;
3285                 break;
3286         case C(UR_GET_STATUS, UT_READ_DEVICE):
3287                 len = 2;
3288                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3289                 break;
3290         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3291         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3292                 len = 2;
3293                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3294                 break;
3295         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3296                 if (value >= XHCI_MAX_DEVICES) {
3297                         err = USB_ERR_IOERROR;
3298                         goto done;
3299                 }
3300                 break;
3301         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3302                 if (value != 0 && value != 1) {
3303                         err = USB_ERR_IOERROR;
3304                         goto done;
3305                 }
3306                 sc->sc_conf = value;
3307                 break;
3308         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3309                 break;
3310         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3311         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3312         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3313                 err = USB_ERR_IOERROR;
3314                 goto done;
3315         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3316                 break;
3317         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3318                 break;
3319                 /* Hub requests */
3320         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3321                 break;
3322         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3323                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3324
3325                 if ((index < 1) ||
3326                     (index > sc->sc_noport)) {
3327                         err = USB_ERR_IOERROR;
3328                         goto done;
3329                 }
3330                 port = XHCI_PORTSC(index);
3331
3332                 v = XREAD4(sc, oper, port);
3333                 i = XHCI_PS_PLS_GET(v);
3334                 v &= ~XHCI_PS_CLEAR;
3335
3336                 switch (value) {
3337                 case UHF_C_BH_PORT_RESET:
3338                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3339                         break;
3340                 case UHF_C_PORT_CONFIG_ERROR:
3341                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3342                         break;
3343                 case UHF_C_PORT_SUSPEND:
3344                 case UHF_C_PORT_LINK_STATE:
3345                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3346                         break;
3347                 case UHF_C_PORT_CONNECTION:
3348                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3349                         break;
3350                 case UHF_C_PORT_ENABLE:
3351                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3352                         break;
3353                 case UHF_C_PORT_OVER_CURRENT:
3354                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3355                         break;
3356                 case UHF_C_PORT_RESET:
3357                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3358                         break;
3359                 case UHF_PORT_ENABLE:
3360                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3361                         break;
3362                 case UHF_PORT_POWER:
3363                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3364                         break;
3365                 case UHF_PORT_INDICATOR:
3366                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3367                         break;
3368                 case UHF_PORT_SUSPEND:
3369
3370                         /* U3 -> U15 */
3371                         if (i == 3) {
3372                                 XWRITE4(sc, oper, port, v |
3373                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3374                         }
3375
3376                         /* wait 20ms for resume sequence to complete */
3377                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3378
3379                         /* U0 */
3380                         XWRITE4(sc, oper, port, v |
3381                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3382                         break;
3383                 default:
3384                         err = USB_ERR_IOERROR;
3385                         goto done;
3386                 }
3387                 break;
3388
3389         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3390                 if ((value & 0xff) != 0) {
3391                         err = USB_ERR_IOERROR;
3392                         goto done;
3393                 }
3394
3395                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3396
3397                 sc->sc_hub_desc.hubd = xhci_hubd;
3398
3399                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3400
3401                 if (XHCI_HCS0_PPC(v))
3402                         i = UHD_PWR_INDIVIDUAL;
3403                 else
3404                         i = UHD_PWR_GANGED;
3405
3406                 if (XHCI_HCS0_PIND(v))
3407                         i |= UHD_PORT_IND;
3408
3409                 i |= UHD_OC_INDIVIDUAL;
3410
3411                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3412
3413                 /* see XHCI section 5.4.9: */
3414                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3415
3416                 for (j = 1; j <= sc->sc_noport; j++) {
3417
3418                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3419                         if (v & XHCI_PS_DR) {
3420                                 sc->sc_hub_desc.hubd.
3421                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3422                         }
3423                 }
3424                 len = sc->sc_hub_desc.hubd.bLength;
3425                 break;
3426
3427         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3428                 len = 16;
3429                 memset(sc->sc_hub_desc.temp, 0, 16);
3430                 break;
3431
3432         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3433                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3434
3435                 if ((index < 1) ||
3436                     (index > sc->sc_noport)) {
3437                         err = USB_ERR_IOERROR;
3438                         goto done;
3439                 }
3440
3441                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3442
3443                 DPRINTFN(9, "port status=0x%08x\n", v);
3444
3445                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3446
3447                 switch (XHCI_PS_SPEED_GET(v)) {
3448                 case 3:
3449                         i |= UPS_HIGH_SPEED;
3450                         break;
3451                 case 2:
3452                         i |= UPS_LOW_SPEED;
3453                         break;
3454                 case 1:
3455                         /* FULL speed */
3456                         break;
3457                 default:
3458                         i |= UPS_OTHER_SPEED;
3459                         break;
3460                 }
3461
3462                 if (v & XHCI_PS_CCS)
3463                         i |= UPS_CURRENT_CONNECT_STATUS;
3464                 if (v & XHCI_PS_PED)
3465                         i |= UPS_PORT_ENABLED;
3466                 if (v & XHCI_PS_OCA)
3467                         i |= UPS_OVERCURRENT_INDICATOR;
3468                 if (v & XHCI_PS_PR)
3469                         i |= UPS_RESET;
3470                 if (v & XHCI_PS_PP) {
3471                         /*
3472                          * The USB 3.0 RH is using the
3473                          * USB 2.0's power bit
3474                          */
3475                         i |= UPS_PORT_POWER;
3476                 }
3477                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3478
3479                 i = 0;
3480                 if (v & XHCI_PS_CSC)
3481                         i |= UPS_C_CONNECT_STATUS;
3482                 if (v & XHCI_PS_PEC)
3483                         i |= UPS_C_PORT_ENABLED;
3484                 if (v & XHCI_PS_OCC)
3485                         i |= UPS_C_OVERCURRENT_INDICATOR;
3486                 if (v & XHCI_PS_WRC)
3487                         i |= UPS_C_BH_PORT_RESET;
3488                 if (v & XHCI_PS_PRC)
3489                         i |= UPS_C_PORT_RESET;
3490                 if (v & XHCI_PS_PLC)
3491                         i |= UPS_C_PORT_LINK_STATE;
3492                 if (v & XHCI_PS_CEC)
3493                         i |= UPS_C_PORT_CONFIG_ERROR;
3494
3495                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3496                 len = sizeof(sc->sc_hub_desc.ps);
3497                 break;
3498
3499         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3500                 err = USB_ERR_IOERROR;
3501                 goto done;
3502
3503         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3504                 break;
3505
3506         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3507
3508                 i = index >> 8;
3509                 index &= 0x00FF;
3510
3511                 if ((index < 1) ||
3512                     (index > sc->sc_noport)) {
3513                         err = USB_ERR_IOERROR;
3514                         goto done;
3515                 }
3516
3517                 port = XHCI_PORTSC(index);
3518                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3519
3520                 switch (value) {
3521                 case UHF_PORT_U1_TIMEOUT:
3522                         if (XHCI_PS_SPEED_GET(v) != 4) {
3523                                 err = USB_ERR_IOERROR;
3524                                 goto done;
3525                         }
3526                         port = XHCI_PORTPMSC(index);
3527                         v = XREAD4(sc, oper, port);
3528                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3529                         v |= XHCI_PM3_U1TO_SET(i);
3530                         XWRITE4(sc, oper, port, v);
3531                         break;
3532                 case UHF_PORT_U2_TIMEOUT:
3533                         if (XHCI_PS_SPEED_GET(v) != 4) {
3534                                 err = USB_ERR_IOERROR;
3535                                 goto done;
3536                         }
3537                         port = XHCI_PORTPMSC(index);
3538                         v = XREAD4(sc, oper, port);
3539                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3540                         v |= XHCI_PM3_U2TO_SET(i);
3541                         XWRITE4(sc, oper, port, v);
3542                         break;
3543                 case UHF_BH_PORT_RESET:
3544                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3545                         break;
3546                 case UHF_PORT_LINK_STATE:
3547                         XWRITE4(sc, oper, port, v |
3548                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3549                         /* 4ms settle time */
3550                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3551                         break;
3552                 case UHF_PORT_ENABLE:
3553                         DPRINTFN(3, "set port enable %d\n", index);
3554                         break;
3555                 case UHF_PORT_SUSPEND:
3556                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3557                         j = XHCI_PS_SPEED_GET(v);
3558                         if ((j < 1) || (j > 3)) {
3559                                 /* non-supported speed */
3560                                 err = USB_ERR_IOERROR;
3561                                 goto done;
3562                         }
3563                         XWRITE4(sc, oper, port, v |
3564                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3565                         break;
3566                 case UHF_PORT_RESET:
3567                         DPRINTFN(6, "reset port %d\n", index);
3568                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3569                         break;
3570                 case UHF_PORT_POWER:
3571                         DPRINTFN(3, "set port power %d\n", index);
3572                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3573                         break;
3574                 case UHF_PORT_TEST:
3575                         DPRINTFN(3, "set port test %d\n", index);
3576                         break;
3577                 case UHF_PORT_INDICATOR:
3578                         DPRINTFN(3, "set port indicator %d\n", index);
3579
3580                         v &= ~XHCI_PS_PIC_SET(3);
3581                         v |= XHCI_PS_PIC_SET(1);
3582
3583                         XWRITE4(sc, oper, port, v);
3584                         break;
3585                 default:
3586                         err = USB_ERR_IOERROR;
3587                         goto done;
3588                 }
3589                 break;
3590
3591         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3592         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3593         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3594         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3595                 break;
3596         default:
3597                 err = USB_ERR_IOERROR;
3598                 goto done;
3599         }
3600 done:
3601         *plength = len;
3602         *pptr = ptr;
3603         return (err);
3604 }
3605
3606 static void
3607 xhci_xfer_setup(struct usb_setup_params *parm)
3608 {
3609         struct usb_page_search page_info;
3610         struct usb_page_cache *pc;
3611         struct xhci_softc *sc;
3612         struct usb_xfer *xfer;
3613         void *last_obj;
3614         uint32_t ntd;
3615         uint32_t n;
3616
3617         sc = XHCI_BUS2SC(parm->udev->bus);
3618         xfer = parm->curr_xfer;
3619
3620         /*
3621          * The proof for the "ntd" formula is illustrated like this:
3622          *
3623          * +------------------------------------+
3624          * |                                    |
3625          * |         |remainder ->              |
3626          * |   +-----+---+                      |
3627          * |   | xxx | x | frm 0                |
3628          * |   +-----+---++                     |
3629          * |   | xxx | xx | frm 1               |
3630          * |   +-----+----+                     |
3631          * |            ...                     |
3632          * +------------------------------------+
3633          *
3634          * "xxx" means a completely full USB transfer descriptor
3635          *
3636          * "x" and "xx" means a short USB packet
3637          *
3638          * For the remainder of an USB transfer modulo
3639          * "max_data_length" we need two USB transfer descriptors.
3640          * One to transfer the remaining data and one to finalise with
3641          * a zero length packet in case the "force_short_xfer" flag is
3642          * set. We only need two USB transfer descriptors in the case
3643          * where the transfer length of the first one is a factor of
3644          * "max_frame_size". The rest of the needed USB transfer
3645          * descriptors is given by the buffer size divided by the
3646          * maximum data payload.
3647          */
3648         parm->hc_max_packet_size = 0x400;
3649         parm->hc_max_packet_count = 16 * 3;
3650         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3651
3652         xfer->flags_int.bdma_enable = 1;
3653
3654         usbd_transfer_setup_sub(parm);
3655
3656         if (xfer->flags_int.isochronous_xfr) {
3657                 ntd = ((1 * xfer->nframes)
3658                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3659         } else if (xfer->flags_int.control_xfr) {
3660                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3661                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3662         } else {
3663                 ntd = ((2 * xfer->nframes)
3664                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3665         }
3666
3667 alloc_dma_set:
3668
3669         if (parm->err)
3670                 return;
3671
3672         /*
3673          * Allocate queue heads and transfer descriptors
3674          */
3675         last_obj = NULL;
3676
3677         if (usbd_transfer_setup_sub_malloc(
3678             parm, &pc, sizeof(struct xhci_td),
3679             XHCI_TD_ALIGN, ntd)) {
3680                 parm->err = USB_ERR_NOMEM;
3681                 return;
3682         }
3683         if (parm->buf) {
3684                 for (n = 0; n != ntd; n++) {
3685                         struct xhci_td *td;
3686
3687                         usbd_get_page(pc + n, 0, &page_info);
3688
3689                         td = page_info.buffer;
3690
3691                         /* init TD */
3692                         td->td_self = page_info.physaddr;
3693                         td->obj_next = last_obj;
3694                         td->page_cache = pc + n;
3695
3696                         last_obj = td;
3697
3698                         usb_pc_cpu_flush(pc + n);
3699                 }
3700         }
3701         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3702
3703         if (!xfer->flags_int.curr_dma_set) {
3704                 xfer->flags_int.curr_dma_set = 1;
3705                 goto alloc_dma_set;
3706         }
3707 }
3708
3709 static usb_error_t
3710 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3711 {
3712         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3713         struct usb_page_search buf_inp;
3714         struct usb_device *udev;
3715         struct xhci_endpoint_ext *pepext;
3716         struct usb_endpoint_descriptor *edesc;
3717         struct usb_page_cache *pcinp;
3718         usb_error_t err;
3719         usb_stream_t stream_id;
3720         uint8_t index;
3721         uint8_t epno;
3722
3723         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3724             xfer->endpoint->edesc);
3725
3726         udev = xfer->xroot->udev;
3727         index = udev->controller_slot_id;
3728
3729         pcinp = &sc->sc_hw.devs[index].input_pc;
3730
3731         usbd_get_page(pcinp, 0, &buf_inp);
3732
3733         edesc = xfer->endpoint->edesc;
3734
3735         epno = edesc->bEndpointAddress;
3736         stream_id = xfer->stream_id;
3737
3738         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3739                 epno |= UE_DIR_IN;
3740
3741         epno = XHCI_EPNO2EPID(epno);
3742
3743         if (epno == 0)
3744                 return (USB_ERR_NO_PIPE);               /* invalid */
3745
3746         XHCI_CMD_LOCK(sc);
3747
3748         /* configure endpoint */
3749
3750         err = xhci_configure_endpoint_by_xfer(xfer);
3751
3752         if (err != 0) {
3753                 XHCI_CMD_UNLOCK(sc);
3754                 return (err);
3755         }
3756
3757         /*
3758          * Get the endpoint into the stopped state according to the
3759          * endpoint context state diagram in the XHCI specification:
3760          */
3761
3762         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3763
3764         if (err != 0)
3765                 DPRINTF("Could not stop endpoint %u\n", epno);
3766
3767         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3768
3769         if (err != 0)
3770                 DPRINTF("Could not reset endpoint %u\n", epno);
3771
3772         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3773             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3774             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3775             stream_id, epno, index);
3776
3777         if (err != 0)
3778                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3779
3780         /*
3781          * Get the endpoint into the running state according to the
3782          * endpoint context state diagram in the XHCI specification:
3783          */
3784
3785         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3786
3787         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3788
3789         if (err != 0)
3790                 DPRINTF("Could not configure endpoint %u\n", epno);
3791
3792         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3793
3794         if (err != 0)
3795                 DPRINTF("Could not configure endpoint %u\n", epno);
3796
3797         XHCI_CMD_UNLOCK(sc);
3798
3799         return (0);
3800 }
3801
3802 static void
3803 xhci_xfer_unsetup(struct usb_xfer *xfer)
3804 {
3805         return;
3806 }
3807
3808 static void
3809 xhci_start_dma_delay(struct usb_xfer *xfer)
3810 {
3811         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3812
3813         /* put transfer on interrupt queue (again) */
3814         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3815
3816         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3817             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3818 }
3819
3820 static void
3821 xhci_configure_msg(struct usb_proc_msg *pm)
3822 {
3823         struct xhci_softc *sc;
3824         struct xhci_endpoint_ext *pepext;
3825         struct usb_xfer *xfer;
3826
3827         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3828
3829 restart:
3830         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3831
3832                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3833                     xfer->endpoint->edesc);
3834
3835                 if ((pepext->trb_halted != 0) ||
3836                     (pepext->trb_running == 0)) {
3837
3838                         uint16_t i;
3839
3840                         /* clear halted and running */
3841                         pepext->trb_halted = 0;
3842                         pepext->trb_running = 0;
3843
3844                         /* nuke remaining buffered transfers */
3845
3846                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3847                             XHCI_MAX_STREAMS); i++) {
3848                                 /*
3849                                  * NOTE: We need to use the timeout
3850                                  * error code here else existing
3851                                  * isochronous clients can get
3852                                  * confused:
3853                                  */
3854                                 if (pepext->xfer[i] != NULL) {
3855                                         xhci_device_done(pepext->xfer[i],
3856                                             USB_ERR_TIMEOUT);
3857                                 }
3858                         }
3859
3860                         /*
3861                          * NOTE: The USB transfer cannot vanish in
3862                          * this state!
3863                          */
3864
3865                         USB_BUS_UNLOCK(&sc->sc_bus);
3866
3867                         xhci_configure_reset_endpoint(xfer);
3868
3869                         USB_BUS_LOCK(&sc->sc_bus);
3870
3871                         /* check if halted is still cleared */
3872                         if (pepext->trb_halted == 0) {
3873                                 pepext->trb_running = 1;
3874                                 memset(pepext->trb_index, 0,
3875                                     sizeof(pepext->trb_index));
3876                         }
3877                         goto restart;
3878                 }
3879
3880                 if (xfer->flags_int.did_dma_delay) {
3881
3882                         /* remove transfer from interrupt queue (again) */
3883                         usbd_transfer_dequeue(xfer);
3884
3885                         /* we are finally done */
3886                         usb_dma_delay_done_cb(xfer);
3887
3888                         /* queue changed - restart */
3889                         goto restart;
3890                 }
3891         }
3892
3893         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3894
3895                 /* try to insert xfer on HW queue */
3896                 xhci_transfer_insert(xfer);
3897
3898                 /* try to multi buffer */
3899                 xhci_device_generic_multi_enter(xfer->endpoint,
3900                     xfer->stream_id, NULL);
3901         }
3902 }
3903
3904 static void
3905 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3906     struct usb_endpoint *ep)
3907 {
3908         struct xhci_endpoint_ext *pepext;
3909
3910         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3911             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3912
3913         if (udev->parent_hub == NULL) {
3914                 /* root HUB has special endpoint handling */
3915                 return;
3916         }
3917
3918         ep->methods = &xhci_device_generic_methods;
3919
3920         pepext = xhci_get_endpoint_ext(udev, edesc);
3921
3922         USB_BUS_LOCK(udev->bus);
3923         pepext->trb_halted = 1;
3924         pepext->trb_running = 0;
3925         USB_BUS_UNLOCK(udev->bus);
3926 }
3927
3928 static void
3929 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3930 {
3931
3932 }
3933
3934 static void
3935 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
3936 {
3937         struct xhci_endpoint_ext *pepext;
3938
3939         DPRINTF("\n");
3940
3941         if (udev->flags.usb_mode != USB_MODE_HOST) {
3942                 /* not supported */
3943                 return;
3944         }
3945         if (udev->parent_hub == NULL) {
3946                 /* root HUB has special endpoint handling */
3947                 return;
3948         }
3949
3950         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
3951
3952         USB_BUS_LOCK(udev->bus);
3953         pepext->trb_halted = 1;
3954         pepext->trb_running = 0;
3955         USB_BUS_UNLOCK(udev->bus);
3956 }
3957
3958 static usb_error_t
3959 xhci_device_init(struct usb_device *udev)
3960 {
3961         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3962         usb_error_t err;
3963         uint8_t temp;
3964
3965         /* no init for root HUB */
3966         if (udev->parent_hub == NULL)
3967                 return (0);
3968
3969         XHCI_CMD_LOCK(sc);
3970
3971         /* set invalid default */
3972
3973         udev->controller_slot_id = sc->sc_noslot + 1;
3974
3975         /* try to get a new slot ID from the XHCI */
3976
3977         err = xhci_cmd_enable_slot(sc, &temp);
3978
3979         if (err) {
3980                 XHCI_CMD_UNLOCK(sc);
3981                 return (err);
3982         }
3983
3984         if (temp > sc->sc_noslot) {
3985                 XHCI_CMD_UNLOCK(sc);
3986                 return (USB_ERR_BAD_ADDRESS);
3987         }
3988
3989         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
3990                 DPRINTF("slot %u already allocated.\n", temp);
3991                 XHCI_CMD_UNLOCK(sc);
3992                 return (USB_ERR_BAD_ADDRESS);
3993         }
3994
3995         /* store slot ID for later reference */
3996
3997         udev->controller_slot_id = temp;
3998
3999         /* reset data structure */
4000
4001         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4002
4003         /* set mark slot allocated */
4004
4005         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4006
4007         err = xhci_alloc_device_ext(udev);
4008
4009         XHCI_CMD_UNLOCK(sc);
4010
4011         /* get device into default state */
4012
4013         if (err == 0)
4014                 err = xhci_set_address(udev, NULL, 0);
4015
4016         return (err);
4017 }
4018
4019 static void
4020 xhci_device_uninit(struct usb_device *udev)
4021 {
4022         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4023         uint8_t index;
4024
4025         /* no init for root HUB */
4026         if (udev->parent_hub == NULL)
4027                 return;
4028
4029         XHCI_CMD_LOCK(sc);
4030
4031         index = udev->controller_slot_id;
4032
4033         if (index <= sc->sc_noslot) {
4034                 xhci_cmd_disable_slot(sc, index);
4035                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4036
4037                 /* free device extension */
4038                 xhci_free_device_ext(udev);
4039         }
4040
4041         XHCI_CMD_UNLOCK(sc);
4042 }
4043
4044 static void
4045 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4046 {
4047         /*
4048          * Wait until the hardware has finished any possible use of
4049          * the transfer descriptor(s)
4050          */
4051         *pus = 2048;                    /* microseconds */
4052 }
4053
4054 static void
4055 xhci_device_resume(struct usb_device *udev)
4056 {
4057         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4058         uint8_t index;
4059         uint8_t n;
4060         uint8_t p;
4061
4062         DPRINTF("\n");
4063
4064         /* check for root HUB */
4065         if (udev->parent_hub == NULL)
4066                 return;
4067
4068         index = udev->controller_slot_id;
4069
4070         XHCI_CMD_LOCK(sc);
4071
4072         /* blindly resume all endpoints */
4073
4074         USB_BUS_LOCK(udev->bus);
4075
4076         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4077                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4078                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4079                             n | XHCI_DB_SID_SET(p));
4080                 }
4081         }
4082
4083         USB_BUS_UNLOCK(udev->bus);
4084
4085         XHCI_CMD_UNLOCK(sc);
4086 }
4087
4088 static void
4089 xhci_device_suspend(struct usb_device *udev)
4090 {
4091         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4092         uint8_t index;
4093         uint8_t n;
4094         usb_error_t err;
4095
4096         DPRINTF("\n");
4097
4098         /* check for root HUB */
4099         if (udev->parent_hub == NULL)
4100                 return;
4101
4102         index = udev->controller_slot_id;
4103
4104         XHCI_CMD_LOCK(sc);
4105
4106         /* blindly suspend all endpoints */
4107
4108         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4109                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4110                 if (err != 0) {
4111                         DPRINTF("Failed to suspend endpoint "
4112                             "%u on slot %u (ignored).\n", n, index);
4113                 }
4114         }
4115
4116         XHCI_CMD_UNLOCK(sc);
4117 }
4118
4119 static void
4120 xhci_set_hw_power(struct usb_bus *bus)
4121 {
4122         DPRINTF("\n");
4123 }
4124
4125 static void
4126 xhci_device_state_change(struct usb_device *udev)
4127 {
4128         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4129         struct usb_page_search buf_inp;
4130         usb_error_t err;
4131         uint8_t index;
4132
4133         /* check for root HUB */
4134         if (udev->parent_hub == NULL)
4135                 return;
4136
4137         index = udev->controller_slot_id;
4138
4139         DPRINTF("\n");
4140
4141         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4142                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4143                     &sc->sc_hw.devs[index].tt);
4144                 if (err != 0)
4145                         sc->sc_hw.devs[index].nports = 0;
4146         }
4147
4148         XHCI_CMD_LOCK(sc);
4149
4150         switch (usb_get_device_state(udev)) {
4151         case USB_STATE_POWERED:
4152                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4153                         break;
4154
4155                 /* set default state */
4156                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4157
4158                 /* reset number of contexts */
4159                 sc->sc_hw.devs[index].context_num = 0;
4160
4161                 err = xhci_cmd_reset_dev(sc, index);
4162
4163                 if (err != 0) {
4164                         DPRINTF("Device reset failed "
4165                             "for slot %u.\n", index);
4166                 }
4167                 break;
4168
4169         case USB_STATE_ADDRESSED:
4170                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4171                         break;
4172
4173                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4174
4175                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4176
4177                 if (err) {
4178                         DPRINTF("Failed to deconfigure "
4179                             "slot %u.\n", index);
4180                 }
4181                 break;
4182
4183         case USB_STATE_CONFIGURED:
4184                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4185                         break;
4186
4187                 /* set configured state */
4188                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4189
4190                 /* reset number of contexts */
4191                 sc->sc_hw.devs[index].context_num = 0;
4192
4193                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4194
4195                 xhci_configure_mask(udev, 3, 0);
4196
4197                 err = xhci_configure_device(udev);
4198                 if (err != 0) {
4199                         DPRINTF("Could not configure device "
4200                             "at slot %u.\n", index);
4201                 }
4202
4203                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4204                 if (err != 0) {
4205                         DPRINTF("Could not evaluate device "
4206                             "context at slot %u.\n", index);
4207                 }
4208                 break;
4209
4210         default:
4211                 break;
4212         }
4213         XHCI_CMD_UNLOCK(sc);
4214 }
4215
4216 static usb_error_t
4217 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4218     uint8_t ep_mode)
4219 {
4220         switch (ep_mode) {
4221         case USB_EP_MODE_DEFAULT:
4222                 return (0);
4223         case USB_EP_MODE_STREAMS:
4224                 if (xhcistreams == 0 ||
4225                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4226                     udev->speed != USB_SPEED_SUPER)
4227                         return (USB_ERR_INVAL);
4228                 return (0);
4229         default:
4230                 return (USB_ERR_INVAL);
4231         }
4232 }
4233
4234 struct usb_bus_methods xhci_bus_methods = {
4235         .endpoint_init = xhci_ep_init,
4236         .endpoint_uninit = xhci_ep_uninit,
4237         .xfer_setup = xhci_xfer_setup,
4238         .xfer_unsetup = xhci_xfer_unsetup,
4239         .get_dma_delay = xhci_get_dma_delay,
4240         .device_init = xhci_device_init,
4241         .device_uninit = xhci_device_uninit,
4242         .device_resume = xhci_device_resume,
4243         .device_suspend = xhci_device_suspend,
4244         .set_hw_power = xhci_set_hw_power,
4245         .roothub_exec = xhci_roothub_exec,
4246         .xfer_poll = xhci_do_poll,
4247         .start_dma_delay = xhci_start_dma_delay,
4248         .set_address = xhci_set_address,
4249         .clear_stall = xhci_ep_clear_stall,
4250         .device_state_change = xhci_device_state_change,
4251         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4252         .set_endpoint_mode = xhci_set_endpoint_mode,
4253 };