sys/dev/usb/controller/xhci.c

   1 /* $FreeBSD$ */
   2 /*-
   3  * Copyright (c) 2010 Hans Petter Selasky. All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  15  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  16  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  17  * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
  18  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  19  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  20  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  22  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  23  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  24  * SUCH DAMAGE.
  25  */
  26
  27 /*
  28  * USB eXtensible Host Controller Interface, a.k.a. USB 3.0 controller.
  29  *
  30  * The XHCI 1.0 spec can be found at
  31  * http://www.intel.com/technology/usb/download/xHCI_Specification_for_USB.pdf
  32  * and the USB 3.0 spec at
  33  * http://www.usb.org/developers/docs/usb_30_spec_060910.zip
  34  */
  35
  36 /*
  37  * A few words about the design implementation: This driver emulates
  38  * the concept about TDs which is found in EHCI specification. This
  39  * way we achieve that the USB controller drivers look similar to
  40  * eachother which makes it easier to understand the code.
  41  */
  42
  43 #ifdef USB_GLOBAL_INCLUDE_FILE
  44 #include USB_GLOBAL_INCLUDE_FILE
  45 #else
  46 #include <sys/stdint.h>
  47 #include <sys/stddef.h>
  48 #include <sys/param.h>
  49 #include <sys/queue.h>
  50 #include <sys/types.h>
  51 #include <sys/systm.h>
  52 #include <sys/kernel.h>
  53 #include <sys/bus.h>
  54 #include <sys/module.h>
  55 #include <sys/lock.h>
  56 #include <sys/mutex.h>
  57 #include <sys/condvar.h>
  58 #include <sys/sysctl.h>
  59 #include <sys/sx.h>
  60 #include <sys/unistd.h>
  61 #include <sys/callout.h>
  62 #include <sys/malloc.h>
  63 #include <sys/priv.h>
  64
  65 #include <dev/usb/usb.h>
  66 #include <dev/usb/usbdi.h>
  67
  68 #define USB_DEBUG_VAR xhcidebug
  69
  70 #include <dev/usb/usb_core.h>
  71 #include <dev/usb/usb_debug.h>
  72 #include <dev/usb/usb_busdma.h>
  73 #include <dev/usb/usb_process.h>
  74 #include <dev/usb/usb_transfer.h>
  75 #include <dev/usb/usb_device.h>
  76 #include <dev/usb/usb_hub.h>
  77 #include <dev/usb/usb_util.h>
  78
  79 #include <dev/usb/usb_controller.h>
  80 #include <dev/usb/usb_bus.h>
  81 #endif                  /* USB_GLOBAL_INCLUDE_FILE */
  82
  83 #include <dev/usb/controller/xhci.h>
  84 #include <dev/usb/controller/xhcireg.h>
  85
  86 #define XHCI_BUS2SC(bus) \
  87    ((struct xhci_softc *)(((uint8_t *)(bus)) - \
  88     ((uint8_t *)&(((struct xhci_softc *)0)->sc_bus))))
  89
  90 static SYSCTL_NODE(_hw_usb, OID_AUTO, xhci, CTLFLAG_RW, 0, "USB XHCI");
  91
  92 static int xhcistreams;
  93 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, streams, CTLFLAG_RW | CTLFLAG_TUN,
  94     &xhcistreams, 0, "Set to enable streams mode support");
  95 TUNABLE_INT("hw.usb.xhci.streams", &xhcistreams);
  96
  97 #ifdef USB_DEBUG
  98 static int xhcidebug;
  99 static int xhciroute;
 100 static int xhcipolling;
 101
 102 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN,
 103     &xhcidebug, 0, "Debug level");
 104 TUNABLE_INT("hw.usb.xhci.debug", &xhcidebug);
 105 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, xhci_port_route, CTLFLAG_RW | CTLFLAG_TUN,
 106     &xhciroute, 0, "Routing bitmap for switching EHCI ports to XHCI controller");
 107 TUNABLE_INT("hw.usb.xhci.xhci_port_route", &xhciroute);
 108 SYSCTL_INT(_hw_usb_xhci, OID_AUTO, use_polling, CTLFLAG_RW | CTLFLAG_TUN,
 109     &xhcipolling, 0, "Set to enable software interrupt polling for XHCI controller");
 110 TUNABLE_INT("hw.usb.xhci.use_polling", &xhcipolling);
 111 #else
 112 #define xhciroute 0
 113 #endif
 114
 115 #define XHCI_INTR_ENDPT 1
 116
 117 struct xhci_std_temp {
 118         struct xhci_softc       *sc;
 119         struct usb_page_cache   *pc;
 120         struct xhci_td          *td;
 121         struct xhci_td          *td_next;
 122         uint32_t                len;
 123         uint32_t                offset;
 124         uint32_t                max_packet_size;
 125         uint32_t                average;
 126         uint16_t                isoc_delta;
 127         uint16_t                isoc_frame;
 128         uint8_t                 shortpkt;
 129         uint8_t                 multishort;
 130         uint8_t                 last_frame;
 131         uint8_t                 trb_type;
 132         uint8_t                 direction;
 133         uint8_t                 tbc;
 134         uint8_t                 tlbpc;
 135         uint8_t                 step_td;
 136         uint8_t                 do_isoc_sync;
 137 };
 138
 139 static void     xhci_do_poll(struct usb_bus *);
 140 static void     xhci_device_done(struct usb_xfer *, usb_error_t);
 141 static void     xhci_root_intr(struct xhci_softc *);
 142 static void     xhci_free_device_ext(struct usb_device *);
 143 static struct xhci_endpoint_ext *xhci_get_endpoint_ext(struct usb_device *,
 144                     struct usb_endpoint_descriptor *);
 145 static usb_proc_callback_t xhci_configure_msg;
 146 static usb_error_t xhci_configure_device(struct usb_device *);
 147 static usb_error_t xhci_configure_endpoint(struct usb_device *,
 148                    struct usb_endpoint_descriptor *, struct xhci_endpoint_ext *,
 149                    uint16_t, uint8_t, uint8_t, uint8_t, uint16_t, uint16_t,
 150                    uint8_t);
 151 static usb_error_t xhci_configure_mask(struct usb_device *,
 152                     uint32_t, uint8_t);
 153 static usb_error_t xhci_cmd_evaluate_ctx(struct xhci_softc *,
 154                     uint64_t, uint8_t);
 155 static void xhci_endpoint_doorbell(struct usb_xfer *);
 156 static void xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val);
 157 static uint32_t xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr);
 158 static void xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val);
 159 #ifdef USB_DEBUG
 160 static uint64_t xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr);
 161 #endif
 162
 163 extern struct usb_bus_methods xhci_bus_methods;
 164
 165 #ifdef USB_DEBUG
 166 static void
 167 xhci_dump_trb(struct xhci_trb *trb)
 168 {
 169         DPRINTFN(5, "trb = %p\n", trb);
 170         DPRINTFN(5, "qwTrb0 = 0x%016llx\n", (long long)le64toh(trb->qwTrb0));
 171         DPRINTFN(5, "dwTrb2 = 0x%08x\n", le32toh(trb->dwTrb2));
 172         DPRINTFN(5, "dwTrb3 = 0x%08x\n", le32toh(trb->dwTrb3));
 173 }
 174
 175 static void
 176 xhci_dump_endpoint(struct xhci_softc *sc, struct xhci_endp_ctx *pep)
 177 {
 178         DPRINTFN(5, "pep = %p\n", pep);
 179         DPRINTFN(5, "dwEpCtx0=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx0));
 180         DPRINTFN(5, "dwEpCtx1=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx1));
 181         DPRINTFN(5, "qwEpCtx2=0x%016llx\n", (long long)xhci_ctx_get_le64(sc, &pep->qwEpCtx2));
 182         DPRINTFN(5, "dwEpCtx4=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx4));
 183         DPRINTFN(5, "dwEpCtx5=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx5));
 184         DPRINTFN(5, "dwEpCtx6=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx6));
 185         DPRINTFN(5, "dwEpCtx7=0x%08x\n", xhci_ctx_get_le32(sc, &pep->dwEpCtx7));
 186 }
 187
 188 static void
 189 xhci_dump_device(struct xhci_softc *sc, struct xhci_slot_ctx *psl)
 190 {
 191         DPRINTFN(5, "psl = %p\n", psl);
 192         DPRINTFN(5, "dwSctx0=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx0));
 193         DPRINTFN(5, "dwSctx1=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx1));
 194         DPRINTFN(5, "dwSctx2=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx2));
 195         DPRINTFN(5, "dwSctx3=0x%08x\n", xhci_ctx_get_le32(sc, &psl->dwSctx3));
 196 }
 197 #endif
 198
 199 uint8_t
 200 xhci_use_polling(void)
 201 {
 202 #ifdef USB_DEBUG
 203         return (xhcipolling != 0);
 204 #else
 205         return (0);
 206 #endif
 207 }
 208
 209 static void
 210 xhci_iterate_hw_softc(struct usb_bus *bus, usb_bus_mem_sub_cb_t *cb)
 211 {
 212         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 213         uint8_t i;
 214
 215         cb(bus, &sc->sc_hw.root_pc, &sc->sc_hw.root_pg,
 216            sizeof(struct xhci_hw_root), XHCI_PAGE_SIZE);
 217
 218         cb(bus, &sc->sc_hw.ctx_pc, &sc->sc_hw.ctx_pg,
 219            sizeof(struct xhci_dev_ctx_addr), XHCI_PAGE_SIZE);
 220
 221         for (i = 0; i != XHCI_MAX_SCRATCHPADS; i++) {
 222                 cb(bus, &sc->sc_hw.scratch_pc[i], &sc->sc_hw.scratch_pg[i],
 223                     XHCI_PAGE_SIZE, XHCI_PAGE_SIZE);
 224         }
 225 }
 226
 227 static void
 228 xhci_ctx_set_le32(struct xhci_softc *sc, volatile uint32_t *ptr, uint32_t val)
 229 {
 230         if (sc->sc_ctx_is_64_byte) {
 231                 uint32_t offset;
 232                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 233                 /* all contexts are initially 32-bytes */
 234                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 235                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 236         }
 237         *ptr = htole32(val);
 238 }
 239
 240 static uint32_t
 241 xhci_ctx_get_le32(struct xhci_softc *sc, volatile uint32_t *ptr)
 242 {
 243         if (sc->sc_ctx_is_64_byte) {
 244                 uint32_t offset;
 245                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 246                 /* all contexts are initially 32-bytes */
 247                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 248                 ptr = (volatile uint32_t *)(((volatile uint8_t *)ptr) + offset);
 249         }
 250         return (le32toh(*ptr));
 251 }
 252
 253 static void
 254 xhci_ctx_set_le64(struct xhci_softc *sc, volatile uint64_t *ptr, uint64_t val)
 255 {
 256         if (sc->sc_ctx_is_64_byte) {
 257                 uint32_t offset;
 258                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 259                 /* all contexts are initially 32-bytes */
 260                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 261                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 262         }
 263         *ptr = htole64(val);
 264 }
 265
 266 #ifdef USB_DEBUG
 267 static uint64_t
 268 xhci_ctx_get_le64(struct xhci_softc *sc, volatile uint64_t *ptr)
 269 {
 270         if (sc->sc_ctx_is_64_byte) {
 271                 uint32_t offset;
 272                 /* exploit the fact that our structures are XHCI_PAGE_SIZE aligned */
 273                 /* all contexts are initially 32-bytes */
 274                 offset = ((uintptr_t)ptr) & ((XHCI_PAGE_SIZE - 1) & ~(31U));
 275                 ptr = (volatile uint64_t *)(((volatile uint8_t *)ptr) + offset);
 276         }
 277         return (le64toh(*ptr));
 278 }
 279 #endif
 280
 281 static int
 282 xhci_reset_command_queue_locked(struct xhci_softc *sc)
 283 {
 284         struct usb_page_search buf_res;
 285         struct xhci_hw_root *phwr;
 286         uint64_t addr;
 287         uint32_t temp;
 288
 289         DPRINTF("\n");
 290
 291         temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 292         if (temp & XHCI_CRCR_LO_CRR) {
 293                 DPRINTF("Command ring running\n");
 294                 temp &= ~(XHCI_CRCR_LO_CS | XHCI_CRCR_LO_CA);
 295
 296                 /*
 297                  * Try to abort the last command as per section
 298                  * 4.6.1.2 "Aborting a Command" of the XHCI
 299                  * specification:
 300                  */
 301
 302                 /* stop and cancel */
 303                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CS);
 304                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 305
 306                 XWRITE4(sc, oper, XHCI_CRCR_LO, temp | XHCI_CRCR_LO_CA);
 307                 XWRITE4(sc, oper, XHCI_CRCR_HI, 0);
 308
 309                 /* wait 250ms */
 310                 usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 4);
 311
 312                 /* check if command ring is still running */
 313                 temp = XREAD4(sc, oper, XHCI_CRCR_LO);
 314                 if (temp & XHCI_CRCR_LO_CRR) {
 315                         DPRINTF("Comand ring still running\n");
 316                         return (USB_ERR_IOERROR);
 317                 }
 318         }
 319
 320         /* reset command ring */
 321         sc->sc_command_ccs = 1;
 322         sc->sc_command_idx = 0;
 323
 324         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 325
 326         /* set up command ring control base address */
 327         addr = buf_res.physaddr;
 328         phwr = buf_res.buffer;
 329         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 330
 331         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 332
 333         memset(phwr->hwr_commands, 0, sizeof(phwr->hwr_commands));
 334         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 335
 336         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
 337
 338         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 339         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 340
 341         return (0);
 342 }
 343
 344 usb_error_t
 345 xhci_start_controller(struct xhci_softc *sc)
 346 {
 347         struct usb_page_search buf_res;
 348         struct xhci_hw_root *phwr;
 349         struct xhci_dev_ctx_addr *pdctxa;
 350         uint64_t addr;
 351         uint32_t temp;
 352         uint16_t i;
 353
 354         DPRINTF("\n");
 355
 356         sc->sc_event_ccs = 1;
 357         sc->sc_event_idx = 0;
 358         sc->sc_command_ccs = 1;
 359         sc->sc_command_idx = 0;
 360
 361         /* Reset controller */
 362         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_HCRST);
 363
 364         for (i = 0; i != 100; i++) {
 365                 usb_pause_mtx(NULL, hz / 100);
 366                 temp = (XREAD4(sc, oper, XHCI_USBCMD) & XHCI_CMD_HCRST) |
 367                     (XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_CNR);
 368                 if (!temp)
 369                         break;
 370         }
 371
 372         if (temp) {
 373                 device_printf(sc->sc_bus.parent, "Controller "
 374                     "reset timeout.\n");
 375                 return (USB_ERR_IOERROR);
 376         }
 377
 378         if (!(XREAD4(sc, oper, XHCI_PAGESIZE) & XHCI_PAGESIZE_4K)) {
 379                 device_printf(sc->sc_bus.parent, "Controller does "
 380                     "not support 4K page size.\n");
 381                 return (USB_ERR_IOERROR);
 382         }
 383
 384         temp = XREAD4(sc, capa, XHCI_HCSPARAMS1);
 385
 386         i = XHCI_HCS1_N_PORTS(temp);
 387
 388         if (i == 0) {
 389                 device_printf(sc->sc_bus.parent, "Invalid number "
 390                     "of ports: %u\n", i);
 391                 return (USB_ERR_IOERROR);
 392         }
 393
 394         sc->sc_noport = i;
 395         sc->sc_noslot = XHCI_HCS1_DEVSLOT_MAX(temp);
 396
 397         if (sc->sc_noslot > XHCI_MAX_DEVICES)
 398                 sc->sc_noslot = XHCI_MAX_DEVICES;
 399
 400         /* set up number of device slots */
 401
 402         DPRINTF("CONFIG=0x%08x -> 0x%08x\n",
 403             XREAD4(sc, oper, XHCI_CONFIG), sc->sc_noslot);
 404
 405         XWRITE4(sc, oper, XHCI_CONFIG, sc->sc_noslot);
 406
 407         DPRINTF("Max slots: %u\n", sc->sc_noslot);
 408
 409         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 410
 411         sc->sc_noscratch = XHCI_HCS2_SPB_MAX(temp);
 412
 413         if (sc->sc_noscratch > XHCI_MAX_SCRATCHPADS) {
 414                 device_printf(sc->sc_bus.parent, "XHCI request "
 415                     "too many scratchpads\n");
 416                 return (USB_ERR_NOMEM);
 417         }
 418
 419         DPRINTF("Max scratch: %u\n", sc->sc_noscratch);
 420
 421         temp = XREAD4(sc, capa, XHCI_HCSPARAMS3);
 422
 423         sc->sc_exit_lat_max = XHCI_HCS3_U1_DEL(temp) +
 424             XHCI_HCS3_U2_DEL(temp) + 250 /* us */;
 425
 426         temp = XREAD4(sc, oper, XHCI_USBSTS);
 427
 428         /* clear interrupts */
 429         XWRITE4(sc, oper, XHCI_USBSTS, temp);
 430         /* disable all device notifications */
 431         XWRITE4(sc, oper, XHCI_DNCTRL, 0);
 432
 433         /* set up device context base address */
 434         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
 435         pdctxa = buf_res.buffer;
 436         memset(pdctxa, 0, sizeof(*pdctxa));
 437
 438         addr = buf_res.physaddr;
 439         addr += (uintptr_t)&((struct xhci_dev_ctx_addr *)0)->qwSpBufPtr[0];
 440
 441         /* slot 0 points to the table of scratchpad pointers */
 442         pdctxa->qwBaaDevCtxAddr[0] = htole64(addr);
 443
 444         for (i = 0; i != sc->sc_noscratch; i++) {
 445                 struct usb_page_search buf_scp;
 446                 usbd_get_page(&sc->sc_hw.scratch_pc[i], 0, &buf_scp);
 447                 pdctxa->qwSpBufPtr[i] = htole64((uint64_t)buf_scp.physaddr);
 448         }
 449
 450         addr = buf_res.physaddr;
 451
 452         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 453         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 454         XWRITE4(sc, oper, XHCI_DCBAAP_LO, (uint32_t)addr);
 455         XWRITE4(sc, oper, XHCI_DCBAAP_HI, (uint32_t)(addr >> 32));
 456
 457         /* Setup event table size */
 458
 459         temp = XREAD4(sc, capa, XHCI_HCSPARAMS2);
 460
 461         DPRINTF("HCS2=0x%08x\n", temp);
 462
 463         temp = XHCI_HCS2_ERST_MAX(temp);
 464         temp = 1U << temp;
 465         if (temp > XHCI_MAX_RSEG)
 466                 temp = XHCI_MAX_RSEG;
 467
 468         sc->sc_erst_max = temp;
 469
 470         DPRINTF("ERSTSZ=0x%08x -> 0x%08x\n",
 471             XREAD4(sc, runt, XHCI_ERSTSZ(0)), temp);
 472
 473         XWRITE4(sc, runt, XHCI_ERSTSZ(0), XHCI_ERSTS_SET(temp));
 474
 475         /* Check if we should use the default IMOD value */
 476         if (sc->sc_imod_default == 0)
 477                 sc->sc_imod_default = XHCI_IMOD_DEFAULT;
 478
 479         /* Setup interrupt rate */
 480         XWRITE4(sc, runt, XHCI_IMOD(0), sc->sc_imod_default);
 481
 482         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
 483
 484         phwr = buf_res.buffer;
 485         addr = buf_res.physaddr;
 486         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[0];
 487
 488         /* reset hardware root structure */
 489         memset(phwr, 0, sizeof(*phwr));
 490
 491         phwr->hwr_ring_seg[0].qwEvrsTablePtr = htole64(addr);
 492         phwr->hwr_ring_seg[0].dwEvrsTableSize = htole32(XHCI_MAX_EVENTS);
 493
 494         DPRINTF("ERDP(0)=0x%016llx\n", (unsigned long long)addr);
 495
 496         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
 497         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
 498
 499         addr = buf_res.physaddr;
 500
 501         DPRINTF("ERSTBA(0)=0x%016llx\n", (unsigned long long)addr);
 502
 503         XWRITE4(sc, runt, XHCI_ERSTBA_LO(0), (uint32_t)addr);
 504         XWRITE4(sc, runt, XHCI_ERSTBA_HI(0), (uint32_t)(addr >> 32));
 505
 506         /* Setup interrupter registers */
 507
 508         temp = XREAD4(sc, runt, XHCI_IMAN(0));
 509         temp |= XHCI_IMAN_INTR_ENA;
 510         XWRITE4(sc, runt, XHCI_IMAN(0), temp);
 511
 512         /* set up command ring control base address */
 513         addr = buf_res.physaddr;
 514         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[0];
 515
 516         DPRINTF("CRCR=0x%016llx\n", (unsigned long long)addr);
 517
 518         XWRITE4(sc, oper, XHCI_CRCR_LO, ((uint32_t)addr) | XHCI_CRCR_LO_RCS);
 519         XWRITE4(sc, oper, XHCI_CRCR_HI, (uint32_t)(addr >> 32));
 520
 521         phwr->hwr_commands[XHCI_MAX_COMMANDS - 1].qwTrb0 = htole64(addr);
 522
 523         usb_bus_mem_flush_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 524
 525         /* Go! */
 526         XWRITE4(sc, oper, XHCI_USBCMD, XHCI_CMD_RS |
 527             XHCI_CMD_INTE | XHCI_CMD_HSEE);
 528
 529         for (i = 0; i != 100; i++) {
 530                 usb_pause_mtx(NULL, hz / 100);
 531                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 532                 if (!temp)
 533                         break;
 534         }
 535         if (temp) {
 536                 XWRITE4(sc, oper, XHCI_USBCMD, 0);
 537                 device_printf(sc->sc_bus.parent, "Run timeout.\n");
 538                 return (USB_ERR_IOERROR);
 539         }
 540
 541         /* catch any lost interrupts */
 542         xhci_do_poll(&sc->sc_bus);
 543
 544         if (sc->sc_port_route != NULL) {
 545                 /* Route all ports to the XHCI by default */
 546                 sc->sc_port_route(sc->sc_bus.parent,
 547                     ~xhciroute, xhciroute);
 548         }
 549         return (0);
 550 }
 551
 552 usb_error_t
 553 xhci_halt_controller(struct xhci_softc *sc)
 554 {
 555         uint32_t temp;
 556         uint16_t i;
 557
 558         DPRINTF("\n");
 559
 560         sc->sc_capa_off = 0;
 561         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 562         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0xF;
 563         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 564
 565         /* Halt controller */
 566         XWRITE4(sc, oper, XHCI_USBCMD, 0);
 567
 568         for (i = 0; i != 100; i++) {
 569                 usb_pause_mtx(NULL, hz / 100);
 570                 temp = XREAD4(sc, oper, XHCI_USBSTS) & XHCI_STS_HCH;
 571                 if (temp)
 572                         break;
 573         }
 574
 575         if (!temp) {
 576                 device_printf(sc->sc_bus.parent, "Controller halt timeout.\n");
 577                 return (USB_ERR_IOERROR);
 578         }
 579         return (0);
 580 }
 581
 582 usb_error_t
 583 xhci_init(struct xhci_softc *sc, device_t self)
 584 {
 585         uint32_t temp;
 586
 587         DPRINTF("\n");
 588
 589         /* initialize some bus fields */
 590         sc->sc_bus.parent = self;
 591
 592         /* set the bus revision */
 593         sc->sc_bus.usbrev = USB_REV_3_0;
 594
 595         /* set up the bus struct */
 596         sc->sc_bus.methods = &xhci_bus_methods;
 597
 598         /* set up devices array */
 599         sc->sc_bus.devices = sc->sc_devices;
 600         sc->sc_bus.devices_max = XHCI_MAX_DEVICES;
 601
 602         /* set default cycle state in case of early interrupts */
 603         sc->sc_event_ccs = 1;
 604         sc->sc_command_ccs = 1;
 605
 606         /* set up bus space offsets */
 607         sc->sc_capa_off = 0;
 608         sc->sc_oper_off = XREAD1(sc, capa, XHCI_CAPLENGTH);
 609         sc->sc_runt_off = XREAD4(sc, capa, XHCI_RTSOFF) & ~0x1F;
 610         sc->sc_door_off = XREAD4(sc, capa, XHCI_DBOFF) & ~0x3;
 611
 612         DPRINTF("CAPLENGTH=0x%x\n", sc->sc_oper_off);
 613         DPRINTF("RUNTIMEOFFSET=0x%x\n", sc->sc_runt_off);
 614         DPRINTF("DOOROFFSET=0x%x\n", sc->sc_door_off);
 615
 616         DPRINTF("xHCI version = 0x%04x\n", XREAD2(sc, capa, XHCI_HCIVERSION));
 617
 618         temp = XREAD4(sc, capa, XHCI_HCSPARAMS0);
 619
 620         DPRINTF("HCS0 = 0x%08x\n", temp);
 621
 622         /* set up context size */
 623         if (XHCI_HCS0_CSZ(temp)) {
 624                 sc->sc_ctx_is_64_byte = 1;
 625         } else {
 626                 sc->sc_ctx_is_64_byte = 0;
 627         }
 628
 629         /* get DMA bits */
 630         sc->sc_bus.dma_bits = XHCI_HCS0_AC64(temp) ? 64 : 32;
 631
 632         device_printf(self, "%d bytes context size, %d-bit DMA\n",
 633             sc->sc_ctx_is_64_byte ? 64 : 32, (int)sc->sc_bus.dma_bits);
 634
 635         /* get all DMA memory */
 636         if (usb_bus_mem_alloc_all(&sc->sc_bus,
 637             USB_GET_DMA_TAG(self), &xhci_iterate_hw_softc)) {
 638                 return (ENOMEM);
 639         }
 640
 641         /* set up command queue mutex and condition varible */
 642         cv_init(&sc->sc_cmd_cv, "CMDQ");
 643         sx_init(&sc->sc_cmd_sx, "CMDQ lock");
 644
 645         sc->sc_config_msg[0].hdr.pm_callback = &xhci_configure_msg;
 646         sc->sc_config_msg[0].bus = &sc->sc_bus;
 647         sc->sc_config_msg[1].hdr.pm_callback = &xhci_configure_msg;
 648         sc->sc_config_msg[1].bus = &sc->sc_bus;
 649
 650         return (0);
 651 }
 652
 653 void
 654 xhci_uninit(struct xhci_softc *sc)
 655 {
 656         /*
 657          * NOTE: At this point the control transfer process is gone
 658          * and "xhci_configure_msg" is no longer called. Consequently
 659          * waiting for the configuration messages to complete is not
 660          * needed.
 661          */
 662         usb_bus_mem_free_all(&sc->sc_bus, &xhci_iterate_hw_softc);
 663
 664         cv_destroy(&sc->sc_cmd_cv);
 665         sx_destroy(&sc->sc_cmd_sx);
 666 }
 667
 668 static void
 669 xhci_set_hw_power_sleep(struct usb_bus *bus, uint32_t state)
 670 {
 671         struct xhci_softc *sc = XHCI_BUS2SC(bus);
 672
 673         switch (state) {
 674         case USB_HW_POWER_SUSPEND:
 675                 DPRINTF("Stopping the XHCI\n");
 676                 xhci_halt_controller(sc);
 677                 break;
 678         case USB_HW_POWER_SHUTDOWN:
 679                 DPRINTF("Stopping the XHCI\n");
 680                 xhci_halt_controller(sc);
 681                 break;
 682         case USB_HW_POWER_RESUME:
 683                 DPRINTF("Starting the XHCI\n");
 684                 xhci_start_controller(sc);
 685                 break;
 686         default:
 687                 break;
 688         }
 689 }
 690
 691 static usb_error_t
 692 xhci_generic_done_sub(struct usb_xfer *xfer)
 693 {
 694         struct xhci_td *td;
 695         struct xhci_td *td_alt_next;
 696         uint32_t len;
 697         uint8_t status;
 698
 699         td = xfer->td_transfer_cache;
 700         td_alt_next = td->alt_next;
 701
 702         if (xfer->aframes != xfer->nframes)
 703                 usbd_xfer_set_frame_len(xfer, xfer->aframes, 0);
 704
 705         while (1) {
 706
 707                 usb_pc_cpu_invalidate(td->page_cache);
 708
 709                 status = td->status;
 710                 len = td->remainder;
 711
 712                 DPRINTFN(4, "xfer=%p[%u/%u] rem=%u/%u status=%u\n",
 713                     xfer, (unsigned int)xfer->aframes,
 714                     (unsigned int)xfer->nframes,
 715                     (unsigned int)len, (unsigned int)td->len,
 716                     (unsigned int)status);
 717
 718                 /*
 719                  * Verify the status length and
 720                  * add the length to "frlengths[]":
 721                  */
 722                 if (len > td->len) {
 723                         /* should not happen */
 724                         DPRINTF("Invalid status length, "
 725                             "0x%04x/0x%04x bytes\n", len, td->len);
 726                         status = XHCI_TRB_ERROR_LENGTH;
 727                 } else if (xfer->aframes != xfer->nframes) {
 728                         xfer->frlengths[xfer->aframes] += td->len - len;
 729                 }
 730                 /* Check for last transfer */
 731                 if (((void *)td) == xfer->td_transfer_last) {
 732                         td = NULL;
 733                         break;
 734                 }
 735                 /* Check for transfer error */
 736                 if (status != XHCI_TRB_ERROR_SHORT_PKT &&
 737                     status != XHCI_TRB_ERROR_SUCCESS) {
 738                         /* the transfer is finished */
 739                         td = NULL;
 740                         break;
 741                 }
 742                 /* Check for short transfer */
 743                 if (len > 0) {
 744                         if (xfer->flags_int.short_frames_ok ||
 745                             xfer->flags_int.isochronous_xfr ||
 746                             xfer->flags_int.control_xfr) {
 747                                 /* follow alt next */
 748                                 td = td->alt_next;
 749                         } else {
 750                                 /* the transfer is finished */
 751                                 td = NULL;
 752                         }
 753                         break;
 754                 }
 755                 td = td->obj_next;
 756
 757                 if (td->alt_next != td_alt_next) {
 758                         /* this USB frame is complete */
 759                         break;
 760                 }
 761         }
 762
 763         /* update transfer cache */
 764
 765         xfer->td_transfer_cache = td;
 766
 767         return ((status == XHCI_TRB_ERROR_STALL) ? USB_ERR_STALLED :
 768             (status != XHCI_TRB_ERROR_SHORT_PKT &&
 769             status != XHCI_TRB_ERROR_SUCCESS) ? USB_ERR_IOERROR :
 770             USB_ERR_NORMAL_COMPLETION);
 771 }
 772
 773 static void
 774 xhci_generic_done(struct usb_xfer *xfer)
 775 {
 776         usb_error_t err = 0;
 777
 778         DPRINTFN(13, "xfer=%p endpoint=%p transfer done\n",
 779             xfer, xfer->endpoint);
 780
 781         /* reset scanner */
 782
 783         xfer->td_transfer_cache = xfer->td_transfer_first;
 784
 785         if (xfer->flags_int.control_xfr) {
 786
 787                 if (xfer->flags_int.control_hdr)
 788                         err = xhci_generic_done_sub(xfer);
 789
 790                 xfer->aframes = 1;
 791
 792                 if (xfer->td_transfer_cache == NULL)
 793                         goto done;
 794         }
 795
 796         while (xfer->aframes != xfer->nframes) {
 797
 798                 err = xhci_generic_done_sub(xfer);
 799                 xfer->aframes++;
 800
 801                 if (xfer->td_transfer_cache == NULL)
 802                         goto done;
 803         }
 804
 805         if (xfer->flags_int.control_xfr &&
 806             !xfer->flags_int.control_act)
 807                 err = xhci_generic_done_sub(xfer);
 808 done:
 809         /* transfer is complete */
 810         xhci_device_done(xfer, err);
 811 }
 812
 813 static void
 814 xhci_activate_transfer(struct usb_xfer *xfer)
 815 {
 816         struct xhci_td *td;
 817
 818         td = xfer->td_transfer_cache;
 819
 820         usb_pc_cpu_invalidate(td->page_cache);
 821
 822         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 823
 824                 /* activate the transfer */
 825
 826                 td->td_trb[0].dwTrb3 |= htole32(XHCI_TRB_3_CYCLE_BIT);
 827                 usb_pc_cpu_flush(td->page_cache);
 828
 829                 xhci_endpoint_doorbell(xfer);
 830         }
 831 }
 832
 833 static void
 834 xhci_skip_transfer(struct usb_xfer *xfer)
 835 {
 836         struct xhci_td *td;
 837         struct xhci_td *td_last;
 838
 839         td = xfer->td_transfer_cache;
 840         td_last = xfer->td_transfer_last;
 841
 842         td = td->alt_next;
 843
 844         usb_pc_cpu_invalidate(td->page_cache);
 845
 846         if (!(td->td_trb[0].dwTrb3 & htole32(XHCI_TRB_3_CYCLE_BIT))) {
 847
 848                 usb_pc_cpu_invalidate(td_last->page_cache);
 849
 850                 /* copy LINK TRB to current waiting location */
 851
 852                 td->td_trb[0].qwTrb0 = td_last->td_trb[td_last->ntrb].qwTrb0;
 853                 td->td_trb[0].dwTrb2 = td_last->td_trb[td_last->ntrb].dwTrb2;
 854                 usb_pc_cpu_flush(td->page_cache);
 855
 856                 td->td_trb[0].dwTrb3 = td_last->td_trb[td_last->ntrb].dwTrb3;
 857                 usb_pc_cpu_flush(td->page_cache);
 858
 859                 xhci_endpoint_doorbell(xfer);
 860         }
 861 }
 862
 863 /*------------------------------------------------------------------------*
 864  *      xhci_check_transfer
 865  *------------------------------------------------------------------------*/
 866 static void
 867 xhci_check_transfer(struct xhci_softc *sc, struct xhci_trb *trb)
 868 {
 869         struct xhci_endpoint_ext *pepext;
 870         int64_t offset;
 871         uint64_t td_event;
 872         uint32_t temp;
 873         uint32_t remainder;
 874         uint16_t stream_id;
 875         uint16_t i;
 876         uint8_t status;
 877         uint8_t halted;
 878         uint8_t epno;
 879         uint8_t index;
 880
 881         /* decode TRB */
 882         td_event = le64toh(trb->qwTrb0);
 883         temp = le32toh(trb->dwTrb2);
 884
 885         remainder = XHCI_TRB_2_REM_GET(temp);
 886         status = XHCI_TRB_2_ERROR_GET(temp);
 887         stream_id = XHCI_TRB_2_STREAM_GET(temp);
 888
 889         temp = le32toh(trb->dwTrb3);
 890         epno = XHCI_TRB_3_EP_GET(temp);
 891         index = XHCI_TRB_3_SLOT_GET(temp);
 892
 893         /* check if error means halted */
 894         halted = (status != XHCI_TRB_ERROR_SHORT_PKT &&
 895             status != XHCI_TRB_ERROR_SUCCESS);
 896
 897         DPRINTF("slot=%u epno=%u stream=%u remainder=%u status=%u\n",
 898             index, epno, stream_id, remainder, status);
 899
 900         if (index > sc->sc_noslot) {
 901                 DPRINTF("Invalid slot.\n");
 902                 return;
 903         }
 904
 905         if ((epno == 0) || (epno >= XHCI_MAX_ENDPOINTS)) {
 906                 DPRINTF("Invalid endpoint.\n");
 907                 return;
 908         }
 909
 910         pepext = &sc->sc_hw.devs[index].endp[epno];
 911
 912         if (pepext->trb_ep_mode != USB_EP_MODE_STREAMS) {
 913                 stream_id = 0;
 914                 DPRINTF("stream_id=0\n");
 915         } else if (stream_id >= XHCI_MAX_STREAMS) {
 916                 DPRINTF("Invalid stream ID.\n");
 917                 return;
 918         }
 919
 920         /* try to find the USB transfer that generated the event */
 921         for (i = 0; i != (XHCI_MAX_TRANSFERS - 1); i++) {
 922                 struct usb_xfer *xfer;
 923                 struct xhci_td *td;
 924
 925                 xfer = pepext->xfer[i + (XHCI_MAX_TRANSFERS * stream_id)];
 926                 if (xfer == NULL)
 927                         continue;
 928
 929                 td = xfer->td_transfer_cache;
 930
 931                 DPRINTFN(5, "Checking if 0x%016llx == (0x%016llx .. 0x%016llx)\n",
 932                         (long long)td_event,
 933                         (long long)td->td_self,
 934                         (long long)td->td_self + sizeof(td->td_trb));
 935
 936                 /*
 937                  * NOTE: Some XHCI implementations might not trigger
 938                  * an event on the last LINK TRB so we need to
 939                  * consider both the last and second last event
 940                  * address as conditions for a successful transfer.
 941                  *
 942                  * NOTE: We assume that the XHCI will only trigger one
 943                  * event per chain of TRBs.
 944                  */
 945
 946                 offset = td_event - td->td_self;
 947
 948                 if (offset >= 0 &&
 949                     offset < (int64_t)sizeof(td->td_trb)) {
 950
 951                         usb_pc_cpu_invalidate(td->page_cache);
 952
 953                         /* compute rest of remainder, if any */
 954                         for (i = (offset / 16) + 1; i < td->ntrb; i++) {
 955                                 temp = le32toh(td->td_trb[i].dwTrb2);
 956                                 remainder += XHCI_TRB_2_BYTES_GET(temp);
 957                         }
 958
 959                         DPRINTFN(5, "New remainder: %u\n", remainder);
 960
 961                         /* clear isochronous transfer errors */
 962                         if (xfer->flags_int.isochronous_xfr) {
 963                                 if (halted) {
 964                                         halted = 0;
 965                                         status = XHCI_TRB_ERROR_SUCCESS;
 966                                         remainder = td->len;
 967                                 }
 968                         }
 969
 970                         /* "td->remainder" is verified later */
 971                         td->remainder = remainder;
 972                         td->status = status;
 973
 974                         usb_pc_cpu_flush(td->page_cache);
 975
 976                         /*
 977                          * 1) Last transfer descriptor makes the
 978                          * transfer done
 979                          */
 980                         if (((void *)td) == xfer->td_transfer_last) {
 981                                 DPRINTF("TD is last\n");
 982                                 xhci_generic_done(xfer);
 983                                 break;
 984                         }
 985
 986                         /*
 987                          * 2) Any kind of error makes the transfer
 988                          * done
 989                          */
 990                         if (halted) {
 991                                 DPRINTF("TD has I/O error\n");
 992                                 xhci_generic_done(xfer);
 993                                 break;
 994                         }
 995
 996                         /*
 997                          * 3) If there is no alternate next transfer,
 998                          * a short packet also makes the transfer done
 999                          */
1000                         if (td->remainder > 0) {
1001                                 if (td->alt_next == NULL) {
1002                                         DPRINTF(
1003                                             "short TD has no alternate next\n");
1004                                         xhci_generic_done(xfer);
1005                                         break;
1006                                 }
1007                                 DPRINTF("TD has short pkt\n");
1008                                 if (xfer->flags_int.short_frames_ok ||
1009                                     xfer->flags_int.isochronous_xfr ||
1010                                     xfer->flags_int.control_xfr) {
1011                                         /* follow the alt next */
1012                                         xfer->td_transfer_cache = td->alt_next;
1013                                         xhci_activate_transfer(xfer);
1014                                         break;
1015                                 }
1016                                 xhci_skip_transfer(xfer);
1017                                 xhci_generic_done(xfer);
1018                                 break;
1019                         }
1020
1021                         /*
1022                          * 4) Transfer complete - go to next TD
1023                          */
1024                         DPRINTF("Following next TD\n");
1025                         xfer->td_transfer_cache = td->obj_next;
1026                         xhci_activate_transfer(xfer);
1027                         break;          /* there should only be one match */
1028                 }
1029         }
1030 }
1031
1032 static int
1033 xhci_check_command(struct xhci_softc *sc, struct xhci_trb *trb)
1034 {
1035         if (sc->sc_cmd_addr == trb->qwTrb0) {
1036                 DPRINTF("Received command event\n");
1037                 sc->sc_cmd_result[0] = trb->dwTrb2;
1038                 sc->sc_cmd_result[1] = trb->dwTrb3;
1039                 cv_signal(&sc->sc_cmd_cv);
1040                 return (1);     /* command match */
1041         }
1042         return (0);
1043 }
1044
1045 static int
1046 xhci_interrupt_poll(struct xhci_softc *sc)
1047 {
1048         struct usb_page_search buf_res;
1049         struct xhci_hw_root *phwr;
1050         uint64_t addr;
1051         uint32_t temp;
1052         int retval = 0;
1053         uint16_t i;
1054         uint8_t event;
1055         uint8_t j;
1056         uint8_t k;
1057         uint8_t t;
1058
1059         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1060
1061         phwr = buf_res.buffer;
1062
1063         /* Receive any events */
1064
1065         usb_pc_cpu_invalidate(&sc->sc_hw.root_pc);
1066
1067         i = sc->sc_event_idx;
1068         j = sc->sc_event_ccs;
1069         t = 2;
1070
1071         while (1) {
1072
1073                 temp = le32toh(phwr->hwr_events[i].dwTrb3);
1074
1075                 k = (temp & XHCI_TRB_3_CYCLE_BIT) ? 1 : 0;
1076
1077                 if (j != k)
1078                         break;
1079
1080                 event = XHCI_TRB_3_TYPE_GET(temp);
1081
1082                 DPRINTFN(10, "event[%u] = %u (0x%016llx 0x%08lx 0x%08lx)\n",
1083                     i, event, (long long)le64toh(phwr->hwr_events[i].qwTrb0),
1084                     (long)le32toh(phwr->hwr_events[i].dwTrb2),
1085                     (long)le32toh(phwr->hwr_events[i].dwTrb3));
1086
1087                 switch (event) {
1088                 case XHCI_TRB_EVENT_TRANSFER:
1089                         xhci_check_transfer(sc, &phwr->hwr_events[i]);
1090                         break;
1091                 case XHCI_TRB_EVENT_CMD_COMPLETE:
1092                         retval |= xhci_check_command(sc, &phwr->hwr_events[i]);
1093                         break;
1094                 default:
1095                         DPRINTF("Unhandled event = %u\n", event);
1096                         break;
1097                 }
1098
1099                 i++;
1100
1101                 if (i == XHCI_MAX_EVENTS) {
1102                         i = 0;
1103                         j ^= 1;
1104
1105                         /* check for timeout */
1106                         if (!--t)
1107                                 break;
1108                 }
1109         }
1110
1111         sc->sc_event_idx = i;
1112         sc->sc_event_ccs = j;
1113
1114         /*
1115          * NOTE: The Event Ring Dequeue Pointer Register is 64-bit
1116          * latched. That means to activate the register we need to
1117          * write both the low and high double word of the 64-bit
1118          * register.
1119          */
1120
1121         addr = buf_res.physaddr;
1122         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_events[i];
1123
1124         /* try to clear busy bit */
1125         addr |= XHCI_ERDP_LO_BUSY;
1126
1127         XWRITE4(sc, runt, XHCI_ERDP_LO(0), (uint32_t)addr);
1128         XWRITE4(sc, runt, XHCI_ERDP_HI(0), (uint32_t)(addr >> 32));
1129
1130         return (retval);
1131 }
1132
1133 static usb_error_t
1134 xhci_do_command(struct xhci_softc *sc, struct xhci_trb *trb,
1135     uint16_t timeout_ms)
1136 {
1137         struct usb_page_search buf_res;
1138         struct xhci_hw_root *phwr;
1139         uint64_t addr;
1140         uint32_t temp;
1141         uint8_t i;
1142         uint8_t j;
1143         uint8_t timeout = 0;
1144         int err;
1145
1146         XHCI_CMD_ASSERT_LOCKED(sc);
1147
1148         /* get hardware root structure */
1149
1150         usbd_get_page(&sc->sc_hw.root_pc, 0, &buf_res);
1151
1152         phwr = buf_res.buffer;
1153
1154         /* Queue command */
1155
1156         USB_BUS_LOCK(&sc->sc_bus);
1157 retry:
1158         i = sc->sc_command_idx;
1159         j = sc->sc_command_ccs;
1160
1161         DPRINTFN(10, "command[%u] = %u (0x%016llx, 0x%08lx, 0x%08lx)\n",
1162             i, XHCI_TRB_3_TYPE_GET(le32toh(trb->dwTrb3)),
1163             (long long)le64toh(trb->qwTrb0),
1164             (long)le32toh(trb->dwTrb2),
1165             (long)le32toh(trb->dwTrb3));
1166
1167         phwr->hwr_commands[i].qwTrb0 = trb->qwTrb0;
1168         phwr->hwr_commands[i].dwTrb2 = trb->dwTrb2;
1169
1170         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1171
1172         temp = trb->dwTrb3;
1173
1174         if (j)
1175                 temp |= htole32(XHCI_TRB_3_CYCLE_BIT);
1176         else
1177                 temp &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1178
1179         temp &= ~htole32(XHCI_TRB_3_TC_BIT);
1180
1181         phwr->hwr_commands[i].dwTrb3 = temp;
1182
1183         usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1184
1185         addr = buf_res.physaddr;
1186         addr += (uintptr_t)&((struct xhci_hw_root *)0)->hwr_commands[i];
1187
1188         sc->sc_cmd_addr = htole64(addr);
1189
1190         i++;
1191
1192         if (i == (XHCI_MAX_COMMANDS - 1)) {
1193
1194                 if (j) {
1195                         temp = htole32(XHCI_TRB_3_TC_BIT |
1196                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1197                             XHCI_TRB_3_CYCLE_BIT);
1198                 } else {
1199                         temp = htole32(XHCI_TRB_3_TC_BIT |
1200                             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
1201                 }
1202
1203                 phwr->hwr_commands[i].dwTrb3 = temp;
1204
1205                 usb_pc_cpu_flush(&sc->sc_hw.root_pc);
1206
1207                 i = 0;
1208                 j ^= 1;
1209         }
1210
1211         sc->sc_command_idx = i;
1212         sc->sc_command_ccs = j;
1213
1214         XWRITE4(sc, door, XHCI_DOORBELL(0), 0);
1215
1216         err = cv_timedwait(&sc->sc_cmd_cv, &sc->sc_bus.bus_mtx,
1217             USB_MS_TO_TICKS(timeout_ms));
1218
1219         /*
1220          * In some error cases event interrupts are not generated.
1221          * Poll one time to see if the command has completed.
1222          */
1223         if (err != 0 && xhci_interrupt_poll(sc) != 0) {
1224                 DPRINTF("Command was completed when polling\n");
1225                 err = 0;
1226         }
1227         if (err != 0) {
1228                 DPRINTF("Command timeout!\n");
1229                 /*
1230                  * After some weeks of continuous operation, it has
1231                  * been observed that the ASMedia Technology, ASM1042
1232                  * SuperSpeed USB Host Controller can suddenly stop
1233                  * accepting commands via the command queue. Try to
1234                  * first reset the command queue. If that fails do a
1235                  * host controller reset.
1236                  */
1237                 if (timeout == 0 &&
1238                     xhci_reset_command_queue_locked(sc) == 0) {
1239                         temp = le32toh(trb->dwTrb3);
1240
1241                         /*
1242                          * Avoid infinite XHCI reset loops if the set
1243                          * address command fails to respond due to a
1244                          * non-enumerating device:
1245                          */
1246                         if (XHCI_TRB_3_TYPE_GET(temp) == XHCI_TRB_TYPE_ADDRESS_DEVICE &&
1247                             (temp & XHCI_TRB_3_BSR_BIT) == 0) {
1248                                 DPRINTF("Set address timeout\n");
1249                         } else {
1250                                 timeout = 1;
1251                                 goto retry;
1252                         }
1253                 } else {
1254                         DPRINTF("Controller reset!\n");
1255                         usb_bus_reset_async_locked(&sc->sc_bus);
1256                 }
1257                 err = USB_ERR_TIMEOUT;
1258                 trb->dwTrb2 = 0;
1259                 trb->dwTrb3 = 0;
1260         } else {
1261                 temp = le32toh(sc->sc_cmd_result[0]);
1262                 if (XHCI_TRB_2_ERROR_GET(temp) != XHCI_TRB_ERROR_SUCCESS)
1263                         err = USB_ERR_IOERROR;
1264
1265                 trb->dwTrb2 = sc->sc_cmd_result[0];
1266                 trb->dwTrb3 = sc->sc_cmd_result[1];
1267         }
1268
1269         USB_BUS_UNLOCK(&sc->sc_bus);
1270
1271         return (err);
1272 }
1273
1274 #if 0
1275 static usb_error_t
1276 xhci_cmd_nop(struct xhci_softc *sc)
1277 {
1278         struct xhci_trb trb;
1279         uint32_t temp;
1280
1281         DPRINTF("\n");
1282
1283         trb.qwTrb0 = 0;
1284         trb.dwTrb2 = 0;
1285         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NOOP);
1286
1287         trb.dwTrb3 = htole32(temp);
1288
1289         return (xhci_do_command(sc, &trb, 100 /* ms */));
1290 }
1291 #endif
1292
1293 static usb_error_t
1294 xhci_cmd_enable_slot(struct xhci_softc *sc, uint8_t *pslot)
1295 {
1296         struct xhci_trb trb;
1297         uint32_t temp;
1298         usb_error_t err;
1299
1300         DPRINTF("\n");
1301
1302         trb.qwTrb0 = 0;
1303         trb.dwTrb2 = 0;
1304         trb.dwTrb3 = htole32(XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ENABLE_SLOT));
1305
1306         err = xhci_do_command(sc, &trb, 100 /* ms */);
1307         if (err)
1308                 goto done;
1309
1310         temp = le32toh(trb.dwTrb3);
1311
1312         *pslot = XHCI_TRB_3_SLOT_GET(temp);
1313
1314 done:
1315         return (err);
1316 }
1317
1318 static usb_error_t
1319 xhci_cmd_disable_slot(struct xhci_softc *sc, uint8_t slot_id)
1320 {
1321         struct xhci_trb trb;
1322         uint32_t temp;
1323
1324         DPRINTF("\n");
1325
1326         trb.qwTrb0 = 0;
1327         trb.dwTrb2 = 0;
1328         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DISABLE_SLOT) |
1329             XHCI_TRB_3_SLOT_SET(slot_id);
1330
1331         trb.dwTrb3 = htole32(temp);
1332
1333         return (xhci_do_command(sc, &trb, 100 /* ms */));
1334 }
1335
1336 static usb_error_t
1337 xhci_cmd_set_address(struct xhci_softc *sc, uint64_t input_ctx,
1338     uint8_t bsr, uint8_t slot_id)
1339 {
1340         struct xhci_trb trb;
1341         uint32_t temp;
1342
1343         DPRINTF("\n");
1344
1345         trb.qwTrb0 = htole64(input_ctx);
1346         trb.dwTrb2 = 0;
1347         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ADDRESS_DEVICE) |
1348             XHCI_TRB_3_SLOT_SET(slot_id);
1349
1350         if (bsr)
1351                 temp |= XHCI_TRB_3_BSR_BIT;
1352
1353         trb.dwTrb3 = htole32(temp);
1354
1355         return (xhci_do_command(sc, &trb, 500 /* ms */));
1356 }
1357
1358 static usb_error_t
1359 xhci_set_address(struct usb_device *udev, struct mtx *mtx, uint16_t address)
1360 {
1361         struct usb_page_search buf_inp;
1362         struct usb_page_search buf_dev;
1363         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
1364         struct xhci_hw_dev *hdev;
1365         struct xhci_dev_ctx *pdev;
1366         struct xhci_endpoint_ext *pepext;
1367         uint32_t temp;
1368         uint16_t mps;
1369         usb_error_t err;
1370         uint8_t index;
1371
1372         /* the root HUB case is not handled here */
1373         if (udev->parent_hub == NULL)
1374                 return (USB_ERR_INVAL);
1375
1376         index = udev->controller_slot_id;
1377
1378         hdev =  &sc->sc_hw.devs[index];
1379
1380         if (mtx != NULL)
1381                 mtx_unlock(mtx);
1382
1383         XHCI_CMD_LOCK(sc);
1384
1385         switch (hdev->state) {
1386         case XHCI_ST_DEFAULT:
1387         case XHCI_ST_ENABLED:
1388
1389                 hdev->state = XHCI_ST_ENABLED;
1390
1391                 /* set configure mask to slot and EP0 */
1392                 xhci_configure_mask(udev, 3, 0);
1393
1394                 /* configure input slot context structure */
1395                 err = xhci_configure_device(udev);
1396
1397                 if (err != 0) {
1398                         DPRINTF("Could not configure device\n");
1399                         break;
1400                 }
1401
1402                 /* configure input endpoint context structure */
1403                 switch (udev->speed) {
1404                 case USB_SPEED_LOW:
1405                 case USB_SPEED_FULL:
1406                         mps = 8;
1407                         break;
1408                 case USB_SPEED_HIGH:
1409                         mps = 64;
1410                         break;
1411                 default:
1412                         mps = 512;
1413                         break;
1414                 }
1415
1416                 pepext = xhci_get_endpoint_ext(udev,
1417                     &udev->ctrl_ep_desc);
1418                 err = xhci_configure_endpoint(udev,
1419                     &udev->ctrl_ep_desc, pepext,
1420                     0, 1, 1, 0, mps, mps, USB_EP_MODE_DEFAULT);
1421
1422                 if (err != 0) {
1423                         DPRINTF("Could not configure default endpoint\n");
1424                         break;
1425                 }
1426
1427                 /* execute set address command */
1428                 usbd_get_page(&hdev->input_pc, 0, &buf_inp);
1429
1430                 err = xhci_cmd_set_address(sc, buf_inp.physaddr,
1431                     (address == 0), index);
1432
1433                 if (err != 0) {
1434                         temp = le32toh(sc->sc_cmd_result[0]);
1435                         if (address == 0 && sc->sc_port_route != NULL &&
1436                             XHCI_TRB_2_ERROR_GET(temp) ==
1437                             XHCI_TRB_ERROR_PARAMETER) {
1438                                 /* LynxPoint XHCI - ports are not switchable */
1439                                 /* Un-route all ports from the XHCI */
1440                                 sc->sc_port_route(sc->sc_bus.parent, 0, ~0);
1441                         }
1442                         DPRINTF("Could not set address "
1443                             "for slot %u.\n", index);
1444                         if (address != 0)
1445                                 break;
1446                 }
1447
1448                 /* update device address to new value */
1449
1450                 usbd_get_page(&hdev->device_pc, 0, &buf_dev);
1451                 pdev = buf_dev.buffer;
1452                 usb_pc_cpu_invalidate(&hdev->device_pc);
1453
1454                 temp = xhci_ctx_get_le32(sc, &pdev->ctx_slot.dwSctx3);
1455                 udev->address = XHCI_SCTX_3_DEV_ADDR_GET(temp);
1456
1457                 /* update device state to new value */
1458
1459                 if (address != 0)
1460                         hdev->state = XHCI_ST_ADDRESSED;
1461                 else
1462                         hdev->state = XHCI_ST_DEFAULT;
1463                 break;
1464
1465         default:
1466                 DPRINTF("Wrong state for set address.\n");
1467                 err = USB_ERR_IOERROR;
1468                 break;
1469         }
1470         XHCI_CMD_UNLOCK(sc);
1471
1472         if (mtx != NULL)
1473                 mtx_lock(mtx);
1474
1475         return (err);
1476 }
1477
1478 static usb_error_t
1479 xhci_cmd_configure_ep(struct xhci_softc *sc, uint64_t input_ctx,
1480     uint8_t deconfigure, uint8_t slot_id)
1481 {
1482         struct xhci_trb trb;
1483         uint32_t temp;
1484
1485         DPRINTF("\n");
1486
1487         trb.qwTrb0 = htole64(input_ctx);
1488         trb.dwTrb2 = 0;
1489         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_CONFIGURE_EP) |
1490             XHCI_TRB_3_SLOT_SET(slot_id);
1491
1492         if (deconfigure)
1493                 temp |= XHCI_TRB_3_DCEP_BIT;
1494
1495         trb.dwTrb3 = htole32(temp);
1496
1497         return (xhci_do_command(sc, &trb, 100 /* ms */));
1498 }
1499
1500 static usb_error_t
1501 xhci_cmd_evaluate_ctx(struct xhci_softc *sc, uint64_t input_ctx,
1502     uint8_t slot_id)
1503 {
1504         struct xhci_trb trb;
1505         uint32_t temp;
1506
1507         DPRINTF("\n");
1508
1509         trb.qwTrb0 = htole64(input_ctx);
1510         trb.dwTrb2 = 0;
1511         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_EVALUATE_CTX) |
1512             XHCI_TRB_3_SLOT_SET(slot_id);
1513         trb.dwTrb3 = htole32(temp);
1514
1515         return (xhci_do_command(sc, &trb, 100 /* ms */));
1516 }
1517
1518 static usb_error_t
1519 xhci_cmd_reset_ep(struct xhci_softc *sc, uint8_t preserve,
1520     uint8_t ep_id, uint8_t slot_id)
1521 {
1522         struct xhci_trb trb;
1523         uint32_t temp;
1524
1525         DPRINTF("\n");
1526
1527         trb.qwTrb0 = 0;
1528         trb.dwTrb2 = 0;
1529         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_EP) |
1530             XHCI_TRB_3_SLOT_SET(slot_id) |
1531             XHCI_TRB_3_EP_SET(ep_id);
1532
1533         if (preserve)
1534                 temp |= XHCI_TRB_3_PRSV_BIT;
1535
1536         trb.dwTrb3 = htole32(temp);
1537
1538         return (xhci_do_command(sc, &trb, 100 /* ms */));
1539 }
1540
1541 static usb_error_t
1542 xhci_cmd_set_tr_dequeue_ptr(struct xhci_softc *sc, uint64_t dequeue_ptr,
1543     uint16_t stream_id, uint8_t ep_id, uint8_t slot_id)
1544 {
1545         struct xhci_trb trb;
1546         uint32_t temp;
1547
1548         DPRINTF("\n");
1549
1550         trb.qwTrb0 = htole64(dequeue_ptr);
1551
1552         temp = XHCI_TRB_2_STREAM_SET(stream_id);
1553         trb.dwTrb2 = htole32(temp);
1554
1555         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SET_TR_DEQUEUE) |
1556             XHCI_TRB_3_SLOT_SET(slot_id) |
1557             XHCI_TRB_3_EP_SET(ep_id);
1558         trb.dwTrb3 = htole32(temp);
1559
1560         return (xhci_do_command(sc, &trb, 100 /* ms */));
1561 }
1562
1563 static usb_error_t
1564 xhci_cmd_stop_ep(struct xhci_softc *sc, uint8_t suspend,
1565     uint8_t ep_id, uint8_t slot_id)
1566 {
1567         struct xhci_trb trb;
1568         uint32_t temp;
1569
1570         DPRINTF("\n");
1571
1572         trb.qwTrb0 = 0;
1573         trb.dwTrb2 = 0;
1574         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STOP_EP) |
1575             XHCI_TRB_3_SLOT_SET(slot_id) |
1576             XHCI_TRB_3_EP_SET(ep_id);
1577
1578         if (suspend)
1579                 temp |= XHCI_TRB_3_SUSP_EP_BIT;
1580
1581         trb.dwTrb3 = htole32(temp);
1582
1583         return (xhci_do_command(sc, &trb, 100 /* ms */));
1584 }
1585
1586 static usb_error_t
1587 xhci_cmd_reset_dev(struct xhci_softc *sc, uint8_t slot_id)
1588 {
1589         struct xhci_trb trb;
1590         uint32_t temp;
1591
1592         DPRINTF("\n");
1593
1594         trb.qwTrb0 = 0;
1595         trb.dwTrb2 = 0;
1596         temp = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_RESET_DEVICE) |
1597             XHCI_TRB_3_SLOT_SET(slot_id);
1598
1599         trb.dwTrb3 = htole32(temp);
1600
1601         return (xhci_do_command(sc, &trb, 100 /* ms */));
1602 }
1603
1604 /*------------------------------------------------------------------------*
1605  *      xhci_interrupt - XHCI interrupt handler
1606  *------------------------------------------------------------------------*/
1607 void
1608 xhci_interrupt(struct xhci_softc *sc)
1609 {
1610         uint32_t status;
1611         uint32_t temp;
1612
1613         USB_BUS_LOCK(&sc->sc_bus);
1614
1615         status = XREAD4(sc, oper, XHCI_USBSTS);
1616
1617         /* acknowledge interrupts, if any */
1618         if (status != 0) {
1619                 XWRITE4(sc, oper, XHCI_USBSTS, status);
1620                 DPRINTFN(16, "real interrupt (status=0x%08x)\n", status);
1621         }
1622
1623         temp = XREAD4(sc, runt, XHCI_IMAN(0));
1624
1625         /* force clearing of pending interrupts */
1626         if (temp & XHCI_IMAN_INTR_PEND)
1627                 XWRITE4(sc, runt, XHCI_IMAN(0), temp);
1628
1629         /* check for event(s) */
1630         xhci_interrupt_poll(sc);
1631
1632         if (status & (XHCI_STS_PCD | XHCI_STS_HCH |
1633             XHCI_STS_HSE | XHCI_STS_HCE)) {
1634
1635                 if (status & XHCI_STS_PCD) {
1636                         xhci_root_intr(sc);
1637                 }
1638
1639                 if (status & XHCI_STS_HCH) {
1640                         printf("%s: host controller halted\n",
1641                             __FUNCTION__);
1642                 }
1643
1644                 if (status & XHCI_STS_HSE) {
1645                         printf("%s: host system error\n",
1646                             __FUNCTION__);
1647                 }
1648
1649                 if (status & XHCI_STS_HCE) {
1650                         printf("%s: host controller error\n",
1651                            __FUNCTION__);
1652                 }
1653         }
1654         USB_BUS_UNLOCK(&sc->sc_bus);
1655 }
1656
1657 /*------------------------------------------------------------------------*
1658  *      xhci_timeout - XHCI timeout handler
1659  *------------------------------------------------------------------------*/
1660 static void
1661 xhci_timeout(void *arg)
1662 {
1663         struct usb_xfer *xfer = arg;
1664
1665         DPRINTF("xfer=%p\n", xfer);
1666
1667         USB_BUS_LOCK_ASSERT(xfer->xroot->bus, MA_OWNED);
1668
1669         /* transfer is transferred */
1670         xhci_device_done(xfer, USB_ERR_TIMEOUT);
1671 }
1672
1673 static void
1674 xhci_do_poll(struct usb_bus *bus)
1675 {
1676         struct xhci_softc *sc = XHCI_BUS2SC(bus);
1677
1678         USB_BUS_LOCK(&sc->sc_bus);
1679         xhci_interrupt_poll(sc);
1680         USB_BUS_UNLOCK(&sc->sc_bus);
1681 }
1682
1683 static void
1684 xhci_setup_generic_chain_sub(struct xhci_std_temp *temp)
1685 {
1686         struct usb_page_search buf_res;
1687         struct xhci_td *td;
1688         struct xhci_td *td_next;
1689         struct xhci_td *td_alt_next;
1690         struct xhci_td *td_first;
1691         uint32_t buf_offset;
1692         uint32_t average;
1693         uint32_t len_old;
1694         uint32_t npkt_off;
1695         uint32_t dword;
1696         uint8_t shortpkt_old;
1697         uint8_t precompute;
1698         uint8_t x;
1699
1700         td_alt_next = NULL;
1701         buf_offset = 0;
1702         shortpkt_old = temp->shortpkt;
1703         len_old = temp->len;
1704         npkt_off = 0;
1705         precompute = 1;
1706
1707 restart:
1708
1709         td = temp->td;
1710         td_next = td_first = temp->td_next;
1711
1712         while (1) {
1713
1714                 if (temp->len == 0) {
1715
1716                         if (temp->shortpkt)
1717                                 break;
1718
1719                         /* send a Zero Length Packet, ZLP, last */
1720
1721                         temp->shortpkt = 1;
1722                         average = 0;
1723
1724                 } else {
1725
1726                         average = temp->average;
1727
1728                         if (temp->len < average) {
1729                                 if (temp->len % temp->max_packet_size) {
1730                                         temp->shortpkt = 1;
1731                                 }
1732                                 average = temp->len;
1733                         }
1734                 }
1735
1736                 if (td_next == NULL)
1737                         panic("%s: out of XHCI transfer descriptors!", __FUNCTION__);
1738
1739                 /* get next TD */
1740
1741                 td = td_next;
1742                 td_next = td->obj_next;
1743
1744                 /* check if we are pre-computing */
1745
1746                 if (precompute) {
1747
1748                         /* update remaining length */
1749
1750                         temp->len -= average;
1751
1752                         continue;
1753                 }
1754                 /* fill out current TD */
1755
1756                 td->len = average;
1757                 td->remainder = 0;
1758                 td->status = 0;
1759
1760                 /* update remaining length */
1761
1762                 temp->len -= average;
1763
1764                 /* reset TRB index */
1765
1766                 x = 0;
1767
1768                 if (temp->trb_type == XHCI_TRB_TYPE_SETUP_STAGE) {
1769                         /* immediate data */
1770
1771                         if (average > 8)
1772                                 average = 8;
1773
1774                         td->td_trb[0].qwTrb0 = 0;
1775
1776                         usbd_copy_out(temp->pc, temp->offset + buf_offset,
1777                            (uint8_t *)(uintptr_t)&td->td_trb[0].qwTrb0,
1778                            average);
1779
1780                         dword = XHCI_TRB_2_BYTES_SET(8) |
1781                             XHCI_TRB_2_TDSZ_SET(0) |
1782                             XHCI_TRB_2_IRQ_SET(0);
1783
1784                         td->td_trb[0].dwTrb2 = htole32(dword);
1785
1786                         dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_SETUP_STAGE) |
1787                           XHCI_TRB_3_IDT_BIT | XHCI_TRB_3_CYCLE_BIT;
1788
1789                         /* check wLength */
1790                         if (td->td_trb[0].qwTrb0 &
1791                            htole64(XHCI_TRB_0_WLENGTH_MASK)) {
1792                                 if (td->td_trb[0].qwTrb0 &
1793                                     htole64(XHCI_TRB_0_DIR_IN_MASK))
1794                                         dword |= XHCI_TRB_3_TRT_IN;
1795                                 else
1796                                         dword |= XHCI_TRB_3_TRT_OUT;
1797                         }
1798
1799                         td->td_trb[0].dwTrb3 = htole32(dword);
1800 #ifdef USB_DEBUG
1801                         xhci_dump_trb(&td->td_trb[x]);
1802 #endif
1803                         x++;
1804
1805                 } else do {
1806
1807                         uint32_t npkt;
1808
1809                         /* fill out buffer pointers */
1810
1811                         if (average == 0) {
1812                                 memset(&buf_res, 0, sizeof(buf_res));
1813                         } else {
1814                                 usbd_get_page(temp->pc, temp->offset +
1815                                     buf_offset, &buf_res);
1816
1817                                 /* get length to end of page */
1818                                 if (buf_res.length > average)
1819                                         buf_res.length = average;
1820
1821                                 /* check for maximum length */
1822                                 if (buf_res.length > XHCI_TD_PAGE_SIZE)
1823                                         buf_res.length = XHCI_TD_PAGE_SIZE;
1824
1825                                 npkt_off += buf_res.length;
1826                         }
1827
1828                         /* set up npkt */
1829                         npkt = (len_old - npkt_off + temp->max_packet_size - 1) /
1830                             temp->max_packet_size;
1831
1832                         if (npkt == 0)
1833                                 npkt = 1;
1834                         else if (npkt > 31)
1835                                 npkt = 31;
1836
1837                         /* fill out TRB's */
1838                         td->td_trb[x].qwTrb0 =
1839                             htole64((uint64_t)buf_res.physaddr);
1840
1841                         dword =
1842                           XHCI_TRB_2_BYTES_SET(buf_res.length) |
1843                           XHCI_TRB_2_TDSZ_SET(npkt) |
1844                           XHCI_TRB_2_IRQ_SET(0);
1845
1846                         td->td_trb[x].dwTrb2 = htole32(dword);
1847
1848                         switch (temp->trb_type) {
1849                         case XHCI_TRB_TYPE_ISOCH:
1850                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1851                                     XHCI_TRB_3_TBC_SET(temp->tbc) |
1852                                     XHCI_TRB_3_TLBPC_SET(temp->tlbpc);
1853                                 if (td != td_first) {
1854                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1855                                 } else if (temp->do_isoc_sync != 0) {
1856                                         temp->do_isoc_sync = 0;
1857                                         /* wait until "isoc_frame" */
1858                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1859                                             XHCI_TRB_3_FRID_SET(temp->isoc_frame / 8);
1860                                 } else {
1861                                         /* start data transfer at next interval */
1862                                         dword |= XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_ISOCH) |
1863                                             XHCI_TRB_3_ISO_SIA_BIT;
1864                                 }
1865                                 if (temp->direction == UE_DIR_IN)
1866                                         dword |= XHCI_TRB_3_ISP_BIT;
1867                                 break;
1868                         case XHCI_TRB_TYPE_DATA_STAGE:
1869                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1870                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_DATA_STAGE);
1871                                 if (temp->direction == UE_DIR_IN)
1872                                         dword |= XHCI_TRB_3_DIR_IN | XHCI_TRB_3_ISP_BIT;
1873                                 /*
1874                                  * Section 3.2.9 in the XHCI
1875                                  * specification about control
1876                                  * transfers says that we should use a
1877                                  * normal-TRB if there are more TRBs
1878                                  * extending the data-stage
1879                                  * TRB. Update the "trb_type".
1880                                  */
1881                                 temp->trb_type = XHCI_TRB_TYPE_NORMAL;
1882                                 break;
1883                         case XHCI_TRB_TYPE_STATUS_STAGE:
1884                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1885                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_STATUS_STAGE);
1886                                 if (temp->direction == UE_DIR_IN)
1887                                         dword |= XHCI_TRB_3_DIR_IN;
1888                                 break;
1889                         default:        /* XHCI_TRB_TYPE_NORMAL */
1890                                 dword = XHCI_TRB_3_CHAIN_BIT | XHCI_TRB_3_CYCLE_BIT |
1891                                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_NORMAL);
1892                                 if (temp->direction == UE_DIR_IN)
1893                                         dword |= XHCI_TRB_3_ISP_BIT;
1894                                 break;
1895                         }
1896                         td->td_trb[x].dwTrb3 = htole32(dword);
1897
1898                         average -= buf_res.length;
1899                         buf_offset += buf_res.length;
1900 #ifdef USB_DEBUG
1901                         xhci_dump_trb(&td->td_trb[x]);
1902 #endif
1903                         x++;
1904
1905                 } while (average != 0);
1906
1907                 td->td_trb[x-1].dwTrb3 |= htole32(XHCI_TRB_3_IOC_BIT);
1908
1909                 /* store number of data TRB's */
1910
1911                 td->ntrb = x;
1912
1913                 DPRINTF("NTRB=%u\n", x);
1914
1915                 /* fill out link TRB */
1916
1917                 if (td_next != NULL) {
1918                         /* link the current TD with the next one */
1919                         td->td_trb[x].qwTrb0 = htole64((uint64_t)td_next->td_self);
1920                         DPRINTF("LINK=0x%08llx\n", (long long)td_next->td_self);
1921                 } else {
1922                         /* this field will get updated later */
1923                         DPRINTF("NOLINK\n");
1924                 }
1925
1926                 dword = XHCI_TRB_2_IRQ_SET(0);
1927
1928                 td->td_trb[x].dwTrb2 = htole32(dword);
1929
1930                 dword = XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK) |
1931                     XHCI_TRB_3_CYCLE_BIT | XHCI_TRB_3_IOC_BIT |
1932                     /*
1933                      * CHAIN-BIT: Ensure that a multi-TRB IN-endpoint
1934                      * frame only receives a single short packet event
1935                      * by setting the CHAIN bit in the LINK field. In
1936                      * addition some XHCI controllers have problems
1937                      * sending a ZLP unless the CHAIN-BIT is set in
1938                      * the LINK TRB.
1939                      */
1940                     XHCI_TRB_3_CHAIN_BIT;
1941
1942                 td->td_trb[x].dwTrb3 = htole32(dword);
1943
1944                 td->alt_next = td_alt_next;
1945 #ifdef USB_DEBUG
1946                 xhci_dump_trb(&td->td_trb[x]);
1947 #endif
1948                 usb_pc_cpu_flush(td->page_cache);
1949         }
1950
1951         if (precompute) {
1952                 precompute = 0;
1953
1954                 /* set up alt next pointer, if any */
1955                 if (temp->last_frame) {
1956                         td_alt_next = NULL;
1957                 } else {
1958                         /* we use this field internally */
1959                         td_alt_next = td_next;
1960                 }
1961
1962                 /* restore */
1963                 temp->shortpkt = shortpkt_old;
1964                 temp->len = len_old;
1965                 goto restart;
1966         }
1967
1968         /*
1969          * Remove cycle bit from the first TRB if we are
1970          * stepping them:
1971          */
1972         if (temp->step_td != 0) {
1973                 td_first->td_trb[0].dwTrb3 &= ~htole32(XHCI_TRB_3_CYCLE_BIT);
1974                 usb_pc_cpu_flush(td_first->page_cache);
1975         }
1976
1977         /* clear TD SIZE to zero, hence this is the last TRB */
1978         /* remove chain bit because this is the last data TRB in the chain */
1979         td->td_trb[td->ntrb - 1].dwTrb2 &= ~htole32(XHCI_TRB_2_TDSZ_SET(15));
1980         td->td_trb[td->ntrb - 1].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1981         /* remove CHAIN-BIT from last LINK TRB */
1982         td->td_trb[td->ntrb].dwTrb3 &= ~htole32(XHCI_TRB_3_CHAIN_BIT);
1983
1984         usb_pc_cpu_flush(td->page_cache);
1985
1986         temp->td = td;
1987         temp->td_next = td_next;
1988 }
1989
1990 static void
1991 xhci_setup_generic_chain(struct usb_xfer *xfer)
1992 {
1993         struct xhci_std_temp temp;
1994         struct xhci_td *td;
1995         uint32_t x;
1996         uint32_t y;
1997         uint8_t mult;
1998
1999         temp.do_isoc_sync = 0;
2000         temp.step_td = 0;
2001         temp.tbc = 0;
2002         temp.tlbpc = 0;
2003         temp.average = xfer->max_hc_frame_size;
2004         temp.max_packet_size = xfer->max_packet_size;
2005         temp.sc = XHCI_BUS2SC(xfer->xroot->bus);
2006         temp.pc = NULL;
2007         temp.last_frame = 0;
2008         temp.offset = 0;
2009         temp.multishort = xfer->flags_int.isochronous_xfr ||
2010             xfer->flags_int.control_xfr ||
2011             xfer->flags_int.short_frames_ok;
2012
2013         /* toggle the DMA set we are using */
2014         xfer->flags_int.curr_dma_set ^= 1;
2015
2016         /* get next DMA set */
2017         td = xfer->td_start[xfer->flags_int.curr_dma_set];
2018
2019         temp.td = NULL;
2020         temp.td_next = td;
2021
2022         xfer->td_transfer_first = td;
2023         xfer->td_transfer_cache = td;
2024
2025         if (xfer->flags_int.isochronous_xfr) {
2026                 uint8_t shift;
2027
2028                 /* compute multiplier for ISOCHRONOUS transfers */
2029                 mult = xfer->endpoint->ecomp ?
2030                     UE_GET_SS_ISO_MULT(xfer->endpoint->ecomp->bmAttributes)
2031                     : 0;
2032                 /* check for USB 2.0 multiplier */
2033                 if (mult == 0) {
2034                         mult = (xfer->endpoint->edesc->
2035                             wMaxPacketSize[1] >> 3) & 3;
2036                 }
2037                 /* range check */
2038                 if (mult > 2)
2039                         mult = 3;
2040                 else
2041                         mult++;
2042
2043                 x = XREAD4(temp.sc, runt, XHCI_MFINDEX);
2044
2045                 DPRINTF("MFINDEX=0x%08x\n", x);
2046
2047                 switch (usbd_get_speed(xfer->xroot->udev)) {
2048                 case USB_SPEED_FULL:
2049                         shift = 3;
2050                         temp.isoc_delta = 8;    /* 1ms */
2051                         x += temp.isoc_delta - 1;
2052                         x &= ~(temp.isoc_delta - 1);
2053                         break;
2054                 default:
2055                         shift = usbd_xfer_get_fps_shift(xfer);
2056                         temp.isoc_delta = 1U << shift;
2057                         x += temp.isoc_delta - 1;
2058                         x &= ~(temp.isoc_delta - 1);
2059                         /* simple frame load balancing */
2060                         x += xfer->endpoint->usb_uframe;
2061                         break;
2062                 }
2063
2064                 y = XHCI_MFINDEX_GET(x - xfer->endpoint->isoc_next);
2065
2066                 if ((xfer->endpoint->is_synced == 0) ||
2067                     (y < (xfer->nframes << shift)) ||
2068                     (XHCI_MFINDEX_GET(-y) >= (128 * 8))) {
2069                         /*
2070                          * If there is data underflow or the pipe
2071                          * queue is empty we schedule the transfer a
2072                          * few frames ahead of the current frame
2073                          * position. Else two isochronous transfers
2074                          * might overlap.
2075                          */
2076                         xfer->endpoint->isoc_next = XHCI_MFINDEX_GET(x + (3 * 8));
2077                         xfer->endpoint->is_synced = 1;
2078                         temp.do_isoc_sync = 1;
2079
2080                         DPRINTFN(3, "start next=%d\n", xfer->endpoint->isoc_next);
2081                 }
2082
2083                 /* compute isochronous completion time */
2084
2085                 y = XHCI_MFINDEX_GET(xfer->endpoint->isoc_next - (x & ~7));
2086
2087                 xfer->isoc_time_complete =
2088                     usb_isoc_time_expand(&temp.sc->sc_bus, x / 8) +
2089                     (y / 8) + (((xfer->nframes << shift) + 7) / 8);
2090
2091                 x = 0;
2092                 temp.isoc_frame = xfer->endpoint->isoc_next;
2093                 temp.trb_type = XHCI_TRB_TYPE_ISOCH;
2094
2095                 xfer->endpoint->isoc_next += xfer->nframes << shift;
2096
2097         } else if (xfer->flags_int.control_xfr) {
2098
2099                 /* check if we should prepend a setup message */
2100
2101                 if (xfer->flags_int.control_hdr) {
2102
2103                         temp.len = xfer->frlengths[0];
2104                         temp.pc = xfer->frbuffers + 0;
2105                         temp.shortpkt = temp.len ? 1 : 0;
2106                         temp.trb_type = XHCI_TRB_TYPE_SETUP_STAGE;
2107                         temp.direction = 0;
2108
2109                         /* check for last frame */
2110                         if (xfer->nframes == 1) {
2111                                 /* no STATUS stage yet, SETUP is last */
2112                                 if (xfer->flags_int.control_act)
2113                                         temp.last_frame = 1;
2114                         }
2115
2116                         xhci_setup_generic_chain_sub(&temp);
2117                 }
2118                 x = 1;
2119                 mult = 1;
2120                 temp.isoc_delta = 0;
2121                 temp.isoc_frame = 0;
2122                 temp.trb_type = xfer->flags_int.control_did_data ?
2123                     XHCI_TRB_TYPE_NORMAL : XHCI_TRB_TYPE_DATA_STAGE;
2124         } else {
2125                 x = 0;
2126                 mult = 1;
2127                 temp.isoc_delta = 0;
2128                 temp.isoc_frame = 0;
2129                 temp.trb_type = XHCI_TRB_TYPE_NORMAL;
2130         }
2131
2132         if (x != xfer->nframes) {
2133                 /* set up page_cache pointer */
2134                 temp.pc = xfer->frbuffers + x;
2135                 /* set endpoint direction */
2136                 temp.direction = UE_GET_DIR(xfer->endpointno);
2137         }
2138
2139         while (x != xfer->nframes) {
2140
2141                 /* DATA0 / DATA1 message */
2142
2143                 temp.len = xfer->frlengths[x];
2144                 temp.step_td = ((xfer->endpointno & UE_DIR_IN) &&
2145                     x != 0 && temp.multishort == 0);
2146
2147                 x++;
2148
2149                 if (x == xfer->nframes) {
2150                         if (xfer->flags_int.control_xfr) {
2151                                 /* no STATUS stage yet, DATA is last */
2152                                 if (xfer->flags_int.control_act)
2153                                         temp.last_frame = 1;
2154                         } else {
2155                                 temp.last_frame = 1;
2156                         }
2157                 }
2158                 if (temp.len == 0) {
2159
2160                         /* make sure that we send an USB packet */
2161
2162                         temp.shortpkt = 0;
2163
2164                         temp.tbc = 0;
2165                         temp.tlbpc = mult - 1;
2166
2167                 } else if (xfer->flags_int.isochronous_xfr) {
2168
2169                         uint8_t tdpc;
2170
2171                         /*
2172                          * Isochronous transfers don't have short
2173                          * packet termination:
2174                          */
2175
2176                         temp.shortpkt = 1;
2177
2178                         /* isochronous transfers have a transfer limit */
2179
2180                         if (temp.len > xfer->max_frame_size)
2181                                 temp.len = xfer->max_frame_size;
2182
2183                         /* compute TD packet count */
2184                         tdpc = (temp.len + xfer->max_packet_size - 1) /
2185                             xfer->max_packet_size;
2186
2187                         temp.tbc = ((tdpc + mult - 1) / mult) - 1;
2188                         temp.tlbpc = (tdpc % mult);
2189
2190                         if (temp.tlbpc == 0)
2191                                 temp.tlbpc = mult - 1;
2192                         else
2193                                 temp.tlbpc--;
2194                 } else {
2195
2196                         /* regular data transfer */
2197
2198                         temp.shortpkt = xfer->flags.force_short_xfer ? 0 : 1;
2199                 }
2200
2201                 xhci_setup_generic_chain_sub(&temp);
2202
2203                 if (xfer->flags_int.isochronous_xfr) {
2204                         temp.offset += xfer->frlengths[x - 1];
2205                         temp.isoc_frame += temp.isoc_delta;
2206                 } else {
2207                         /* get next Page Cache pointer */
2208                         temp.pc = xfer->frbuffers + x;
2209                 }
2210         }
2211
2212         /* check if we should append a status stage */
2213
2214         if (xfer->flags_int.control_xfr &&
2215             !xfer->flags_int.control_act) {
2216
2217                 /*
2218                  * Send a DATA1 message and invert the current
2219                  * endpoint direction.
2220                  */
2221                 temp.step_td = (xfer->nframes != 0);
2222                 temp.direction = UE_GET_DIR(xfer->endpointno) ^ UE_DIR_IN;
2223                 temp.len = 0;
2224                 temp.pc = NULL;
2225                 temp.shortpkt = 0;
2226                 temp.last_frame = 1;
2227                 temp.trb_type = XHCI_TRB_TYPE_STATUS_STAGE;
2228
2229                 xhci_setup_generic_chain_sub(&temp);
2230         }
2231
2232         td = temp.td;
2233
2234         /* must have at least one frame! */
2235
2236         xfer->td_transfer_last = td;
2237
2238         DPRINTF("first=%p last=%p\n", xfer->td_transfer_first, td);
2239 }
2240
2241 static void
2242 xhci_set_slot_pointer(struct xhci_softc *sc, uint8_t index, uint64_t dev_addr)
2243 {
2244         struct usb_page_search buf_res;
2245         struct xhci_dev_ctx_addr *pdctxa;
2246
2247         usbd_get_page(&sc->sc_hw.ctx_pc, 0, &buf_res);
2248
2249         pdctxa = buf_res.buffer;
2250
2251         DPRINTF("addr[%u]=0x%016llx\n", index, (long long)dev_addr);
2252
2253         pdctxa->qwBaaDevCtxAddr[index] = htole64(dev_addr);
2254
2255         usb_pc_cpu_flush(&sc->sc_hw.ctx_pc);
2256 }
2257
2258 static usb_error_t
2259 xhci_configure_mask(struct usb_device *udev, uint32_t mask, uint8_t drop)
2260 {
2261         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2262         struct usb_page_search buf_inp;
2263         struct xhci_input_dev_ctx *pinp;
2264         uint32_t temp;
2265         uint8_t index;
2266         uint8_t x;
2267
2268         index = udev->controller_slot_id;
2269
2270         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2271
2272         pinp = buf_inp.buffer;
2273
2274         if (drop) {
2275                 mask &= XHCI_INCTX_NON_CTRL_MASK;
2276                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0, mask);
2277                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, 0);
2278         } else {
2279                 /*
2280                  * Some hardware requires that we drop the endpoint
2281                  * context before adding it again:
2282                  */
2283                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx0,
2284                     mask & XHCI_INCTX_NON_CTRL_MASK);
2285
2286                 /* Add new endpoint context */
2287                 xhci_ctx_set_le32(sc, &pinp->ctx_input.dwInCtx1, mask);
2288
2289                 /* find most significant set bit */
2290                 for (x = 31; x != 1; x--) {
2291                         if (mask & (1 << x))
2292                                 break;
2293                 }
2294
2295                 /* adjust */
2296                 x--;
2297
2298                 /* figure out the maximum number of contexts */
2299                 if (x > sc->sc_hw.devs[index].context_num)
2300                         sc->sc_hw.devs[index].context_num = x;
2301                 else
2302                         x = sc->sc_hw.devs[index].context_num;
2303
2304                 /* update number of contexts */
2305                 temp = xhci_ctx_get_le32(sc, &pinp->ctx_slot.dwSctx0);
2306                 temp &= ~XHCI_SCTX_0_CTX_NUM_SET(31);
2307                 temp |= XHCI_SCTX_0_CTX_NUM_SET(x + 1);
2308                 xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2309         }
2310         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2311         return (0);
2312 }
2313
2314 static usb_error_t
2315 xhci_configure_endpoint(struct usb_device *udev,
2316     struct usb_endpoint_descriptor *edesc, struct xhci_endpoint_ext *pepext,
2317     uint16_t interval, uint8_t max_packet_count,
2318     uint8_t mult, uint8_t fps_shift, uint16_t max_packet_size,
2319     uint16_t max_frame_size, uint8_t ep_mode)
2320 {
2321         struct usb_page_search buf_inp;
2322         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2323         struct xhci_input_dev_ctx *pinp;
2324         uint64_t ring_addr = pepext->physaddr;
2325         uint32_t temp;
2326         uint8_t index;
2327         uint8_t epno;
2328         uint8_t type;
2329
2330         index = udev->controller_slot_id;
2331
2332         usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
2333
2334         pinp = buf_inp.buffer;
2335
2336         epno = edesc->bEndpointAddress;
2337         type = edesc->bmAttributes & UE_XFERTYPE;
2338
2339         if (type == UE_CONTROL)
2340                 epno |= UE_DIR_IN;
2341
2342         epno = XHCI_EPNO2EPID(epno);
2343
2344         if (epno == 0)
2345                 return (USB_ERR_NO_PIPE);               /* invalid */
2346
2347         if (max_packet_count == 0)
2348                 return (USB_ERR_BAD_BUFSIZE);
2349
2350         max_packet_count--;
2351
2352         if (mult == 0)
2353                 return (USB_ERR_BAD_BUFSIZE);
2354
2355         /* store endpoint mode */
2356         pepext->trb_ep_mode = ep_mode;
2357         usb_pc_cpu_flush(pepext->page_cache);
2358
2359         if (ep_mode == USB_EP_MODE_STREAMS) {
2360                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2361                     XHCI_EPCTX_0_MAXP_STREAMS_SET(XHCI_MAX_STREAMS_LOG - 1) |
2362                     XHCI_EPCTX_0_LSA_SET(1);
2363
2364                 ring_addr += sizeof(struct xhci_trb) *
2365                     XHCI_MAX_TRANSFERS * XHCI_MAX_STREAMS;
2366         } else {
2367                 temp = XHCI_EPCTX_0_EPSTATE_SET(0) |
2368                     XHCI_EPCTX_0_MAXP_STREAMS_SET(0) |
2369                     XHCI_EPCTX_0_LSA_SET(0);
2370
2371                 ring_addr |= XHCI_EPCTX_2_DCS_SET(1);
2372         }
2373
2374         switch (udev->speed) {
2375         case USB_SPEED_FULL:
2376         case USB_SPEED_LOW:
2377                 /* 1ms -> 125us */
2378                 fps_shift += 3;
2379                 break;
2380         default:
2381                 break;
2382         }
2383
2384         switch (type) {
2385         case UE_INTERRUPT:
2386                 if (fps_shift > 3)
2387                         fps_shift--;
2388                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2389                 break;
2390         case UE_ISOCHRONOUS:
2391                 temp |= XHCI_EPCTX_0_IVAL_SET(fps_shift);
2392
2393                 switch (udev->speed) {
2394                 case USB_SPEED_SUPER:
2395                         if (mult > 3)
2396                                 mult = 3;
2397                         temp |= XHCI_EPCTX_0_MULT_SET(mult - 1);
2398                         max_packet_count /= mult;
2399                         break;
2400                 default:
2401                         break;
2402                 }
2403                 break;
2404         default:
2405                 break;
2406         }
2407
2408         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx0, temp);
2409
2410         temp =
2411             XHCI_EPCTX_1_HID_SET(0) |
2412             XHCI_EPCTX_1_MAXB_SET(max_packet_count) |
2413             XHCI_EPCTX_1_MAXP_SIZE_SET(max_packet_size);
2414
2415         /*
2416          * Always enable the "three strikes and you are gone" feature
2417          * except for ISOCHRONOUS endpoints. This is suggested by
2418          * section 4.3.3 in the XHCI specification about device slot
2419          * initialisation.
2420          */
2421         if (type != UE_ISOCHRONOUS)
2422                 temp |= XHCI_EPCTX_1_CERR_SET(3);
2423
2424         switch (type) {
2425         case UE_CONTROL:
2426                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2427                 break;
2428         case UE_ISOCHRONOUS:
2429                 temp |= XHCI_EPCTX_1_EPTYPE_SET(1);
2430                 break;
2431         case UE_BULK:
2432                 temp |= XHCI_EPCTX_1_EPTYPE_SET(2);
2433                 break;
2434         default:
2435                 temp |= XHCI_EPCTX_1_EPTYPE_SET(3);
2436                 break;
2437         }
2438
2439         /* check for IN direction */
2440         if (epno & 1)
2441                 temp |= XHCI_EPCTX_1_EPTYPE_SET(4);
2442
2443         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx1, temp);
2444         xhci_ctx_set_le64(sc, &pinp->ctx_ep[epno - 1].qwEpCtx2, ring_addr);
2445
2446         switch (edesc->bmAttributes & UE_XFERTYPE) {
2447         case UE_INTERRUPT:
2448         case UE_ISOCHRONOUS:
2449                 temp = XHCI_EPCTX_4_MAX_ESIT_PAYLOAD_SET(max_frame_size) |
2450                     XHCI_EPCTX_4_AVG_TRB_LEN_SET(MIN(XHCI_PAGE_SIZE,
2451                     max_frame_size));
2452                 break;
2453         case UE_CONTROL:
2454                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(8);
2455                 break;
2456         default:
2457                 temp = XHCI_EPCTX_4_AVG_TRB_LEN_SET(XHCI_PAGE_SIZE);
2458                 break;
2459         }
2460
2461         xhci_ctx_set_le32(sc, &pinp->ctx_ep[epno - 1].dwEpCtx4, temp);
2462
2463 #ifdef USB_DEBUG
2464         xhci_dump_endpoint(sc, &pinp->ctx_ep[epno - 1]);
2465 #endif
2466         usb_pc_cpu_flush(&sc->sc_hw.devs[index].input_pc);
2467
2468         return (0);             /* success */
2469 }
2470
2471 static usb_error_t
2472 xhci_configure_endpoint_by_xfer(struct usb_xfer *xfer)
2473 {
2474         struct xhci_endpoint_ext *pepext;
2475         struct usb_endpoint_ss_comp_descriptor *ecomp;
2476         usb_stream_t x;
2477
2478         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2479             xfer->endpoint->edesc);
2480
2481         ecomp = xfer->endpoint->ecomp;
2482
2483         for (x = 0; x != XHCI_MAX_STREAMS; x++) {
2484                 uint64_t temp;
2485
2486                 /* halt any transfers */
2487                 pepext->trb[x * XHCI_MAX_TRANSFERS].dwTrb3 = 0;
2488
2489                 /* compute start of TRB ring for stream "x" */
2490                 temp = pepext->physaddr +
2491                     (x * XHCI_MAX_TRANSFERS * sizeof(struct xhci_trb)) +
2492                     XHCI_SCTX_0_SCT_SEC_TR_RING;
2493
2494                 /* make tree structure */
2495                 pepext->trb[(XHCI_MAX_TRANSFERS *
2496                     XHCI_MAX_STREAMS) + x].qwTrb0 = htole64(temp);
2497
2498                 /* reserved fields */
2499                 pepext->trb[(XHCI_MAX_TRANSFERS *
2500                     XHCI_MAX_STREAMS) + x].dwTrb2 = 0;
2501                 pepext->trb[(XHCI_MAX_TRANSFERS *
2502                     XHCI_MAX_STREAMS) + x].dwTrb3 = 0;
2503         }
2504         usb_pc_cpu_flush(pepext->page_cache);
2505
2506         return (xhci_configure_endpoint(xfer->xroot->udev,
2507             xfer->endpoint->edesc, pepext,
2508             xfer->interval, xfer->max_packet_count,
2509             (ecomp != NULL) ? UE_GET_SS_ISO_MULT(ecomp->bmAttributes) + 1 : 1,
2510             usbd_xfer_get_fps_shift(xfer), xfer->max_packet_size,
2511             xfer->max_frame_size, xfer->endpoint->ep_mode));
2512 }
2513
2514 static usb_error_t
2515 xhci_configure_device(struct usb_device *udev)
2516 {
2517         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2518         struct usb_page_search buf_inp;
2519         struct usb_page_cache *pcinp;
2520         struct xhci_input_dev_ctx *pinp;
2521         struct usb_device *hubdev;
2522         uint32_t temp;
2523         uint32_t route;
2524         uint32_t rh_port;
2525         uint8_t is_hub;
2526         uint8_t index;
2527         uint8_t depth;
2528
2529         index = udev->controller_slot_id;
2530
2531         DPRINTF("index=%u\n", index);
2532
2533         pcinp = &sc->sc_hw.devs[index].input_pc;
2534
2535         usbd_get_page(pcinp, 0, &buf_inp);
2536
2537         pinp = buf_inp.buffer;
2538
2539         rh_port = 0;
2540         route = 0;
2541
2542         /* figure out route string and root HUB port number */
2543
2544         for (hubdev = udev; hubdev != NULL; hubdev = hubdev->parent_hub) {
2545
2546                 if (hubdev->parent_hub == NULL)
2547                         break;
2548
2549                 depth = hubdev->parent_hub->depth;
2550
2551                 /*
2552                  * NOTE: HS/FS/LS devices and the SS root HUB can have
2553                  * more than 15 ports
2554                  */
2555
2556                 rh_port = hubdev->port_no;
2557
2558                 if (depth == 0)
2559                         break;
2560
2561                 if (rh_port > 15)
2562                         rh_port = 15;
2563
2564                 if (depth < 6)
2565                         route |= rh_port << (4 * (depth - 1));
2566         }
2567
2568         DPRINTF("Route=0x%08x\n", route);
2569
2570         temp = XHCI_SCTX_0_ROUTE_SET(route) |
2571             XHCI_SCTX_0_CTX_NUM_SET(
2572             sc->sc_hw.devs[index].context_num + 1);
2573
2574         switch (udev->speed) {
2575         case USB_SPEED_LOW:
2576                 temp |= XHCI_SCTX_0_SPEED_SET(2);
2577                 if (udev->parent_hs_hub != NULL &&
2578                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2579                     UDPROTO_HSHUBMTT) {
2580                         DPRINTF("Device inherits MTT\n");
2581                         temp |= XHCI_SCTX_0_MTT_SET(1);
2582                 }
2583                 break;
2584         case USB_SPEED_HIGH:
2585                 temp |= XHCI_SCTX_0_SPEED_SET(3);
2586                 if (sc->sc_hw.devs[index].nports != 0 &&
2587                     udev->ddesc.bDeviceProtocol == UDPROTO_HSHUBMTT) {
2588                         DPRINTF("HUB supports MTT\n");
2589                         temp |= XHCI_SCTX_0_MTT_SET(1);
2590                 }
2591                 break;
2592         case USB_SPEED_FULL:
2593                 temp |= XHCI_SCTX_0_SPEED_SET(1);
2594                 if (udev->parent_hs_hub != NULL &&
2595                     udev->parent_hs_hub->ddesc.bDeviceProtocol ==
2596                     UDPROTO_HSHUBMTT) {
2597                         DPRINTF("Device inherits MTT\n");
2598                         temp |= XHCI_SCTX_0_MTT_SET(1);
2599                 }
2600                 break;
2601         default:
2602                 temp |= XHCI_SCTX_0_SPEED_SET(4);
2603                 break;
2604         }
2605
2606         is_hub = sc->sc_hw.devs[index].nports != 0 &&
2607             (udev->speed == USB_SPEED_SUPER ||
2608             udev->speed == USB_SPEED_HIGH);
2609
2610         if (is_hub)
2611                 temp |= XHCI_SCTX_0_HUB_SET(1);
2612
2613         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx0, temp);
2614
2615         temp = XHCI_SCTX_1_RH_PORT_SET(rh_port);
2616
2617         if (is_hub) {
2618                 temp |= XHCI_SCTX_1_NUM_PORTS_SET(
2619                     sc->sc_hw.devs[index].nports);
2620         }
2621
2622         switch (udev->speed) {
2623         case USB_SPEED_SUPER:
2624                 switch (sc->sc_hw.devs[index].state) {
2625                 case XHCI_ST_ADDRESSED:
2626                 case XHCI_ST_CONFIGURED:
2627                         /* enable power save */
2628                         temp |= XHCI_SCTX_1_MAX_EL_SET(sc->sc_exit_lat_max);
2629                         break;
2630                 default:
2631                         /* disable power save */
2632                         break;
2633                 }
2634                 break;
2635         default:
2636                 break;
2637         }
2638
2639         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx1, temp);
2640
2641         temp = XHCI_SCTX_2_IRQ_TARGET_SET(0);
2642
2643         if (is_hub) {
2644                 temp |= XHCI_SCTX_2_TT_THINK_TIME_SET(
2645                     sc->sc_hw.devs[index].tt);
2646         }
2647
2648         hubdev = udev->parent_hs_hub;
2649
2650         /* check if we should activate the transaction translator */
2651         switch (udev->speed) {
2652         case USB_SPEED_FULL:
2653         case USB_SPEED_LOW:
2654                 if (hubdev != NULL) {
2655                         temp |= XHCI_SCTX_2_TT_HUB_SID_SET(
2656                             hubdev->controller_slot_id);
2657                         temp |= XHCI_SCTX_2_TT_PORT_NUM_SET(
2658                             udev->hs_port_no);
2659                 }
2660                 break;
2661         default:
2662                 break;
2663         }
2664
2665         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx2, temp);
2666
2667         /*
2668          * These fields should be initialized to zero, according to
2669          * XHCI section 6.2.2 - slot context:
2670          */
2671         temp = XHCI_SCTX_3_DEV_ADDR_SET(0) |
2672             XHCI_SCTX_3_SLOT_STATE_SET(0);
2673
2674         xhci_ctx_set_le32(sc, &pinp->ctx_slot.dwSctx3, temp);
2675
2676 #ifdef USB_DEBUG
2677         xhci_dump_device(sc, &pinp->ctx_slot);
2678 #endif
2679         usb_pc_cpu_flush(pcinp);
2680
2681         return (0);             /* success */
2682 }
2683
2684 static usb_error_t
2685 xhci_alloc_device_ext(struct usb_device *udev)
2686 {
2687         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2688         struct usb_page_search buf_dev;
2689         struct usb_page_search buf_ep;
2690         struct xhci_trb *trb;
2691         struct usb_page_cache *pc;
2692         struct usb_page *pg;
2693         uint64_t addr;
2694         uint8_t index;
2695         uint8_t i;
2696
2697         index = udev->controller_slot_id;
2698
2699         pc = &sc->sc_hw.devs[index].device_pc;
2700         pg = &sc->sc_hw.devs[index].device_pg;
2701
2702         /* need to initialize the page cache */
2703         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2704
2705         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2706             (2 * sizeof(struct xhci_dev_ctx)) :
2707             sizeof(struct xhci_dev_ctx), XHCI_PAGE_SIZE))
2708                 goto error;
2709
2710         usbd_get_page(pc, 0, &buf_dev);
2711
2712         pc = &sc->sc_hw.devs[index].input_pc;
2713         pg = &sc->sc_hw.devs[index].input_pg;
2714
2715         /* need to initialize the page cache */
2716         pc->tag_parent = sc->sc_bus.dma_parent_tag;
2717
2718         if (usb_pc_alloc_mem(pc, pg, sc->sc_ctx_is_64_byte ?
2719             (2 * sizeof(struct xhci_input_dev_ctx)) :
2720             sizeof(struct xhci_input_dev_ctx), XHCI_PAGE_SIZE)) {
2721                 goto error;
2722         }
2723
2724         /* initialize all endpoint LINK TRBs */
2725
2726         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++) {
2727
2728                 pc = &sc->sc_hw.devs[index].endpoint_pc[i];
2729                 pg = &sc->sc_hw.devs[index].endpoint_pg[i];
2730
2731                 /* need to initialize the page cache */
2732                 pc->tag_parent = sc->sc_bus.dma_parent_tag;
2733
2734                 if (usb_pc_alloc_mem(pc, pg,
2735                     sizeof(struct xhci_dev_endpoint_trbs), XHCI_TRB_ALIGN)) {
2736                         goto error;
2737                 }
2738
2739                 /* lookup endpoint TRB ring */
2740                 usbd_get_page(pc, 0, &buf_ep);
2741
2742                 /* get TRB pointer */
2743                 trb = buf_ep.buffer;
2744                 trb += XHCI_MAX_TRANSFERS - 1;
2745
2746                 /* get TRB start address */
2747                 addr = buf_ep.physaddr;
2748
2749                 /* create LINK TRB */
2750                 trb->qwTrb0 = htole64(addr);
2751                 trb->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2752                 trb->dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2753                     XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2754
2755                 usb_pc_cpu_flush(pc);
2756         }
2757
2758         xhci_set_slot_pointer(sc, index, buf_dev.physaddr);
2759
2760         return (0);
2761
2762 error:
2763         xhci_free_device_ext(udev);
2764
2765         return (USB_ERR_NOMEM);
2766 }
2767
2768 static void
2769 xhci_free_device_ext(struct usb_device *udev)
2770 {
2771         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2772         uint8_t index;
2773         uint8_t i;
2774
2775         index = udev->controller_slot_id;
2776         xhci_set_slot_pointer(sc, index, 0);
2777
2778         usb_pc_free_mem(&sc->sc_hw.devs[index].device_pc);
2779         usb_pc_free_mem(&sc->sc_hw.devs[index].input_pc);
2780         for (i = 0; i != XHCI_MAX_ENDPOINTS; i++)
2781                 usb_pc_free_mem(&sc->sc_hw.devs[index].endpoint_pc[i]);
2782 }
2783
2784 static struct xhci_endpoint_ext *
2785 xhci_get_endpoint_ext(struct usb_device *udev, struct usb_endpoint_descriptor *edesc)
2786 {
2787         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
2788         struct xhci_endpoint_ext *pepext;
2789         struct usb_page_cache *pc;
2790         struct usb_page_search buf_ep;
2791         uint8_t epno;
2792         uint8_t index;
2793
2794         epno = edesc->bEndpointAddress;
2795         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
2796                 epno |= UE_DIR_IN;
2797
2798         epno = XHCI_EPNO2EPID(epno);
2799
2800         index = udev->controller_slot_id;
2801
2802         pc = &sc->sc_hw.devs[index].endpoint_pc[epno];
2803
2804         usbd_get_page(pc, 0, &buf_ep);
2805
2806         pepext = &sc->sc_hw.devs[index].endp[epno];
2807         pepext->page_cache = pc;
2808         pepext->trb = buf_ep.buffer;
2809         pepext->physaddr = buf_ep.physaddr;
2810
2811         return (pepext);
2812 }
2813
2814 static void
2815 xhci_endpoint_doorbell(struct usb_xfer *xfer)
2816 {
2817         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2818         uint8_t epno;
2819         uint8_t index;
2820
2821         epno = xfer->endpointno;
2822         if (xfer->flags_int.control_xfr)
2823                 epno |= UE_DIR_IN;
2824
2825         epno = XHCI_EPNO2EPID(epno);
2826         index = xfer->xroot->udev->controller_slot_id;
2827
2828         if (xfer->xroot->udev->flags.self_suspended == 0) {
2829                 XWRITE4(sc, door, XHCI_DOORBELL(index),
2830                     epno | XHCI_DB_SID_SET(xfer->stream_id));
2831         }
2832 }
2833
2834 static void
2835 xhci_transfer_remove(struct usb_xfer *xfer, usb_error_t error)
2836 {
2837         struct xhci_endpoint_ext *pepext;
2838
2839         if (xfer->flags_int.bandwidth_reclaimed) {
2840                 xfer->flags_int.bandwidth_reclaimed = 0;
2841
2842                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2843                     xfer->endpoint->edesc);
2844
2845                 pepext->trb_used[xfer->stream_id]--;
2846
2847                 pepext->xfer[xfer->qh_pos] = NULL;
2848
2849                 if (error && pepext->trb_running != 0) {
2850                         pepext->trb_halted = 1;
2851                         pepext->trb_running = 0;
2852                 }
2853         }
2854 }
2855
2856 static usb_error_t
2857 xhci_transfer_insert(struct usb_xfer *xfer)
2858 {
2859         struct xhci_td *td_first;
2860         struct xhci_td *td_last;
2861         struct xhci_trb *trb_link;
2862         struct xhci_endpoint_ext *pepext;
2863         uint64_t addr;
2864         usb_stream_t id;
2865         uint8_t i;
2866         uint8_t inext;
2867         uint8_t trb_limit;
2868
2869         DPRINTFN(8, "\n");
2870
2871         id = xfer->stream_id;
2872
2873         /* check if already inserted */
2874         if (xfer->flags_int.bandwidth_reclaimed) {
2875                 DPRINTFN(8, "Already in schedule\n");
2876                 return (0);
2877         }
2878
2879         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
2880             xfer->endpoint->edesc);
2881
2882         td_first = xfer->td_transfer_first;
2883         td_last = xfer->td_transfer_last;
2884         addr = pepext->physaddr;
2885
2886         switch (xfer->endpoint->edesc->bmAttributes & UE_XFERTYPE) {
2887         case UE_CONTROL:
2888         case UE_INTERRUPT:
2889                 /* single buffered */
2890                 trb_limit = 1;
2891                 break;
2892         default:
2893                 /* multi buffered */
2894                 trb_limit = (XHCI_MAX_TRANSFERS - 2);
2895                 break;
2896         }
2897
2898         if (pepext->trb_used[id] >= trb_limit) {
2899                 DPRINTFN(8, "Too many TDs queued.\n");
2900                 return (USB_ERR_NOMEM);
2901         }
2902
2903         /* check for stopped condition, after putting transfer on interrupt queue */
2904         if (pepext->trb_running == 0) {
2905                 struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
2906
2907                 DPRINTFN(8, "Not running\n");
2908
2909                 /* start configuration */
2910                 (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
2911                     &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
2912                 return (0);
2913         }
2914
2915         pepext->trb_used[id]++;
2916
2917         /* get current TRB index */
2918         i = pepext->trb_index[id];
2919
2920         /* get next TRB index */
2921         inext = (i + 1);
2922
2923         /* the last entry of the ring is a hardcoded link TRB */
2924         if (inext >= (XHCI_MAX_TRANSFERS - 1))
2925                 inext = 0;
2926
2927         /* store next TRB index, before stream ID offset is added */
2928         pepext->trb_index[id] = inext;
2929
2930         /* offset for stream */
2931         i += id * XHCI_MAX_TRANSFERS;
2932         inext += id * XHCI_MAX_TRANSFERS;
2933
2934         /* compute terminating return address */
2935         addr += (inext * sizeof(struct xhci_trb));
2936
2937         /* compute link TRB pointer */
2938         trb_link = td_last->td_trb + td_last->ntrb;
2939
2940         /* update next pointer of last link TRB */
2941         trb_link->qwTrb0 = htole64(addr);
2942         trb_link->dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2943         trb_link->dwTrb3 = htole32(XHCI_TRB_3_IOC_BIT |
2944             XHCI_TRB_3_CYCLE_BIT |
2945             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2946
2947 #ifdef USB_DEBUG
2948         xhci_dump_trb(&td_last->td_trb[td_last->ntrb]);
2949 #endif
2950         usb_pc_cpu_flush(td_last->page_cache);
2951
2952         /* write ahead chain end marker */
2953
2954         pepext->trb[inext].qwTrb0 = 0;
2955         pepext->trb[inext].dwTrb2 = 0;
2956         pepext->trb[inext].dwTrb3 = 0;
2957
2958         /* update next pointer of link TRB */
2959
2960         pepext->trb[i].qwTrb0 = htole64((uint64_t)td_first->td_self);
2961         pepext->trb[i].dwTrb2 = htole32(XHCI_TRB_2_IRQ_SET(0));
2962
2963 #ifdef USB_DEBUG
2964         xhci_dump_trb(&pepext->trb[i]);
2965 #endif
2966         usb_pc_cpu_flush(pepext->page_cache);
2967
2968         /* toggle cycle bit which activates the transfer chain */
2969
2970         pepext->trb[i].dwTrb3 = htole32(XHCI_TRB_3_CYCLE_BIT |
2971             XHCI_TRB_3_TYPE_SET(XHCI_TRB_TYPE_LINK));
2972
2973         usb_pc_cpu_flush(pepext->page_cache);
2974
2975         DPRINTF("qh_pos = %u\n", i);
2976
2977         pepext->xfer[i] = xfer;
2978
2979         xfer->qh_pos = i;
2980
2981         xfer->flags_int.bandwidth_reclaimed = 1;
2982
2983         xhci_endpoint_doorbell(xfer);
2984
2985         return (0);
2986 }
2987
2988 static void
2989 xhci_root_intr(struct xhci_softc *sc)
2990 {
2991         uint16_t i;
2992
2993         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
2994
2995         /* clear any old interrupt data */
2996         memset(sc->sc_hub_idata, 0, sizeof(sc->sc_hub_idata));
2997
2998         for (i = 1; i <= sc->sc_noport; i++) {
2999                 /* pick out CHANGE bits from the status register */
3000                 if (XREAD4(sc, oper, XHCI_PORTSC(i)) & (
3001                     XHCI_PS_CSC | XHCI_PS_PEC |
3002                     XHCI_PS_OCC | XHCI_PS_WRC |
3003                     XHCI_PS_PRC | XHCI_PS_PLC |
3004                     XHCI_PS_CEC)) {
3005                         sc->sc_hub_idata[i / 8] |= 1 << (i % 8);
3006                         DPRINTF("port %d changed\n", i);
3007                 }
3008         }
3009         uhub_root_intr(&sc->sc_bus, sc->sc_hub_idata,
3010             sizeof(sc->sc_hub_idata));
3011 }
3012
3013 /*------------------------------------------------------------------------*
3014  *      xhci_device_done - XHCI done handler
3015  *
3016  * NOTE: This function can be called two times in a row on
3017  * the same USB transfer. From close and from interrupt.
3018  *------------------------------------------------------------------------*/
3019 static void
3020 xhci_device_done(struct usb_xfer *xfer, usb_error_t error)
3021 {
3022         DPRINTFN(2, "xfer=%p, endpoint=%p, error=%d\n",
3023             xfer, xfer->endpoint, error);
3024
3025         /* remove transfer from HW queue */
3026         xhci_transfer_remove(xfer, error);
3027
3028         /* dequeue transfer and start next transfer */
3029         usbd_transfer_done(xfer, error);
3030 }
3031
3032 /*------------------------------------------------------------------------*
3033  * XHCI data transfer support (generic type)
3034  *------------------------------------------------------------------------*/
3035 static void
3036 xhci_device_generic_open(struct usb_xfer *xfer)
3037 {
3038         if (xfer->flags_int.isochronous_xfr) {
3039                 switch (xfer->xroot->udev->speed) {
3040                 case USB_SPEED_FULL:
3041                         break;
3042                 default:
3043                         usb_hs_bandwidth_alloc(xfer);
3044                         break;
3045                 }
3046         }
3047 }
3048
3049 static void
3050 xhci_device_generic_close(struct usb_xfer *xfer)
3051 {
3052         DPRINTF("\n");
3053
3054         xhci_device_done(xfer, USB_ERR_CANCELLED);
3055
3056         if (xfer->flags_int.isochronous_xfr) {
3057                 switch (xfer->xroot->udev->speed) {
3058                 case USB_SPEED_FULL:
3059                         break;
3060                 default:
3061                         usb_hs_bandwidth_free(xfer);
3062                         break;
3063                 }
3064         }
3065 }
3066
3067 static void
3068 xhci_device_generic_multi_enter(struct usb_endpoint *ep,
3069     usb_stream_t stream_id, struct usb_xfer *enter_xfer)
3070 {
3071         struct usb_xfer *xfer;
3072
3073         /* check if there is a current transfer */
3074         xfer = ep->endpoint_q[stream_id].curr;
3075         if (xfer == NULL)
3076                 return;
3077
3078         /*
3079          * Check if the current transfer is started and then pickup
3080          * the next one, if any. Else wait for next start event due to
3081          * block on failure feature.
3082          */
3083         if (!xfer->flags_int.bandwidth_reclaimed)
3084                 return;
3085
3086         xfer = TAILQ_FIRST(&ep->endpoint_q[stream_id].head);
3087         if (xfer == NULL) {
3088                 /*
3089                  * In case of enter we have to consider that the
3090                  * transfer is queued by the USB core after the enter
3091                  * method is called.
3092                  */
3093                 xfer = enter_xfer;
3094
3095                 if (xfer == NULL)
3096                         return;
3097         }
3098
3099         /* try to multi buffer */
3100         xhci_transfer_insert(xfer);
3101 }
3102
3103 static void
3104 xhci_device_generic_enter(struct usb_xfer *xfer)
3105 {
3106         DPRINTF("\n");
3107
3108         /* set up TD's and QH */
3109         xhci_setup_generic_chain(xfer);
3110
3111         xhci_device_generic_multi_enter(xfer->endpoint,
3112             xfer->stream_id, xfer);
3113 }
3114
3115 static void
3116 xhci_device_generic_start(struct usb_xfer *xfer)
3117 {
3118         DPRINTF("\n");
3119
3120         /* try to insert xfer on HW queue */
3121         xhci_transfer_insert(xfer);
3122
3123         /* try to multi buffer */
3124         xhci_device_generic_multi_enter(xfer->endpoint,
3125             xfer->stream_id, NULL);
3126
3127         /* add transfer last on interrupt queue */
3128         usbd_transfer_enqueue(&xfer->xroot->bus->intr_q, xfer);
3129
3130         /* start timeout, if any */
3131         if (xfer->timeout != 0)
3132                 usbd_transfer_timeout_ms(xfer, &xhci_timeout, xfer->timeout);
3133 }
3134
3135 struct usb_pipe_methods xhci_device_generic_methods =
3136 {
3137         .open = xhci_device_generic_open,
3138         .close = xhci_device_generic_close,
3139         .enter = xhci_device_generic_enter,
3140         .start = xhci_device_generic_start,
3141 };
3142
3143 /*------------------------------------------------------------------------*
3144  * xhci root HUB support
3145  *------------------------------------------------------------------------*
3146  * Simulate a hardware HUB by handling all the necessary requests.
3147  *------------------------------------------------------------------------*/
3148
3149 #define HSETW(ptr, val) ptr = { (uint8_t)(val), (uint8_t)((val) >> 8) }
3150
3151 static const
3152 struct usb_device_descriptor xhci_devd =
3153 {
3154         .bLength = sizeof(xhci_devd),
3155         .bDescriptorType = UDESC_DEVICE,        /* type */
3156         HSETW(.bcdUSB, 0x0300),                 /* USB version */
3157         .bDeviceClass = UDCLASS_HUB,            /* class */
3158         .bDeviceSubClass = UDSUBCLASS_HUB,      /* subclass */
3159         .bDeviceProtocol = UDPROTO_SSHUB,       /* protocol */
3160         .bMaxPacketSize = 9,                    /* max packet size */
3161         HSETW(.idVendor, 0x0000),               /* vendor */
3162         HSETW(.idProduct, 0x0000),              /* product */
3163         HSETW(.bcdDevice, 0x0100),              /* device version */
3164         .iManufacturer = 1,
3165         .iProduct = 2,
3166         .iSerialNumber = 0,
3167         .bNumConfigurations = 1,                /* # of configurations */
3168 };
3169
3170 static const
3171 struct xhci_bos_desc xhci_bosd = {
3172         .bosd = {
3173                 .bLength = sizeof(xhci_bosd.bosd),
3174                 .bDescriptorType = UDESC_BOS,
3175                 HSETW(.wTotalLength, sizeof(xhci_bosd)),
3176                 .bNumDeviceCaps = 3,
3177         },
3178         .usb2extd = {
3179                 .bLength = sizeof(xhci_bosd.usb2extd),
3180                 .bDescriptorType = 1,
3181                 .bDevCapabilityType = 2,
3182                 .bmAttributes[0] = 2,
3183         },
3184         .usbdcd = {
3185                 .bLength = sizeof(xhci_bosd.usbdcd),
3186                 .bDescriptorType = UDESC_DEVICE_CAPABILITY,
3187                 .bDevCapabilityType = 3,
3188                 .bmAttributes = 0, /* XXX */
3189                 HSETW(.wSpeedsSupported, 0x000C),
3190                 .bFunctionalitySupport = 8,
3191                 .bU1DevExitLat = 255,   /* dummy - not used */
3192                 .wU2DevExitLat = { 0x00, 0x08 },
3193         },
3194         .cidd = {
3195                 .bLength = sizeof(xhci_bosd.cidd),
3196                 .bDescriptorType = 1,
3197                 .bDevCapabilityType = 4,
3198                 .bReserved = 0,
3199                 .bContainerID = 0, /* XXX */
3200         },
3201 };
3202
3203 static const
3204 struct xhci_config_desc xhci_confd = {
3205         .confd = {
3206                 .bLength = sizeof(xhci_confd.confd),
3207                 .bDescriptorType = UDESC_CONFIG,
3208                 .wTotalLength[0] = sizeof(xhci_confd),
3209                 .bNumInterface = 1,
3210                 .bConfigurationValue = 1,
3211                 .iConfiguration = 0,
3212                 .bmAttributes = UC_SELF_POWERED,
3213                 .bMaxPower = 0          /* max power */
3214         },
3215         .ifcd = {
3216                 .bLength = sizeof(xhci_confd.ifcd),
3217                 .bDescriptorType = UDESC_INTERFACE,
3218                 .bNumEndpoints = 1,
3219                 .bInterfaceClass = UICLASS_HUB,
3220                 .bInterfaceSubClass = UISUBCLASS_HUB,
3221                 .bInterfaceProtocol = 0,
3222         },
3223         .endpd = {
3224                 .bLength = sizeof(xhci_confd.endpd),
3225                 .bDescriptorType = UDESC_ENDPOINT,
3226                 .bEndpointAddress = UE_DIR_IN | XHCI_INTR_ENDPT,
3227                 .bmAttributes = UE_INTERRUPT,
3228                 .wMaxPacketSize[0] = 2,         /* max 15 ports */
3229                 .bInterval = 255,
3230         },
3231         .endpcd = {
3232                 .bLength = sizeof(xhci_confd.endpcd),
3233                 .bDescriptorType = UDESC_ENDPOINT_SS_COMP,
3234                 .bMaxBurst = 0,
3235                 .bmAttributes = 0,
3236         },
3237 };
3238
3239 static const
3240 struct usb_hub_ss_descriptor xhci_hubd = {
3241         .bLength = sizeof(xhci_hubd),
3242         .bDescriptorType = UDESC_SS_HUB,
3243 };
3244
3245 static usb_error_t
3246 xhci_roothub_exec(struct usb_device *udev,
3247     struct usb_device_request *req, const void **pptr, uint16_t *plength)
3248 {
3249         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
3250         const char *str_ptr;
3251         const void *ptr;
3252         uint32_t port;
3253         uint32_t v;
3254         uint16_t len;
3255         uint16_t i;
3256         uint16_t value;
3257         uint16_t index;
3258         uint8_t j;
3259         usb_error_t err;
3260
3261         USB_BUS_LOCK_ASSERT(&sc->sc_bus, MA_OWNED);
3262
3263         /* buffer reset */
3264         ptr = (const void *)&sc->sc_hub_desc;
3265         len = 0;
3266         err = 0;
3267
3268         value = UGETW(req->wValue);
3269         index = UGETW(req->wIndex);
3270
3271         DPRINTFN(3, "type=0x%02x request=0x%02x wLen=0x%04x "
3272             "wValue=0x%04x wIndex=0x%04x\n",
3273             req->bmRequestType, req->bRequest,
3274             UGETW(req->wLength), value, index);
3275
3276 #define C(x,y) ((x) | ((y) << 8))
3277         switch (C(req->bRequest, req->bmRequestType)) {
3278         case C(UR_CLEAR_FEATURE, UT_WRITE_DEVICE):
3279         case C(UR_CLEAR_FEATURE, UT_WRITE_INTERFACE):
3280         case C(UR_CLEAR_FEATURE, UT_WRITE_ENDPOINT):
3281                 /*
3282                  * DEVICE_REMOTE_WAKEUP and ENDPOINT_HALT are no-ops
3283                  * for the integrated root hub.
3284                  */
3285                 break;
3286         case C(UR_GET_CONFIG, UT_READ_DEVICE):
3287                 len = 1;
3288                 sc->sc_hub_desc.temp[0] = sc->sc_conf;
3289                 break;
3290         case C(UR_GET_DESCRIPTOR, UT_READ_DEVICE):
3291                 switch (value >> 8) {
3292                 case UDESC_DEVICE:
3293                         if ((value & 0xff) != 0) {
3294                                 err = USB_ERR_IOERROR;
3295                                 goto done;
3296                         }
3297                         len = sizeof(xhci_devd);
3298                         ptr = (const void *)&xhci_devd;
3299                         break;
3300
3301                 case UDESC_BOS:
3302                         if ((value & 0xff) != 0) {
3303                                 err = USB_ERR_IOERROR;
3304                                 goto done;
3305                         }
3306                         len = sizeof(xhci_bosd);
3307                         ptr = (const void *)&xhci_bosd;
3308                         break;
3309
3310                 case UDESC_CONFIG:
3311                         if ((value & 0xff) != 0) {
3312                                 err = USB_ERR_IOERROR;
3313                                 goto done;
3314                         }
3315                         len = sizeof(xhci_confd);
3316                         ptr = (const void *)&xhci_confd;
3317                         break;
3318
3319                 case UDESC_STRING:
3320                         switch (value & 0xff) {
3321                         case 0: /* Language table */
3322                                 str_ptr = "\001";
3323                                 break;
3324
3325                         case 1: /* Vendor */
3326                                 str_ptr = sc->sc_vendor;
3327                                 break;
3328
3329                         case 2: /* Product */
3330                                 str_ptr = "XHCI root HUB";
3331                                 break;
3332
3333                         default:
3334                                 str_ptr = "";
3335                                 break;
3336                         }
3337
3338                         len = usb_make_str_desc(
3339                             sc->sc_hub_desc.temp,
3340                             sizeof(sc->sc_hub_desc.temp),
3341                             str_ptr);
3342                         break;
3343
3344                 default:
3345                         err = USB_ERR_IOERROR;
3346                         goto done;
3347                 }
3348                 break;
3349         case C(UR_GET_INTERFACE, UT_READ_INTERFACE):
3350                 len = 1;
3351                 sc->sc_hub_desc.temp[0] = 0;
3352                 break;
3353         case C(UR_GET_STATUS, UT_READ_DEVICE):
3354                 len = 2;
3355                 USETW(sc->sc_hub_desc.stat.wStatus, UDS_SELF_POWERED);
3356                 break;
3357         case C(UR_GET_STATUS, UT_READ_INTERFACE):
3358         case C(UR_GET_STATUS, UT_READ_ENDPOINT):
3359                 len = 2;
3360                 USETW(sc->sc_hub_desc.stat.wStatus, 0);
3361                 break;
3362         case C(UR_SET_ADDRESS, UT_WRITE_DEVICE):
3363                 if (value >= XHCI_MAX_DEVICES) {
3364                         err = USB_ERR_IOERROR;
3365                         goto done;
3366                 }
3367                 break;
3368         case C(UR_SET_CONFIG, UT_WRITE_DEVICE):
3369                 if (value != 0 && value != 1) {
3370                         err = USB_ERR_IOERROR;
3371                         goto done;
3372                 }
3373                 sc->sc_conf = value;
3374                 break;
3375         case C(UR_SET_DESCRIPTOR, UT_WRITE_DEVICE):
3376                 break;
3377         case C(UR_SET_FEATURE, UT_WRITE_DEVICE):
3378         case C(UR_SET_FEATURE, UT_WRITE_INTERFACE):
3379         case C(UR_SET_FEATURE, UT_WRITE_ENDPOINT):
3380                 err = USB_ERR_IOERROR;
3381                 goto done;
3382         case C(UR_SET_INTERFACE, UT_WRITE_INTERFACE):
3383                 break;
3384         case C(UR_SYNCH_FRAME, UT_WRITE_ENDPOINT):
3385                 break;
3386                 /* Hub requests */
3387         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_DEVICE):
3388                 break;
3389         case C(UR_CLEAR_FEATURE, UT_WRITE_CLASS_OTHER):
3390                 DPRINTFN(9, "UR_CLEAR_PORT_FEATURE\n");
3391
3392                 if ((index < 1) ||
3393                     (index > sc->sc_noport)) {
3394                         err = USB_ERR_IOERROR;
3395                         goto done;
3396                 }
3397                 port = XHCI_PORTSC(index);
3398
3399                 v = XREAD4(sc, oper, port);
3400                 i = XHCI_PS_PLS_GET(v);
3401                 v &= ~XHCI_PS_CLEAR;
3402
3403                 switch (value) {
3404                 case UHF_C_BH_PORT_RESET:
3405                         XWRITE4(sc, oper, port, v | XHCI_PS_WRC);
3406                         break;
3407                 case UHF_C_PORT_CONFIG_ERROR:
3408                         XWRITE4(sc, oper, port, v | XHCI_PS_CEC);
3409                         break;
3410                 case UHF_C_PORT_SUSPEND:
3411                 case UHF_C_PORT_LINK_STATE:
3412                         XWRITE4(sc, oper, port, v | XHCI_PS_PLC);
3413                         break;
3414                 case UHF_C_PORT_CONNECTION:
3415                         XWRITE4(sc, oper, port, v | XHCI_PS_CSC);
3416                         break;
3417                 case UHF_C_PORT_ENABLE:
3418                         XWRITE4(sc, oper, port, v | XHCI_PS_PEC);
3419                         break;
3420                 case UHF_C_PORT_OVER_CURRENT:
3421                         XWRITE4(sc, oper, port, v | XHCI_PS_OCC);
3422                         break;
3423                 case UHF_C_PORT_RESET:
3424                         XWRITE4(sc, oper, port, v | XHCI_PS_PRC);
3425                         break;
3426                 case UHF_PORT_ENABLE:
3427                         XWRITE4(sc, oper, port, v | XHCI_PS_PED);
3428                         break;
3429                 case UHF_PORT_POWER:
3430                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PP);
3431                         break;
3432                 case UHF_PORT_INDICATOR:
3433                         XWRITE4(sc, oper, port, v & ~XHCI_PS_PIC_SET(3));
3434                         break;
3435                 case UHF_PORT_SUSPEND:
3436
3437                         /* U3 -> U15 */
3438                         if (i == 3) {
3439                                 XWRITE4(sc, oper, port, v |
3440                                     XHCI_PS_PLS_SET(0xF) | XHCI_PS_LWS);
3441                         }
3442
3443                         /* wait 20ms for resume sequence to complete */
3444                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 50);
3445
3446                         /* U0 */
3447                         XWRITE4(sc, oper, port, v |
3448                             XHCI_PS_PLS_SET(0) | XHCI_PS_LWS);
3449                         break;
3450                 default:
3451                         err = USB_ERR_IOERROR;
3452                         goto done;
3453                 }
3454                 break;
3455
3456         case C(UR_GET_DESCRIPTOR, UT_READ_CLASS_DEVICE):
3457                 if ((value & 0xff) != 0) {
3458                         err = USB_ERR_IOERROR;
3459                         goto done;
3460                 }
3461
3462                 v = XREAD4(sc, capa, XHCI_HCSPARAMS0);
3463
3464                 sc->sc_hub_desc.hubd = xhci_hubd;
3465
3466                 sc->sc_hub_desc.hubd.bNbrPorts = sc->sc_noport;
3467
3468                 if (XHCI_HCS0_PPC(v))
3469                         i = UHD_PWR_INDIVIDUAL;
3470                 else
3471                         i = UHD_PWR_GANGED;
3472
3473                 if (XHCI_HCS0_PIND(v))
3474                         i |= UHD_PORT_IND;
3475
3476                 i |= UHD_OC_INDIVIDUAL;
3477
3478                 USETW(sc->sc_hub_desc.hubd.wHubCharacteristics, i);
3479
3480                 /* see XHCI section 5.4.9: */
3481                 sc->sc_hub_desc.hubd.bPwrOn2PwrGood = 10;
3482
3483                 for (j = 1; j <= sc->sc_noport; j++) {
3484
3485                         v = XREAD4(sc, oper, XHCI_PORTSC(j));
3486                         if (v & XHCI_PS_DR) {
3487                                 sc->sc_hub_desc.hubd.
3488                                     DeviceRemovable[j / 8] |= 1U << (j % 8);
3489                         }
3490                 }
3491                 len = sc->sc_hub_desc.hubd.bLength;
3492                 break;
3493
3494         case C(UR_GET_STATUS, UT_READ_CLASS_DEVICE):
3495                 len = 16;
3496                 memset(sc->sc_hub_desc.temp, 0, 16);
3497                 break;
3498
3499         case C(UR_GET_STATUS, UT_READ_CLASS_OTHER):
3500                 DPRINTFN(9, "UR_GET_STATUS i=%d\n", index);
3501
3502                 if ((index < 1) ||
3503                     (index > sc->sc_noport)) {
3504                         err = USB_ERR_IOERROR;
3505                         goto done;
3506                 }
3507
3508                 v = XREAD4(sc, oper, XHCI_PORTSC(index));
3509
3510                 DPRINTFN(9, "port status=0x%08x\n", v);
3511
3512                 i = UPS_PORT_LINK_STATE_SET(XHCI_PS_PLS_GET(v));
3513
3514                 switch (XHCI_PS_SPEED_GET(v)) {
3515                 case 3:
3516                         i |= UPS_HIGH_SPEED;
3517                         break;
3518                 case 2:
3519                         i |= UPS_LOW_SPEED;
3520                         break;
3521                 case 1:
3522                         /* FULL speed */
3523                         break;
3524                 default:
3525                         i |= UPS_OTHER_SPEED;
3526                         break;
3527                 }
3528
3529                 if (v & XHCI_PS_CCS)
3530                         i |= UPS_CURRENT_CONNECT_STATUS;
3531                 if (v & XHCI_PS_PED)
3532                         i |= UPS_PORT_ENABLED;
3533                 if (v & XHCI_PS_OCA)
3534                         i |= UPS_OVERCURRENT_INDICATOR;
3535                 if (v & XHCI_PS_PR)
3536                         i |= UPS_RESET;
3537                 if (v & XHCI_PS_PP) {
3538                         /*
3539                          * The USB 3.0 RH is using the
3540                          * USB 2.0's power bit
3541                          */
3542                         i |= UPS_PORT_POWER;
3543                 }
3544                 USETW(sc->sc_hub_desc.ps.wPortStatus, i);
3545
3546                 i = 0;
3547                 if (v & XHCI_PS_CSC)
3548                         i |= UPS_C_CONNECT_STATUS;
3549                 if (v & XHCI_PS_PEC)
3550                         i |= UPS_C_PORT_ENABLED;
3551                 if (v & XHCI_PS_OCC)
3552                         i |= UPS_C_OVERCURRENT_INDICATOR;
3553                 if (v & XHCI_PS_WRC)
3554                         i |= UPS_C_BH_PORT_RESET;
3555                 if (v & XHCI_PS_PRC)
3556                         i |= UPS_C_PORT_RESET;
3557                 if (v & XHCI_PS_PLC)
3558                         i |= UPS_C_PORT_LINK_STATE;
3559                 if (v & XHCI_PS_CEC)
3560                         i |= UPS_C_PORT_CONFIG_ERROR;
3561
3562                 USETW(sc->sc_hub_desc.ps.wPortChange, i);
3563                 len = sizeof(sc->sc_hub_desc.ps);
3564                 break;
3565
3566         case C(UR_SET_DESCRIPTOR, UT_WRITE_CLASS_DEVICE):
3567                 err = USB_ERR_IOERROR;
3568                 goto done;
3569
3570         case C(UR_SET_FEATURE, UT_WRITE_CLASS_DEVICE):
3571                 break;
3572
3573         case C(UR_SET_FEATURE, UT_WRITE_CLASS_OTHER):
3574
3575                 i = index >> 8;
3576                 index &= 0x00FF;
3577
3578                 if ((index < 1) ||
3579                     (index > sc->sc_noport)) {
3580                         err = USB_ERR_IOERROR;
3581                         goto done;
3582                 }
3583
3584                 port = XHCI_PORTSC(index);
3585                 v = XREAD4(sc, oper, port) & ~XHCI_PS_CLEAR;
3586
3587                 switch (value) {
3588                 case UHF_PORT_U1_TIMEOUT:
3589                         if (XHCI_PS_SPEED_GET(v) != 4) {
3590                                 err = USB_ERR_IOERROR;
3591                                 goto done;
3592                         }
3593                         port = XHCI_PORTPMSC(index);
3594                         v = XREAD4(sc, oper, port);
3595                         v &= ~XHCI_PM3_U1TO_SET(0xFF);
3596                         v |= XHCI_PM3_U1TO_SET(i);
3597                         XWRITE4(sc, oper, port, v);
3598                         break;
3599                 case UHF_PORT_U2_TIMEOUT:
3600                         if (XHCI_PS_SPEED_GET(v) != 4) {
3601                                 err = USB_ERR_IOERROR;
3602                                 goto done;
3603                         }
3604                         port = XHCI_PORTPMSC(index);
3605                         v = XREAD4(sc, oper, port);
3606                         v &= ~XHCI_PM3_U2TO_SET(0xFF);
3607                         v |= XHCI_PM3_U2TO_SET(i);
3608                         XWRITE4(sc, oper, port, v);
3609                         break;
3610                 case UHF_BH_PORT_RESET:
3611                         XWRITE4(sc, oper, port, v | XHCI_PS_WPR);
3612                         break;
3613                 case UHF_PORT_LINK_STATE:
3614                         XWRITE4(sc, oper, port, v |
3615                             XHCI_PS_PLS_SET(i) | XHCI_PS_LWS);
3616                         /* 4ms settle time */
3617                         usb_pause_mtx(&sc->sc_bus.bus_mtx, hz / 250);
3618                         break;
3619                 case UHF_PORT_ENABLE:
3620                         DPRINTFN(3, "set port enable %d\n", index);
3621                         break;
3622                 case UHF_PORT_SUSPEND:
3623                         DPRINTFN(6, "suspend port %u (LPM=%u)\n", index, i);
3624                         j = XHCI_PS_SPEED_GET(v);
3625                         if ((j < 1) || (j > 3)) {
3626                                 /* non-supported speed */
3627                                 err = USB_ERR_IOERROR;
3628                                 goto done;
3629                         }
3630                         XWRITE4(sc, oper, port, v |
3631                             XHCI_PS_PLS_SET(i ? 2 /* LPM */ : 3) | XHCI_PS_LWS);
3632                         break;
3633                 case UHF_PORT_RESET:
3634                         DPRINTFN(6, "reset port %d\n", index);
3635                         XWRITE4(sc, oper, port, v | XHCI_PS_PR);
3636                         break;
3637                 case UHF_PORT_POWER:
3638                         DPRINTFN(3, "set port power %d\n", index);
3639                         XWRITE4(sc, oper, port, v | XHCI_PS_PP);
3640                         break;
3641                 case UHF_PORT_TEST:
3642                         DPRINTFN(3, "set port test %d\n", index);
3643                         break;
3644                 case UHF_PORT_INDICATOR:
3645                         DPRINTFN(3, "set port indicator %d\n", index);
3646
3647                         v &= ~XHCI_PS_PIC_SET(3);
3648                         v |= XHCI_PS_PIC_SET(1);
3649
3650                         XWRITE4(sc, oper, port, v);
3651                         break;
3652                 default:
3653                         err = USB_ERR_IOERROR;
3654                         goto done;
3655                 }
3656                 break;
3657
3658         case C(UR_CLEAR_TT_BUFFER, UT_WRITE_CLASS_OTHER):
3659         case C(UR_RESET_TT, UT_WRITE_CLASS_OTHER):
3660         case C(UR_GET_TT_STATE, UT_READ_CLASS_OTHER):
3661         case C(UR_STOP_TT, UT_WRITE_CLASS_OTHER):
3662                 break;
3663         default:
3664                 err = USB_ERR_IOERROR;
3665                 goto done;
3666         }
3667 done:
3668         *plength = len;
3669         *pptr = ptr;
3670         return (err);
3671 }
3672
3673 static void
3674 xhci_xfer_setup(struct usb_setup_params *parm)
3675 {
3676         struct usb_page_search page_info;
3677         struct usb_page_cache *pc;
3678         struct xhci_softc *sc;
3679         struct usb_xfer *xfer;
3680         void *last_obj;
3681         uint32_t ntd;
3682         uint32_t n;
3683
3684         sc = XHCI_BUS2SC(parm->udev->bus);
3685         xfer = parm->curr_xfer;
3686
3687         /*
3688          * The proof for the "ntd" formula is illustrated like this:
3689          *
3690          * +------------------------------------+
3691          * |                                    |
3692          * |         |remainder ->              |
3693          * |   +-----+---+                      |
3694          * |   | xxx | x | frm 0                |
3695          * |   +-----+---++                     |
3696          * |   | xxx | xx | frm 1               |
3697          * |   +-----+----+                     |
3698          * |            ...                     |
3699          * +------------------------------------+
3700          *
3701          * "xxx" means a completely full USB transfer descriptor
3702          *
3703          * "x" and "xx" means a short USB packet
3704          *
3705          * For the remainder of an USB transfer modulo
3706          * "max_data_length" we need two USB transfer descriptors.
3707          * One to transfer the remaining data and one to finalise with
3708          * a zero length packet in case the "force_short_xfer" flag is
3709          * set. We only need two USB transfer descriptors in the case
3710          * where the transfer length of the first one is a factor of
3711          * "max_frame_size". The rest of the needed USB transfer
3712          * descriptors is given by the buffer size divided by the
3713          * maximum data payload.
3714          */
3715         parm->hc_max_packet_size = 0x400;
3716         parm->hc_max_packet_count = 16 * 3;
3717         parm->hc_max_frame_size = XHCI_TD_PAYLOAD_MAX;
3718
3719         xfer->flags_int.bdma_enable = 1;
3720
3721         usbd_transfer_setup_sub(parm);
3722
3723         if (xfer->flags_int.isochronous_xfr) {
3724                 ntd = ((1 * xfer->nframes)
3725                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3726         } else if (xfer->flags_int.control_xfr) {
3727                 ntd = ((2 * xfer->nframes) + 1  /* STATUS */
3728                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3729         } else {
3730                 ntd = ((2 * xfer->nframes)
3731                     + (xfer->max_data_length / xfer->max_hc_frame_size));
3732         }
3733
3734 alloc_dma_set:
3735
3736         if (parm->err)
3737                 return;
3738
3739         /*
3740          * Allocate queue heads and transfer descriptors
3741          */
3742         last_obj = NULL;
3743
3744         if (usbd_transfer_setup_sub_malloc(
3745             parm, &pc, sizeof(struct xhci_td),
3746             XHCI_TD_ALIGN, ntd)) {
3747                 parm->err = USB_ERR_NOMEM;
3748                 return;
3749         }
3750         if (parm->buf) {
3751                 for (n = 0; n != ntd; n++) {
3752                         struct xhci_td *td;
3753
3754                         usbd_get_page(pc + n, 0, &page_info);
3755
3756                         td = page_info.buffer;
3757
3758                         /* init TD */
3759                         td->td_self = page_info.physaddr;
3760                         td->obj_next = last_obj;
3761                         td->page_cache = pc + n;
3762
3763                         last_obj = td;
3764
3765                         usb_pc_cpu_flush(pc + n);
3766                 }
3767         }
3768         xfer->td_start[xfer->flags_int.curr_dma_set] = last_obj;
3769
3770         if (!xfer->flags_int.curr_dma_set) {
3771                 xfer->flags_int.curr_dma_set = 1;
3772                 goto alloc_dma_set;
3773         }
3774 }
3775
3776 static usb_error_t
3777 xhci_configure_reset_endpoint(struct usb_xfer *xfer)
3778 {
3779         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3780         struct usb_page_search buf_inp;
3781         struct usb_device *udev;
3782         struct xhci_endpoint_ext *pepext;
3783         struct usb_endpoint_descriptor *edesc;
3784         struct usb_page_cache *pcinp;
3785         usb_error_t err;
3786         usb_stream_t stream_id;
3787         uint8_t index;
3788         uint8_t epno;
3789
3790         pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3791             xfer->endpoint->edesc);
3792
3793         udev = xfer->xroot->udev;
3794         index = udev->controller_slot_id;
3795
3796         pcinp = &sc->sc_hw.devs[index].input_pc;
3797
3798         usbd_get_page(pcinp, 0, &buf_inp);
3799
3800         edesc = xfer->endpoint->edesc;
3801
3802         epno = edesc->bEndpointAddress;
3803         stream_id = xfer->stream_id;
3804
3805         if ((edesc->bmAttributes & UE_XFERTYPE) == UE_CONTROL)
3806                 epno |= UE_DIR_IN;
3807
3808         epno = XHCI_EPNO2EPID(epno);
3809
3810         if (epno == 0)
3811                 return (USB_ERR_NO_PIPE);               /* invalid */
3812
3813         XHCI_CMD_LOCK(sc);
3814
3815         /* configure endpoint */
3816
3817         err = xhci_configure_endpoint_by_xfer(xfer);
3818
3819         if (err != 0) {
3820                 XHCI_CMD_UNLOCK(sc);
3821                 return (err);
3822         }
3823
3824         /*
3825          * Get the endpoint into the stopped state according to the
3826          * endpoint context state diagram in the XHCI specification:
3827          */
3828
3829         err = xhci_cmd_stop_ep(sc, 0, epno, index);
3830
3831         if (err != 0)
3832                 DPRINTF("Could not stop endpoint %u\n", epno);
3833
3834         err = xhci_cmd_reset_ep(sc, 0, epno, index);
3835
3836         if (err != 0)
3837                 DPRINTF("Could not reset endpoint %u\n", epno);
3838
3839         err = xhci_cmd_set_tr_dequeue_ptr(sc,
3840             (pepext->physaddr + (stream_id * sizeof(struct xhci_trb) *
3841             XHCI_MAX_TRANSFERS)) | XHCI_EPCTX_2_DCS_SET(1),
3842             stream_id, epno, index);
3843
3844         if (err != 0)
3845                 DPRINTF("Could not set dequeue ptr for endpoint %u\n", epno);
3846
3847         /*
3848          * Get the endpoint into the running state according to the
3849          * endpoint context state diagram in the XHCI specification:
3850          */
3851
3852         xhci_configure_mask(udev, (1U << epno) | 1U, 0);
3853
3854         err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
3855
3856         if (err != 0)
3857                 DPRINTF("Could not configure endpoint %u\n", epno);
3858
3859         err = xhci_cmd_configure_ep(sc, buf_inp.physaddr, 0, index);
3860
3861         if (err != 0)
3862                 DPRINTF("Could not configure endpoint %u\n", epno);
3863
3864         XHCI_CMD_UNLOCK(sc);
3865
3866         return (0);
3867 }
3868
3869 static void
3870 xhci_xfer_unsetup(struct usb_xfer *xfer)
3871 {
3872         return;
3873 }
3874
3875 static void
3876 xhci_start_dma_delay(struct usb_xfer *xfer)
3877 {
3878         struct xhci_softc *sc = XHCI_BUS2SC(xfer->xroot->bus);
3879
3880         /* put transfer on interrupt queue (again) */
3881         usbd_transfer_enqueue(&sc->sc_bus.intr_q, xfer);
3882
3883         (void)usb_proc_msignal(USB_BUS_CONTROL_XFER_PROC(&sc->sc_bus),
3884             &sc->sc_config_msg[0], &sc->sc_config_msg[1]);
3885 }
3886
3887 static void
3888 xhci_configure_msg(struct usb_proc_msg *pm)
3889 {
3890         struct xhci_softc *sc;
3891         struct xhci_endpoint_ext *pepext;
3892         struct usb_xfer *xfer;
3893
3894         sc = XHCI_BUS2SC(((struct usb_bus_msg *)pm)->bus);
3895
3896 restart:
3897         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3898
3899                 pepext = xhci_get_endpoint_ext(xfer->xroot->udev,
3900                     xfer->endpoint->edesc);
3901
3902                 if ((pepext->trb_halted != 0) ||
3903                     (pepext->trb_running == 0)) {
3904
3905                         uint16_t i;
3906
3907                         /* clear halted and running */
3908                         pepext->trb_halted = 0;
3909                         pepext->trb_running = 0;
3910
3911                         /* nuke remaining buffered transfers */
3912
3913                         for (i = 0; i != (XHCI_MAX_TRANSFERS *
3914                             XHCI_MAX_STREAMS); i++) {
3915                                 /*
3916                                  * NOTE: We need to use the timeout
3917                                  * error code here else existing
3918                                  * isochronous clients can get
3919                                  * confused:
3920                                  */
3921                                 if (pepext->xfer[i] != NULL) {
3922                                         xhci_device_done(pepext->xfer[i],
3923                                             USB_ERR_TIMEOUT);
3924                                 }
3925                         }
3926
3927                         /*
3928                          * NOTE: The USB transfer cannot vanish in
3929                          * this state!
3930                          */
3931
3932                         USB_BUS_UNLOCK(&sc->sc_bus);
3933
3934                         xhci_configure_reset_endpoint(xfer);
3935
3936                         USB_BUS_LOCK(&sc->sc_bus);
3937
3938                         /* check if halted is still cleared */
3939                         if (pepext->trb_halted == 0) {
3940                                 pepext->trb_running = 1;
3941                                 memset(pepext->trb_index, 0,
3942                                     sizeof(pepext->trb_index));
3943                         }
3944                         goto restart;
3945                 }
3946
3947                 if (xfer->flags_int.did_dma_delay) {
3948
3949                         /* remove transfer from interrupt queue (again) */
3950                         usbd_transfer_dequeue(xfer);
3951
3952                         /* we are finally done */
3953                         usb_dma_delay_done_cb(xfer);
3954
3955                         /* queue changed - restart */
3956                         goto restart;
3957                 }
3958         }
3959
3960         TAILQ_FOREACH(xfer, &sc->sc_bus.intr_q.head, wait_entry) {
3961
3962                 /* try to insert xfer on HW queue */
3963                 xhci_transfer_insert(xfer);
3964
3965                 /* try to multi buffer */
3966                 xhci_device_generic_multi_enter(xfer->endpoint,
3967                     xfer->stream_id, NULL);
3968         }
3969 }
3970
3971 static void
3972 xhci_ep_init(struct usb_device *udev, struct usb_endpoint_descriptor *edesc,
3973     struct usb_endpoint *ep)
3974 {
3975         struct xhci_endpoint_ext *pepext;
3976
3977         DPRINTFN(2, "endpoint=%p, addr=%d, endpt=%d, mode=%d\n",
3978             ep, udev->address, edesc->bEndpointAddress, udev->flags.usb_mode);
3979
3980         if (udev->parent_hub == NULL) {
3981                 /* root HUB has special endpoint handling */
3982                 return;
3983         }
3984
3985         ep->methods = &xhci_device_generic_methods;
3986
3987         pepext = xhci_get_endpoint_ext(udev, edesc);
3988
3989         USB_BUS_LOCK(udev->bus);
3990         pepext->trb_halted = 1;
3991         pepext->trb_running = 0;
3992         USB_BUS_UNLOCK(udev->bus);
3993 }
3994
3995 static void
3996 xhci_ep_uninit(struct usb_device *udev, struct usb_endpoint *ep)
3997 {
3998
3999 }
4000
4001 static void
4002 xhci_ep_clear_stall(struct usb_device *udev, struct usb_endpoint *ep)
4003 {
4004         struct xhci_endpoint_ext *pepext;
4005
4006         DPRINTF("\n");
4007
4008         if (udev->flags.usb_mode != USB_MODE_HOST) {
4009                 /* not supported */
4010                 return;
4011         }
4012         if (udev->parent_hub == NULL) {
4013                 /* root HUB has special endpoint handling */
4014                 return;
4015         }
4016
4017         pepext = xhci_get_endpoint_ext(udev, ep->edesc);
4018
4019         USB_BUS_LOCK(udev->bus);
4020         pepext->trb_halted = 1;
4021         pepext->trb_running = 0;
4022         USB_BUS_UNLOCK(udev->bus);
4023 }
4024
4025 static usb_error_t
4026 xhci_device_init(struct usb_device *udev)
4027 {
4028         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4029         usb_error_t err;
4030         uint8_t temp;
4031
4032         /* no init for root HUB */
4033         if (udev->parent_hub == NULL)
4034                 return (0);
4035
4036         XHCI_CMD_LOCK(sc);
4037
4038         /* set invalid default */
4039
4040         udev->controller_slot_id = sc->sc_noslot + 1;
4041
4042         /* try to get a new slot ID from the XHCI */
4043
4044         err = xhci_cmd_enable_slot(sc, &temp);
4045
4046         if (err) {
4047                 XHCI_CMD_UNLOCK(sc);
4048                 return (err);
4049         }
4050
4051         if (temp > sc->sc_noslot) {
4052                 XHCI_CMD_UNLOCK(sc);
4053                 return (USB_ERR_BAD_ADDRESS);
4054         }
4055
4056         if (sc->sc_hw.devs[temp].state != XHCI_ST_DISABLED) {
4057                 DPRINTF("slot %u already allocated.\n", temp);
4058                 XHCI_CMD_UNLOCK(sc);
4059                 return (USB_ERR_BAD_ADDRESS);
4060         }
4061
4062         /* store slot ID for later reference */
4063
4064         udev->controller_slot_id = temp;
4065
4066         /* reset data structure */
4067
4068         memset(&sc->sc_hw.devs[temp], 0, sizeof(sc->sc_hw.devs[0]));
4069
4070         /* set mark slot allocated */
4071
4072         sc->sc_hw.devs[temp].state = XHCI_ST_ENABLED;
4073
4074         err = xhci_alloc_device_ext(udev);
4075
4076         XHCI_CMD_UNLOCK(sc);
4077
4078         /* get device into default state */
4079
4080         if (err == 0)
4081                 err = xhci_set_address(udev, NULL, 0);
4082
4083         return (err);
4084 }
4085
4086 static void
4087 xhci_device_uninit(struct usb_device *udev)
4088 {
4089         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4090         uint8_t index;
4091
4092         /* no init for root HUB */
4093         if (udev->parent_hub == NULL)
4094                 return;
4095
4096         XHCI_CMD_LOCK(sc);
4097
4098         index = udev->controller_slot_id;
4099
4100         if (index <= sc->sc_noslot) {
4101                 xhci_cmd_disable_slot(sc, index);
4102                 sc->sc_hw.devs[index].state = XHCI_ST_DISABLED;
4103
4104                 /* free device extension */
4105                 xhci_free_device_ext(udev);
4106         }
4107
4108         XHCI_CMD_UNLOCK(sc);
4109 }
4110
4111 static void
4112 xhci_get_dma_delay(struct usb_device *udev, uint32_t *pus)
4113 {
4114         /*
4115          * Wait until the hardware has finished any possible use of
4116          * the transfer descriptor(s)
4117          */
4118         *pus = 2048;                    /* microseconds */
4119 }
4120
4121 static void
4122 xhci_device_resume(struct usb_device *udev)
4123 {
4124         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4125         uint8_t index;
4126         uint8_t n;
4127         uint8_t p;
4128
4129         DPRINTF("\n");
4130
4131         /* check for root HUB */
4132         if (udev->parent_hub == NULL)
4133                 return;
4134
4135         index = udev->controller_slot_id;
4136
4137         XHCI_CMD_LOCK(sc);
4138
4139         /* blindly resume all endpoints */
4140
4141         USB_BUS_LOCK(udev->bus);
4142
4143         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4144                 for (p = 0; p != XHCI_MAX_STREAMS; p++) {
4145                         XWRITE4(sc, door, XHCI_DOORBELL(index),
4146                             n | XHCI_DB_SID_SET(p));
4147                 }
4148         }
4149
4150         USB_BUS_UNLOCK(udev->bus);
4151
4152         XHCI_CMD_UNLOCK(sc);
4153 }
4154
4155 static void
4156 xhci_device_suspend(struct usb_device *udev)
4157 {
4158         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4159         uint8_t index;
4160         uint8_t n;
4161         usb_error_t err;
4162
4163         DPRINTF("\n");
4164
4165         /* check for root HUB */
4166         if (udev->parent_hub == NULL)
4167                 return;
4168
4169         index = udev->controller_slot_id;
4170
4171         XHCI_CMD_LOCK(sc);
4172
4173         /* blindly suspend all endpoints */
4174
4175         for (n = 1; n != XHCI_MAX_ENDPOINTS; n++) {
4176                 err = xhci_cmd_stop_ep(sc, 1, n, index);
4177                 if (err != 0) {
4178                         DPRINTF("Failed to suspend endpoint "
4179                             "%u on slot %u (ignored).\n", n, index);
4180                 }
4181         }
4182
4183         XHCI_CMD_UNLOCK(sc);
4184 }
4185
4186 static void
4187 xhci_set_hw_power(struct usb_bus *bus)
4188 {
4189         DPRINTF("\n");
4190 }
4191
4192 static void
4193 xhci_device_state_change(struct usb_device *udev)
4194 {
4195         struct xhci_softc *sc = XHCI_BUS2SC(udev->bus);
4196         struct usb_page_search buf_inp;
4197         usb_error_t err;
4198         uint8_t index;
4199
4200         /* check for root HUB */
4201         if (udev->parent_hub == NULL)
4202                 return;
4203
4204         index = udev->controller_slot_id;
4205
4206         DPRINTF("\n");
4207
4208         if (usb_get_device_state(udev) == USB_STATE_CONFIGURED) {
4209                 err = uhub_query_info(udev, &sc->sc_hw.devs[index].nports,
4210                     &sc->sc_hw.devs[index].tt);
4211                 if (err != 0)
4212                         sc->sc_hw.devs[index].nports = 0;
4213         }
4214
4215         XHCI_CMD_LOCK(sc);
4216
4217         switch (usb_get_device_state(udev)) {
4218         case USB_STATE_POWERED:
4219                 if (sc->sc_hw.devs[index].state == XHCI_ST_DEFAULT)
4220                         break;
4221
4222                 /* set default state */
4223                 sc->sc_hw.devs[index].state = XHCI_ST_DEFAULT;
4224
4225                 /* reset number of contexts */
4226                 sc->sc_hw.devs[index].context_num = 0;
4227
4228                 err = xhci_cmd_reset_dev(sc, index);
4229
4230                 if (err != 0) {
4231                         DPRINTF("Device reset failed "
4232                             "for slot %u.\n", index);
4233                 }
4234                 break;
4235
4236         case USB_STATE_ADDRESSED:
4237                 if (sc->sc_hw.devs[index].state == XHCI_ST_ADDRESSED)
4238                         break;
4239
4240                 sc->sc_hw.devs[index].state = XHCI_ST_ADDRESSED;
4241
4242                 err = xhci_cmd_configure_ep(sc, 0, 1, index);
4243
4244                 if (err) {
4245                         DPRINTF("Failed to deconfigure "
4246                             "slot %u.\n", index);
4247                 }
4248                 break;
4249
4250         case USB_STATE_CONFIGURED:
4251                 if (sc->sc_hw.devs[index].state == XHCI_ST_CONFIGURED)
4252                         break;
4253
4254                 /* set configured state */
4255                 sc->sc_hw.devs[index].state = XHCI_ST_CONFIGURED;
4256
4257                 /* reset number of contexts */
4258                 sc->sc_hw.devs[index].context_num = 0;
4259
4260                 usbd_get_page(&sc->sc_hw.devs[index].input_pc, 0, &buf_inp);
4261
4262                 xhci_configure_mask(udev, 3, 0);
4263
4264                 err = xhci_configure_device(udev);
4265                 if (err != 0) {
4266                         DPRINTF("Could not configure device "
4267                             "at slot %u.\n", index);
4268                 }
4269
4270                 err = xhci_cmd_evaluate_ctx(sc, buf_inp.physaddr, index);
4271                 if (err != 0) {
4272                         DPRINTF("Could not evaluate device "
4273                             "context at slot %u.\n", index);
4274                 }
4275                 break;
4276
4277         default:
4278                 break;
4279         }
4280         XHCI_CMD_UNLOCK(sc);
4281 }
4282
4283 static usb_error_t
4284 xhci_set_endpoint_mode(struct usb_device *udev, struct usb_endpoint *ep,
4285     uint8_t ep_mode)
4286 {
4287         switch (ep_mode) {
4288         case USB_EP_MODE_DEFAULT:
4289                 return (0);
4290         case USB_EP_MODE_STREAMS:
4291                 if (xhcistreams == 0 ||
4292                     (ep->edesc->bmAttributes & UE_XFERTYPE) != UE_BULK ||
4293                     udev->speed != USB_SPEED_SUPER)
4294                         return (USB_ERR_INVAL);
4295                 return (0);
4296         default:
4297                 return (USB_ERR_INVAL);
4298         }
4299 }
4300
4301 struct usb_bus_methods xhci_bus_methods = {
4302         .endpoint_init = xhci_ep_init,
4303         .endpoint_uninit = xhci_ep_uninit,
4304         .xfer_setup = xhci_xfer_setup,
4305         .xfer_unsetup = xhci_xfer_unsetup,
4306         .get_dma_delay = xhci_get_dma_delay,
4307         .device_init = xhci_device_init,
4308         .device_uninit = xhci_device_uninit,
4309         .device_resume = xhci_device_resume,
4310         .device_suspend = xhci_device_suspend,
4311         .set_hw_power = xhci_set_hw_power,
4312         .roothub_exec = xhci_roothub_exec,
4313         .xfer_poll = xhci_do_poll,
4314         .start_dma_delay = xhci_start_dma_delay,
4315         .set_address = xhci_set_address,
4316         .clear_stall = xhci_ep_clear_stall,
4317         .device_state_change = xhci_device_state_change,
4318         .set_hw_power_sleep = xhci_set_hw_power_sleep,
4319         .set_endpoint_mode = xhci_set_endpoint_mode,
4320 };