2 * Copyright (c) 2008 Weongyo Jeong <weongyo@FreeBSD.org>
4 * Permission to use, copy, modify, and distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
17 #include <sys/cdefs.h>
18 __FBSDID("$FreeBSD$");
19 #include <sys/param.h>
20 #include <sys/sockio.h>
21 #include <sys/sysctl.h>
23 #include <sys/mutex.h>
25 #include <sys/kernel.h>
26 #include <sys/socket.h>
27 #include <sys/systm.h>
28 #include <sys/malloc.h>
29 #include <sys/module.h>
31 #include <sys/endian.h>
35 #include <net/if_arp.h>
36 #include <net/ethernet.h>
37 #include <net/if_dl.h>
38 #include <net/if_media.h>
39 #include <net/if_types.h>
42 #include <netinet/in.h>
43 #include <netinet/in_systm.h>
44 #include <netinet/in_var.h>
45 #include <netinet/if_ether.h>
46 #include <netinet/ip.h>
49 #include <net80211/ieee80211_var.h>
50 #include <net80211/ieee80211_regdomain.h>
51 #include <net80211/ieee80211_radiotap.h>
53 #include <dev/usb/usb.h>
54 #include <dev/usb/usbdi.h>
57 #include <dev/usb/wlan/if_urtwreg.h>
58 #include <dev/usb/wlan/if_urtwvar.h>
60 static SYSCTL_NODE(_hw_usb, OID_AUTO, urtw, CTLFLAG_RW, 0, "USB Realtek 8187L");
63 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, debug, CTLFLAG_RW | CTLFLAG_TUN, &urtw_debug, 0,
64 "control debugging printfs");
65 TUNABLE_INT("hw.usb.urtw.debug", &urtw_debug);
67 URTW_DEBUG_XMIT = 0x00000001, /* basic xmit operation */
68 URTW_DEBUG_RECV = 0x00000002, /* basic recv operation */
69 URTW_DEBUG_RESET = 0x00000004, /* reset processing */
70 URTW_DEBUG_TX_PROC = 0x00000008, /* tx ISR proc */
71 URTW_DEBUG_RX_PROC = 0x00000010, /* rx ISR proc */
72 URTW_DEBUG_STATE = 0x00000020, /* 802.11 state transitions */
73 URTW_DEBUG_STAT = 0x00000040, /* statistic */
74 URTW_DEBUG_INIT = 0x00000080, /* initialization of dev */
75 URTW_DEBUG_TXSTATUS = 0x00000100, /* tx status */
76 URTW_DEBUG_ANY = 0xffffffff
78 #define DPRINTF(sc, m, fmt, ...) do { \
79 if (sc->sc_debug & (m)) \
80 printf(fmt, __VA_ARGS__); \
83 #define DPRINTF(sc, m, fmt, ...) do { \
87 static int urtw_preamble_mode = URTW_PREAMBLE_MODE_LONG;
88 SYSCTL_INT(_hw_usb_urtw, OID_AUTO, preamble_mode, CTLFLAG_RW | CTLFLAG_TUN,
89 &urtw_preamble_mode, 0, "set the preable mode (long or short)");
90 TUNABLE_INT("hw.usb.urtw.preamble_mode", &urtw_preamble_mode);
92 /* recognized device vendors/products */
93 #define urtw_lookup(v, p) \
94 ((const struct urtw_type *)usb_lookup(urtw_devs, v, p))
95 #define URTW_DEV_B(v,p) \
96 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187B) }
97 #define URTW_DEV_L(v,p) \
98 { USB_VPI(USB_VENDOR_##v, USB_PRODUCT_##v##_##p, URTW_REV_RTL8187L) }
99 #define URTW_REV_RTL8187B 0
100 #define URTW_REV_RTL8187L 1
101 static const STRUCT_USB_HOST_ID urtw_devs[] = {
102 URTW_DEV_B(NETGEAR, WG111V3),
103 URTW_DEV_B(REALTEK, RTL8187B_0),
104 URTW_DEV_B(REALTEK, RTL8187B_1),
105 URTW_DEV_B(REALTEK, RTL8187B_2),
106 URTW_DEV_B(SITECOMEU, WL168V4),
107 URTW_DEV_L(ASUS, P5B_WIFI),
108 URTW_DEV_L(BELKIN, F5D7050E),
109 URTW_DEV_L(LINKSYS4, WUSB54GCV2),
110 URTW_DEV_L(NETGEAR, WG111V2),
111 URTW_DEV_L(REALTEK, RTL8187),
112 URTW_DEV_L(SITECOMEU, WL168V1),
113 URTW_DEV_L(SURECOM, EP9001G2A),
114 { USB_VPI(USB_VENDOR_OVISLINK, 0x8187, URTW_REV_RTL8187L) },
115 { USB_VPI(USB_VENDOR_DICKSMITH, 0x9401, URTW_REV_RTL8187L) },
116 { USB_VPI(USB_VENDOR_HP, 0xca02, URTW_REV_RTL8187L) },
117 { USB_VPI(USB_VENDOR_LOGITEC, 0x010c, URTW_REV_RTL8187L) },
118 { USB_VPI(USB_VENDOR_NETGEAR, 0x6100, URTW_REV_RTL8187L) },
119 { USB_VPI(USB_VENDOR_SPHAIRON, 0x0150, URTW_REV_RTL8187L) },
120 { USB_VPI(USB_VENDOR_QCOM, 0x6232, URTW_REV_RTL8187L) },
125 #define urtw_read8_m(sc, val, data) do { \
126 error = urtw_read8_c(sc, val, data); \
130 #define urtw_write8_m(sc, val, data) do { \
131 error = urtw_write8_c(sc, val, data); \
135 #define urtw_read16_m(sc, val, data) do { \
136 error = urtw_read16_c(sc, val, data); \
140 #define urtw_write16_m(sc, val, data) do { \
141 error = urtw_write16_c(sc, val, data); \
145 #define urtw_read32_m(sc, val, data) do { \
146 error = urtw_read32_c(sc, val, data); \
150 #define urtw_write32_m(sc, val, data) do { \
151 error = urtw_write32_c(sc, val, data); \
155 #define urtw_8187_write_phy_ofdm(sc, val, data) do { \
156 error = urtw_8187_write_phy_ofdm_c(sc, val, data); \
160 #define urtw_8187_write_phy_cck(sc, val, data) do { \
161 error = urtw_8187_write_phy_cck_c(sc, val, data); \
165 #define urtw_8225_write(sc, val, data) do { \
166 error = urtw_8225_write_c(sc, val, data); \
176 static uint8_t urtw_8225_agc[] = {
177 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9e, 0x9d, 0x9c, 0x9b,
178 0x9a, 0x99, 0x98, 0x97, 0x96, 0x95, 0x94, 0x93, 0x92, 0x91, 0x90,
179 0x8f, 0x8e, 0x8d, 0x8c, 0x8b, 0x8a, 0x89, 0x88, 0x87, 0x86, 0x85,
180 0x84, 0x83, 0x82, 0x81, 0x80, 0x3f, 0x3e, 0x3d, 0x3c, 0x3b, 0x3a,
181 0x39, 0x38, 0x37, 0x36, 0x35, 0x34, 0x33, 0x32, 0x31, 0x30, 0x2f,
182 0x2e, 0x2d, 0x2c, 0x2b, 0x2a, 0x29, 0x28, 0x27, 0x26, 0x25, 0x24,
183 0x23, 0x22, 0x21, 0x20, 0x1f, 0x1e, 0x1d, 0x1c, 0x1b, 0x1a, 0x19,
184 0x18, 0x17, 0x16, 0x15, 0x14, 0x13, 0x12, 0x11, 0x10, 0x0f, 0x0e,
185 0x0d, 0x0c, 0x0b, 0x0a, 0x09, 0x08, 0x07, 0x06, 0x05, 0x04, 0x03,
186 0x02, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
187 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01,
188 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01
191 static uint8_t urtw_8225z2_agc[] = {
192 0x5e, 0x5e, 0x5e, 0x5e, 0x5d, 0x5b, 0x59, 0x57, 0x55, 0x53, 0x51,
193 0x4f, 0x4d, 0x4b, 0x49, 0x47, 0x45, 0x43, 0x41, 0x3f, 0x3d, 0x3b,
194 0x39, 0x37, 0x35, 0x33, 0x31, 0x2f, 0x2d, 0x2b, 0x29, 0x27, 0x25,
195 0x23, 0x21, 0x1f, 0x1d, 0x1b, 0x19, 0x17, 0x15, 0x13, 0x11, 0x0f,
196 0x0d, 0x0b, 0x09, 0x07, 0x05, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01,
197 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x19, 0x19,
198 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x19, 0x20, 0x21, 0x22, 0x23,
199 0x24, 0x25, 0x26, 0x26, 0x27, 0x27, 0x28, 0x28, 0x29, 0x2a, 0x2a,
200 0x2a, 0x2b, 0x2b, 0x2b, 0x2c, 0x2c, 0x2c, 0x2d, 0x2d, 0x2d, 0x2d,
201 0x2e, 0x2e, 0x2e, 0x2e, 0x2f, 0x2f, 0x2f, 0x30, 0x30, 0x31, 0x31,
202 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31,
203 0x31, 0x31, 0x31, 0x31, 0x31, 0x31, 0x31
206 static uint32_t urtw_8225_channel[] = {
207 0x0000, /* dummy channel 0 */
224 static uint8_t urtw_8225_gain[] = {
225 0x23, 0x88, 0x7c, 0xa5, /* -82dbm */
226 0x23, 0x88, 0x7c, 0xb5, /* -82dbm */
227 0x23, 0x88, 0x7c, 0xc5, /* -82dbm */
228 0x33, 0x80, 0x79, 0xc5, /* -78dbm */
229 0x43, 0x78, 0x76, 0xc5, /* -74dbm */
230 0x53, 0x60, 0x73, 0xc5, /* -70dbm */
231 0x63, 0x58, 0x70, 0xc5, /* -66dbm */
234 static struct urtw_pair urtw_8225_rf_part1[] = {
235 { 0x00, 0x0067 }, { 0x01, 0x0fe0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
236 { 0x04, 0x0486 }, { 0x05, 0x0bc0 }, { 0x06, 0x0ae6 }, { 0x07, 0x082a },
237 { 0x08, 0x001f }, { 0x09, 0x0334 }, { 0x0a, 0x0fd4 }, { 0x0b, 0x0391 },
238 { 0x0c, 0x0050 }, { 0x0d, 0x06db }, { 0x0e, 0x0029 }, { 0x0f, 0x0914 },
241 static struct urtw_pair urtw_8225_rf_part2[] = {
242 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
243 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
244 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x09 }, { 0x0b, 0x80 },
245 { 0x0c, 0x01 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 }, { 0x10, 0x84 },
246 { 0x11, 0x06 }, { 0x12, 0x20 }, { 0x13, 0x20 }, { 0x14, 0x00 },
247 { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 }, { 0x18, 0xef },
248 { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x76 }, { 0x1c, 0x04 },
249 { 0x1e, 0x95 }, { 0x1f, 0x75 }, { 0x20, 0x1f }, { 0x21, 0x27 },
250 { 0x22, 0x16 }, { 0x24, 0x46 }, { 0x25, 0x20 }, { 0x26, 0x90 },
254 static struct urtw_pair urtw_8225_rf_part3[] = {
255 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
256 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x10, 0x9b },
257 { 0x11, 0x88 }, { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 },
258 { 0x1a, 0xa0 }, { 0x1b, 0x08 }, { 0x40, 0x86 }, { 0x41, 0x8d },
259 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x1f }, { 0x45, 0x1e },
260 { 0x46, 0x1a }, { 0x47, 0x15 }, { 0x48, 0x10 }, { 0x49, 0x0a },
261 { 0x4a, 0x05 }, { 0x4b, 0x02 }, { 0x4c, 0x05 }
264 static uint16_t urtw_8225_rxgain[] = {
265 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
266 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
267 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
268 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
269 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
270 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
271 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
272 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
273 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
274 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
275 0x07aa, 0x07ab, 0x07ac, 0x07ad, 0x07b0, 0x07b1, 0x07b2, 0x07b3,
276 0x07b4, 0x07b5, 0x07b8, 0x07b9, 0x07ba, 0x07bb, 0x07bb
279 static uint8_t urtw_8225_threshold[] = {
280 0x8d, 0x8d, 0x8d, 0x8d, 0x9d, 0xad, 0xbd,
283 static uint8_t urtw_8225_tx_gain_cck_ofdm[] = {
284 0x02, 0x06, 0x0e, 0x1e, 0x3e, 0x7e
287 static uint8_t urtw_8225_txpwr_cck[] = {
288 0x18, 0x17, 0x15, 0x11, 0x0c, 0x08, 0x04, 0x02,
289 0x1b, 0x1a, 0x17, 0x13, 0x0e, 0x09, 0x04, 0x02,
290 0x1f, 0x1e, 0x1a, 0x15, 0x10, 0x0a, 0x05, 0x02,
291 0x22, 0x21, 0x1d, 0x18, 0x11, 0x0b, 0x06, 0x02,
292 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03,
293 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03
296 static uint8_t urtw_8225_txpwr_cck_ch14[] = {
297 0x18, 0x17, 0x15, 0x0c, 0x00, 0x00, 0x00, 0x00,
298 0x1b, 0x1a, 0x17, 0x0e, 0x00, 0x00, 0x00, 0x00,
299 0x1f, 0x1e, 0x1a, 0x0f, 0x00, 0x00, 0x00, 0x00,
300 0x22, 0x21, 0x1d, 0x11, 0x00, 0x00, 0x00, 0x00,
301 0x26, 0x25, 0x21, 0x13, 0x00, 0x00, 0x00, 0x00,
302 0x2b, 0x2a, 0x25, 0x15, 0x00, 0x00, 0x00, 0x00
305 static uint8_t urtw_8225_txpwr_ofdm[]={
306 0x80, 0x90, 0xa2, 0xb5, 0xcb, 0xe4
309 static uint8_t urtw_8225v2_gain_bg[]={
310 0x23, 0x15, 0xa5, /* -82-1dbm */
311 0x23, 0x15, 0xb5, /* -82-2dbm */
312 0x23, 0x15, 0xc5, /* -82-3dbm */
313 0x33, 0x15, 0xc5, /* -78dbm */
314 0x43, 0x15, 0xc5, /* -74dbm */
315 0x53, 0x15, 0xc5, /* -70dbm */
316 0x63, 0x15, 0xc5, /* -66dbm */
319 static struct urtw_pair urtw_8225v2_rf_part1[] = {
320 { 0x00, 0x02bf }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
321 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
322 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
323 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
326 static struct urtw_pair urtw_8225v2b_rf_part0[] = {
327 { 0x00, 0x00b7 }, { 0x01, 0x0ee0 }, { 0x02, 0x044d }, { 0x03, 0x0441 },
328 { 0x04, 0x08c3 }, { 0x05, 0x0c72 }, { 0x06, 0x00e6 }, { 0x07, 0x082a },
329 { 0x08, 0x003f }, { 0x09, 0x0335 }, { 0x0a, 0x09d4 }, { 0x0b, 0x07bb },
330 { 0x0c, 0x0850 }, { 0x0d, 0x0cdf }, { 0x0e, 0x002b }, { 0x0f, 0x0114 }
333 static struct urtw_pair urtw_8225v2b_rf_part1[] = {
334 {0x0f0, 0x32}, {0x0f1, 0x32}, {0x0f2, 0x00},
335 {0x0f3, 0x00}, {0x0f4, 0x32}, {0x0f5, 0x43},
336 {0x0f6, 0x00}, {0x0f7, 0x00}, {0x0f8, 0x46},
337 {0x0f9, 0xa4}, {0x0fa, 0x00}, {0x0fb, 0x00},
338 {0x0fc, 0x96}, {0x0fd, 0xa4}, {0x0fe, 0x00},
339 {0x0ff, 0x00}, {0x158, 0x4b}, {0x159, 0x00},
340 {0x15a, 0x4b}, {0x15b, 0x00}, {0x160, 0x4b},
341 {0x161, 0x09}, {0x162, 0x4b}, {0x163, 0x09},
342 {0x1ce, 0x0f}, {0x1cf, 0x00}, {0x1e0, 0xff},
343 {0x1e1, 0x0f}, {0x1e2, 0x00}, {0x1f0, 0x4e},
344 {0x1f1, 0x01}, {0x1f2, 0x02}, {0x1f3, 0x03},
345 {0x1f4, 0x04}, {0x1f5, 0x05}, {0x1f6, 0x06},
346 {0x1f7, 0x07}, {0x1f8, 0x08}, {0x24e, 0x00},
347 {0x20c, 0x04}, {0x221, 0x61}, {0x222, 0x68},
348 {0x223, 0x6f}, {0x224, 0x76}, {0x225, 0x7d},
349 {0x226, 0x84}, {0x227, 0x8d}, {0x24d, 0x08},
350 {0x250, 0x05}, {0x251, 0xf5}, {0x252, 0x04},
351 {0x253, 0xa0}, {0x254, 0x1f}, {0x255, 0x23},
352 {0x256, 0x45}, {0x257, 0x67}, {0x258, 0x08},
353 {0x259, 0x08}, {0x25a, 0x08}, {0x25b, 0x08},
354 {0x260, 0x08}, {0x261, 0x08}, {0x262, 0x08},
355 {0x263, 0x08}, {0x264, 0xcf}, {0x272, 0x56},
356 {0x273, 0x9a}, {0x034, 0xf0}, {0x035, 0x0f},
357 {0x05b, 0x40}, {0x084, 0x88}, {0x085, 0x24},
358 {0x088, 0x54}, {0x08b, 0xb8}, {0x08c, 0x07},
359 {0x08d, 0x00}, {0x094, 0x1b}, {0x095, 0x12},
360 {0x096, 0x00}, {0x097, 0x06}, {0x09d, 0x1a},
361 {0x09f, 0x10}, {0x0b4, 0x22}, {0x0be, 0x80},
362 {0x0db, 0x00}, {0x0ee, 0x00}, {0x091, 0x03},
363 {0x24c, 0x00}, {0x39f, 0x00}, {0x08c, 0x01},
364 {0x08d, 0x10}, {0x08e, 0x08}, {0x08f, 0x00}
367 static struct urtw_pair urtw_8225v2_rf_part2[] = {
368 { 0x00, 0x01 }, { 0x01, 0x02 }, { 0x02, 0x42 }, { 0x03, 0x00 },
369 { 0x04, 0x00 }, { 0x05, 0x00 }, { 0x06, 0x40 }, { 0x07, 0x00 },
370 { 0x08, 0x40 }, { 0x09, 0xfe }, { 0x0a, 0x08 }, { 0x0b, 0x80 },
371 { 0x0c, 0x01 }, { 0x0d, 0x43 }, { 0x0e, 0xd3 }, { 0x0f, 0x38 },
372 { 0x10, 0x84 }, { 0x11, 0x07 }, { 0x12, 0x20 }, { 0x13, 0x20 },
373 { 0x14, 0x00 }, { 0x15, 0x40 }, { 0x16, 0x00 }, { 0x17, 0x40 },
374 { 0x18, 0xef }, { 0x19, 0x19 }, { 0x1a, 0x20 }, { 0x1b, 0x15 },
375 { 0x1c, 0x04 }, { 0x1d, 0xc5 }, { 0x1e, 0x95 }, { 0x1f, 0x75 },
376 { 0x20, 0x1f }, { 0x21, 0x17 }, { 0x22, 0x16 }, { 0x23, 0x80 },
377 { 0x24, 0x46 }, { 0x25, 0x00 }, { 0x26, 0x90 }, { 0x27, 0x88 }
380 static struct urtw_pair urtw_8225v2b_rf_part2[] = {
381 { 0x00, 0x10 }, { 0x01, 0x0d }, { 0x02, 0x01 }, { 0x03, 0x00 },
382 { 0x04, 0x14 }, { 0x05, 0xfb }, { 0x06, 0xfb }, { 0x07, 0x60 },
383 { 0x08, 0x00 }, { 0x09, 0x60 }, { 0x0a, 0x00 }, { 0x0b, 0x00 },
384 { 0x0c, 0x00 }, { 0x0d, 0x5c }, { 0x0e, 0x00 }, { 0x0f, 0x00 },
385 { 0x10, 0x40 }, { 0x11, 0x00 }, { 0x12, 0x40 }, { 0x13, 0x00 },
386 { 0x14, 0x00 }, { 0x15, 0x00 }, { 0x16, 0xa8 }, { 0x17, 0x26 },
387 { 0x18, 0x32 }, { 0x19, 0x33 }, { 0x1a, 0x07 }, { 0x1b, 0xa5 },
388 { 0x1c, 0x6f }, { 0x1d, 0x55 }, { 0x1e, 0xc8 }, { 0x1f, 0xb3 },
389 { 0x20, 0x0a }, { 0x21, 0xe1 }, { 0x22, 0x2C }, { 0x23, 0x8a },
390 { 0x24, 0x86 }, { 0x25, 0x83 }, { 0x26, 0x34 }, { 0x27, 0x0f },
391 { 0x28, 0x4f }, { 0x29, 0x24 }, { 0x2a, 0x6f }, { 0x2b, 0xc2 },
392 { 0x2c, 0x6b }, { 0x2d, 0x40 }, { 0x2e, 0x80 }, { 0x2f, 0x00 },
393 { 0x30, 0xc0 }, { 0x31, 0xc1 }, { 0x32, 0x58 }, { 0x33, 0xf1 },
394 { 0x34, 0x00 }, { 0x35, 0xe4 }, { 0x36, 0x90 }, { 0x37, 0x3e },
395 { 0x38, 0x6d }, { 0x39, 0x3c }, { 0x3a, 0xfb }, { 0x3b, 0x07 }
398 static struct urtw_pair urtw_8225v2_rf_part3[] = {
399 { 0x00, 0x98 }, { 0x03, 0x20 }, { 0x04, 0x7e }, { 0x05, 0x12 },
400 { 0x06, 0xfc }, { 0x07, 0x78 }, { 0x08, 0x2e }, { 0x09, 0x11 },
401 { 0x0a, 0x17 }, { 0x0b, 0x11 }, { 0x10, 0x9b }, { 0x11, 0x88 },
402 { 0x12, 0x47 }, { 0x13, 0xd0 }, { 0x19, 0x00 }, { 0x1a, 0xa0 },
403 { 0x1b, 0x08 }, { 0x1d, 0x00 }, { 0x40, 0x86 }, { 0x41, 0x9d },
404 { 0x42, 0x15 }, { 0x43, 0x18 }, { 0x44, 0x36 }, { 0x45, 0x35 },
405 { 0x46, 0x2e }, { 0x47, 0x25 }, { 0x48, 0x1c }, { 0x49, 0x12 },
406 { 0x4a, 0x09 }, { 0x4b, 0x04 }, { 0x4c, 0x05 }
409 static uint16_t urtw_8225v2_rxgain[] = {
410 0x0000, 0x0001, 0x0002, 0x0003, 0x0004, 0x0005, 0x0008, 0x0009,
411 0x000a, 0x000b, 0x0102, 0x0103, 0x0104, 0x0105, 0x0140, 0x0141,
412 0x0142, 0x0143, 0x0144, 0x0145, 0x0180, 0x0181, 0x0182, 0x0183,
413 0x0184, 0x0185, 0x0188, 0x0189, 0x018a, 0x018b, 0x0243, 0x0244,
414 0x0245, 0x0280, 0x0281, 0x0282, 0x0283, 0x0284, 0x0285, 0x0288,
415 0x0289, 0x028a, 0x028b, 0x028c, 0x0342, 0x0343, 0x0344, 0x0345,
416 0x0380, 0x0381, 0x0382, 0x0383, 0x0384, 0x0385, 0x0388, 0x0389,
417 0x038a, 0x038b, 0x038c, 0x038d, 0x0390, 0x0391, 0x0392, 0x0393,
418 0x0394, 0x0395, 0x0398, 0x0399, 0x039a, 0x039b, 0x039c, 0x039d,
419 0x03a0, 0x03a1, 0x03a2, 0x03a3, 0x03a4, 0x03a5, 0x03a8, 0x03a9,
420 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
421 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
424 static uint16_t urtw_8225v2b_rxgain[] = {
425 0x0400, 0x0401, 0x0402, 0x0403, 0x0404, 0x0405, 0x0408, 0x0409,
426 0x040a, 0x040b, 0x0502, 0x0503, 0x0504, 0x0505, 0x0540, 0x0541,
427 0x0542, 0x0543, 0x0544, 0x0545, 0x0580, 0x0581, 0x0582, 0x0583,
428 0x0584, 0x0585, 0x0588, 0x0589, 0x058a, 0x058b, 0x0643, 0x0644,
429 0x0645, 0x0680, 0x0681, 0x0682, 0x0683, 0x0684, 0x0685, 0x0688,
430 0x0689, 0x068a, 0x068b, 0x068c, 0x0742, 0x0743, 0x0744, 0x0745,
431 0x0780, 0x0781, 0x0782, 0x0783, 0x0784, 0x0785, 0x0788, 0x0789,
432 0x078a, 0x078b, 0x078c, 0x078d, 0x0790, 0x0791, 0x0792, 0x0793,
433 0x0794, 0x0795, 0x0798, 0x0799, 0x079a, 0x079b, 0x079c, 0x079d,
434 0x07a0, 0x07a1, 0x07a2, 0x07a3, 0x07a4, 0x07a5, 0x07a8, 0x07a9,
435 0x03aa, 0x03ab, 0x03ac, 0x03ad, 0x03b0, 0x03b1, 0x03b2, 0x03b3,
436 0x03b4, 0x03b5, 0x03b8, 0x03b9, 0x03ba, 0x03bb, 0x03bb
439 static uint8_t urtw_8225v2_tx_gain_cck_ofdm[] = {
440 0x00, 0x01, 0x02, 0x03, 0x04, 0x05,
441 0x06, 0x07, 0x08, 0x09, 0x0a, 0x0b,
442 0x0c, 0x0d, 0x0e, 0x0f, 0x10, 0x11,
443 0x12, 0x13, 0x14, 0x15, 0x16, 0x17,
444 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d,
445 0x1e, 0x1f, 0x20, 0x21, 0x22, 0x23,
448 static uint8_t urtw_8225v2_txpwr_cck[] = {
449 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04
452 static uint8_t urtw_8225v2_txpwr_cck_ch14[] = {
453 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00
456 static uint8_t urtw_8225v2b_txpwr_cck[] = {
457 0x36, 0x35, 0x2e, 0x25, 0x1c, 0x12, 0x09, 0x04,
458 0x30, 0x2f, 0x29, 0x21, 0x19, 0x10, 0x08, 0x03,
459 0x2b, 0x2a, 0x25, 0x1e, 0x16, 0x0e, 0x07, 0x03,
460 0x26, 0x25, 0x21, 0x1b, 0x14, 0x0d, 0x06, 0x03
463 static uint8_t urtw_8225v2b_txpwr_cck_ch14[] = {
464 0x36, 0x35, 0x2e, 0x1b, 0x00, 0x00, 0x00, 0x00,
465 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
466 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00,
467 0x30, 0x2f, 0x29, 0x15, 0x00, 0x00, 0x00, 0x00
470 static struct urtw_pair urtw_ratetable[] = {
471 { 2, 0 }, { 4, 1 }, { 11, 2 }, { 12, 4 }, { 18, 5 },
472 { 22, 3 }, { 24, 6 }, { 36, 7 }, { 48, 8 }, { 72, 9 },
473 { 96, 10 }, { 108, 11 }
477 static const uint8_t urtw_8187b_reg_table[][3] = {
478 { 0xf0, 0x32, 0 }, { 0xf1, 0x32, 0 }, { 0xf2, 0x00, 0 },
479 { 0xf3, 0x00, 0 }, { 0xf4, 0x32, 0 }, { 0xf5, 0x43, 0 },
480 { 0xf6, 0x00, 0 }, { 0xf7, 0x00, 0 }, { 0xf8, 0x46, 0 },
481 { 0xf9, 0xa4, 0 }, { 0xfa, 0x00, 0 }, { 0xfb, 0x00, 0 },
482 { 0xfc, 0x96, 0 }, { 0xfd, 0xa4, 0 }, { 0xfe, 0x00, 0 },
483 { 0xff, 0x00, 0 }, { 0x58, 0x4b, 1 }, { 0x59, 0x00, 1 },
484 { 0x5a, 0x4b, 1 }, { 0x5b, 0x00, 1 }, { 0x60, 0x4b, 1 },
485 { 0x61, 0x09, 1 }, { 0x62, 0x4b, 1 }, { 0x63, 0x09, 1 },
486 { 0xce, 0x0f, 1 }, { 0xcf, 0x00, 1 }, { 0xe0, 0xff, 1 },
487 { 0xe1, 0x0f, 1 }, { 0xe2, 0x00, 1 }, { 0xf0, 0x4e, 1 },
488 { 0xf1, 0x01, 1 }, { 0xf2, 0x02, 1 }, { 0xf3, 0x03, 1 },
489 { 0xf4, 0x04, 1 }, { 0xf5, 0x05, 1 }, { 0xf6, 0x06, 1 },
490 { 0xf7, 0x07, 1 }, { 0xf8, 0x08, 1 }, { 0x4e, 0x00, 2 },
491 { 0x0c, 0x04, 2 }, { 0x21, 0x61, 2 }, { 0x22, 0x68, 2 },
492 { 0x23, 0x6f, 2 }, { 0x24, 0x76, 2 }, { 0x25, 0x7d, 2 },
493 { 0x26, 0x84, 2 }, { 0x27, 0x8d, 2 }, { 0x4d, 0x08, 2 },
494 { 0x50, 0x05, 2 }, { 0x51, 0xf5, 2 }, { 0x52, 0x04, 2 },
495 { 0x53, 0xa0, 2 }, { 0x54, 0x1f, 2 }, { 0x55, 0x23, 2 },
496 { 0x56, 0x45, 2 }, { 0x57, 0x67, 2 }, { 0x58, 0x08, 2 },
497 { 0x59, 0x08, 2 }, { 0x5a, 0x08, 2 }, { 0x5b, 0x08, 2 },
498 { 0x60, 0x08, 2 }, { 0x61, 0x08, 2 }, { 0x62, 0x08, 2 },
499 { 0x63, 0x08, 2 }, { 0x64, 0xcf, 2 }, { 0x72, 0x56, 2 },
500 { 0x73, 0x9a, 2 }, { 0x34, 0xf0, 0 }, { 0x35, 0x0f, 0 },
501 { 0x5b, 0x40, 0 }, { 0x84, 0x88, 0 }, { 0x85, 0x24, 0 },
502 { 0x88, 0x54, 0 }, { 0x8b, 0xb8, 0 }, { 0x8c, 0x07, 0 },
503 { 0x8d, 0x00, 0 }, { 0x94, 0x1b, 0 }, { 0x95, 0x12, 0 },
504 { 0x96, 0x00, 0 }, { 0x97, 0x06, 0 }, { 0x9d, 0x1a, 0 },
505 { 0x9f, 0x10, 0 }, { 0xb4, 0x22, 0 }, { 0xbe, 0x80, 0 },
506 { 0xdb, 0x00, 0 }, { 0xee, 0x00, 0 }, { 0x91, 0x03, 0 },
507 { 0x4c, 0x00, 2 }, { 0x9f, 0x00, 3 }, { 0x8c, 0x01, 0 },
508 { 0x8d, 0x10, 0 }, { 0x8e, 0x08, 0 }, { 0x8f, 0x00, 0 }
512 static usb_callback_t urtw_bulk_rx_callback;
513 static usb_callback_t urtw_bulk_tx_callback;
514 static usb_callback_t urtw_bulk_tx_status_callback;
516 static const struct usb_config urtw_8187b_usbconfig[URTW_8187B_N_XFERS] = {
517 [URTW_8187B_BULK_RX] = {
520 .direction = UE_DIR_IN,
527 .callback = urtw_bulk_rx_callback
529 [URTW_8187B_BULK_TX_STATUS] = {
532 .direction = UE_DIR_IN,
533 .bufsize = sizeof(uint64_t),
538 .callback = urtw_bulk_tx_status_callback
540 [URTW_8187B_BULK_TX_BE] = {
542 .endpoint = URTW_8187B_TXPIPE_BE,
543 .direction = UE_DIR_OUT,
544 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
546 .force_short_xfer = 1,
549 .callback = urtw_bulk_tx_callback,
550 .timeout = URTW_DATA_TIMEOUT
552 [URTW_8187B_BULK_TX_BK] = {
554 .endpoint = URTW_8187B_TXPIPE_BK,
555 .direction = UE_DIR_OUT,
556 .bufsize = URTW_TX_MAXSIZE,
559 .force_short_xfer = 1,
562 .callback = urtw_bulk_tx_callback,
563 .timeout = URTW_DATA_TIMEOUT
565 [URTW_8187B_BULK_TX_VI] = {
567 .endpoint = URTW_8187B_TXPIPE_VI,
568 .direction = UE_DIR_OUT,
569 .bufsize = URTW_TX_MAXSIZE,
572 .force_short_xfer = 1,
575 .callback = urtw_bulk_tx_callback,
576 .timeout = URTW_DATA_TIMEOUT
578 [URTW_8187B_BULK_TX_VO] = {
580 .endpoint = URTW_8187B_TXPIPE_VO,
581 .direction = UE_DIR_OUT,
582 .bufsize = URTW_TX_MAXSIZE,
585 .force_short_xfer = 1,
588 .callback = urtw_bulk_tx_callback,
589 .timeout = URTW_DATA_TIMEOUT
591 [URTW_8187B_BULK_TX_EP12] = {
594 .direction = UE_DIR_OUT,
595 .bufsize = URTW_TX_MAXSIZE,
598 .force_short_xfer = 1,
601 .callback = urtw_bulk_tx_callback,
602 .timeout = URTW_DATA_TIMEOUT
606 static const struct usb_config urtw_8187l_usbconfig[URTW_8187L_N_XFERS] = {
607 [URTW_8187L_BULK_RX] = {
610 .direction = UE_DIR_IN,
617 .callback = urtw_bulk_rx_callback
619 [URTW_8187L_BULK_TX_LOW] = {
622 .direction = UE_DIR_OUT,
623 .bufsize = URTW_TX_MAXSIZE * URTW_TX_DATA_LIST_COUNT,
625 .force_short_xfer = 1,
628 .callback = urtw_bulk_tx_callback,
629 .timeout = URTW_DATA_TIMEOUT
631 [URTW_8187L_BULK_TX_NORMAL] = {
634 .direction = UE_DIR_OUT,
635 .bufsize = URTW_TX_MAXSIZE,
638 .force_short_xfer = 1,
641 .callback = urtw_bulk_tx_callback,
642 .timeout = URTW_DATA_TIMEOUT
646 static struct ieee80211vap *urtw_vap_create(struct ieee80211com *,
647 const char [IFNAMSIZ], int, enum ieee80211_opmode,
648 int, const uint8_t [IEEE80211_ADDR_LEN],
649 const uint8_t [IEEE80211_ADDR_LEN]);
650 static void urtw_vap_delete(struct ieee80211vap *);
651 static void urtw_init(void *);
652 static void urtw_stop(struct ifnet *);
653 static void urtw_stop_locked(struct ifnet *);
654 static int urtw_ioctl(struct ifnet *, u_long, caddr_t);
655 static void urtw_start(struct ifnet *);
656 static int urtw_alloc_rx_data_list(struct urtw_softc *);
657 static int urtw_alloc_tx_data_list(struct urtw_softc *);
658 static int urtw_raw_xmit(struct ieee80211_node *, struct mbuf *,
659 const struct ieee80211_bpf_params *);
660 static void urtw_scan_start(struct ieee80211com *);
661 static void urtw_scan_end(struct ieee80211com *);
662 static void urtw_set_channel(struct ieee80211com *);
663 static void urtw_update_mcast(struct ifnet *);
664 static int urtw_tx_start(struct urtw_softc *,
665 struct ieee80211_node *, struct mbuf *,
666 struct urtw_data *, int);
667 static int urtw_newstate(struct ieee80211vap *,
668 enum ieee80211_state, int);
669 static void urtw_led_ch(void *);
670 static void urtw_ledtask(void *, int);
671 static void urtw_watchdog(void *);
672 static void urtw_set_multi(void *);
673 static int urtw_isbmode(uint16_t);
674 static uint16_t urtw_rate2rtl(uint32_t);
675 static uint16_t urtw_rtl2rate(uint32_t);
676 static usb_error_t urtw_set_rate(struct urtw_softc *);
677 static usb_error_t urtw_update_msr(struct urtw_softc *);
678 static usb_error_t urtw_read8_c(struct urtw_softc *, int, uint8_t *);
679 static usb_error_t urtw_read16_c(struct urtw_softc *, int, uint16_t *);
680 static usb_error_t urtw_read32_c(struct urtw_softc *, int, uint32_t *);
681 static usb_error_t urtw_write8_c(struct urtw_softc *, int, uint8_t);
682 static usb_error_t urtw_write16_c(struct urtw_softc *, int, uint16_t);
683 static usb_error_t urtw_write32_c(struct urtw_softc *, int, uint32_t);
684 static usb_error_t urtw_eprom_cs(struct urtw_softc *, int);
685 static usb_error_t urtw_eprom_ck(struct urtw_softc *);
686 static usb_error_t urtw_eprom_sendbits(struct urtw_softc *, int16_t *,
688 static usb_error_t urtw_eprom_read32(struct urtw_softc *, uint32_t,
690 static usb_error_t urtw_eprom_readbit(struct urtw_softc *, int16_t *);
691 static usb_error_t urtw_eprom_writebit(struct urtw_softc *, int16_t);
692 static usb_error_t urtw_get_macaddr(struct urtw_softc *);
693 static usb_error_t urtw_get_txpwr(struct urtw_softc *);
694 static usb_error_t urtw_get_rfchip(struct urtw_softc *);
695 static usb_error_t urtw_led_init(struct urtw_softc *);
696 static usb_error_t urtw_8185_rf_pins_enable(struct urtw_softc *);
697 static usb_error_t urtw_8185_tx_antenna(struct urtw_softc *, uint8_t);
698 static usb_error_t urtw_8187_write_phy(struct urtw_softc *, uint8_t,
700 static usb_error_t urtw_8187_write_phy_ofdm_c(struct urtw_softc *,
702 static usb_error_t urtw_8187_write_phy_cck_c(struct urtw_softc *, uint8_t,
704 static usb_error_t urtw_8225_setgain(struct urtw_softc *, int16_t);
705 static usb_error_t urtw_8225_usb_init(struct urtw_softc *);
706 static usb_error_t urtw_8225_write_c(struct urtw_softc *, uint8_t,
708 static usb_error_t urtw_8225_write_s16(struct urtw_softc *, uint8_t, int,
710 static usb_error_t urtw_8225_read(struct urtw_softc *, uint8_t,
712 static usb_error_t urtw_8225_rf_init(struct urtw_softc *);
713 static usb_error_t urtw_8225_rf_set_chan(struct urtw_softc *, int);
714 static usb_error_t urtw_8225_rf_set_sens(struct urtw_softc *, int);
715 static usb_error_t urtw_8225_set_txpwrlvl(struct urtw_softc *, int);
716 static usb_error_t urtw_8225_rf_stop(struct urtw_softc *);
717 static usb_error_t urtw_8225v2_rf_init(struct urtw_softc *);
718 static usb_error_t urtw_8225v2_rf_set_chan(struct urtw_softc *, int);
719 static usb_error_t urtw_8225v2_set_txpwrlvl(struct urtw_softc *, int);
720 static usb_error_t urtw_8225v2_setgain(struct urtw_softc *, int16_t);
721 static usb_error_t urtw_8225_isv2(struct urtw_softc *, int *);
722 static usb_error_t urtw_8225v2b_rf_init(struct urtw_softc *);
723 static usb_error_t urtw_8225v2b_rf_set_chan(struct urtw_softc *, int);
724 static usb_error_t urtw_read8e(struct urtw_softc *, int, uint8_t *);
725 static usb_error_t urtw_write8e(struct urtw_softc *, int, uint8_t);
726 static usb_error_t urtw_8180_set_anaparam(struct urtw_softc *, uint32_t);
727 static usb_error_t urtw_8185_set_anaparam2(struct urtw_softc *, uint32_t);
728 static usb_error_t urtw_intr_enable(struct urtw_softc *);
729 static usb_error_t urtw_intr_disable(struct urtw_softc *);
730 static usb_error_t urtw_reset(struct urtw_softc *);
731 static usb_error_t urtw_led_on(struct urtw_softc *, int);
732 static usb_error_t urtw_led_ctl(struct urtw_softc *, int);
733 static usb_error_t urtw_led_blink(struct urtw_softc *);
734 static usb_error_t urtw_led_mode0(struct urtw_softc *, int);
735 static usb_error_t urtw_led_mode1(struct urtw_softc *, int);
736 static usb_error_t urtw_led_mode2(struct urtw_softc *, int);
737 static usb_error_t urtw_led_mode3(struct urtw_softc *, int);
738 static usb_error_t urtw_rx_setconf(struct urtw_softc *);
739 static usb_error_t urtw_rx_enable(struct urtw_softc *);
740 static usb_error_t urtw_tx_enable(struct urtw_softc *sc);
741 static void urtw_free_tx_data_list(struct urtw_softc *);
742 static void urtw_free_rx_data_list(struct urtw_softc *);
743 static void urtw_free_data_list(struct urtw_softc *,
744 struct urtw_data data[], int, int);
745 static usb_error_t urtw_adapter_start(struct urtw_softc *);
746 static usb_error_t urtw_adapter_start_b(struct urtw_softc *);
747 static usb_error_t urtw_set_mode(struct urtw_softc *, uint32_t);
748 static usb_error_t urtw_8187b_cmd_reset(struct urtw_softc *);
749 static usb_error_t urtw_do_request(struct urtw_softc *,
750 struct usb_device_request *, void *);
751 static usb_error_t urtw_8225v2b_set_txpwrlvl(struct urtw_softc *, int);
752 static usb_error_t urtw_led_off(struct urtw_softc *, int);
753 static void urtw_abort_xfers(struct urtw_softc *);
754 static struct urtw_data *
755 urtw_getbuf(struct urtw_softc *sc);
756 static int urtw_compute_txtime(uint16_t, uint16_t, uint8_t,
758 static void urtw_updateslot(struct ifnet *);
759 static void urtw_updateslottask(void *, int);
760 static void urtw_sysctl_node(struct urtw_softc *);
763 urtw_match(device_t dev)
765 struct usb_attach_arg *uaa = device_get_ivars(dev);
767 if (uaa->usb_mode != USB_MODE_HOST)
769 if (uaa->info.bConfigIndex != URTW_CONFIG_INDEX)
771 if (uaa->info.bIfaceIndex != URTW_IFACE_INDEX)
774 return (usbd_lookup_id_by_uaa(urtw_devs, sizeof(urtw_devs), uaa));
778 urtw_attach(device_t dev)
780 const struct usb_config *setup_start;
782 struct urtw_softc *sc = device_get_softc(dev);
783 struct usb_attach_arg *uaa = device_get_ivars(dev);
784 struct ieee80211com *ic;
786 uint8_t bands, iface_index = URTW_IFACE_INDEX; /* XXX */
791 device_set_usb_desc(dev);
794 sc->sc_udev = uaa->device;
795 if (USB_GET_DRIVER_INFO(uaa) == URTW_REV_RTL8187B)
796 sc->sc_flags |= URTW_RTL8187B;
798 sc->sc_debug = urtw_debug;
801 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->sc_dev), MTX_NETWORK_LOCK,
803 usb_callout_init_mtx(&sc->sc_led_ch, &sc->sc_mtx, 0);
804 TASK_INIT(&sc->sc_led_task, 0, urtw_ledtask, sc);
805 TASK_INIT(&sc->sc_updateslot_task, 0, urtw_updateslottask, sc);
806 callout_init(&sc->sc_watchdog_ch, 0);
808 if (sc->sc_flags & URTW_RTL8187B) {
809 setup_start = urtw_8187b_usbconfig;
810 n_setup = URTW_8187B_N_XFERS;
812 setup_start = urtw_8187l_usbconfig;
813 n_setup = URTW_8187L_N_XFERS;
816 error = usbd_transfer_setup(uaa->device, &iface_index, sc->sc_xfer,
817 setup_start, n_setup, sc, &sc->sc_mtx);
819 device_printf(dev, "could not allocate USB transfers, "
820 "err=%s\n", usbd_errstr(error));
825 if (sc->sc_flags & URTW_RTL8187B) {
827 usbd_xfer_get_frame_buffer(sc->sc_xfer[
828 URTW_8187B_BULK_TX_BE], 0);
831 usbd_xfer_get_frame_buffer(sc->sc_xfer[
832 URTW_8187L_BULK_TX_LOW], 0);
837 urtw_read32_m(sc, URTW_RX, &data);
838 sc->sc_epromtype = (data & URTW_RX_9356SEL) ? URTW_EEPROM_93C56 :
841 error = urtw_get_rfchip(sc);
844 error = urtw_get_macaddr(sc);
847 error = urtw_get_txpwr(sc);
850 error = urtw_led_init(sc);
856 sc->sc_rts_retry = URTW_DEFAULT_RTS_RETRY;
857 sc->sc_tx_retry = URTW_DEFAULT_TX_RETRY;
859 sc->sc_preamble_mode = urtw_preamble_mode;
861 ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211);
863 device_printf(sc->sc_dev, "can not allocate ifnet\n");
869 if_initname(ifp, "urtw", device_get_unit(sc->sc_dev));
870 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST;
871 ifp->if_init = urtw_init;
872 ifp->if_ioctl = urtw_ioctl;
873 ifp->if_start = urtw_start;
874 /* XXX URTW_TX_DATA_LIST_COUNT */
875 IFQ_SET_MAXLEN(&ifp->if_snd, ifqmaxlen);
876 ifp->if_snd.ifq_drv_maxlen = ifqmaxlen;
877 IFQ_SET_READY(&ifp->if_snd);
881 ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
882 ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
884 /* set device capabilities */
886 IEEE80211_C_STA | /* station mode */
887 IEEE80211_C_MONITOR | /* monitor mode supported */
888 IEEE80211_C_TXPMGT | /* tx power management */
889 IEEE80211_C_SHPREAMBLE | /* short preamble supported */
890 IEEE80211_C_SHSLOT | /* short slot time supported */
891 IEEE80211_C_BGSCAN | /* capable of bg scanning */
892 IEEE80211_C_WPA; /* 802.11i */
895 setbit(&bands, IEEE80211_MODE_11B);
896 setbit(&bands, IEEE80211_MODE_11G);
897 ieee80211_init_channels(ic, NULL, &bands);
899 ieee80211_ifattach(ic, sc->sc_bssid);
900 ic->ic_raw_xmit = urtw_raw_xmit;
901 ic->ic_scan_start = urtw_scan_start;
902 ic->ic_scan_end = urtw_scan_end;
903 ic->ic_set_channel = urtw_set_channel;
904 ic->ic_updateslot = urtw_updateslot;
905 ic->ic_vap_create = urtw_vap_create;
906 ic->ic_vap_delete = urtw_vap_delete;
907 ic->ic_update_mcast = urtw_update_mcast;
909 ieee80211_radiotap_attach(ic,
910 &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap),
911 URTW_TX_RADIOTAP_PRESENT,
912 &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap),
913 URTW_RX_RADIOTAP_PRESENT);
915 urtw_sysctl_node(sc);
918 ieee80211_announce(ic);
921 fail: URTW_UNLOCK(sc);
922 fail1: usbd_transfer_unsetup(sc->sc_xfer, (sc->sc_flags & URTW_RTL8187B) ?
923 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS);
929 urtw_detach(device_t dev)
931 struct urtw_softc *sc = device_get_softc(dev);
932 struct ifnet *ifp = sc->sc_ifp;
933 struct ieee80211com *ic = ifp->if_l2com;
935 unsigned int n_xfers;
937 /* Prevent further ioctls */
939 sc->sc_flags |= URTW_DETACHED;
944 ieee80211_draintask(ic, &sc->sc_updateslot_task);
945 ieee80211_draintask(ic, &sc->sc_led_task);
947 usb_callout_drain(&sc->sc_led_ch);
948 callout_drain(&sc->sc_watchdog_ch);
950 n_xfers = (sc->sc_flags & URTW_RTL8187B) ?
951 URTW_8187B_N_XFERS : URTW_8187L_N_XFERS;
953 /* prevent further allocations from RX/TX data lists */
955 STAILQ_INIT(&sc->sc_tx_active);
956 STAILQ_INIT(&sc->sc_tx_inactive);
957 STAILQ_INIT(&sc->sc_tx_pending);
959 STAILQ_INIT(&sc->sc_rx_active);
960 STAILQ_INIT(&sc->sc_rx_inactive);
963 /* drain USB transfers */
964 for (x = 0; x != n_xfers; x++)
965 usbd_transfer_drain(sc->sc_xfer[x]);
967 /* free data buffers */
969 urtw_free_tx_data_list(sc);
970 urtw_free_rx_data_list(sc);
973 /* free USB transfers and some data buffers */
974 usbd_transfer_unsetup(sc->sc_xfer, n_xfers);
976 ieee80211_ifdetach(ic);
978 mtx_destroy(&sc->sc_mtx);
983 urtw_free_tx_data_list(struct urtw_softc *sc)
985 urtw_free_data_list(sc, sc->sc_tx, URTW_TX_DATA_LIST_COUNT, 0);
989 urtw_free_rx_data_list(struct urtw_softc *sc)
991 urtw_free_data_list(sc, sc->sc_rx, URTW_RX_DATA_LIST_COUNT, 1);
995 urtw_free_data_list(struct urtw_softc *sc, struct urtw_data data[], int ndata,
1000 for (i = 0; i < ndata; i++) {
1001 struct urtw_data *dp = &data[i];
1003 if (fillmbuf == 1) {
1004 if (dp->m != NULL) {
1012 if (dp->ni != NULL) {
1013 ieee80211_free_node(dp->ni);
1019 static struct ieee80211vap *
1020 urtw_vap_create(struct ieee80211com *ic, const char name[IFNAMSIZ], int unit,
1021 enum ieee80211_opmode opmode, int flags,
1022 const uint8_t bssid[IEEE80211_ADDR_LEN],
1023 const uint8_t mac[IEEE80211_ADDR_LEN])
1025 struct urtw_vap *uvp;
1026 struct ieee80211vap *vap;
1028 if (!TAILQ_EMPTY(&ic->ic_vaps)) /* only one at a time */
1030 uvp = (struct urtw_vap *) malloc(sizeof(struct urtw_vap),
1031 M_80211_VAP, M_NOWAIT | M_ZERO);
1035 /* enable s/w bmiss handling for sta mode */
1037 if (ieee80211_vap_setup(ic, vap, name, unit, opmode,
1038 flags | IEEE80211_CLONE_NOBEACONS, bssid, mac) != 0) {
1040 free(uvp, M_80211_VAP);
1044 /* override state transition machine */
1045 uvp->newstate = vap->iv_newstate;
1046 vap->iv_newstate = urtw_newstate;
1048 /* complete setup */
1049 ieee80211_vap_attach(vap, ieee80211_media_change,
1050 ieee80211_media_status);
1051 ic->ic_opmode = opmode;
1056 urtw_vap_delete(struct ieee80211vap *vap)
1058 struct urtw_vap *uvp = URTW_VAP(vap);
1060 ieee80211_vap_detach(vap);
1061 free(uvp, M_80211_VAP);
1065 urtw_init_locked(void *arg)
1068 struct urtw_softc *sc = arg;
1069 struct ifnet *ifp = sc->sc_ifp;
1072 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1073 urtw_stop_locked(ifp);
1075 error = (sc->sc_flags & URTW_RTL8187B) ? urtw_adapter_start_b(sc) :
1076 urtw_adapter_start(sc);
1080 /* reset softc variables */
1083 if (!(sc->sc_flags & URTW_INIT_ONCE)) {
1084 ret = urtw_alloc_rx_data_list(sc);
1087 ret = urtw_alloc_tx_data_list(sc);
1090 sc->sc_flags |= URTW_INIT_ONCE;
1093 error = urtw_rx_enable(sc);
1096 error = urtw_tx_enable(sc);
1100 if (sc->sc_flags & URTW_RTL8187B)
1101 usbd_transfer_start(sc->sc_xfer[URTW_8187B_BULK_TX_STATUS]);
1103 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
1104 ifp->if_drv_flags |= IFF_DRV_RUNNING;
1106 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1112 urtw_init(void *arg)
1114 struct urtw_softc *sc = arg;
1117 urtw_init_locked(arg);
1122 urtw_adapter_start_b(struct urtw_softc *sc)
1124 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1128 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1132 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1133 urtw_write8_m(sc, URTW_CONFIG3,
1134 data8 | URTW_CONFIG3_ANAPARAM_WRITE | URTW_CONFIG3_GNT_SELECT);
1135 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8187B_8225_ANAPARAM2_ON);
1136 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_ON);
1137 urtw_write8_m(sc, URTW_ANAPARAM3, URTW_8187B_8225_ANAPARAM3_ON);
1139 urtw_write8_m(sc, 0x61, 0x10);
1140 urtw_read8_m(sc, 0x62, &data8);
1141 urtw_write8_m(sc, 0x62, data8 & ~(1 << 5));
1142 urtw_write8_m(sc, 0x62, data8 | (1 << 5));
1144 urtw_read8_m(sc, URTW_CONFIG3, &data8);
1145 data8 &= ~URTW_CONFIG3_ANAPARAM_WRITE;
1146 urtw_write8_m(sc, URTW_CONFIG3, data8);
1148 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1152 error = urtw_8187b_cmd_reset(sc);
1156 error = sc->sc_rf_init(sc);
1159 urtw_write8_m(sc, URTW_CMD, URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1161 /* fix RTL8187B RX stall */
1162 error = urtw_intr_enable(sc);
1166 error = urtw_write8e(sc, 0x41, 0xf4);
1169 error = urtw_write8e(sc, 0x40, 0x00);
1172 error = urtw_write8e(sc, 0x42, 0x00);
1175 error = urtw_write8e(sc, 0x42, 0x01);
1178 error = urtw_write8e(sc, 0x40, 0x0f);
1181 error = urtw_write8e(sc, 0x42, 0x00);
1184 error = urtw_write8e(sc, 0x42, 0x01);
1188 urtw_read8_m(sc, 0xdb, &data8);
1189 urtw_write8_m(sc, 0xdb, data8 | (1 << 2));
1190 urtw_write16_m(sc, 0x372, 0x59fa);
1191 urtw_write16_m(sc, 0x374, 0x59d2);
1192 urtw_write16_m(sc, 0x376, 0x59d2);
1193 urtw_write16_m(sc, 0x378, 0x19fa);
1194 urtw_write16_m(sc, 0x37a, 0x19fa);
1195 urtw_write16_m(sc, 0x37c, 0x00d0);
1196 urtw_write8_m(sc, 0x61, 0);
1198 urtw_write8_m(sc, 0x180, 0x0f);
1199 urtw_write8_m(sc, 0x183, 0x03);
1200 urtw_write8_m(sc, 0xda, 0x10);
1201 urtw_write8_m(sc, 0x24d, 0x08);
1202 urtw_write32_m(sc, URTW_HSSI_PARA, 0x0600321b);
1204 urtw_write16_m(sc, 0x1ec, 0x800); /* RX MAX SIZE */
1211 urtw_adapter_start(struct urtw_softc *sc)
1215 error = urtw_reset(sc);
1219 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 0);
1220 urtw_write8_m(sc, URTW_GPIO, 0);
1223 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1224 error = urtw_led_ctl(sc, URTW_LED_CTL_POWER_ON);
1228 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1231 /* applying MAC address again. */
1232 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
1233 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
1234 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1238 error = urtw_update_msr(sc);
1242 urtw_write32_m(sc, URTW_INT_TIMEOUT, 0);
1243 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
1244 urtw_write8_m(sc, URTW_RATE_FALLBACK, URTW_RATE_FALLBACK_ENABLE | 0x1);
1245 error = urtw_set_rate(sc);
1249 error = sc->sc_rf_init(sc);
1252 if (sc->sc_rf_set_sens != NULL)
1253 sc->sc_rf_set_sens(sc, sc->sc_sens);
1255 /* XXX correct? to call write16 */
1256 urtw_write16_m(sc, URTW_PSR, 1);
1257 urtw_write16_m(sc, URTW_ADDR_MAGIC2, 0x10);
1258 urtw_write8_m(sc, URTW_TALLY_SEL, 0x80);
1259 urtw_write8_m(sc, URTW_ADDR_MAGIC3, 0x60);
1260 /* XXX correct? to call write16 */
1261 urtw_write16_m(sc, URTW_PSR, 0);
1262 urtw_write8_m(sc, URTW_ADDR_MAGIC1, 4);
1264 error = urtw_intr_enable(sc);
1273 urtw_set_mode(struct urtw_softc *sc, uint32_t mode)
1278 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
1279 data = (data & ~URTW_EPROM_CMD_MASK) | (mode << URTW_EPROM_CMD_SHIFT);
1280 data = data & ~(URTW_EPROM_CS | URTW_EPROM_CK);
1281 urtw_write8_m(sc, URTW_EPROM_CMD, data);
1287 urtw_8187b_cmd_reset(struct urtw_softc *sc)
1293 /* XXX the code can be duplicate with urtw_reset(). */
1294 urtw_read8_m(sc, URTW_CMD, &data8);
1295 data8 = (data8 & 0x2) | URTW_CMD_RST;
1296 urtw_write8_m(sc, URTW_CMD, data8);
1298 for (i = 0; i < 20; i++) {
1299 usb_pause_mtx(&sc->sc_mtx, 2);
1300 urtw_read8_m(sc, URTW_CMD, &data8);
1301 if (!(data8 & URTW_CMD_RST))
1305 device_printf(sc->sc_dev, "reset timeout\n");
1313 urtw_do_request(struct urtw_softc *sc,
1314 struct usb_device_request *req, void *data)
1319 URTW_ASSERT_LOCKED(sc);
1322 err = usbd_do_request_flags(sc->sc_udev, &sc->sc_mtx,
1323 req, data, 0, NULL, 250 /* ms */);
1327 DPRINTF(sc, URTW_DEBUG_INIT,
1328 "Control request failed, %s (retrying)\n",
1330 usb_pause_mtx(&sc->sc_mtx, hz / 100);
1336 urtw_stop_locked(struct ifnet *ifp)
1338 struct urtw_softc *sc = ifp->if_softc;
1342 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE);
1344 error = urtw_intr_disable(sc);
1347 urtw_read8_m(sc, URTW_CMD, &data8);
1348 data8 &= ~(URTW_CMD_RX_ENABLE | URTW_CMD_TX_ENABLE);
1349 urtw_write8_m(sc, URTW_CMD, data8);
1351 error = sc->sc_rf_stop(sc);
1355 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
1358 urtw_read8_m(sc, URTW_CONFIG4, &data8);
1359 urtw_write8_m(sc, URTW_CONFIG4, data8 | URTW_CONFIG4_VCOOFF);
1360 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
1365 device_printf(sc->sc_dev, "failed to stop (%s)\n",
1366 usbd_errstr(error));
1368 usb_callout_stop(&sc->sc_led_ch);
1369 callout_stop(&sc->sc_watchdog_ch);
1371 urtw_abort_xfers(sc);
1375 urtw_stop(struct ifnet *ifp)
1377 struct urtw_softc *sc = ifp->if_softc;
1380 urtw_stop_locked(ifp);
1385 urtw_abort_xfers(struct urtw_softc *sc)
1389 URTW_ASSERT_LOCKED(sc);
1391 max = (sc->sc_flags & URTW_RTL8187B) ? URTW_8187B_N_XFERS :
1394 /* abort any pending transfers */
1395 for (i = 0; i < max; i++)
1396 usbd_transfer_stop(sc->sc_xfer[i]);
1400 urtw_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data)
1402 struct urtw_softc *sc = ifp->if_softc;
1403 struct ieee80211com *ic = ifp->if_l2com;
1404 struct ifreq *ifr = (struct ifreq *) data;
1409 error = (sc->sc_flags & URTW_DETACHED) ? ENXIO : 0;
1416 if (ifp->if_flags & IFF_UP) {
1417 if (ifp->if_drv_flags & IFF_DRV_RUNNING) {
1418 if ((ifp->if_flags ^ sc->sc_if_flags) &
1419 (IFF_ALLMULTI | IFF_PROMISC))
1422 urtw_init(ifp->if_softc);
1426 if (ifp->if_drv_flags & IFF_DRV_RUNNING)
1429 sc->sc_if_flags = ifp->if_flags;
1431 ieee80211_start_all(ic);
1434 error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd);
1437 error = ether_ioctl(ifp, cmd, data);
1447 urtw_start(struct ifnet *ifp)
1449 struct urtw_data *bf;
1450 struct urtw_softc *sc = ifp->if_softc;
1451 struct ieee80211_node *ni;
1454 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
1459 IFQ_DRV_DEQUEUE(&ifp->if_snd, m);
1462 bf = urtw_getbuf(sc);
1464 IFQ_DRV_PREPEND(&ifp->if_snd, m);
1468 ni = (struct ieee80211_node *)m->m_pkthdr.rcvif;
1469 m->m_pkthdr.rcvif = NULL;
1471 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_NORMAL) != 0) {
1473 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1474 ieee80211_free_node(ni);
1479 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1485 urtw_alloc_data_list(struct urtw_softc *sc, struct urtw_data data[],
1486 int ndata, int maxsz, void *dma_buf)
1490 for (i = 0; i < ndata; i++) {
1491 struct urtw_data *dp = &data[i];
1494 if (dma_buf == NULL) {
1495 dp->m = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
1496 if (dp->m == NULL) {
1497 device_printf(sc->sc_dev,
1498 "could not allocate rx mbuf\n");
1502 dp->buf = mtod(dp->m, uint8_t *);
1505 dp->buf = ((uint8_t *)dma_buf) +
1512 fail: urtw_free_data_list(sc, data, ndata, 1);
1517 urtw_alloc_rx_data_list(struct urtw_softc *sc)
1521 error = urtw_alloc_data_list(sc,
1522 sc->sc_rx, URTW_RX_DATA_LIST_COUNT,
1523 MCLBYTES, NULL /* mbufs */);
1527 STAILQ_INIT(&sc->sc_rx_active);
1528 STAILQ_INIT(&sc->sc_rx_inactive);
1530 for (i = 0; i < URTW_RX_DATA_LIST_COUNT; i++)
1531 STAILQ_INSERT_HEAD(&sc->sc_rx_inactive, &sc->sc_rx[i], next);
1537 urtw_alloc_tx_data_list(struct urtw_softc *sc)
1541 error = urtw_alloc_data_list(sc,
1542 sc->sc_tx, URTW_TX_DATA_LIST_COUNT, URTW_TX_MAXSIZE,
1543 sc->sc_tx_dma_buf /* no mbufs */);
1547 STAILQ_INIT(&sc->sc_tx_active);
1548 STAILQ_INIT(&sc->sc_tx_inactive);
1549 STAILQ_INIT(&sc->sc_tx_pending);
1551 for (i = 0; i < URTW_TX_DATA_LIST_COUNT; i++)
1552 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, &sc->sc_tx[i],
1559 urtw_raw_xmit(struct ieee80211_node *ni, struct mbuf *m,
1560 const struct ieee80211_bpf_params *params)
1562 struct ieee80211com *ic = ni->ni_ic;
1563 struct ifnet *ifp = ic->ic_ifp;
1564 struct urtw_data *bf;
1565 struct urtw_softc *sc = ifp->if_softc;
1567 /* prevent management frames from being sent if we're not ready */
1568 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) {
1570 ieee80211_free_node(ni);
1574 bf = urtw_getbuf(sc);
1576 ieee80211_free_node(ni);
1579 return (ENOBUFS); /* XXX */
1583 if (urtw_tx_start(sc, ni, m, bf, URTW_PRIORITY_LOW) != 0) {
1584 ieee80211_free_node(ni);
1586 STAILQ_INSERT_HEAD(&sc->sc_tx_inactive, bf, next);
1597 urtw_scan_start(struct ieee80211com *ic)
1600 /* XXX do nothing? */
1604 urtw_scan_end(struct ieee80211com *ic)
1607 /* XXX do nothing? */
1611 urtw_set_channel(struct ieee80211com *ic)
1613 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1614 struct ifnet *ifp = sc->sc_ifp;
1615 uint32_t data, orig;
1619 * if the user set a channel explicitly using ifconfig(8) this function
1620 * can be called earlier than we're expected that in some cases the
1621 * initialization would be failed if setting a channel is called before
1622 * the init have done.
1624 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING))
1627 if (sc->sc_curchan != NULL && sc->sc_curchan == ic->ic_curchan)
1633 * during changing th channel we need to temporarily be disable
1636 urtw_read32_m(sc, URTW_TX_CONF, &orig);
1637 data = orig & ~URTW_TX_LOOPBACK_MASK;
1638 urtw_write32_m(sc, URTW_TX_CONF, data | URTW_TX_LOOPBACK_MAC);
1640 error = sc->sc_rf_set_chan(sc, ieee80211_chan2ieee(ic, ic->ic_curchan));
1643 usb_pause_mtx(&sc->sc_mtx, 10);
1644 urtw_write32_m(sc, URTW_TX_CONF, orig);
1646 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1647 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1648 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
1649 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1654 sc->sc_curchan = ic->ic_curchan;
1657 device_printf(sc->sc_dev, "could not change the channel\n");
1661 urtw_update_mcast(struct ifnet *ifp)
1664 /* XXX do nothing? */
1668 urtw_tx_start(struct urtw_softc *sc, struct ieee80211_node *ni, struct mbuf *m0,
1669 struct urtw_data *data, int prior)
1671 struct ifnet *ifp = sc->sc_ifp;
1672 struct ieee80211_frame *wh = mtod(m0, struct ieee80211_frame *);
1673 struct ieee80211_key *k;
1674 const struct ieee80211_txparam *tp;
1675 struct ieee80211com *ic = ifp->if_l2com;
1676 struct ieee80211vap *vap = ni->ni_vap;
1677 struct usb_xfer *rtl8187b_pipes[URTW_8187B_TXPIPE_MAX] = {
1678 sc->sc_xfer[URTW_8187B_BULK_TX_BE],
1679 sc->sc_xfer[URTW_8187B_BULK_TX_BK],
1680 sc->sc_xfer[URTW_8187B_BULK_TX_VI],
1681 sc->sc_xfer[URTW_8187B_BULK_TX_VO]
1683 struct usb_xfer *xfer;
1684 int dur = 0, rtsdur = 0, rtsenable = 0, ctsenable = 0, rate,
1685 pkttime = 0, txdur = 0, isshort = 0, xferlen;
1686 uint16_t acktime, rtstime, ctstime;
1690 URTW_ASSERT_LOCKED(sc);
1695 if (wh->i_fc[1] & IEEE80211_FC1_PROTECTED) {
1696 k = ieee80211_crypto_encap(ni, m0);
1698 device_printf(sc->sc_dev,
1699 "ieee80211_crypto_encap returns NULL.\n");
1700 /* XXX we don't expect the fragmented frames */
1705 /* in case packet header moved, reset pointer */
1706 wh = mtod(m0, struct ieee80211_frame *);
1709 if (ieee80211_radiotap_active_vap(vap)) {
1710 struct urtw_tx_radiotap_header *tap = &sc->sc_txtap;
1712 /* XXX Are variables correct? */
1714 tap->wt_chan_freq = htole16(ic->ic_curchan->ic_freq);
1715 tap->wt_chan_flags = htole16(ic->ic_curchan->ic_flags);
1717 ieee80211_radiotap_tx(vap, m0);
1720 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_MGT ||
1721 (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_CTL) {
1722 tp = &vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)];
1723 rate = tp->mgmtrate;
1725 tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)];
1726 /* for data frames */
1727 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1728 rate = tp->mcastrate;
1729 else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE)
1730 rate = tp->ucastrate;
1732 rate = urtw_rtl2rate(sc->sc_currate);
1735 sc->sc_stats.txrates[sc->sc_currate]++;
1737 if (IEEE80211_IS_MULTICAST(wh->i_addr1))
1738 txdur = pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1739 IEEE80211_CRC_LEN, rate, 0, 0);
1741 acktime = urtw_compute_txtime(14, 2,0, 0);
1742 if ((m0->m_pkthdr.len + 4) > vap->iv_rtsthreshold) {
1745 rtstime = urtw_compute_txtime(URTW_ACKCTS_LEN, 2, 0, 0);
1746 ctstime = urtw_compute_txtime(14, 2, 0, 0);
1747 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1748 IEEE80211_CRC_LEN, rate, 0, isshort);
1749 rtsdur = ctstime + pkttime + acktime +
1750 3 * URTW_ASIFS_TIME;
1751 txdur = rtstime + rtsdur;
1753 rtsenable = ctsenable = rtsdur = 0;
1754 pkttime = urtw_compute_txtime(m0->m_pkthdr.len +
1755 IEEE80211_CRC_LEN, rate, 0, isshort);
1756 txdur = pkttime + URTW_ASIFS_TIME + acktime;
1759 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1760 dur = urtw_compute_txtime(m0->m_pkthdr.len +
1761 IEEE80211_CRC_LEN, rate, 0, isshort) +
1762 3 * URTW_ASIFS_TIME +
1765 dur = URTW_ASIFS_TIME + acktime;
1767 USETW(wh->i_dur, dur);
1769 xferlen = m0->m_pkthdr.len;
1770 xferlen += (sc->sc_flags & URTW_RTL8187B) ? (4 * 8) : (4 * 3);
1771 if ((0 == xferlen % 64) || (0 == xferlen % 512))
1774 memset(data->buf, 0, URTW_TX_MAXSIZE);
1775 flags = m0->m_pkthdr.len & 0xfff;
1776 flags |= URTW_TX_FLAG_NO_ENC;
1777 if ((ic->ic_flags & IEEE80211_F_SHPREAMBLE) &&
1778 (ni->ni_capinfo & IEEE80211_CAPINFO_SHORT_PREAMBLE) &&
1779 (sc->sc_preamble_mode == URTW_PREAMBLE_MODE_SHORT) &&
1780 (sc->sc_currate != 0))
1781 flags |= URTW_TX_FLAG_SPLCP;
1782 if (wh->i_fc[1] & IEEE80211_FC1_MORE_FRAG)
1783 flags |= URTW_TX_FLAG_MOREFRAG;
1785 flags |= (sc->sc_currate & 0xf) << URTW_TX_FLAG_TXRATE_SHIFT;
1787 if (sc->sc_flags & URTW_RTL8187B) {
1788 struct urtw_8187b_txhdr *tx;
1790 tx = (struct urtw_8187b_txhdr *)data->buf;
1792 flags |= URTW_TX_FLAG_CTS;
1794 flags |= URTW_TX_FLAG_RTS;
1795 flags |= (urtw_rate2rtl(11) & 0xf) <<
1796 URTW_TX_FLAG_RTSRATE_SHIFT;
1797 tx->rtsdur = rtsdur;
1799 tx->flag = htole32(flags);
1801 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) ==
1802 IEEE80211_FC0_TYPE_MGT &&
1803 (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) ==
1804 IEEE80211_FC0_SUBTYPE_PROBE_RESP)
1807 tx->retry = URTW_TX_MAXRETRY;
1808 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1810 struct urtw_8187l_txhdr *tx;
1812 tx = (struct urtw_8187l_txhdr *)data->buf;
1814 flags |= URTW_TX_FLAG_RTS;
1815 tx->rtsdur = rtsdur;
1817 flags |= (urtw_rate2rtl(11) & 0xf) << URTW_TX_FLAG_RTSRATE_SHIFT;
1818 tx->flag = htole32(flags);
1819 tx->retry = 3; /* CW minimum */
1820 tx->retry = 7 << 4; /* CW maximum */
1821 tx->retry = URTW_TX_MAXRETRY << 8; /* retry limitation */
1822 m_copydata(m0, 0, m0->m_pkthdr.len, (uint8_t *)(tx + 1));
1825 data->buflen = xferlen;
1829 if (sc->sc_flags & URTW_RTL8187B) {
1830 switch (wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) {
1831 case IEEE80211_FC0_TYPE_CTL:
1832 case IEEE80211_FC0_TYPE_MGT:
1833 xfer = sc->sc_xfer[URTW_8187B_BULK_TX_EP12];
1836 KASSERT(M_WME_GETAC(m0) < URTW_8187B_TXPIPE_MAX,
1837 ("unsupported WME pipe %d", M_WME_GETAC(m0)));
1838 xfer = rtl8187b_pipes[M_WME_GETAC(m0)];
1842 xfer = (prior == URTW_PRIORITY_LOW) ?
1843 sc->sc_xfer[URTW_8187L_BULK_TX_LOW] :
1844 sc->sc_xfer[URTW_8187L_BULK_TX_NORMAL];
1846 STAILQ_INSERT_TAIL(&sc->sc_tx_pending, data, next);
1847 usbd_transfer_start(xfer);
1849 error = urtw_led_ctl(sc, URTW_LED_CTL_TX);
1851 device_printf(sc->sc_dev, "could not control LED (%d)\n",
1857 urtw_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg)
1859 struct ieee80211com *ic = vap->iv_ic;
1860 struct urtw_softc *sc = ic->ic_ifp->if_softc;
1861 struct urtw_vap *uvp = URTW_VAP(vap);
1862 struct ieee80211_node *ni;
1863 usb_error_t error = 0;
1865 DPRINTF(sc, URTW_DEBUG_STATE, "%s: %s -> %s\n", __func__,
1866 ieee80211_state_name[vap->iv_state],
1867 ieee80211_state_name[nstate]);
1869 sc->sc_state = nstate;
1871 IEEE80211_UNLOCK(ic);
1873 usb_callout_stop(&sc->sc_led_ch);
1874 callout_stop(&sc->sc_watchdog_ch);
1877 case IEEE80211_S_INIT:
1878 case IEEE80211_S_SCAN:
1879 case IEEE80211_S_AUTH:
1880 case IEEE80211_S_ASSOC:
1882 case IEEE80211_S_RUN:
1883 ni = ieee80211_ref_node(vap->iv_bss);
1884 /* setting bssid. */
1885 urtw_write32_m(sc, URTW_BSSID, ((uint32_t *)ni->ni_bssid)[0]);
1886 urtw_write16_m(sc, URTW_BSSID + 4,
1887 ((uint16_t *)ni->ni_bssid)[2]);
1888 urtw_update_msr(sc);
1889 /* XXX maybe the below would be incorrect. */
1890 urtw_write16_m(sc, URTW_ATIM_WND, 2);
1891 urtw_write16_m(sc, URTW_ATIM_TR_ITV, 100);
1892 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 0x64);
1893 urtw_write16_m(sc, URTW_BEACON_INTERVAL_TIME, 100);
1894 error = urtw_led_ctl(sc, URTW_LED_CTL_LINK);
1896 device_printf(sc->sc_dev,
1897 "could not control LED (%d)\n", error);
1898 ieee80211_free_node(ni);
1906 return (uvp->newstate(vap, nstate, arg));
1910 urtw_watchdog(void *arg)
1912 struct urtw_softc *sc = arg;
1913 struct ifnet *ifp = sc->sc_ifp;
1915 if (sc->sc_txtimer > 0) {
1916 if (--sc->sc_txtimer == 0) {
1917 device_printf(sc->sc_dev, "device timeout\n");
1921 callout_reset(&sc->sc_watchdog_ch, hz, urtw_watchdog, sc);
1926 urtw_set_multi(void *arg)
1928 struct urtw_softc *sc = arg;
1929 struct ifnet *ifp = sc->sc_ifp;
1931 if (!(ifp->if_flags & IFF_UP))
1935 * XXX don't know how to set a device. Lack of docs. Just try to set
1936 * IFF_ALLMULTI flag here.
1938 ifp->if_flags |= IFF_ALLMULTI;
1942 urtw_set_rate(struct urtw_softc *sc)
1944 int i, basic_rate, min_rr_rate, max_rr_rate;
1948 basic_rate = urtw_rate2rtl(48);
1949 min_rr_rate = urtw_rate2rtl(12);
1950 max_rr_rate = urtw_rate2rtl(48);
1952 urtw_write8_m(sc, URTW_RESP_RATE,
1953 max_rr_rate << URTW_RESP_MAX_RATE_SHIFT |
1954 min_rr_rate << URTW_RESP_MIN_RATE_SHIFT);
1956 urtw_read16_m(sc, URTW_BRSR, &data);
1957 data &= ~URTW_BRSR_MBR_8185;
1959 for (i = 0; i <= basic_rate; i++)
1962 urtw_write16_m(sc, URTW_BRSR, data);
1968 urtw_rate2rtl(uint32_t rate)
1970 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1973 for (i = 0; i < N(urtw_ratetable); i++) {
1974 if (rate == urtw_ratetable[i].reg)
1975 return urtw_ratetable[i].val;
1983 urtw_rtl2rate(uint32_t rate)
1985 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
1988 for (i = 0; i < N(urtw_ratetable); i++) {
1989 if (rate == urtw_ratetable[i].val)
1990 return urtw_ratetable[i].reg;
1998 urtw_update_msr(struct urtw_softc *sc)
2000 struct ifnet *ifp = sc->sc_ifp;
2001 struct ieee80211com *ic = ifp->if_l2com;
2005 urtw_read8_m(sc, URTW_MSR, &data);
2006 data &= ~URTW_MSR_LINK_MASK;
2008 if (sc->sc_state == IEEE80211_S_RUN) {
2009 switch (ic->ic_opmode) {
2010 case IEEE80211_M_STA:
2011 case IEEE80211_M_MONITOR:
2012 data |= URTW_MSR_LINK_STA;
2013 if (sc->sc_flags & URTW_RTL8187B)
2014 data |= URTW_MSR_LINK_ENEDCA;
2016 case IEEE80211_M_IBSS:
2017 data |= URTW_MSR_LINK_ADHOC;
2019 case IEEE80211_M_HOSTAP:
2020 data |= URTW_MSR_LINK_HOSTAP;
2023 DPRINTF(sc, URTW_DEBUG_STATE,
2024 "unsupported operation mode 0x%x\n",
2026 error = USB_ERR_INVAL;
2030 data |= URTW_MSR_LINK_NONE;
2032 urtw_write8_m(sc, URTW_MSR, data);
2038 urtw_read8_c(struct urtw_softc *sc, int val, uint8_t *data)
2040 struct usb_device_request req;
2043 URTW_ASSERT_LOCKED(sc);
2045 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2046 req.bRequest = URTW_8187_GETREGS_REQ;
2047 USETW(req.wValue, (val & 0xff) | 0xff00);
2048 USETW(req.wIndex, (val >> 8) & 0x3);
2049 USETW(req.wLength, sizeof(uint8_t));
2051 error = urtw_do_request(sc, &req, data);
2056 urtw_read16_c(struct urtw_softc *sc, int val, uint16_t *data)
2058 struct usb_device_request req;
2061 URTW_ASSERT_LOCKED(sc);
2063 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2064 req.bRequest = URTW_8187_GETREGS_REQ;
2065 USETW(req.wValue, (val & 0xff) | 0xff00);
2066 USETW(req.wIndex, (val >> 8) & 0x3);
2067 USETW(req.wLength, sizeof(uint16_t));
2069 error = urtw_do_request(sc, &req, data);
2074 urtw_read32_c(struct urtw_softc *sc, int val, uint32_t *data)
2076 struct usb_device_request req;
2079 URTW_ASSERT_LOCKED(sc);
2081 req.bmRequestType = UT_READ_VENDOR_DEVICE;
2082 req.bRequest = URTW_8187_GETREGS_REQ;
2083 USETW(req.wValue, (val & 0xff) | 0xff00);
2084 USETW(req.wIndex, (val >> 8) & 0x3);
2085 USETW(req.wLength, sizeof(uint32_t));
2087 error = urtw_do_request(sc, &req, data);
2092 urtw_write8_c(struct urtw_softc *sc, int val, uint8_t data)
2094 struct usb_device_request req;
2096 URTW_ASSERT_LOCKED(sc);
2098 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2099 req.bRequest = URTW_8187_SETREGS_REQ;
2100 USETW(req.wValue, (val & 0xff) | 0xff00);
2101 USETW(req.wIndex, (val >> 8) & 0x3);
2102 USETW(req.wLength, sizeof(uint8_t));
2104 return (urtw_do_request(sc, &req, &data));
2108 urtw_write16_c(struct urtw_softc *sc, int val, uint16_t data)
2110 struct usb_device_request req;
2112 URTW_ASSERT_LOCKED(sc);
2114 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2115 req.bRequest = URTW_8187_SETREGS_REQ;
2116 USETW(req.wValue, (val & 0xff) | 0xff00);
2117 USETW(req.wIndex, (val >> 8) & 0x3);
2118 USETW(req.wLength, sizeof(uint16_t));
2120 return (urtw_do_request(sc, &req, &data));
2124 urtw_write32_c(struct urtw_softc *sc, int val, uint32_t data)
2126 struct usb_device_request req;
2128 URTW_ASSERT_LOCKED(sc);
2130 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2131 req.bRequest = URTW_8187_SETREGS_REQ;
2132 USETW(req.wValue, (val & 0xff) | 0xff00);
2133 USETW(req.wIndex, (val >> 8) & 0x3);
2134 USETW(req.wLength, sizeof(uint32_t));
2136 return (urtw_do_request(sc, &req, &data));
2140 urtw_get_macaddr(struct urtw_softc *sc)
2145 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR, &data);
2148 sc->sc_bssid[0] = data & 0xff;
2149 sc->sc_bssid[1] = (data & 0xff00) >> 8;
2150 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 1, &data);
2153 sc->sc_bssid[2] = data & 0xff;
2154 sc->sc_bssid[3] = (data & 0xff00) >> 8;
2155 error = urtw_eprom_read32(sc, URTW_EPROM_MACADDR + 2, &data);
2158 sc->sc_bssid[4] = data & 0xff;
2159 sc->sc_bssid[5] = (data & 0xff00) >> 8;
2165 urtw_eprom_read32(struct urtw_softc *sc, uint32_t addr, uint32_t *data)
2167 #define URTW_READCMD_LEN 3
2169 int16_t addrstr[8], data16, readcmd[] = { 1, 1, 0 };
2172 /* NB: make sure the buffer is initialized */
2175 /* enable EPROM programming */
2176 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_PROGRAM_MODE);
2177 DELAY(URTW_EPROM_DELAY);
2179 error = urtw_eprom_cs(sc, URTW_EPROM_ENABLE);
2182 error = urtw_eprom_ck(sc);
2185 error = urtw_eprom_sendbits(sc, readcmd, URTW_READCMD_LEN);
2188 if (sc->sc_epromtype == URTW_EEPROM_93C56) {
2190 addrstr[0] = addr & (1 << 7);
2191 addrstr[1] = addr & (1 << 6);
2192 addrstr[2] = addr & (1 << 5);
2193 addrstr[3] = addr & (1 << 4);
2194 addrstr[4] = addr & (1 << 3);
2195 addrstr[5] = addr & (1 << 2);
2196 addrstr[6] = addr & (1 << 1);
2197 addrstr[7] = addr & (1 << 0);
2200 addrstr[0] = addr & (1 << 5);
2201 addrstr[1] = addr & (1 << 4);
2202 addrstr[2] = addr & (1 << 3);
2203 addrstr[3] = addr & (1 << 2);
2204 addrstr[4] = addr & (1 << 1);
2205 addrstr[5] = addr & (1 << 0);
2207 error = urtw_eprom_sendbits(sc, addrstr, addrlen);
2211 error = urtw_eprom_writebit(sc, 0);
2215 for (i = 0; i < 16; i++) {
2216 error = urtw_eprom_ck(sc);
2219 error = urtw_eprom_readbit(sc, &data16);
2223 (*data) |= (data16 << (15 - i));
2226 error = urtw_eprom_cs(sc, URTW_EPROM_DISABLE);
2229 error = urtw_eprom_ck(sc);
2233 /* now disable EPROM programming */
2234 urtw_write8_m(sc, URTW_EPROM_CMD, URTW_EPROM_CMD_NORMAL_MODE);
2237 #undef URTW_READCMD_LEN
2241 urtw_eprom_cs(struct urtw_softc *sc, int able)
2246 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2247 if (able == URTW_EPROM_ENABLE)
2248 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CS);
2250 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CS);
2251 DELAY(URTW_EPROM_DELAY);
2257 urtw_eprom_ck(struct urtw_softc *sc)
2263 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2264 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_CK);
2265 DELAY(URTW_EPROM_DELAY);
2267 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2268 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_CK);
2269 DELAY(URTW_EPROM_DELAY);
2275 urtw_eprom_readbit(struct urtw_softc *sc, int16_t *data)
2280 urtw_read8_m(sc, URTW_EPROM_CMD, &data8);
2281 *data = (data8 & URTW_EPROM_READBIT) ? 1 : 0;
2282 DELAY(URTW_EPROM_DELAY);
2289 urtw_eprom_writebit(struct urtw_softc *sc, int16_t bit)
2294 urtw_read8_m(sc, URTW_EPROM_CMD, &data);
2296 urtw_write8_m(sc, URTW_EPROM_CMD, data | URTW_EPROM_WRITEBIT);
2298 urtw_write8_m(sc, URTW_EPROM_CMD, data & ~URTW_EPROM_WRITEBIT);
2299 DELAY(URTW_EPROM_DELAY);
2305 urtw_eprom_sendbits(struct urtw_softc *sc, int16_t *buf, int buflen)
2308 usb_error_t error = 0;
2310 for (i = 0; i < buflen; i++) {
2311 error = urtw_eprom_writebit(sc, buf[i]);
2314 error = urtw_eprom_ck(sc);
2324 urtw_get_txpwr(struct urtw_softc *sc)
2330 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW_BASE, &data);
2333 sc->sc_txpwr_cck_base = data & 0xf;
2334 sc->sc_txpwr_ofdm_base = (data >> 4) & 0xf;
2336 for (i = 1, j = 0; i < 6; i += 2, j++) {
2337 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW0 + j, &data);
2340 sc->sc_txpwr_cck[i] = data & 0xf;
2341 sc->sc_txpwr_cck[i + 1] = (data & 0xf00) >> 8;
2342 sc->sc_txpwr_ofdm[i] = (data & 0xf0) >> 4;
2343 sc->sc_txpwr_ofdm[i + 1] = (data & 0xf000) >> 12;
2345 for (i = 1, j = 0; i < 4; i += 2, j++) {
2346 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW1 + j, &data);
2349 sc->sc_txpwr_cck[i + 6] = data & 0xf;
2350 sc->sc_txpwr_cck[i + 6 + 1] = (data & 0xf00) >> 8;
2351 sc->sc_txpwr_ofdm[i + 6] = (data & 0xf0) >> 4;
2352 sc->sc_txpwr_ofdm[i + 6 + 1] = (data & 0xf000) >> 12;
2354 if (sc->sc_flags & URTW_RTL8187B) {
2355 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2, &data);
2358 sc->sc_txpwr_cck[1 + 6 + 4] = data & 0xf;
2359 sc->sc_txpwr_ofdm[1 + 6 + 4] = (data & 0xf0) >> 4;
2360 error = urtw_eprom_read32(sc, 0x0a, &data);
2363 sc->sc_txpwr_cck[2 + 6 + 4] = data & 0xf;
2364 sc->sc_txpwr_ofdm[2 + 6 + 4] = (data & 0xf0) >> 4;
2365 error = urtw_eprom_read32(sc, 0x1c, &data);
2368 sc->sc_txpwr_cck[3 + 6 + 4] = data & 0xf;
2369 sc->sc_txpwr_cck[3 + 6 + 4 + 1] = (data & 0xf00) >> 8;
2370 sc->sc_txpwr_ofdm[3 + 6 + 4] = (data & 0xf0) >> 4;
2371 sc->sc_txpwr_ofdm[3 + 6 + 4 + 1] = (data & 0xf000) >> 12;
2373 for (i = 1, j = 0; i < 4; i += 2, j++) {
2374 error = urtw_eprom_read32(sc, URTW_EPROM_TXPW2 + j,
2378 sc->sc_txpwr_cck[i + 6 + 4] = data & 0xf;
2379 sc->sc_txpwr_cck[i + 6 + 4 + 1] = (data & 0xf00) >> 8;
2380 sc->sc_txpwr_ofdm[i + 6 + 4] = (data & 0xf0) >> 4;
2381 sc->sc_txpwr_ofdm[i + 6 + 4 + 1] = (data & 0xf000) >> 12;
2390 urtw_get_rfchip(struct urtw_softc *sc)
2397 if (sc->sc_flags & URTW_RTL8187B) {
2398 urtw_read8_m(sc, 0xe1, &data8);
2401 sc->sc_flags |= URTW_RTL8187B_REV_B;
2404 sc->sc_flags |= URTW_RTL8187B_REV_D;
2407 sc->sc_flags |= URTW_RTL8187B_REV_E;
2410 device_printf(sc->sc_dev, "unknown type: %#x\n", data8);
2411 sc->sc_flags |= URTW_RTL8187B_REV_B;
2415 urtw_read32_m(sc, URTW_TX_CONF, &data);
2416 switch (data & URTW_TX_HWMASK) {
2417 case URTW_TX_R8187vD_B:
2418 sc->sc_flags |= URTW_RTL8187B;
2420 case URTW_TX_R8187vD:
2423 device_printf(sc->sc_dev, "unknown RTL8187L type: %#x\n",
2424 data & URTW_TX_HWMASK);
2429 error = urtw_eprom_read32(sc, URTW_EPROM_RFCHIPID, &data);
2432 switch (data & 0xff) {
2433 case URTW_EPROM_RFCHIPID_RTL8225U:
2434 error = urtw_8225_isv2(sc, &ret);
2438 sc->sc_rf_init = urtw_8225_rf_init;
2439 sc->sc_rf_set_sens = urtw_8225_rf_set_sens;
2440 sc->sc_rf_set_chan = urtw_8225_rf_set_chan;
2441 sc->sc_rf_stop = urtw_8225_rf_stop;
2443 sc->sc_rf_init = urtw_8225v2_rf_init;
2444 sc->sc_rf_set_chan = urtw_8225v2_rf_set_chan;
2445 sc->sc_rf_stop = urtw_8225_rf_stop;
2447 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2448 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2450 case URTW_EPROM_RFCHIPID_RTL8225Z2:
2451 sc->sc_rf_init = urtw_8225v2b_rf_init;
2452 sc->sc_rf_set_chan = urtw_8225v2b_rf_set_chan;
2453 sc->sc_max_sens = URTW_8225_RF_MAX_SENS;
2454 sc->sc_sens = URTW_8225_RF_DEF_SENS;
2455 sc->sc_rf_stop = urtw_8225_rf_stop;
2458 DPRINTF(sc, URTW_DEBUG_STATE,
2459 "unsupported RF chip %d\n", data & 0xff);
2460 error = USB_ERR_INVAL;
2464 device_printf(sc->sc_dev, "%s rf %s hwrev %s\n",
2465 (sc->sc_flags & URTW_RTL8187B) ? "rtl8187b" : "rtl8187l",
2466 ((data & 0xff) == URTW_EPROM_RFCHIPID_RTL8225U) ? "rtl8225u" :
2468 (sc->sc_flags & URTW_RTL8187B) ? ((data8 == 0) ? "b" :
2469 (data8 == 1) ? "d" : "e") : "none");
2477 urtw_led_init(struct urtw_softc *sc)
2482 urtw_read8_m(sc, URTW_PSR, &sc->sc_psr);
2483 error = urtw_eprom_read32(sc, URTW_EPROM_SWREV, &rev);
2487 switch (rev & URTW_EPROM_CID_MASK) {
2488 case URTW_EPROM_CID_ALPHA0:
2489 sc->sc_strategy = URTW_SW_LED_MODE1;
2491 case URTW_EPROM_CID_SERCOMM_PS:
2492 sc->sc_strategy = URTW_SW_LED_MODE3;
2494 case URTW_EPROM_CID_HW_LED:
2495 sc->sc_strategy = URTW_HW_LED;
2497 case URTW_EPROM_CID_RSVD0:
2498 case URTW_EPROM_CID_RSVD1:
2500 sc->sc_strategy = URTW_SW_LED_MODE0;
2504 sc->sc_gpio_ledpin = URTW_LED_PIN_GPIO0;
2512 urtw_8225_rf_init(struct urtw_softc *sc)
2514 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2519 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2523 error = urtw_8225_usb_init(sc);
2527 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2528 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2529 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2530 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2532 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2535 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2536 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2540 error = urtw_8185_rf_pins_enable(sc);
2543 usb_pause_mtx(&sc->sc_mtx, 1000);
2545 for (i = 0; i < N(urtw_8225_rf_part1); i++) {
2546 urtw_8225_write(sc, urtw_8225_rf_part1[i].reg,
2547 urtw_8225_rf_part1[i].val);
2548 usb_pause_mtx(&sc->sc_mtx, 1);
2550 usb_pause_mtx(&sc->sc_mtx, 100);
2552 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2553 usb_pause_mtx(&sc->sc_mtx, 200);
2555 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2556 usb_pause_mtx(&sc->sc_mtx, 200);
2558 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC3);
2560 for (i = 0; i < 95; i++) {
2561 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2562 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, urtw_8225_rxgain[i]);
2566 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC4);
2568 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC5);
2570 for (i = 0; i < 128; i++) {
2571 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2572 usb_pause_mtx(&sc->sc_mtx, 1);
2573 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2574 usb_pause_mtx(&sc->sc_mtx, 1);
2577 for (i = 0; i < N(urtw_8225_rf_part2); i++) {
2578 urtw_8187_write_phy_ofdm(sc, urtw_8225_rf_part2[i].reg,
2579 urtw_8225_rf_part2[i].val);
2580 usb_pause_mtx(&sc->sc_mtx, 1);
2583 error = urtw_8225_setgain(sc, 4);
2587 for (i = 0; i < N(urtw_8225_rf_part3); i++) {
2588 urtw_8187_write_phy_cck(sc, urtw_8225_rf_part3[i].reg,
2589 urtw_8225_rf_part3[i].val);
2590 usb_pause_mtx(&sc->sc_mtx, 1);
2593 urtw_write8_m(sc, URTW_TESTR, 0x0d);
2595 error = urtw_8225_set_txpwrlvl(sc, 1);
2599 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
2600 usb_pause_mtx(&sc->sc_mtx, 1);
2601 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
2602 usb_pause_mtx(&sc->sc_mtx, 1);
2604 /* TX ant A, 0x0 for B */
2605 error = urtw_8185_tx_antenna(sc, 0x3);
2608 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
2610 error = urtw_8225_rf_set_chan(sc, 1);
2617 urtw_8185_rf_pins_enable(struct urtw_softc *sc)
2619 usb_error_t error = 0;
2621 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1ff7);
2627 urtw_8185_tx_antenna(struct urtw_softc *sc, uint8_t ant)
2631 urtw_write8_m(sc, URTW_TX_ANTENNA, ant);
2632 usb_pause_mtx(&sc->sc_mtx, 1);
2638 urtw_8187_write_phy_ofdm_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2642 return urtw_8187_write_phy(sc, addr, data);
2646 urtw_8187_write_phy_cck_c(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2650 return urtw_8187_write_phy(sc, addr, data | 0x10000);
2654 urtw_8187_write_phy(struct urtw_softc *sc, uint8_t addr, uint32_t data)
2659 phyw = ((data << 8) | (addr | 0x80));
2660 urtw_write8_m(sc, URTW_PHY_MAGIC4, ((phyw & 0xff000000) >> 24));
2661 urtw_write8_m(sc, URTW_PHY_MAGIC3, ((phyw & 0x00ff0000) >> 16));
2662 urtw_write8_m(sc, URTW_PHY_MAGIC2, ((phyw & 0x0000ff00) >> 8));
2663 urtw_write8_m(sc, URTW_PHY_MAGIC1, ((phyw & 0x000000ff)));
2664 usb_pause_mtx(&sc->sc_mtx, 1);
2670 urtw_8225_setgain(struct urtw_softc *sc, int16_t gain)
2674 urtw_8187_write_phy_ofdm(sc, 0x0d, urtw_8225_gain[gain * 4]);
2675 urtw_8187_write_phy_ofdm(sc, 0x1b, urtw_8225_gain[gain * 4 + 2]);
2676 urtw_8187_write_phy_ofdm(sc, 0x1d, urtw_8225_gain[gain * 4 + 3]);
2677 urtw_8187_write_phy_ofdm(sc, 0x23, urtw_8225_gain[gain * 4 + 1]);
2683 urtw_8225_usb_init(struct urtw_softc *sc)
2688 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 0);
2689 urtw_write8_m(sc, URTW_GPIO, 0);
2690 error = urtw_read8e(sc, 0x53, &data);
2693 error = urtw_write8e(sc, 0x53, data | (1 << 7));
2696 urtw_write8_m(sc, URTW_RF_PINS_SELECT + 1, 4);
2697 urtw_write8_m(sc, URTW_GPIO, 0x20);
2698 urtw_write8_m(sc, URTW_GP_ENABLE, 0);
2700 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x80);
2701 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x80);
2702 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x80);
2704 usb_pause_mtx(&sc->sc_mtx, 500);
2710 urtw_8225_write_c(struct urtw_softc *sc, uint8_t addr, uint16_t data)
2712 uint16_t d80, d82, d84;
2715 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &d80);
2716 d80 &= URTW_RF_PINS_MAGIC1;
2717 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &d82);
2718 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &d84);
2719 d84 &= URTW_RF_PINS_MAGIC2;
2720 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, d82 | URTW_RF_PINS_MAGIC3);
2721 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84 | URTW_RF_PINS_MAGIC3);
2724 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2726 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80);
2729 error = urtw_8225_write_s16(sc, addr, 0x8225, &data);
2733 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2735 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, d80 | URTW_BB_HOST_BANG_EN);
2736 urtw_write16_m(sc, URTW_RF_PINS_SELECT, d84);
2737 usb_pause_mtx(&sc->sc_mtx, 2);
2743 urtw_8225_write_s16(struct urtw_softc *sc, uint8_t addr, int index,
2748 struct usb_device_request req;
2749 usb_error_t error = 0;
2753 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
2754 req.bRequest = URTW_8187_SETREGS_REQ;
2755 USETW(req.wValue, addr);
2756 USETW(req.wIndex, index);
2757 USETW(req.wLength, sizeof(uint16_t));
2758 buf[0] = (data16 & 0x00ff);
2759 buf[1] = (data16 & 0xff00) >> 8;
2761 error = urtw_do_request(sc, &req, buf);
2767 urtw_8225_rf_set_chan(struct urtw_softc *sc, int chan)
2771 error = urtw_8225_set_txpwrlvl(sc, chan);
2774 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
2775 usb_pause_mtx(&sc->sc_mtx, 10);
2781 urtw_8225_rf_set_sens(struct urtw_softc *sc, int sens)
2785 if (sens < 0 || sens > 6)
2790 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC1);
2793 URTW_8225_ADDR_C_MAGIC, URTW_8225_ADDR_C_DATA_MAGIC2);
2796 error = urtw_8225_setgain(sc, sens);
2800 urtw_8187_write_phy_cck(sc, 0x41, urtw_8225_threshold[sens]);
2807 urtw_8225_set_txpwrlvl(struct urtw_softc *sc, int chan)
2810 uint8_t *cck_pwltable;
2811 uint8_t cck_pwrlvl_max, ofdm_pwrlvl_min, ofdm_pwrlvl_max;
2812 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
2813 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
2816 cck_pwrlvl_max = 11;
2817 ofdm_pwrlvl_max = 25; /* 12 -> 25 */
2818 ofdm_pwrlvl_min = 10;
2820 /* CCK power setting */
2821 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
2822 idx = cck_pwrlvl % 6;
2823 set = cck_pwrlvl / 6;
2824 cck_pwltable = (chan == 14) ? urtw_8225_txpwr_cck_ch14 :
2825 urtw_8225_txpwr_cck;
2827 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
2828 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2829 for (i = 0; i < 8; i++) {
2830 urtw_8187_write_phy_cck(sc, 0x44 + i,
2831 cck_pwltable[idx * 8 + i]);
2833 usb_pause_mtx(&sc->sc_mtx, 1);
2835 /* OFDM power setting */
2836 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
2837 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
2838 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
2840 idx = ofdm_pwrlvl % 6;
2841 set = ofdm_pwrlvl / 6;
2843 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
2846 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
2847 urtw_8187_write_phy_ofdm(sc, 6, 0);
2848 urtw_8187_write_phy_ofdm(sc, 8, 0);
2850 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
2851 urtw_8225_tx_gain_cck_ofdm[set] >> 1);
2852 urtw_8187_write_phy_ofdm(sc, 0x5, urtw_8225_txpwr_ofdm[idx]);
2853 urtw_8187_write_phy_ofdm(sc, 0x7, urtw_8225_txpwr_ofdm[idx]);
2854 usb_pause_mtx(&sc->sc_mtx, 1);
2861 urtw_8225_rf_stop(struct urtw_softc *sc)
2866 urtw_8225_write(sc, 0x4, 0x1f);
2868 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2872 urtw_read8_m(sc, URTW_CONFIG3, &data);
2873 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
2874 if (sc->sc_flags & URTW_RTL8187B) {
2875 urtw_write32_m(sc, URTW_ANAPARAM2,
2876 URTW_8187B_8225_ANAPARAM2_OFF);
2877 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8187B_8225_ANAPARAM_OFF);
2878 urtw_write32_m(sc, URTW_ANAPARAM3,
2879 URTW_8187B_8225_ANAPARAM3_OFF);
2881 urtw_write32_m(sc, URTW_ANAPARAM2, URTW_8225_ANAPARAM2_OFF);
2882 urtw_write32_m(sc, URTW_ANAPARAM, URTW_8225_ANAPARAM_OFF);
2885 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
2886 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2895 urtw_8225v2_rf_init(struct urtw_softc *sc)
2897 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
2903 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
2907 error = urtw_8225_usb_init(sc);
2911 urtw_write32_m(sc, URTW_RF_TIMING, 0x000a8008);
2912 urtw_read16_m(sc, URTW_BRSR, &data); /* XXX ??? */
2913 urtw_write16_m(sc, URTW_BRSR, 0xffff);
2914 urtw_write32_m(sc, URTW_RF_PARA, 0x100044);
2916 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
2919 urtw_write8_m(sc, URTW_CONFIG3, 0x44);
2920 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
2924 error = urtw_8185_rf_pins_enable(sc);
2928 usb_pause_mtx(&sc->sc_mtx, 500);
2930 for (i = 0; i < N(urtw_8225v2_rf_part1); i++) {
2931 urtw_8225_write(sc, urtw_8225v2_rf_part1[i].reg,
2932 urtw_8225v2_rf_part1[i].val);
2934 usb_pause_mtx(&sc->sc_mtx, 50);
2937 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC1);
2939 for (i = 0; i < 95; i++) {
2940 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
2941 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
2942 urtw_8225v2_rxgain[i]);
2946 URTW_8225_ADDR_3_MAGIC, URTW_8225_ADDR_3_DATA_MAGIC1);
2948 URTW_8225_ADDR_5_MAGIC, URTW_8225_ADDR_5_DATA_MAGIC1);
2950 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC2);
2952 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2953 usb_pause_mtx(&sc->sc_mtx, 100);
2955 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2956 usb_pause_mtx(&sc->sc_mtx, 100);
2958 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2961 if (data32 != URTW_8225_ADDR_6_DATA_MAGIC1)
2962 device_printf(sc->sc_dev, "expect 0xe6!! (0x%x)\n", data32);
2963 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2)) {
2965 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC1);
2966 usb_pause_mtx(&sc->sc_mtx, 100);
2968 URTW_8225_ADDR_2_MAGIC, URTW_8225_ADDR_2_DATA_MAGIC2);
2969 usb_pause_mtx(&sc->sc_mtx, 50);
2970 error = urtw_8225_read(sc, URTW_8225_ADDR_6_MAGIC, &data32);
2973 if (!(data32 & URTW_8225_ADDR_6_DATA_MAGIC2))
2974 device_printf(sc->sc_dev, "RF calibration failed\n");
2976 usb_pause_mtx(&sc->sc_mtx, 100);
2979 URTW_8225_ADDR_0_MAGIC, URTW_8225_ADDR_0_DATA_MAGIC6);
2980 for (i = 0; i < 128; i++) {
2981 urtw_8187_write_phy_ofdm(sc, 0xb, urtw_8225_agc[i]);
2982 urtw_8187_write_phy_ofdm(sc, 0xa, (uint8_t)i + 0x80);
2985 for (i = 0; i < N(urtw_8225v2_rf_part2); i++) {
2986 urtw_8187_write_phy_ofdm(sc, urtw_8225v2_rf_part2[i].reg,
2987 urtw_8225v2_rf_part2[i].val);
2990 error = urtw_8225v2_setgain(sc, 4);
2994 for (i = 0; i < N(urtw_8225v2_rf_part3); i++) {
2995 urtw_8187_write_phy_cck(sc, urtw_8225v2_rf_part3[i].reg,
2996 urtw_8225v2_rf_part3[i].val);
2999 urtw_write8_m(sc, URTW_TESTR, 0x0d);
3001 error = urtw_8225v2_set_txpwrlvl(sc, 1);
3005 urtw_8187_write_phy_cck(sc, 0x10, 0x9b);
3006 urtw_8187_write_phy_ofdm(sc, 0x26, 0x90);
3008 /* TX ant A, 0x0 for B */
3009 error = urtw_8185_tx_antenna(sc, 0x3);
3012 urtw_write32_m(sc, URTW_HSSI_PARA, 0x3dc00002);
3014 error = urtw_8225_rf_set_chan(sc, 1);
3021 urtw_8225v2_rf_set_chan(struct urtw_softc *sc, int chan)
3025 error = urtw_8225v2_set_txpwrlvl(sc, chan);
3029 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3030 usb_pause_mtx(&sc->sc_mtx, 10);
3036 urtw_8225_read(struct urtw_softc *sc, uint8_t addr, uint32_t *data)
3040 uint8_t rlen = 12, wlen = 6;
3041 uint16_t o1, o2, o3, tmp;
3042 uint32_t d2w = ((uint32_t)(addr & 0x1f)) << 27;
3043 uint32_t mask = 0x80000000, value = 0;
3046 urtw_read16_m(sc, URTW_RF_PINS_OUTPUT, &o1);
3047 urtw_read16_m(sc, URTW_RF_PINS_ENABLE, &o2);
3048 urtw_read16_m(sc, URTW_RF_PINS_SELECT, &o3);
3049 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2 | URTW_RF_PINS_MAGIC4);
3050 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3 | URTW_RF_PINS_MAGIC4);
3051 o1 &= ~URTW_RF_PINS_MAGIC4;
3052 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN);
3054 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1);
3057 for (i = 0; i < (wlen / 2); i++, mask = mask >> 1) {
3058 bit = ((d2w & mask) != 0) ? 1 : 0;
3060 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3062 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3063 URTW_BB_HOST_BANG_CLK);
3065 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3066 URTW_BB_HOST_BANG_CLK);
3071 bit = ((d2w & mask) != 0) ? 1 : 0;
3072 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3073 URTW_BB_HOST_BANG_CLK);
3075 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 |
3076 URTW_BB_HOST_BANG_CLK);
3078 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1);
3081 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW |
3082 URTW_BB_HOST_BANG_CLK);
3084 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, bit | o1 | URTW_BB_HOST_BANG_RW);
3086 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_RW);
3090 for (i = 0; i < rlen; i++, mask = mask >> 1) {
3091 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3092 o1 | URTW_BB_HOST_BANG_RW);
3094 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3095 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3097 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3098 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3100 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3101 o1 | URTW_BB_HOST_BANG_RW | URTW_BB_HOST_BANG_CLK);
3104 urtw_read16_m(sc, URTW_RF_PINS_INPUT, &tmp);
3105 value |= ((tmp & URTW_BB_HOST_BANG_CLK) ? mask : 0);
3106 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT,
3107 o1 | URTW_BB_HOST_BANG_RW);
3111 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, o1 | URTW_BB_HOST_BANG_EN |
3112 URTW_BB_HOST_BANG_RW);
3115 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, o2);
3116 urtw_write16_m(sc, URTW_RF_PINS_SELECT, o3);
3117 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_OUTPUT_MAGIC1);
3127 urtw_8225v2_set_txpwrlvl(struct urtw_softc *sc, int chan)
3130 uint8_t *cck_pwrtable;
3131 uint8_t cck_pwrlvl_max = 15, ofdm_pwrlvl_max = 25, ofdm_pwrlvl_min = 10;
3132 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3133 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3136 /* CCK power setting */
3137 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ? cck_pwrlvl_max : cck_pwrlvl;
3138 cck_pwrlvl += sc->sc_txpwr_cck_base;
3139 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3140 cck_pwrtable = (chan == 14) ? urtw_8225v2_txpwr_cck_ch14 :
3141 urtw_8225v2_txpwr_cck;
3143 for (i = 0; i < 8; i++)
3144 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3146 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3147 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl]);
3148 usb_pause_mtx(&sc->sc_mtx, 1);
3150 /* OFDM power setting */
3151 ofdm_pwrlvl = (ofdm_pwrlvl > (ofdm_pwrlvl_max - ofdm_pwrlvl_min)) ?
3152 ofdm_pwrlvl_max : ofdm_pwrlvl + ofdm_pwrlvl_min;
3153 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3154 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3156 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3160 urtw_8187_write_phy_ofdm(sc, 2, 0x42);
3161 urtw_8187_write_phy_ofdm(sc, 5, 0x0);
3162 urtw_8187_write_phy_ofdm(sc, 6, 0x40);
3163 urtw_8187_write_phy_ofdm(sc, 7, 0x0);
3164 urtw_8187_write_phy_ofdm(sc, 8, 0x40);
3166 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3167 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl]);
3168 usb_pause_mtx(&sc->sc_mtx, 1);
3174 urtw_8225v2_setgain(struct urtw_softc *sc, int16_t gain)
3180 gainp = urtw_8225v2_gain_bg;
3181 urtw_8187_write_phy_ofdm(sc, 0x0d, gainp[gain * 3]);
3182 usb_pause_mtx(&sc->sc_mtx, 1);
3183 urtw_8187_write_phy_ofdm(sc, 0x1b, gainp[gain * 3 + 1]);
3184 usb_pause_mtx(&sc->sc_mtx, 1);
3185 urtw_8187_write_phy_ofdm(sc, 0x1d, gainp[gain * 3 + 2]);
3186 usb_pause_mtx(&sc->sc_mtx, 1);
3187 urtw_8187_write_phy_ofdm(sc, 0x21, 0x17);
3188 usb_pause_mtx(&sc->sc_mtx, 1);
3194 urtw_8225_isv2(struct urtw_softc *sc, int *ret)
3201 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, URTW_RF_PINS_MAGIC5);
3202 urtw_write16_m(sc, URTW_RF_PINS_SELECT, URTW_RF_PINS_MAGIC5);
3203 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, URTW_RF_PINS_MAGIC5);
3204 usb_pause_mtx(&sc->sc_mtx, 500);
3206 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3207 URTW_8225_ADDR_0_DATA_MAGIC1);
3209 error = urtw_8225_read(sc, URTW_8225_ADDR_8_MAGIC, &data);
3212 if (data != URTW_8225_ADDR_8_DATA_MAGIC1)
3215 error = urtw_8225_read(sc, URTW_8225_ADDR_9_MAGIC, &data);
3218 if (data != URTW_8225_ADDR_9_DATA_MAGIC1)
3222 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC,
3223 URTW_8225_ADDR_0_DATA_MAGIC2);
3229 urtw_8225v2b_rf_init(struct urtw_softc *sc)
3231 #define N(a) ((int)(sizeof(a) / sizeof((a)[0])))
3236 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3241 * initialize extra registers on 8187
3243 urtw_write16_m(sc, URTW_BRSR_8187B, 0xfff);
3246 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3247 data8 |= URTW_CW_CONF_PERPACKET_RETRY;
3248 urtw_write8_m(sc, URTW_CW_CONF, data8);
3251 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3252 data8 |= URTW_TX_AGC_CTL_PERPACKET_GAIN;
3253 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3255 /* Auto Rate Fallback Control */
3256 #define URTW_ARFR 0x1e0
3257 urtw_write16_m(sc, URTW_ARFR, 0xfff);
3258 urtw_read8_m(sc, URTW_RATE_FALLBACK, &data8);
3259 urtw_write8_m(sc, URTW_RATE_FALLBACK,
3260 data8 | URTW_RATE_FALLBACK_ENABLE);
3262 urtw_read8_m(sc, URTW_MSR, &data8);
3263 urtw_write8_m(sc, URTW_MSR, data8 & 0xf3);
3264 urtw_read8_m(sc, URTW_MSR, &data8);
3265 urtw_write8_m(sc, URTW_MSR, data8 | URTW_MSR_LINK_ENEDCA);
3266 urtw_write8_m(sc, URTW_ACM_CONTROL, sc->sc_acmctl);
3268 urtw_write16_m(sc, URTW_ATIM_WND, 2);
3269 urtw_write16_m(sc, URTW_BEACON_INTERVAL, 100);
3270 #define URTW_FEMR_FOR_8187B 0x1d4
3271 urtw_write16_m(sc, URTW_FEMR_FOR_8187B, 0xffff);
3274 urtw_read8_m(sc, URTW_CONFIG1, &data8);
3275 data8 = (data8 & 0x3f) | 0x80;
3276 urtw_write8_m(sc, URTW_CONFIG1, data8);
3278 /* applying MAC address again. */
3279 urtw_write32_m(sc, URTW_MAC0, ((uint32_t *)sc->sc_bssid)[0]);
3280 urtw_write16_m(sc, URTW_MAC4, ((uint32_t *)sc->sc_bssid)[1] & 0xffff);
3282 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3286 urtw_write8_m(sc, URTW_WPA_CONFIG, 0);
3291 for (i = 0; i < N(urtw_8225v2b_rf_part1); i++)
3292 urtw_write8_m(sc, urtw_8225v2b_rf_part1[i].reg,
3293 urtw_8225v2b_rf_part1[i].val);
3294 urtw_write16_m(sc, URTW_TID_AC_MAP, 0xfa50);
3295 urtw_write16_m(sc, URTW_INT_MIG, 0x0000);
3296 urtw_write32_m(sc, 0x1f0, 0);
3297 urtw_write32_m(sc, 0x1f4, 0);
3298 urtw_write8_m(sc, 0x1f8, 0);
3299 urtw_write32_m(sc, URTW_RF_TIMING, 0x4001);
3301 #define URTW_RFSW_CTRL 0x272
3302 urtw_write16_m(sc, URTW_RFSW_CTRL, 0x569a);
3307 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3310 urtw_read8_m(sc, URTW_CONFIG3, &data8);
3311 urtw_write8_m(sc, URTW_CONFIG3,
3312 data8 | URTW_CONFIG3_ANAPARAM_WRITE);
3314 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3318 /* setup RFE initial timing */
3319 urtw_write16_m(sc, URTW_RF_PINS_OUTPUT, 0x0480);
3320 urtw_write16_m(sc, URTW_RF_PINS_SELECT, 0x2488);
3321 urtw_write16_m(sc, URTW_RF_PINS_ENABLE, 0x1fff);
3322 usb_pause_mtx(&sc->sc_mtx, 1100);
3324 for (i = 0; i < N(urtw_8225v2b_rf_part0); i++) {
3325 urtw_8225_write(sc, urtw_8225v2b_rf_part0[i].reg,
3326 urtw_8225v2b_rf_part0[i].val);
3327 usb_pause_mtx(&sc->sc_mtx, 1);
3329 urtw_8225_write(sc, 0x00, 0x01b7);
3331 for (i = 0; i < 95; i++) {
3332 urtw_8225_write(sc, URTW_8225_ADDR_1_MAGIC, (uint8_t)(i + 1));
3333 usb_pause_mtx(&sc->sc_mtx, 1);
3334 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC,
3335 urtw_8225v2b_rxgain[i]);
3336 usb_pause_mtx(&sc->sc_mtx, 1);
3339 urtw_8225_write(sc, URTW_8225_ADDR_3_MAGIC, 0x080);
3340 usb_pause_mtx(&sc->sc_mtx, 1);
3341 urtw_8225_write(sc, URTW_8225_ADDR_5_MAGIC, 0x004);
3342 usb_pause_mtx(&sc->sc_mtx, 1);
3343 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x0b7);
3344 usb_pause_mtx(&sc->sc_mtx, 1);
3345 usb_pause_mtx(&sc->sc_mtx, 3000);
3346 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0xc4d);
3347 usb_pause_mtx(&sc->sc_mtx, 2000);
3348 urtw_8225_write(sc, URTW_8225_ADDR_2_MAGIC, 0x44d);
3349 usb_pause_mtx(&sc->sc_mtx, 1);
3350 urtw_8225_write(sc, URTW_8225_ADDR_0_MAGIC, 0x2bf);
3351 usb_pause_mtx(&sc->sc_mtx, 1);
3353 urtw_write8_m(sc, URTW_TX_GAIN_CCK, 0x03);
3354 urtw_write8_m(sc, URTW_TX_GAIN_OFDM, 0x07);
3355 urtw_write8_m(sc, URTW_TX_ANTENNA, 0x03);
3357 urtw_8187_write_phy_ofdm(sc, 0x80, 0x12);
3358 for (i = 0; i < 128; i++) {
3359 uint32_t addr, data;
3361 data = (urtw_8225z2_agc[i] << 8) | 0x0000008f;
3362 addr = ((i + 0x80) << 8) | 0x0000008e;
3364 urtw_8187_write_phy_ofdm(sc, data & 0x7f, (data >> 8) & 0xff);
3365 urtw_8187_write_phy_ofdm(sc, addr & 0x7f, (addr >> 8) & 0xff);
3366 urtw_8187_write_phy_ofdm(sc, 0x0e, 0x00);
3368 urtw_8187_write_phy_ofdm(sc, 0x80, 0x10);
3370 for (i = 0; i < N(urtw_8225v2b_rf_part2); i++)
3371 urtw_8187_write_phy_ofdm(sc, i, urtw_8225v2b_rf_part2[i].val);
3373 urtw_write32_m(sc, URTW_8187B_AC_VO, (7 << 12) | (3 << 8) | 0x1c);
3374 urtw_write32_m(sc, URTW_8187B_AC_VI, (7 << 12) | (3 << 8) | 0x1c);
3375 urtw_write32_m(sc, URTW_8187B_AC_BE, (7 << 12) | (3 << 8) | 0x1c);
3376 urtw_write32_m(sc, URTW_8187B_AC_BK, (7 << 12) | (3 << 8) | 0x1c);
3378 urtw_8187_write_phy_ofdm(sc, 0x97, 0x46);
3379 urtw_8187_write_phy_ofdm(sc, 0xa4, 0xb6);
3380 urtw_8187_write_phy_ofdm(sc, 0x85, 0xfc);
3381 urtw_8187_write_phy_cck(sc, 0xc1, 0x88);
3389 urtw_8225v2b_rf_set_chan(struct urtw_softc *sc, int chan)
3393 error = urtw_8225v2b_set_txpwrlvl(sc, chan);
3397 urtw_8225_write(sc, URTW_8225_ADDR_7_MAGIC, urtw_8225_channel[chan]);
3398 usb_pause_mtx(&sc->sc_mtx, 10);
3404 urtw_8225v2b_set_txpwrlvl(struct urtw_softc *sc, int chan)
3407 uint8_t *cck_pwrtable;
3408 uint8_t cck_pwrlvl_max = 15;
3409 uint8_t cck_pwrlvl = sc->sc_txpwr_cck[chan] & 0xff;
3410 uint8_t ofdm_pwrlvl = sc->sc_txpwr_ofdm[chan] & 0xff;
3413 /* CCK power setting */
3414 cck_pwrlvl = (cck_pwrlvl > cck_pwrlvl_max) ?
3415 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? cck_pwrlvl_max : 22) :
3416 (cck_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 0 : 7));
3417 cck_pwrlvl += sc->sc_txpwr_cck_base;
3418 cck_pwrlvl = (cck_pwrlvl > 35) ? 35 : cck_pwrlvl;
3419 cck_pwrtable = (chan == 14) ? urtw_8225v2b_txpwr_cck_ch14 :
3420 urtw_8225v2b_txpwr_cck;
3422 if (sc->sc_flags & URTW_RTL8187B_REV_B)
3423 cck_pwrtable += (cck_pwrlvl <= 6) ? 0 :
3424 ((cck_pwrlvl <= 11) ? 8 : 16);
3426 cck_pwrtable += (cck_pwrlvl <= 5) ? 0 :
3427 ((cck_pwrlvl <= 11) ? 8 : ((cck_pwrlvl <= 17) ? 16 : 24));
3429 for (i = 0; i < 8; i++)
3430 urtw_8187_write_phy_cck(sc, 0x44 + i, cck_pwrtable[i]);
3432 urtw_write8_m(sc, URTW_TX_GAIN_CCK,
3433 urtw_8225v2_tx_gain_cck_ofdm[cck_pwrlvl] << 1);
3434 usb_pause_mtx(&sc->sc_mtx, 1);
3436 /* OFDM power setting */
3437 ofdm_pwrlvl = (ofdm_pwrlvl > 15) ?
3438 ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 17 : 25) :
3439 (ofdm_pwrlvl + ((sc->sc_flags & URTW_RTL8187B_REV_B) ? 2 : 10));
3440 ofdm_pwrlvl += sc->sc_txpwr_ofdm_base;
3441 ofdm_pwrlvl = (ofdm_pwrlvl > 35) ? 35 : ofdm_pwrlvl;
3443 urtw_write8_m(sc, URTW_TX_GAIN_OFDM,
3444 urtw_8225v2_tx_gain_cck_ofdm[ofdm_pwrlvl] << 1);
3446 if (sc->sc_flags & URTW_RTL8187B_REV_B) {
3447 if (ofdm_pwrlvl <= 11) {
3448 urtw_8187_write_phy_ofdm(sc, 0x87, 0x60);
3449 urtw_8187_write_phy_ofdm(sc, 0x89, 0x60);
3451 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3452 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3455 if (ofdm_pwrlvl <= 11) {
3456 urtw_8187_write_phy_ofdm(sc, 0x87, 0x5c);
3457 urtw_8187_write_phy_ofdm(sc, 0x89, 0x5c);
3458 } else if (ofdm_pwrlvl <= 17) {
3459 urtw_8187_write_phy_ofdm(sc, 0x87, 0x54);
3460 urtw_8187_write_phy_ofdm(sc, 0x89, 0x54);
3462 urtw_8187_write_phy_ofdm(sc, 0x87, 0x50);
3463 urtw_8187_write_phy_ofdm(sc, 0x89, 0x50);
3466 usb_pause_mtx(&sc->sc_mtx, 1);
3472 urtw_read8e(struct urtw_softc *sc, int val, uint8_t *data)
3474 struct usb_device_request req;
3477 req.bmRequestType = UT_READ_VENDOR_DEVICE;
3478 req.bRequest = URTW_8187_GETREGS_REQ;
3479 USETW(req.wValue, val | 0xfe00);
3480 USETW(req.wIndex, 0);
3481 USETW(req.wLength, sizeof(uint8_t));
3483 error = urtw_do_request(sc, &req, data);
3488 urtw_write8e(struct urtw_softc *sc, int val, uint8_t data)
3490 struct usb_device_request req;
3492 req.bmRequestType = UT_WRITE_VENDOR_DEVICE;
3493 req.bRequest = URTW_8187_SETREGS_REQ;
3494 USETW(req.wValue, val | 0xfe00);
3495 USETW(req.wIndex, 0);
3496 USETW(req.wLength, sizeof(uint8_t));
3498 return (urtw_do_request(sc, &req, &data));
3502 urtw_8180_set_anaparam(struct urtw_softc *sc, uint32_t val)
3507 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3511 urtw_read8_m(sc, URTW_CONFIG3, &data);
3512 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3513 urtw_write32_m(sc, URTW_ANAPARAM, val);
3514 urtw_read8_m(sc, URTW_CONFIG3, &data);
3515 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3517 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3525 urtw_8185_set_anaparam2(struct urtw_softc *sc, uint32_t val)
3530 error = urtw_set_mode(sc, URTW_EPROM_CMD_CONFIG);
3534 urtw_read8_m(sc, URTW_CONFIG3, &data);
3535 urtw_write8_m(sc, URTW_CONFIG3, data | URTW_CONFIG3_ANAPARAM_WRITE);
3536 urtw_write32_m(sc, URTW_ANAPARAM2, val);
3537 urtw_read8_m(sc, URTW_CONFIG3, &data);
3538 urtw_write8_m(sc, URTW_CONFIG3, data & ~URTW_CONFIG3_ANAPARAM_WRITE);
3540 error = urtw_set_mode(sc, URTW_EPROM_CMD_NORMAL);
3548 urtw_intr_enable(struct urtw_softc *sc)
3552 urtw_write16_m(sc, URTW_INTR_MASK, 0xffff);
3558 urtw_intr_disable(struct urtw_softc *sc)
3562 urtw_write16_m(sc, URTW_INTR_MASK, 0);
3568 urtw_reset(struct urtw_softc *sc)
3573 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3576 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3580 error = urtw_intr_disable(sc);
3583 usb_pause_mtx(&sc->sc_mtx, 100);
3585 error = urtw_write8e(sc, 0x18, 0x10);
3588 error = urtw_write8e(sc, 0x18, 0x11);
3591 error = urtw_write8e(sc, 0x18, 0x00);
3594 usb_pause_mtx(&sc->sc_mtx, 100);
3596 urtw_read8_m(sc, URTW_CMD, &data);
3597 data = (data & 0x2) | URTW_CMD_RST;
3598 urtw_write8_m(sc, URTW_CMD, data);
3599 usb_pause_mtx(&sc->sc_mtx, 100);
3601 urtw_read8_m(sc, URTW_CMD, &data);
3602 if (data & URTW_CMD_RST) {
3603 device_printf(sc->sc_dev, "reset timeout\n");
3607 error = urtw_set_mode(sc, URTW_EPROM_CMD_LOAD);
3610 usb_pause_mtx(&sc->sc_mtx, 100);
3612 error = urtw_8180_set_anaparam(sc, URTW_8225_ANAPARAM_ON);
3615 error = urtw_8185_set_anaparam2(sc, URTW_8225_ANAPARAM2_ON);
3623 urtw_led_ctl(struct urtw_softc *sc, int mode)
3625 usb_error_t error = 0;
3627 switch (sc->sc_strategy) {
3628 case URTW_SW_LED_MODE0:
3629 error = urtw_led_mode0(sc, mode);
3631 case URTW_SW_LED_MODE1:
3632 error = urtw_led_mode1(sc, mode);
3634 case URTW_SW_LED_MODE2:
3635 error = urtw_led_mode2(sc, mode);
3637 case URTW_SW_LED_MODE3:
3638 error = urtw_led_mode3(sc, mode);
3641 DPRINTF(sc, URTW_DEBUG_STATE,
3642 "unsupported LED mode %d\n", sc->sc_strategy);
3643 error = USB_ERR_INVAL;
3651 urtw_led_mode0(struct urtw_softc *sc, int mode)
3655 case URTW_LED_CTL_POWER_ON:
3656 sc->sc_gpio_ledstate = URTW_LED_POWER_ON_BLINK;
3658 case URTW_LED_CTL_TX:
3659 if (sc->sc_gpio_ledinprogress == 1)
3662 sc->sc_gpio_ledstate = URTW_LED_BLINK_NORMAL;
3663 sc->sc_gpio_blinktime = 2;
3665 case URTW_LED_CTL_LINK:
3666 sc->sc_gpio_ledstate = URTW_LED_ON;
3669 DPRINTF(sc, URTW_DEBUG_STATE,
3670 "unsupported LED mode 0x%x", mode);
3671 return (USB_ERR_INVAL);
3674 switch (sc->sc_gpio_ledstate) {
3676 if (sc->sc_gpio_ledinprogress != 0)
3678 urtw_led_on(sc, URTW_LED_GPIO);
3680 case URTW_LED_BLINK_NORMAL:
3681 if (sc->sc_gpio_ledinprogress != 0)
3683 sc->sc_gpio_ledinprogress = 1;
3684 sc->sc_gpio_blinkstate = (sc->sc_gpio_ledon != 0) ?
3685 URTW_LED_OFF : URTW_LED_ON;
3686 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3688 case URTW_LED_POWER_ON_BLINK:
3689 urtw_led_on(sc, URTW_LED_GPIO);
3690 usb_pause_mtx(&sc->sc_mtx, 100);
3691 urtw_led_off(sc, URTW_LED_GPIO);
3694 DPRINTF(sc, URTW_DEBUG_STATE,
3695 "unknown LED status 0x%x", sc->sc_gpio_ledstate);
3696 return (USB_ERR_INVAL);
3702 urtw_led_mode1(struct urtw_softc *sc, int mode)
3704 return (USB_ERR_INVAL);
3708 urtw_led_mode2(struct urtw_softc *sc, int mode)
3710 return (USB_ERR_INVAL);
3714 urtw_led_mode3(struct urtw_softc *sc, int mode)
3716 return (USB_ERR_INVAL);
3720 urtw_led_on(struct urtw_softc *sc, int type)
3724 if (type == URTW_LED_GPIO) {
3725 switch (sc->sc_gpio_ledpin) {
3726 case URTW_LED_PIN_GPIO0:
3727 urtw_write8_m(sc, URTW_GPIO, 0x01);
3728 urtw_write8_m(sc, URTW_GP_ENABLE, 0x00);
3731 DPRINTF(sc, URTW_DEBUG_STATE,
3732 "unsupported LED PIN type 0x%x",
3733 sc->sc_gpio_ledpin);
3734 error = USB_ERR_INVAL;
3738 DPRINTF(sc, URTW_DEBUG_STATE,
3739 "unsupported LED type 0x%x", type);
3740 error = USB_ERR_INVAL;
3744 sc->sc_gpio_ledon = 1;
3750 urtw_led_off(struct urtw_softc *sc, int type)
3754 if (type == URTW_LED_GPIO) {
3755 switch (sc->sc_gpio_ledpin) {
3756 case URTW_LED_PIN_GPIO0:
3757 urtw_write8_m(sc, URTW_GPIO, URTW_GPIO_DATA_MAGIC1);
3759 URTW_GP_ENABLE, URTW_GP_ENABLE_DATA_MAGIC1);
3762 DPRINTF(sc, URTW_DEBUG_STATE,
3763 "unsupported LED PIN type 0x%x",
3764 sc->sc_gpio_ledpin);
3765 error = USB_ERR_INVAL;
3769 DPRINTF(sc, URTW_DEBUG_STATE,
3770 "unsupported LED type 0x%x", type);
3771 error = USB_ERR_INVAL;
3775 sc->sc_gpio_ledon = 0;
3782 urtw_led_ch(void *arg)
3784 struct urtw_softc *sc = arg;
3785 struct ifnet *ifp = sc->sc_ifp;
3786 struct ieee80211com *ic = ifp->if_l2com;
3788 ieee80211_runtask(ic, &sc->sc_led_task);
3792 urtw_ledtask(void *arg, int pending)
3794 struct urtw_softc *sc = arg;
3796 if (sc->sc_strategy != URTW_SW_LED_MODE0) {
3797 DPRINTF(sc, URTW_DEBUG_STATE,
3798 "could not process a LED strategy 0x%x",
3809 urtw_led_blink(struct urtw_softc *sc)
3814 if (sc->sc_gpio_blinkstate == URTW_LED_ON)
3815 error = urtw_led_on(sc, URTW_LED_GPIO);
3817 error = urtw_led_off(sc, URTW_LED_GPIO);
3818 sc->sc_gpio_blinktime--;
3819 if (sc->sc_gpio_blinktime == 0)
3822 if (sc->sc_gpio_ledstate != URTW_LED_BLINK_NORMAL &&
3823 sc->sc_gpio_ledstate != URTW_LED_BLINK_SLOWLY &&
3824 sc->sc_gpio_ledstate != URTW_LED_BLINK_CM3)
3828 if (sc->sc_gpio_ledstate == URTW_LED_ON &&
3829 sc->sc_gpio_ledon == 0)
3830 error = urtw_led_on(sc, URTW_LED_GPIO);
3831 else if (sc->sc_gpio_ledstate == URTW_LED_OFF &&
3832 sc->sc_gpio_ledon == 1)
3833 error = urtw_led_off(sc, URTW_LED_GPIO);
3835 sc->sc_gpio_blinktime = 0;
3836 sc->sc_gpio_ledinprogress = 0;
3840 sc->sc_gpio_blinkstate = (sc->sc_gpio_blinkstate != URTW_LED_ON) ?
3841 URTW_LED_ON : URTW_LED_OFF;
3843 switch (sc->sc_gpio_ledstate) {
3844 case URTW_LED_BLINK_NORMAL:
3845 usb_callout_reset(&sc->sc_led_ch, hz, urtw_led_ch, sc);
3848 DPRINTF(sc, URTW_DEBUG_STATE,
3849 "unknown LED status 0x%x",
3850 sc->sc_gpio_ledstate);
3851 return (USB_ERR_INVAL);
3857 urtw_rx_enable(struct urtw_softc *sc)
3862 usbd_transfer_start((sc->sc_flags & URTW_RTL8187B) ?
3863 sc->sc_xfer[URTW_8187B_BULK_RX] : sc->sc_xfer[URTW_8187L_BULK_RX]);
3865 error = urtw_rx_setconf(sc);
3869 if ((sc->sc_flags & URTW_RTL8187B) == 0) {
3870 urtw_read8_m(sc, URTW_CMD, &data);
3871 urtw_write8_m(sc, URTW_CMD, data | URTW_CMD_RX_ENABLE);
3878 urtw_tx_enable(struct urtw_softc *sc)
3884 if (sc->sc_flags & URTW_RTL8187B) {
3885 urtw_read32_m(sc, URTW_TX_CONF, &data);
3886 data &= ~URTW_TX_LOOPBACK_MASK;
3887 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3888 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3889 data &= ~URTW_TX_SWPLCPLEN;
3890 data |= URTW_TX_HW_SEQNUM | URTW_TX_DISREQQSIZE |
3891 (7 << 8) | /* short retry limit */
3892 (7 << 0) | /* long retry limit */
3893 (7 << 21); /* MAX TX DMA */
3894 urtw_write32_m(sc, URTW_TX_CONF, data);
3896 urtw_read8_m(sc, URTW_MSR, &data8);
3897 data8 |= URTW_MSR_LINK_ENEDCA;
3898 urtw_write8_m(sc, URTW_MSR, data8);
3902 urtw_read8_m(sc, URTW_CW_CONF, &data8);
3903 data8 &= ~(URTW_CW_CONF_PERPACKET_CW | URTW_CW_CONF_PERPACKET_RETRY);
3904 urtw_write8_m(sc, URTW_CW_CONF, data8);
3906 urtw_read8_m(sc, URTW_TX_AGC_CTL, &data8);
3907 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_GAIN;
3908 data8 &= ~URTW_TX_AGC_CTL_PERPACKET_ANTSEL;
3909 data8 &= ~URTW_TX_AGC_CTL_FEEDBACK_ANT;
3910 urtw_write8_m(sc, URTW_TX_AGC_CTL, data8);
3912 urtw_read32_m(sc, URTW_TX_CONF, &data);
3913 data &= ~URTW_TX_LOOPBACK_MASK;
3914 data |= URTW_TX_LOOPBACK_NONE;
3915 data &= ~(URTW_TX_DPRETRY_MASK | URTW_TX_RTSRETRY_MASK);
3916 data |= sc->sc_tx_retry << URTW_TX_DPRETRY_SHIFT;
3917 data |= sc->sc_rts_retry << URTW_TX_RTSRETRY_SHIFT;
3918 data &= ~(URTW_TX_NOCRC | URTW_TX_MXDMA_MASK);
3919 data |= URTW_TX_MXDMA_2048 | URTW_TX_CWMIN | URTW_TX_DISCW;
3920 data &= ~URTW_TX_SWPLCPLEN;
3921 data |= URTW_TX_NOICV;
3922 urtw_write32_m(sc, URTW_TX_CONF, data);
3924 urtw_read8_m(sc, URTW_CMD, &data8);
3925 urtw_write8_m(sc, URTW_CMD, data8 | URTW_CMD_TX_ENABLE);
3931 urtw_rx_setconf(struct urtw_softc *sc)
3933 struct ifnet *ifp = sc->sc_ifp;
3934 struct ieee80211com *ic = ifp->if_l2com;
3938 urtw_read32_m(sc, URTW_RX, &data);
3939 data = data &~ URTW_RX_FILTER_MASK;
3940 if (sc->sc_flags & URTW_RTL8187B) {
3941 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA |
3942 URTW_RX_FILTER_MCAST | URTW_RX_FILTER_BCAST |
3943 URTW_RX_FILTER_NICMAC | URTW_RX_CHECK_BSSID |
3944 URTW_RX_FIFO_THRESHOLD_NONE |
3945 URTW_MAX_RX_DMA_2048 |
3946 URTW_RX_AUTORESETPHY | URTW_RCR_ONLYERLPKT;
3948 data = data | URTW_RX_FILTER_MNG | URTW_RX_FILTER_DATA;
3949 data = data | URTW_RX_FILTER_BCAST | URTW_RX_FILTER_MCAST;
3951 if (ic->ic_opmode == IEEE80211_M_MONITOR) {
3952 data = data | URTW_RX_FILTER_ICVERR;
3953 data = data | URTW_RX_FILTER_PWR;
3955 if (sc->sc_crcmon == 1 && ic->ic_opmode == IEEE80211_M_MONITOR)
3956 data = data | URTW_RX_FILTER_CRCERR;
3958 if (ic->ic_opmode == IEEE80211_M_MONITOR ||
3959 (ifp->if_flags & (IFF_ALLMULTI | IFF_PROMISC))) {
3960 data = data | URTW_RX_FILTER_ALLMAC;
3962 data = data | URTW_RX_FILTER_NICMAC;
3963 data = data | URTW_RX_CHECK_BSSID;
3966 data = data &~ URTW_RX_FIFO_THRESHOLD_MASK;
3967 data = data | URTW_RX_FIFO_THRESHOLD_NONE |
3968 URTW_RX_AUTORESETPHY;
3969 data = data &~ URTW_MAX_RX_DMA_MASK;
3970 data = data | URTW_MAX_RX_DMA_2048 | URTW_RCR_ONLYERLPKT;
3973 urtw_write32_m(sc, URTW_RX, data);
3978 static struct mbuf *
3979 urtw_rxeof(struct usb_xfer *xfer, struct urtw_data *data, int *rssi_p,
3982 int actlen, flen, rssi;
3983 struct ieee80211_frame *wh;
3984 struct mbuf *m, *mnew;
3985 struct urtw_softc *sc = data->sc;
3986 struct ifnet *ifp = sc->sc_ifp;
3987 struct ieee80211com *ic = ifp->if_l2com;
3988 uint8_t noise = 0, rate;
3990 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
3992 if (actlen < (int)URTW_MIN_RXBUFSZ) {
3997 if (sc->sc_flags & URTW_RTL8187B) {
3998 struct urtw_8187b_rxhdr *rx;
4000 rx = (struct urtw_8187b_rxhdr *)(data->buf +
4001 (actlen - (sizeof(struct urtw_8187b_rxhdr))));
4002 flen = le32toh(rx->flag) & 0xfff;
4003 if (flen > actlen) {
4007 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
4009 rssi = rx->rssi & URTW_RX_RSSI_MASK;
4012 struct urtw_8187l_rxhdr *rx;
4014 rx = (struct urtw_8187l_rxhdr *)(data->buf +
4015 (actlen - (sizeof(struct urtw_8187l_rxhdr))));
4016 flen = le32toh(rx->flag) & 0xfff;
4017 if (flen > actlen) {
4022 rate = (le32toh(rx->flag) >> URTW_RX_FLAG_RXRATE_SHIFT) & 0xf;
4024 rssi = rx->rssi & URTW_RX_8187L_RSSI_MASK;
4028 mnew = m_getcl(M_NOWAIT, MT_DATA, M_PKTHDR);
4036 data->buf = mtod(mnew, uint8_t *);
4039 m->m_pkthdr.rcvif = ifp;
4040 m->m_pkthdr.len = m->m_len = flen - IEEE80211_CRC_LEN;
4042 if (ieee80211_radiotap_active(ic)) {
4043 struct urtw_rx_radiotap_header *tap = &sc->sc_rxtap;
4045 /* XXX Are variables correct? */
4046 tap->wr_chan_freq = htole16(ic->ic_curchan->ic_freq);
4047 tap->wr_chan_flags = htole16(ic->ic_curchan->ic_flags);
4048 tap->wr_dbm_antsignal = (int8_t)rssi;
4051 wh = mtod(m, struct ieee80211_frame *);
4052 if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == IEEE80211_FC0_TYPE_DATA)
4053 sc->sc_currate = (rate > 0) ? rate : sc->sc_currate;
4056 *nf_p = noise; /* XXX correct? */
4062 urtw_bulk_rx_callback(struct usb_xfer *xfer, usb_error_t error)
4064 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4065 struct ifnet *ifp = sc->sc_ifp;
4066 struct ieee80211com *ic = ifp->if_l2com;
4067 struct ieee80211_frame *wh;
4068 struct ieee80211_node *ni;
4069 struct mbuf *m = NULL;
4070 struct urtw_data *data;
4074 URTW_ASSERT_LOCKED(sc);
4076 switch (USB_GET_STATE(xfer)) {
4077 case USB_ST_TRANSFERRED:
4078 data = STAILQ_FIRST(&sc->sc_rx_active);
4081 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4082 m = urtw_rxeof(xfer, data, &rssi, &nf);
4083 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4087 data = STAILQ_FIRST(&sc->sc_rx_inactive);
4089 KASSERT(m == NULL, ("mbuf isn't NULL"));
4092 STAILQ_REMOVE_HEAD(&sc->sc_rx_inactive, next);
4093 STAILQ_INSERT_TAIL(&sc->sc_rx_active, data, next);
4094 usbd_xfer_set_frame_data(xfer, 0, data->buf,
4095 usbd_xfer_max_len(xfer));
4096 usbd_transfer_submit(xfer);
4099 * To avoid LOR we should unlock our private mutex here to call
4100 * ieee80211_input() because here is at the end of a USB
4101 * callback and safe to unlock.
4105 wh = mtod(m, struct ieee80211_frame *);
4106 ni = ieee80211_find_rxnode(ic,
4107 (struct ieee80211_frame_min *)wh);
4109 (void) ieee80211_input(ni, m, rssi, nf);
4110 /* node is no longer needed */
4111 ieee80211_free_node(ni);
4113 (void) ieee80211_input_all(ic, m, rssi, nf);
4119 /* needs it to the inactive queue due to a error. */
4120 data = STAILQ_FIRST(&sc->sc_rx_active);
4122 STAILQ_REMOVE_HEAD(&sc->sc_rx_active, next);
4123 STAILQ_INSERT_TAIL(&sc->sc_rx_inactive, data, next);
4125 if (error != USB_ERR_CANCELLED) {
4126 usbd_xfer_set_stall(xfer);
4134 #define URTW_STATUS_TYPE_TXCLOSE 1
4135 #define URTW_STATUS_TYPE_BEACON_INTR 0
4138 urtw_txstatus_eof(struct usb_xfer *xfer)
4140 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4141 struct ifnet *ifp = sc->sc_ifp;
4142 int actlen, type, pktretry, seq;
4145 usbd_xfer_status(xfer, &actlen, NULL, NULL, NULL);
4147 if (actlen != sizeof(uint64_t))
4150 val = le64toh(sc->sc_txstatus);
4151 type = (val >> 30) & 0x3;
4152 if (type == URTW_STATUS_TYPE_TXCLOSE) {
4153 pktretry = val & 0xff;
4154 seq = (val >> 16) & 0xff;
4155 if (pktretry == URTW_TX_MAXRETRY)
4157 DPRINTF(sc, URTW_DEBUG_TXSTATUS, "pktretry %d seq %#x\n",
4163 urtw_bulk_tx_status_callback(struct usb_xfer *xfer, usb_error_t error)
4165 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4166 struct ifnet *ifp = sc->sc_ifp;
4167 void *dma_buf = usbd_xfer_get_frame_buffer(xfer, 0);
4169 URTW_ASSERT_LOCKED(sc);
4171 switch (USB_GET_STATE(xfer)) {
4172 case USB_ST_TRANSFERRED:
4173 urtw_txstatus_eof(xfer);
4177 memcpy(dma_buf, &sc->sc_txstatus, sizeof(uint64_t));
4178 usbd_xfer_set_frame_len(xfer, 0, sizeof(uint64_t));
4179 usbd_transfer_submit(xfer);
4182 if (error != USB_ERR_CANCELLED) {
4183 usbd_xfer_set_stall(xfer);
4192 urtw_txeof(struct usb_xfer *xfer, struct urtw_data *data)
4194 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4195 struct ifnet *ifp = sc->sc_ifp;
4198 URTW_ASSERT_LOCKED(sc);
4201 * Do any tx complete callback. Note this must be done before releasing
4202 * the node reference.
4206 if (m->m_flags & M_TXCB) {
4208 ieee80211_process_callback(data->ni, m, 0);
4214 ieee80211_free_node(data->ni);
4219 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE;
4223 urtw_bulk_tx_callback(struct usb_xfer *xfer, usb_error_t error)
4225 struct urtw_softc *sc = usbd_xfer_softc(xfer);
4226 struct ifnet *ifp = sc->sc_ifp;
4227 struct urtw_data *data;
4229 URTW_ASSERT_LOCKED(sc);
4231 switch (USB_GET_STATE(xfer)) {
4232 case USB_ST_TRANSFERRED:
4233 data = STAILQ_FIRST(&sc->sc_tx_active);
4236 STAILQ_REMOVE_HEAD(&sc->sc_tx_active, next);
4237 urtw_txeof(xfer, data);
4238 STAILQ_INSERT_TAIL(&sc->sc_tx_inactive, data, next);
4242 data = STAILQ_FIRST(&sc->sc_tx_pending);
4244 DPRINTF(sc, URTW_DEBUG_XMIT,
4245 "%s: empty pending queue\n", __func__);
4248 STAILQ_REMOVE_HEAD(&sc->sc_tx_pending, next);
4249 STAILQ_INSERT_TAIL(&sc->sc_tx_active, data, next);
4251 usbd_xfer_set_frame_data(xfer, 0, data->buf, data->buflen);
4252 usbd_transfer_submit(xfer);
4259 data = STAILQ_FIRST(&sc->sc_tx_active);
4262 if (data->ni != NULL) {
4263 ieee80211_free_node(data->ni);
4267 if (error != USB_ERR_CANCELLED) {
4268 usbd_xfer_set_stall(xfer);
4275 static struct urtw_data *
4276 _urtw_getbuf(struct urtw_softc *sc)
4278 struct urtw_data *bf;
4280 bf = STAILQ_FIRST(&sc->sc_tx_inactive);
4282 STAILQ_REMOVE_HEAD(&sc->sc_tx_inactive, next);
4286 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: %s\n", __func__,
4287 "out of xmit buffers");
4291 static struct urtw_data *
4292 urtw_getbuf(struct urtw_softc *sc)
4294 struct urtw_data *bf;
4296 URTW_ASSERT_LOCKED(sc);
4298 bf = _urtw_getbuf(sc);
4300 struct ifnet *ifp = sc->sc_ifp;
4302 DPRINTF(sc, URTW_DEBUG_XMIT, "%s: stop queue\n", __func__);
4303 ifp->if_drv_flags |= IFF_DRV_OACTIVE;
4309 urtw_isbmode(uint16_t rate)
4312 return ((rate <= 22 && rate != 12 && rate != 18) ||
4313 rate == 44) ? (1) : (0);
4317 urtw_rate2dbps(uint16_t rate)
4337 urtw_compute_txtime(uint16_t framelen, uint16_t rate,
4338 uint8_t ismgt, uint8_t isshort)
4340 uint16_t ceiling, frametime, n_dbps;
4342 if (urtw_isbmode(rate)) {
4343 if (ismgt || !isshort || rate == 2)
4344 frametime = (uint16_t)(144 + 48 +
4345 (framelen * 8 / (rate / 2)));
4347 frametime = (uint16_t)(72 + 24 +
4348 (framelen * 8 / (rate / 2)));
4349 if ((framelen * 8 % (rate / 2)) != 0)
4352 n_dbps = urtw_rate2dbps(rate);
4353 ceiling = (16 + 8 * framelen + 6) / n_dbps
4354 + (((16 + 8 * framelen + 6) % n_dbps) ? 1 : 0);
4355 frametime = (uint16_t)(16 + 4 + 4 * ceiling + 6);
4361 * Callback from the 802.11 layer to update the
4362 * slot time based on the current setting.
4365 urtw_updateslot(struct ifnet *ifp)
4367 struct urtw_softc *sc = ifp->if_softc;
4368 struct ieee80211com *ic = ifp->if_l2com;
4370 ieee80211_runtask(ic, &sc->sc_updateslot_task);
4374 urtw_updateslottask(void *arg, int pending)
4376 struct urtw_softc *sc = arg;
4377 struct ifnet *ifp = sc->sc_ifp;
4378 struct ieee80211com *ic = ifp->if_l2com;
4381 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0)
4385 if (sc->sc_flags & URTW_RTL8187B) {
4386 urtw_write8_m(sc, URTW_SIFS, 0x22);
4387 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan))
4388 urtw_write8_m(sc, URTW_SLOT, 0x9);
4390 urtw_write8_m(sc, URTW_SLOT, 0x14);
4391 urtw_write8_m(sc, URTW_8187B_EIFS, 0x5b);
4392 urtw_write8_m(sc, URTW_CARRIER_SCOUNT, 0x5b);
4394 urtw_write8_m(sc, URTW_SIFS, 0x22);
4395 if (sc->sc_state == IEEE80211_S_ASSOC &&
4396 ic->ic_flags & IEEE80211_F_SHSLOT)
4397 urtw_write8_m(sc, URTW_SLOT, 0x9);
4399 urtw_write8_m(sc, URTW_SLOT, 0x14);
4400 if (IEEE80211_IS_CHAN_ANYG(ic->ic_curchan)) {
4401 urtw_write8_m(sc, URTW_DIFS, 0x14);
4402 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x14);
4403 urtw_write8_m(sc, URTW_CW_VAL, 0x73);
4405 urtw_write8_m(sc, URTW_DIFS, 0x24);
4406 urtw_write8_m(sc, URTW_EIFS, 0x5b - 0x24);
4407 urtw_write8_m(sc, URTW_CW_VAL, 0xa5);
4415 urtw_sysctl_node(struct urtw_softc *sc)
4417 #define URTW_SYSCTL_STAT_ADD32(c, h, n, p, d) \
4418 SYSCTL_ADD_UINT(c, h, OID_AUTO, n, CTLFLAG_RD, p, 0, d)
4419 struct sysctl_ctx_list *ctx;
4420 struct sysctl_oid_list *child, *parent;
4421 struct sysctl_oid *tree;
4422 struct urtw_stats *stats = &sc->sc_stats;
4424 ctx = device_get_sysctl_ctx(sc->sc_dev);
4425 child = SYSCTL_CHILDREN(device_get_sysctl_tree(sc->sc_dev));
4427 tree = SYSCTL_ADD_NODE(ctx, child, OID_AUTO, "stats", CTLFLAG_RD,
4428 NULL, "URTW statistics");
4429 parent = SYSCTL_CHILDREN(tree);
4431 /* Tx statistics. */
4432 tree = SYSCTL_ADD_NODE(ctx, parent, OID_AUTO, "tx", CTLFLAG_RD,
4433 NULL, "Tx MAC statistics");
4434 child = SYSCTL_CHILDREN(tree);
4435 URTW_SYSCTL_STAT_ADD32(ctx, child, "1m", &stats->txrates[0],
4437 URTW_SYSCTL_STAT_ADD32(ctx, child, "2m", &stats->txrates[1],
4439 URTW_SYSCTL_STAT_ADD32(ctx, child, "5.5m", &stats->txrates[2],
4441 URTW_SYSCTL_STAT_ADD32(ctx, child, "6m", &stats->txrates[4],
4443 URTW_SYSCTL_STAT_ADD32(ctx, child, "9m", &stats->txrates[5],
4445 URTW_SYSCTL_STAT_ADD32(ctx, child, "11m", &stats->txrates[3],
4447 URTW_SYSCTL_STAT_ADD32(ctx, child, "12m", &stats->txrates[6],
4449 URTW_SYSCTL_STAT_ADD32(ctx, child, "18m", &stats->txrates[7],
4451 URTW_SYSCTL_STAT_ADD32(ctx, child, "24m", &stats->txrates[8],
4453 URTW_SYSCTL_STAT_ADD32(ctx, child, "36m", &stats->txrates[9],
4455 URTW_SYSCTL_STAT_ADD32(ctx, child, "48m", &stats->txrates[10],
4457 URTW_SYSCTL_STAT_ADD32(ctx, child, "54m", &stats->txrates[11],
4459 #undef URTW_SYSCTL_STAT_ADD32
4462 static device_method_t urtw_methods[] = {
4463 DEVMETHOD(device_probe, urtw_match),
4464 DEVMETHOD(device_attach, urtw_attach),
4465 DEVMETHOD(device_detach, urtw_detach),
4468 static driver_t urtw_driver = {
4470 .methods = urtw_methods,
4471 .size = sizeof(struct urtw_softc)
4473 static devclass_t urtw_devclass;
4475 DRIVER_MODULE(urtw, uhub, urtw_driver, urtw_devclass, NULL, 0);
4476 MODULE_DEPEND(urtw, wlan, 1, 1, 1);
4477 MODULE_DEPEND(urtw, usb, 1, 1, 1);
4478 MODULE_VERSION(urtw, 1);