2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
30 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
31 * Copyright (C) 1995, 1996 TooLs GmbH.
32 * All rights reserved.
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 * must display the following acknowledgement:
44 * This product includes software developed by TooLs GmbH.
45 * 4. The name of TooLs GmbH may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
62 * Copyright (C) 2001 Benno Rice.
63 * All rights reserved.
65 * Redistribution and use in source and binary forms, with or without
66 * modification, are permitted provided that the following conditions
68 * 1. Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in the
72 * documentation and/or other materials provided with the distribution.
74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is also stored by the
93 * logical address mapping module, this module may throw away valid virtual
94 * to physical mappings at almost any time. However, invalidations of
95 * mappings must be done as requested.
97 * In order to cope with hardware architectures which make virtual to
98 * physical map invalidates expensive, this module may delay invalidate
99 * reduced protection operations until such time as they are actually
100 * necessary. This module is given full information as to which processors
101 * are currently using which maps, and to when physical maps must be made
105 #include "opt_kstack_pages.h"
107 #include <sys/param.h>
108 #include <sys/kernel.h>
109 #include <sys/queue.h>
110 #include <sys/cpuset.h>
112 #include <sys/lock.h>
113 #include <sys/msgbuf.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
117 #include <sys/sched.h>
118 #include <sys/sysctl.h>
119 #include <sys/systm.h>
120 #include <sys/vmmeter.h>
122 #include <dev/ofw/openfirm.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_object.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_pageout.h>
134 #include <machine/cpu.h>
135 #include <machine/platform.h>
136 #include <machine/bat.h>
137 #include <machine/frame.h>
138 #include <machine/md_var.h>
139 #include <machine/psl.h>
140 #include <machine/pte.h>
141 #include <machine/smp.h>
142 #include <machine/sr.h>
143 #include <machine/mmuvar.h>
144 #include <machine/trap_aim.h>
150 #define TODO panic("%s: not implemented", __func__);
152 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
153 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
154 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
163 extern unsigned char _etext[];
164 extern unsigned char _end[];
166 extern int dumpsys_minidump;
169 * Map of physical memory regions.
171 static struct mem_region *regions;
172 static struct mem_region *pregions;
173 static u_int phys_avail_count;
174 static int regions_sz, pregions_sz;
175 static struct ofw_map *translations;
178 * Lock for the pteg and pvo tables.
180 struct mtx moea_table_mutex;
181 struct mtx moea_vsid_mutex;
183 /* tlbie instruction synchronization */
184 static struct mtx tlbie_mtx;
189 static struct pteg *moea_pteg_table;
190 u_int moea_pteg_count;
191 u_int moea_pteg_mask;
196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
197 struct pvo_head moea_pvo_kunmanaged =
198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
200 static struct rwlock_padalign pvh_global_lock;
202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
205 #define BPVO_POOL_SIZE 32768
206 static struct pvo_entry *moea_bpvo_pool;
207 static int moea_bpvo_pool_index = 0;
209 #define VSID_NBPW (sizeof(u_int32_t) * 8)
210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
212 static boolean_t moea_initialized = FALSE;
217 u_int moea_pte_valid = 0;
218 u_int moea_pte_overflow = 0;
219 u_int moea_pte_replacements = 0;
220 u_int moea_pvo_entries = 0;
221 u_int moea_pvo_enter_calls = 0;
222 u_int moea_pvo_remove_calls = 0;
223 u_int moea_pte_spills = 0;
224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
227 &moea_pte_overflow, 0, "");
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
229 &moea_pte_replacements, 0, "");
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
233 &moea_pvo_enter_calls, 0, "");
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
235 &moea_pvo_remove_calls, 0, "");
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
237 &moea_pte_spills, 0, "");
240 * Allocate physical memory for use in moea_bootstrap.
242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
247 static int moea_pte_insert(u_int, struct pte *);
252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
253 vm_offset_t, vm_offset_t, u_int, int);
254 static void moea_pvo_remove(struct pvo_entry *, int);
255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
261 static void moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
262 vm_prot_t, boolean_t);
263 static void moea_syncicache(vm_offset_t, vm_size_t);
264 static boolean_t moea_query_bit(vm_page_t, int);
265 static u_int moea_clear_bit(vm_page_t, int);
266 static void moea_kremove(mmu_t, vm_offset_t);
267 int moea_pte_spill(vm_offset_t);
270 * Kernel MMU interface
272 void moea_change_wiring(mmu_t, pmap_t, vm_offset_t, boolean_t);
273 void moea_clear_modify(mmu_t, vm_page_t);
274 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
275 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
276 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
277 void moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, boolean_t);
278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
283 void moea_init(mmu_t);
284 boolean_t moea_is_modified(mmu_t, vm_page_t);
285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
286 boolean_t moea_is_referenced(mmu_t, vm_page_t);
287 int moea_ts_referenced(mmu_t, vm_page_t);
288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
290 int moea_page_wired_mappings(mmu_t, vm_page_t);
291 void moea_pinit(mmu_t, pmap_t);
292 void moea_pinit0(mmu_t, pmap_t);
293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
295 void moea_qremove(mmu_t, vm_offset_t, int);
296 void moea_release(mmu_t, pmap_t);
297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
298 void moea_remove_all(mmu_t, vm_page_t);
299 void moea_remove_write(mmu_t, vm_page_t);
300 void moea_zero_page(mmu_t, vm_page_t);
301 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
302 void moea_zero_page_idle(mmu_t, vm_page_t);
303 void moea_activate(mmu_t, struct thread *);
304 void moea_deactivate(mmu_t, struct thread *);
305 void moea_cpu_bootstrap(mmu_t, int);
306 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
307 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
308 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
309 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
310 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
311 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
312 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
313 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
314 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
315 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
316 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
318 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev);
320 static mmu_method_t moea_methods[] = {
321 MMUMETHOD(mmu_change_wiring, moea_change_wiring),
322 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
323 MMUMETHOD(mmu_copy_page, moea_copy_page),
324 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
325 MMUMETHOD(mmu_enter, moea_enter),
326 MMUMETHOD(mmu_enter_object, moea_enter_object),
327 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
328 MMUMETHOD(mmu_extract, moea_extract),
329 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
330 MMUMETHOD(mmu_init, moea_init),
331 MMUMETHOD(mmu_is_modified, moea_is_modified),
332 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
333 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
334 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
335 MMUMETHOD(mmu_map, moea_map),
336 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
337 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
338 MMUMETHOD(mmu_pinit, moea_pinit),
339 MMUMETHOD(mmu_pinit0, moea_pinit0),
340 MMUMETHOD(mmu_protect, moea_protect),
341 MMUMETHOD(mmu_qenter, moea_qenter),
342 MMUMETHOD(mmu_qremove, moea_qremove),
343 MMUMETHOD(mmu_release, moea_release),
344 MMUMETHOD(mmu_remove, moea_remove),
345 MMUMETHOD(mmu_remove_all, moea_remove_all),
346 MMUMETHOD(mmu_remove_write, moea_remove_write),
347 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
348 MMUMETHOD(mmu_zero_page, moea_zero_page),
349 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
350 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
351 MMUMETHOD(mmu_activate, moea_activate),
352 MMUMETHOD(mmu_deactivate, moea_deactivate),
353 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
355 /* Internal interfaces */
356 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
357 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
358 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
359 MMUMETHOD(mmu_mapdev, moea_mapdev),
360 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
361 MMUMETHOD(mmu_kextract, moea_kextract),
362 MMUMETHOD(mmu_kenter, moea_kenter),
363 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
364 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
365 MMUMETHOD(mmu_scan_md, moea_scan_md),
366 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map),
371 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
373 static __inline uint32_t
374 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
379 if (ma != VM_MEMATTR_DEFAULT) {
381 case VM_MEMATTR_UNCACHEABLE:
382 return (PTE_I | PTE_G);
383 case VM_MEMATTR_WRITE_COMBINING:
384 case VM_MEMATTR_WRITE_BACK:
385 case VM_MEMATTR_PREFETCHABLE:
387 case VM_MEMATTR_WRITE_THROUGH:
388 return (PTE_W | PTE_M);
393 * Assume the page is cache inhibited and access is guarded unless
394 * it's in our available memory array.
396 pte_lo = PTE_I | PTE_G;
397 for (i = 0; i < pregions_sz; i++) {
398 if ((pa >= pregions[i].mr_start) &&
399 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
409 tlbie(vm_offset_t va)
412 mtx_lock_spin(&tlbie_mtx);
413 __asm __volatile("ptesync");
414 __asm __volatile("tlbie %0" :: "r"(va));
415 __asm __volatile("eieio; tlbsync; ptesync");
416 mtx_unlock_spin(&tlbie_mtx);
424 for (va = 0; va < 0x00040000; va += 0x00001000) {
425 __asm __volatile("tlbie %0" :: "r"(va));
428 __asm __volatile("tlbsync");
433 va_to_sr(u_int *sr, vm_offset_t va)
435 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
438 static __inline u_int
439 va_to_pteg(u_int sr, vm_offset_t addr)
443 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
445 return (hash & moea_pteg_mask);
448 static __inline struct pvo_head *
449 vm_page_to_pvoh(vm_page_t m)
452 return (&m->md.mdpg_pvoh);
456 moea_attr_clear(vm_page_t m, int ptebit)
459 rw_assert(&pvh_global_lock, RA_WLOCKED);
460 m->md.mdpg_attrs &= ~ptebit;
464 moea_attr_fetch(vm_page_t m)
467 return (m->md.mdpg_attrs);
471 moea_attr_save(vm_page_t m, int ptebit)
474 rw_assert(&pvh_global_lock, RA_WLOCKED);
475 m->md.mdpg_attrs |= ptebit;
479 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
481 if (pt->pte_hi == pvo_pt->pte_hi)
488 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
490 return (pt->pte_hi & ~PTE_VALID) ==
491 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
492 ((va >> ADDR_API_SHFT) & PTE_API) | which);
496 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
499 mtx_assert(&moea_table_mutex, MA_OWNED);
502 * Construct a PTE. Default to IMB initially. Valid bit only gets
503 * set when the real pte is set in memory.
505 * Note: Don't set the valid bit for correct operation of tlb update.
507 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
508 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
513 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
516 mtx_assert(&moea_table_mutex, MA_OWNED);
517 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
521 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
524 mtx_assert(&moea_table_mutex, MA_OWNED);
527 * As shown in Section 7.6.3.2.3
529 pt->pte_lo &= ~ptebit;
534 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
537 mtx_assert(&moea_table_mutex, MA_OWNED);
538 pvo_pt->pte_hi |= PTE_VALID;
541 * Update the PTE as defined in section 7.6.3.1.
542 * Note that the REF/CHG bits are from pvo_pt and thus should have
543 * been saved so this routine can restore them (if desired).
545 pt->pte_lo = pvo_pt->pte_lo;
547 pt->pte_hi = pvo_pt->pte_hi;
553 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
556 mtx_assert(&moea_table_mutex, MA_OWNED);
557 pvo_pt->pte_hi &= ~PTE_VALID;
560 * Force the reg & chg bits back into the PTEs.
565 * Invalidate the pte.
567 pt->pte_hi &= ~PTE_VALID;
572 * Save the reg & chg bits.
574 moea_pte_synch(pt, pvo_pt);
579 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
585 moea_pte_unset(pt, pvo_pt, va);
586 moea_pte_set(pt, pvo_pt);
590 * Quick sort callout for comparing memory regions.
592 static int om_cmp(const void *a, const void *b);
595 om_cmp(const void *a, const void *b)
597 const struct ofw_map *mapa;
598 const struct ofw_map *mapb;
602 if (mapa->om_pa < mapb->om_pa)
604 else if (mapa->om_pa > mapb->om_pa)
611 moea_cpu_bootstrap(mmu_t mmup, int ap)
618 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
619 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
621 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
622 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
628 * Special case for the Wii: don't install the PCI BAT.
630 if (strcmp(installed_platform(), "wii") != 0) {
632 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
633 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
639 __asm __volatile("mtibatu 1,%0" :: "r"(0));
640 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
641 __asm __volatile("mtibatu 2,%0" :: "r"(0));
642 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
643 __asm __volatile("mtibatu 3,%0" :: "r"(0));
646 for (i = 0; i < 16; i++)
647 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
650 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
651 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
658 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
661 phandle_t chosen, mmu;
664 vm_size_t size, physsz, hwphyssz;
665 vm_offset_t pa, va, off;
670 * Set up BAT0 to map the lowest 256 MB area
672 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
673 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
676 * Map PCI memory space.
678 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
679 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
681 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
682 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
684 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
685 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
687 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
688 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
693 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
694 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
697 * Use an IBAT and a DBAT to map the bottom segment of memory
698 * where we are. Turn off instruction relocation temporarily
699 * to prevent faults while reprogramming the IBAT.
702 mtmsr(msr & ~PSL_IR);
703 __asm (".balign 32; \n"
704 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
705 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
706 :: "r"(battable[0].batu), "r"(battable[0].batl));
710 if (strcmp(installed_platform(), "wii") != 0) {
713 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
714 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
720 /* set global direct map flag */
723 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
724 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
726 for (i = 0; i < pregions_sz; i++) {
730 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
731 pregions[i].mr_start,
732 pregions[i].mr_start + pregions[i].mr_size,
733 pregions[i].mr_size);
735 * Install entries into the BAT table to allow all
736 * of physmem to be convered by on-demand BAT entries.
737 * The loop will sometimes set the same battable element
738 * twice, but that's fine since they won't be used for
741 pa = pregions[i].mr_start & 0xf0000000;
742 end = pregions[i].mr_start + pregions[i].mr_size;
744 u_int n = pa >> ADDR_SR_SHFT;
746 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
747 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
748 pa += SEGMENT_LENGTH;
752 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
753 panic("moea_bootstrap: phys_avail too small");
755 phys_avail_count = 0;
758 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
759 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
760 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
761 regions[i].mr_start + regions[i].mr_size,
764 (physsz + regions[i].mr_size) >= hwphyssz) {
765 if (physsz < hwphyssz) {
766 phys_avail[j] = regions[i].mr_start;
767 phys_avail[j + 1] = regions[i].mr_start +
774 phys_avail[j] = regions[i].mr_start;
775 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
777 physsz += regions[i].mr_size;
780 /* Check for overlap with the kernel and exception vectors */
781 for (j = 0; j < 2*phys_avail_count; j+=2) {
782 if (phys_avail[j] < EXC_LAST)
783 phys_avail[j] += EXC_LAST;
785 if (kernelstart >= phys_avail[j] &&
786 kernelstart < phys_avail[j+1]) {
787 if (kernelend < phys_avail[j+1]) {
788 phys_avail[2*phys_avail_count] =
789 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
790 phys_avail[2*phys_avail_count + 1] =
795 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
798 if (kernelend >= phys_avail[j] &&
799 kernelend < phys_avail[j+1]) {
800 if (kernelstart > phys_avail[j]) {
801 phys_avail[2*phys_avail_count] = phys_avail[j];
802 phys_avail[2*phys_avail_count + 1] =
803 kernelstart & ~PAGE_MASK;
807 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
811 physmem = btoc(physsz);
814 * Allocate PTEG table.
817 moea_pteg_count = PTEGCOUNT;
819 moea_pteg_count = 0x1000;
821 while (moea_pteg_count < physmem)
822 moea_pteg_count <<= 1;
824 moea_pteg_count >>= 1;
825 #endif /* PTEGCOUNT */
827 size = moea_pteg_count * sizeof(struct pteg);
828 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
830 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
831 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
832 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
833 moea_pteg_mask = moea_pteg_count - 1;
836 * Allocate pv/overflow lists.
838 size = sizeof(struct pvo_head) * moea_pteg_count;
839 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
841 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
842 for (i = 0; i < moea_pteg_count; i++)
843 LIST_INIT(&moea_pvo_table[i]);
846 * Initialize the lock that synchronizes access to the pteg and pvo
849 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
851 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
853 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
856 * Initialise the unmanaged pvo pool.
858 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
859 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
860 moea_bpvo_pool_index = 0;
863 * Make sure kernel vsid is allocated as well as VSID 0.
865 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
866 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
867 moea_vsid_bitmap[0] |= 1;
870 * Initialize the kernel pmap (which is statically allocated).
872 PMAP_LOCK_INIT(kernel_pmap);
873 for (i = 0; i < 16; i++)
874 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
875 CPU_FILL(&kernel_pmap->pm_active);
876 RB_INIT(&kernel_pmap->pmap_pvo);
879 * Initialize the global pv list lock.
881 rw_init(&pvh_global_lock, "pmap pv global");
884 * Set up the Open Firmware mappings
886 chosen = OF_finddevice("/chosen");
887 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
888 (mmu = OF_instance_to_package(mmui)) != -1 &&
889 (sz = OF_getproplen(mmu, "translations")) != -1) {
891 for (i = 0; phys_avail[i] != 0; i += 2) {
892 if (phys_avail[i + 1] >= sz) {
893 translations = (struct ofw_map *)phys_avail[i];
897 if (translations == NULL)
898 panic("moea_bootstrap: no space to copy translations");
899 bzero(translations, sz);
900 if (OF_getprop(mmu, "translations", translations, sz) == -1)
901 panic("moea_bootstrap: can't get ofw translations");
902 CTR0(KTR_PMAP, "moea_bootstrap: translations");
903 sz /= sizeof(*translations);
904 qsort(translations, sz, sizeof (*translations), om_cmp);
905 for (i = 0; i < sz; i++) {
906 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
907 translations[i].om_pa, translations[i].om_va,
908 translations[i].om_len);
911 * If the mapping is 1:1, let the RAM and device
912 * on-demand BAT tables take care of the translation.
914 if (translations[i].om_va == translations[i].om_pa)
917 /* Enter the pages */
918 for (off = 0; off < translations[i].om_len;
920 moea_kenter(mmup, translations[i].om_va + off,
921 translations[i].om_pa + off);
926 * Calculate the last available physical address.
928 for (i = 0; phys_avail[i + 2] != 0; i += 2)
930 Maxmem = powerpc_btop(phys_avail[i + 1]);
932 moea_cpu_bootstrap(mmup,0);
937 * Set the start and end of kva.
939 virtual_avail = VM_MIN_KERNEL_ADDRESS;
940 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
943 * Allocate a kernel stack with a guard page for thread0 and map it
944 * into the kernel page map.
946 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
947 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
948 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
949 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
950 thread0.td_kstack = va;
951 thread0.td_kstack_pages = KSTACK_PAGES;
952 for (i = 0; i < KSTACK_PAGES; i++) {
953 moea_kenter(mmup, va, pa);
959 * Allocate virtual address space for the message buffer.
961 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
962 msgbufp = (struct msgbuf *)virtual_avail;
964 virtual_avail += round_page(msgbufsize);
965 while (va < virtual_avail) {
966 moea_kenter(mmup, va, pa);
972 * Allocate virtual address space for the dynamic percpu area.
974 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
975 dpcpu = (void *)virtual_avail;
977 virtual_avail += DPCPU_SIZE;
978 while (va < virtual_avail) {
979 moea_kenter(mmup, va, pa);
983 dpcpu_init(dpcpu, 0);
987 * Activate a user pmap. The pmap must be activated before it's address
988 * space can be accessed in any way.
991 moea_activate(mmu_t mmu, struct thread *td)
996 * Load all the data we need up front to encourage the compiler to
997 * not issue any loads while we have interrupts disabled below.
999 pm = &td->td_proc->p_vmspace->vm_pmap;
1000 pmr = pm->pmap_phys;
1002 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1003 PCPU_SET(curpmap, pmr);
1007 moea_deactivate(mmu_t mmu, struct thread *td)
1011 pm = &td->td_proc->p_vmspace->vm_pmap;
1012 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1013 PCPU_SET(curpmap, NULL);
1017 moea_change_wiring(mmu_t mmu, pmap_t pm, vm_offset_t va, boolean_t wired)
1019 struct pvo_entry *pvo;
1022 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1026 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1027 pm->pm_stats.wired_count++;
1028 pvo->pvo_vaddr |= PVO_WIRED;
1030 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1031 pm->pm_stats.wired_count--;
1032 pvo->pvo_vaddr &= ~PVO_WIRED;
1039 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1044 dst = VM_PAGE_TO_PHYS(mdst);
1045 src = VM_PAGE_TO_PHYS(msrc);
1047 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1051 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1052 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1055 vm_offset_t a_pg_offset, b_pg_offset;
1058 while (xfersize > 0) {
1059 a_pg_offset = a_offset & PAGE_MASK;
1060 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1061 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1063 b_pg_offset = b_offset & PAGE_MASK;
1064 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1065 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1067 bcopy(a_cp, b_cp, cnt);
1075 * Zero a page of physical memory by temporarily mapping it into the tlb.
1078 moea_zero_page(mmu_t mmu, vm_page_t m)
1080 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m);
1082 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1083 __asm __volatile("dcbz 0,%0" :: "r"(pa + off));
1087 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1089 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1090 void *va = (void *)(pa + off);
1096 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1099 moea_zero_page(mmu, m);
1103 * Map the given physical page at the specified virtual address in the
1104 * target pmap with the protection requested. If specified the page
1105 * will be wired down.
1108 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1112 rw_wlock(&pvh_global_lock);
1114 moea_enter_locked(pmap, va, m, prot, wired);
1115 rw_wunlock(&pvh_global_lock);
1120 * Map the given physical page at the specified virtual address in the
1121 * target pmap with the protection requested. If specified the page
1122 * will be wired down.
1124 * The page queues and pmap must be locked.
1127 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1130 struct pvo_head *pvo_head;
1133 u_int pte_lo, pvo_flags;
1136 if (!moea_initialized) {
1137 pvo_head = &moea_pvo_kunmanaged;
1138 zone = moea_upvo_zone;
1142 pvo_head = vm_page_to_pvoh(m);
1144 zone = moea_mpvo_zone;
1145 pvo_flags = PVO_MANAGED;
1147 if (pmap_bootstrapped)
1148 rw_assert(&pvh_global_lock, RA_WLOCKED);
1149 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1150 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1151 VM_OBJECT_ASSERT_LOCKED(m->object);
1153 /* XXX change the pvo head for fake pages */
1154 if ((m->oflags & VPO_UNMANAGED) != 0) {
1155 pvo_flags &= ~PVO_MANAGED;
1156 pvo_head = &moea_pvo_kunmanaged;
1157 zone = moea_upvo_zone;
1160 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1162 if (prot & VM_PROT_WRITE) {
1164 if (pmap_bootstrapped &&
1165 (m->oflags & VPO_UNMANAGED) == 0)
1166 vm_page_aflag_set(m, PGA_WRITEABLE);
1170 if (prot & VM_PROT_EXECUTE)
1171 pvo_flags |= PVO_EXECUTABLE;
1174 pvo_flags |= PVO_WIRED;
1176 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1180 * Flush the real page from the instruction cache. This has be done
1181 * for all user mappings to prevent information leakage via the
1182 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1183 * mapping for a page.
1185 if (pmap != kernel_pmap && error == ENOENT &&
1186 (pte_lo & (PTE_I | PTE_G)) == 0)
1187 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1191 * Maps a sequence of resident pages belonging to the same object.
1192 * The sequence begins with the given page m_start. This page is
1193 * mapped at the given virtual address start. Each subsequent page is
1194 * mapped at a virtual address that is offset from start by the same
1195 * amount as the page is offset from m_start within the object. The
1196 * last page in the sequence is the page with the largest offset from
1197 * m_start that can be mapped at a virtual address less than the given
1198 * virtual address end. Not every virtual page between start and end
1199 * is mapped; only those for which a resident page exists with the
1200 * corresponding offset from m_start are mapped.
1203 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1204 vm_page_t m_start, vm_prot_t prot)
1207 vm_pindex_t diff, psize;
1209 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1211 psize = atop(end - start);
1213 rw_wlock(&pvh_global_lock);
1215 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1216 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1217 (VM_PROT_READ | VM_PROT_EXECUTE), FALSE);
1218 m = TAILQ_NEXT(m, listq);
1220 rw_wunlock(&pvh_global_lock);
1225 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1229 rw_wlock(&pvh_global_lock);
1231 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1233 rw_wunlock(&pvh_global_lock);
1238 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1240 struct pvo_entry *pvo;
1244 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1248 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1254 * Atomically extract and hold the physical page with the given
1255 * pmap and virtual address pair if that mapping permits the given
1259 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1261 struct pvo_entry *pvo;
1269 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1270 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1271 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1272 (prot & VM_PROT_WRITE) == 0)) {
1273 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1275 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1284 moea_init(mmu_t mmu)
1287 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1288 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1289 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1290 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1291 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1292 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1293 moea_initialized = TRUE;
1297 moea_is_referenced(mmu_t mmu, vm_page_t m)
1301 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1302 ("moea_is_referenced: page %p is not managed", m));
1303 rw_wlock(&pvh_global_lock);
1304 rv = moea_query_bit(m, PTE_REF);
1305 rw_wunlock(&pvh_global_lock);
1310 moea_is_modified(mmu_t mmu, vm_page_t m)
1314 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1315 ("moea_is_modified: page %p is not managed", m));
1318 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1319 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1320 * is clear, no PTEs can have PTE_CHG set.
1322 VM_OBJECT_ASSERT_WLOCKED(m->object);
1323 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1325 rw_wlock(&pvh_global_lock);
1326 rv = moea_query_bit(m, PTE_CHG);
1327 rw_wunlock(&pvh_global_lock);
1332 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1334 struct pvo_entry *pvo;
1338 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1339 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1345 moea_clear_modify(mmu_t mmu, vm_page_t m)
1348 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1349 ("moea_clear_modify: page %p is not managed", m));
1350 VM_OBJECT_ASSERT_WLOCKED(m->object);
1351 KASSERT(!vm_page_xbusied(m),
1352 ("moea_clear_modify: page %p is exclusive busy", m));
1355 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1356 * set. If the object containing the page is locked and the page is
1357 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1359 if ((m->aflags & PGA_WRITEABLE) == 0)
1361 rw_wlock(&pvh_global_lock);
1362 moea_clear_bit(m, PTE_CHG);
1363 rw_wunlock(&pvh_global_lock);
1367 * Clear the write and modified bits in each of the given page's mappings.
1370 moea_remove_write(mmu_t mmu, vm_page_t m)
1372 struct pvo_entry *pvo;
1377 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1378 ("moea_remove_write: page %p is not managed", m));
1381 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1382 * set by another thread while the object is locked. Thus,
1383 * if PGA_WRITEABLE is clear, no page table entries need updating.
1385 VM_OBJECT_ASSERT_WLOCKED(m->object);
1386 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1388 rw_wlock(&pvh_global_lock);
1389 lo = moea_attr_fetch(m);
1391 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1392 pmap = pvo->pvo_pmap;
1394 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1395 pt = moea_pvo_to_pte(pvo, -1);
1396 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1397 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1399 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1400 lo |= pvo->pvo_pte.pte.pte_lo;
1401 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1402 moea_pte_change(pt, &pvo->pvo_pte.pte,
1404 mtx_unlock(&moea_table_mutex);
1409 if ((lo & PTE_CHG) != 0) {
1410 moea_attr_clear(m, PTE_CHG);
1413 vm_page_aflag_clear(m, PGA_WRITEABLE);
1414 rw_wunlock(&pvh_global_lock);
1418 * moea_ts_referenced:
1420 * Return a count of reference bits for a page, clearing those bits.
1421 * It is not necessary for every reference bit to be cleared, but it
1422 * is necessary that 0 only be returned when there are truly no
1423 * reference bits set.
1425 * XXX: The exact number of bits to check and clear is a matter that
1426 * should be tested and standardized at some point in the future for
1427 * optimal aging of shared pages.
1430 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1434 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1435 ("moea_ts_referenced: page %p is not managed", m));
1436 rw_wlock(&pvh_global_lock);
1437 count = moea_clear_bit(m, PTE_REF);
1438 rw_wunlock(&pvh_global_lock);
1443 * Modify the WIMG settings of all mappings for a page.
1446 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1448 struct pvo_entry *pvo;
1449 struct pvo_head *pvo_head;
1454 if ((m->oflags & VPO_UNMANAGED) != 0) {
1455 m->md.mdpg_cache_attrs = ma;
1459 rw_wlock(&pvh_global_lock);
1460 pvo_head = vm_page_to_pvoh(m);
1461 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1463 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1464 pmap = pvo->pvo_pmap;
1466 pt = moea_pvo_to_pte(pvo, -1);
1467 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1468 pvo->pvo_pte.pte.pte_lo |= lo;
1470 moea_pte_change(pt, &pvo->pvo_pte.pte,
1472 if (pvo->pvo_pmap == kernel_pmap)
1475 mtx_unlock(&moea_table_mutex);
1478 m->md.mdpg_cache_attrs = ma;
1479 rw_wunlock(&pvh_global_lock);
1483 * Map a wired page into kernel virtual address space.
1486 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1489 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1493 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1499 if (va < VM_MIN_KERNEL_ADDRESS)
1500 panic("moea_kenter: attempt to enter non-kernel address %#x",
1504 pte_lo = moea_calc_wimg(pa, ma);
1506 PMAP_LOCK(kernel_pmap);
1507 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1508 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1510 if (error != 0 && error != ENOENT)
1511 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1514 PMAP_UNLOCK(kernel_pmap);
1518 * Extract the physical page address associated with the given kernel virtual
1522 moea_kextract(mmu_t mmu, vm_offset_t va)
1524 struct pvo_entry *pvo;
1528 * Allow direct mappings on 32-bit OEA
1530 if (va < VM_MIN_KERNEL_ADDRESS) {
1534 PMAP_LOCK(kernel_pmap);
1535 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1536 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1537 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1538 PMAP_UNLOCK(kernel_pmap);
1543 * Remove a wired page from kernel virtual address space.
1546 moea_kremove(mmu_t mmu, vm_offset_t va)
1549 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1553 * Map a range of physical addresses into kernel virtual address space.
1555 * The value passed in *virt is a suggested virtual address for the mapping.
1556 * Architectures which can support a direct-mapped physical to virtual region
1557 * can return the appropriate address within that region, leaving '*virt'
1558 * unchanged. We cannot and therefore do not; *virt is updated with the
1559 * first usable address after the mapped region.
1562 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1563 vm_paddr_t pa_end, int prot)
1565 vm_offset_t sva, va;
1569 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1570 moea_kenter(mmu, va, pa_start);
1576 * Returns true if the pmap's pv is one of the first
1577 * 16 pvs linked to from this page. This count may
1578 * be changed upwards or downwards in the future; it
1579 * is only necessary that true be returned for a small
1580 * subset of pmaps for proper page aging.
1583 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1586 struct pvo_entry *pvo;
1589 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1590 ("moea_page_exists_quick: page %p is not managed", m));
1593 rw_wlock(&pvh_global_lock);
1594 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1595 if (pvo->pvo_pmap == pmap) {
1602 rw_wunlock(&pvh_global_lock);
1607 * Return the number of managed mappings to the given physical page
1611 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1613 struct pvo_entry *pvo;
1617 if ((m->oflags & VPO_UNMANAGED) != 0)
1619 rw_wlock(&pvh_global_lock);
1620 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1621 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1623 rw_wunlock(&pvh_global_lock);
1627 static u_int moea_vsidcontext;
1630 moea_pinit(mmu_t mmu, pmap_t pmap)
1635 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1636 RB_INIT(&pmap->pmap_pvo);
1639 __asm __volatile("mftb %0" : "=r"(entropy));
1641 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1643 pmap->pmap_phys = pmap;
1647 mtx_lock(&moea_vsid_mutex);
1649 * Allocate some segment registers for this pmap.
1651 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1655 * Create a new value by mutiplying by a prime and adding in
1656 * entropy from the timebase register. This is to make the
1657 * VSID more random so that the PT hash function collides
1658 * less often. (Note that the prime casues gcc to do shifts
1659 * instead of a multiply.)
1661 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1662 hash = moea_vsidcontext & (NPMAPS - 1);
1663 if (hash == 0) /* 0 is special, avoid it */
1666 mask = 1 << (hash & (VSID_NBPW - 1));
1667 hash = (moea_vsidcontext & 0xfffff);
1668 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1669 /* anything free in this bucket? */
1670 if (moea_vsid_bitmap[n] == 0xffffffff) {
1671 entropy = (moea_vsidcontext >> 20);
1674 i = ffs(~moea_vsid_bitmap[n]) - 1;
1676 hash &= 0xfffff & ~(VSID_NBPW - 1);
1679 KASSERT(!(moea_vsid_bitmap[n] & mask),
1680 ("Allocating in-use VSID group %#x\n", hash));
1681 moea_vsid_bitmap[n] |= mask;
1682 for (i = 0; i < 16; i++)
1683 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1684 mtx_unlock(&moea_vsid_mutex);
1688 mtx_unlock(&moea_vsid_mutex);
1689 panic("moea_pinit: out of segments");
1693 * Initialize the pmap associated with process 0.
1696 moea_pinit0(mmu_t mmu, pmap_t pm)
1700 moea_pinit(mmu, pm);
1701 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1705 * Set the physical protection on the specified range of this map as requested.
1708 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1711 struct pvo_entry *pvo, *tpvo, key;
1714 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1715 ("moea_protect: non current pmap"));
1717 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1718 moea_remove(mmu, pm, sva, eva);
1722 rw_wlock(&pvh_global_lock);
1724 key.pvo_vaddr = sva;
1725 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1726 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1727 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1728 if ((prot & VM_PROT_EXECUTE) == 0)
1729 pvo->pvo_vaddr &= ~PVO_EXECUTABLE;
1732 * Grab the PTE pointer before we diddle with the cached PTE
1735 pt = moea_pvo_to_pte(pvo, -1);
1737 * Change the protection of the page.
1739 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1740 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1743 * If the PVO is in the page table, update that pte as well.
1746 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1747 mtx_unlock(&moea_table_mutex);
1750 rw_wunlock(&pvh_global_lock);
1755 * Map a list of wired pages into kernel virtual address space. This is
1756 * intended for temporary mappings which do not need page modification or
1757 * references recorded. Existing mappings in the region are overwritten.
1760 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1765 while (count-- > 0) {
1766 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1773 * Remove page mappings from kernel virtual address space. Intended for
1774 * temporary mappings entered by moea_qenter.
1777 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1782 while (count-- > 0) {
1783 moea_kremove(mmu, va);
1789 moea_release(mmu_t mmu, pmap_t pmap)
1794 * Free segment register's VSID
1796 if (pmap->pm_sr[0] == 0)
1797 panic("moea_release");
1799 mtx_lock(&moea_vsid_mutex);
1800 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1801 mask = 1 << (idx % VSID_NBPW);
1803 moea_vsid_bitmap[idx] &= ~mask;
1804 mtx_unlock(&moea_vsid_mutex);
1808 * Remove the given range of addresses from the specified map.
1811 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1813 struct pvo_entry *pvo, *tpvo, key;
1815 rw_wlock(&pvh_global_lock);
1817 key.pvo_vaddr = sva;
1818 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1819 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1820 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1821 moea_pvo_remove(pvo, -1);
1824 rw_wunlock(&pvh_global_lock);
1828 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1829 * will reflect changes in pte's back to the vm_page.
1832 moea_remove_all(mmu_t mmu, vm_page_t m)
1834 struct pvo_head *pvo_head;
1835 struct pvo_entry *pvo, *next_pvo;
1838 rw_wlock(&pvh_global_lock);
1839 pvo_head = vm_page_to_pvoh(m);
1840 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1841 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1843 pmap = pvo->pvo_pmap;
1845 moea_pvo_remove(pvo, -1);
1848 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1849 moea_attr_clear(m, PTE_CHG);
1852 vm_page_aflag_clear(m, PGA_WRITEABLE);
1853 rw_wunlock(&pvh_global_lock);
1857 * Allocate a physical page of memory directly from the phys_avail map.
1858 * Can only be called from moea_bootstrap before avail start and end are
1862 moea_bootstrap_alloc(vm_size_t size, u_int align)
1867 size = round_page(size);
1868 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1870 s = (phys_avail[i] + align - 1) & ~(align - 1);
1875 if (s < phys_avail[i] || e > phys_avail[i + 1])
1878 if (s == phys_avail[i]) {
1879 phys_avail[i] += size;
1880 } else if (e == phys_avail[i + 1]) {
1881 phys_avail[i + 1] -= size;
1883 for (j = phys_avail_count * 2; j > i; j -= 2) {
1884 phys_avail[j] = phys_avail[j - 2];
1885 phys_avail[j + 1] = phys_avail[j - 1];
1888 phys_avail[i + 3] = phys_avail[i + 1];
1889 phys_avail[i + 1] = s;
1890 phys_avail[i + 2] = e;
1896 panic("moea_bootstrap_alloc: could not allocate memory");
1900 moea_syncicache(vm_offset_t pa, vm_size_t len)
1902 __syncicache((void *)pa, len);
1906 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1907 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1909 struct pvo_entry *pvo;
1916 moea_pvo_enter_calls++;
1921 * Compute the PTE Group index.
1924 sr = va_to_sr(pm->pm_sr, va);
1925 ptegidx = va_to_pteg(sr, va);
1928 * Remove any existing mapping for this page. Reuse the pvo entry if
1929 * there is a mapping.
1931 mtx_lock(&moea_table_mutex);
1932 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1933 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1934 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1935 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1936 (pte_lo & PTE_PP)) {
1937 mtx_unlock(&moea_table_mutex);
1940 moea_pvo_remove(pvo, -1);
1946 * If we aren't overwriting a mapping, try to allocate.
1948 if (moea_initialized) {
1949 pvo = uma_zalloc(zone, M_NOWAIT);
1951 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1952 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1953 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1954 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1956 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1957 moea_bpvo_pool_index++;
1962 mtx_unlock(&moea_table_mutex);
1967 pvo->pvo_vaddr = va;
1969 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1970 pvo->pvo_vaddr &= ~ADDR_POFF;
1971 if (flags & VM_PROT_EXECUTE)
1972 pvo->pvo_vaddr |= PVO_EXECUTABLE;
1973 if (flags & PVO_WIRED)
1974 pvo->pvo_vaddr |= PVO_WIRED;
1975 if (pvo_head != &moea_pvo_kunmanaged)
1976 pvo->pvo_vaddr |= PVO_MANAGED;
1978 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1980 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
1985 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
1988 * Remember if the list was empty and therefore will be the first
1991 if (LIST_FIRST(pvo_head) == NULL)
1993 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
1995 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
1996 pm->pm_stats.wired_count++;
1997 pm->pm_stats.resident_count++;
1999 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2000 KASSERT(i < 8, ("Invalid PTE index"));
2002 PVO_PTEGIDX_SET(pvo, i);
2004 panic("moea_pvo_enter: overflow");
2005 moea_pte_overflow++;
2007 mtx_unlock(&moea_table_mutex);
2009 return (first ? ENOENT : 0);
2013 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2018 * If there is an active pte entry, we need to deactivate it (and
2019 * save the ref & cfg bits).
2021 pt = moea_pvo_to_pte(pvo, pteidx);
2023 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2024 mtx_unlock(&moea_table_mutex);
2025 PVO_PTEGIDX_CLR(pvo);
2027 moea_pte_overflow--;
2031 * Update our statistics.
2033 pvo->pvo_pmap->pm_stats.resident_count--;
2034 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2035 pvo->pvo_pmap->pm_stats.wired_count--;
2038 * Save the REF/CHG bits into their cache if the page is managed.
2040 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2043 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2045 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2046 (PTE_REF | PTE_CHG));
2051 * Remove this PVO from the PV and pmap lists.
2053 LIST_REMOVE(pvo, pvo_vlink);
2054 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2057 * Remove this from the overflow list and return it to the pool
2058 * if we aren't going to reuse it.
2060 LIST_REMOVE(pvo, pvo_olink);
2061 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2062 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2063 moea_upvo_zone, pvo);
2065 moea_pvo_remove_calls++;
2069 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2074 * We can find the actual pte entry without searching by grabbing
2075 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2076 * noticing the HID bit.
2078 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2079 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2080 pteidx ^= moea_pteg_mask * 8;
2085 static struct pvo_entry *
2086 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2088 struct pvo_entry *pvo;
2093 sr = va_to_sr(pm->pm_sr, va);
2094 ptegidx = va_to_pteg(sr, va);
2096 mtx_lock(&moea_table_mutex);
2097 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2098 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2100 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2104 mtx_unlock(&moea_table_mutex);
2110 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2115 * If we haven't been supplied the ptegidx, calculate it.
2121 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2122 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2123 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2126 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2127 mtx_lock(&moea_table_mutex);
2129 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2130 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2131 "valid pte index", pvo);
2134 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2135 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2136 "pvo but no valid pte", pvo);
2139 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2140 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2141 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2142 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2145 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2147 panic("moea_pvo_to_pte: pvo %p pte does not match "
2148 "pte %p in moea_pteg_table", pvo, pt);
2151 mtx_assert(&moea_table_mutex, MA_OWNED);
2155 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2156 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2157 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2160 mtx_unlock(&moea_table_mutex);
2165 * XXX: THIS STUFF SHOULD BE IN pte.c?
2168 moea_pte_spill(vm_offset_t addr)
2170 struct pvo_entry *source_pvo, *victim_pvo;
2171 struct pvo_entry *pvo;
2180 ptegidx = va_to_pteg(sr, addr);
2183 * Have to substitute some entry. Use the primary hash for this.
2184 * Use low bits of timebase as random generator.
2186 pteg = &moea_pteg_table[ptegidx];
2187 mtx_lock(&moea_table_mutex);
2188 __asm __volatile("mftb %0" : "=r"(i));
2194 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2196 * We need to find a pvo entry for this address.
2198 if (source_pvo == NULL &&
2199 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2200 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2202 * Now found an entry to be spilled into the pteg.
2203 * The PTE is now valid, so we know it's active.
2205 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2208 PVO_PTEGIDX_SET(pvo, j);
2209 moea_pte_overflow--;
2210 mtx_unlock(&moea_table_mutex);
2216 if (victim_pvo != NULL)
2221 * We also need the pvo entry of the victim we are replacing
2222 * so save the R & C bits of the PTE.
2224 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2225 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2227 if (source_pvo != NULL)
2232 if (source_pvo == NULL) {
2233 mtx_unlock(&moea_table_mutex);
2237 if (victim_pvo == NULL) {
2238 if ((pt->pte_hi & PTE_HID) == 0)
2239 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2243 * If this is a secondary PTE, we need to search it's primary
2244 * pvo bucket for the matching PVO.
2246 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2249 * We also need the pvo entry of the victim we are
2250 * replacing so save the R & C bits of the PTE.
2252 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2258 if (victim_pvo == NULL)
2259 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2264 * We are invalidating the TLB entry for the EA we are replacing even
2265 * though it's valid. If we don't, we lose any ref/chg bit changes
2266 * contained in the TLB entry.
2268 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2270 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2271 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2273 PVO_PTEGIDX_CLR(victim_pvo);
2274 PVO_PTEGIDX_SET(source_pvo, i);
2275 moea_pte_replacements++;
2277 mtx_unlock(&moea_table_mutex);
2281 static __inline struct pvo_entry *
2282 moea_pte_spillable_ident(u_int ptegidx)
2285 struct pvo_entry *pvo_walk, *pvo = NULL;
2287 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) {
2288 if (pvo_walk->pvo_vaddr & PVO_WIRED)
2291 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID))
2294 pt = moea_pvo_to_pte(pvo_walk, -1);
2301 mtx_unlock(&moea_table_mutex);
2302 if (!(pt->pte_lo & PTE_REF))
2310 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2313 struct pvo_entry *victim_pvo;
2316 u_int pteg_bkpidx = ptegidx;
2318 mtx_assert(&moea_table_mutex, MA_OWNED);
2321 * First try primary hash.
2323 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2324 if ((pt->pte_hi & PTE_VALID) == 0) {
2325 pvo_pt->pte_hi &= ~PTE_HID;
2326 moea_pte_set(pt, pvo_pt);
2332 * Now try secondary hash.
2334 ptegidx ^= moea_pteg_mask;
2336 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2337 if ((pt->pte_hi & PTE_VALID) == 0) {
2338 pvo_pt->pte_hi |= PTE_HID;
2339 moea_pte_set(pt, pvo_pt);
2344 /* Try again, but this time try to force a PTE out. */
2345 ptegidx = pteg_bkpidx;
2347 victim_pvo = moea_pte_spillable_ident(ptegidx);
2348 if (victim_pvo == NULL) {
2349 ptegidx ^= moea_pteg_mask;
2350 victim_pvo = moea_pte_spillable_ident(ptegidx);
2353 if (victim_pvo == NULL) {
2354 panic("moea_pte_insert: overflow");
2358 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx);
2360 if (pteg_bkpidx == ptegidx)
2361 pvo_pt->pte_hi &= ~PTE_HID;
2363 pvo_pt->pte_hi |= PTE_HID;
2366 * Synchronize the sacrifice PTE with its PVO, then mark both
2367 * invalid. The PVO will be reused when/if the VM system comes
2368 * here after a fault.
2370 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7];
2372 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi)
2373 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2378 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2379 PVO_PTEGIDX_CLR(victim_pvo);
2380 moea_pte_overflow++;
2381 moea_pte_set(pt, pvo_pt);
2383 return (victim_idx & 7);
2387 moea_query_bit(vm_page_t m, int ptebit)
2389 struct pvo_entry *pvo;
2392 rw_assert(&pvh_global_lock, RA_WLOCKED);
2393 if (moea_attr_fetch(m) & ptebit)
2396 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2399 * See if we saved the bit off. If so, cache it and return
2402 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2403 moea_attr_save(m, ptebit);
2409 * No luck, now go through the hard part of looking at the PTEs
2410 * themselves. Sync so that any pending REF/CHG bits are flushed to
2414 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2417 * See if this pvo has a valid PTE. if so, fetch the
2418 * REF/CHG bits from the valid PTE. If the appropriate
2419 * ptebit is set, cache it and return success.
2421 pt = moea_pvo_to_pte(pvo, -1);
2423 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2424 mtx_unlock(&moea_table_mutex);
2425 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2426 moea_attr_save(m, ptebit);
2436 moea_clear_bit(vm_page_t m, int ptebit)
2439 struct pvo_entry *pvo;
2442 rw_assert(&pvh_global_lock, RA_WLOCKED);
2445 * Clear the cached value.
2447 moea_attr_clear(m, ptebit);
2450 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2451 * we can reset the right ones). note that since the pvo entries and
2452 * list heads are accessed via BAT0 and are never placed in the page
2453 * table, we don't have to worry about further accesses setting the
2459 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2460 * valid pte clear the ptebit from the valid pte.
2463 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2464 pt = moea_pvo_to_pte(pvo, -1);
2466 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2467 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2469 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2471 mtx_unlock(&moea_table_mutex);
2473 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2480 * Return true if the physical range is encompassed by the battable[idx]
2483 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2491 * Return immediately if not a valid mapping
2493 if (!(battable[idx].batu & BAT_Vs))
2497 * The BAT entry must be cache-inhibited, guarded, and r/w
2498 * so it can function as an i/o page
2500 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2501 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2505 * The address should be within the BAT range. Assume that the
2506 * start address in the BAT has the correct alignment (thus
2507 * not requiring masking)
2509 start = battable[idx].batl & BAT_PBS;
2510 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2511 end = start | (bat_ble << 15) | 0x7fff;
2513 if ((pa < start) || ((pa + size) > end))
2520 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2525 * This currently does not work for entries that
2526 * overlap 256M BAT segments.
2529 for(i = 0; i < 16; i++)
2530 if (moea_bat_mapped(i, pa, size) == 0)
2537 * Map a set of physical memory pages into the kernel virtual
2538 * address space. Return a pointer to where it is mapped. This
2539 * routine is intended to be used for mapping device memory,
2543 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2546 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2550 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2552 vm_offset_t va, tmpva, ppa, offset;
2555 ppa = trunc_page(pa);
2556 offset = pa & PAGE_MASK;
2557 size = roundup(offset + size, PAGE_SIZE);
2560 * If the physical address lies within a valid BAT table entry,
2561 * return the 1:1 mapping. This currently doesn't work
2562 * for regions that overlap 256M BAT segments.
2564 for (i = 0; i < 16; i++) {
2565 if (moea_bat_mapped(i, pa, size) == 0)
2566 return ((void *) pa);
2569 va = kva_alloc(size);
2571 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2573 for (tmpva = va; size > 0;) {
2574 moea_kenter_attr(mmu, tmpva, ppa, ma);
2581 return ((void *)(va + offset));
2585 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2587 vm_offset_t base, offset;
2590 * If this is outside kernel virtual space, then it's a
2591 * battable entry and doesn't require unmapping
2593 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2594 base = trunc_page(va);
2595 offset = va & PAGE_MASK;
2596 size = roundup(offset + size, PAGE_SIZE);
2597 kva_free(base, size);
2602 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2604 struct pvo_entry *pvo;
2611 lim = round_page(va);
2612 len = MIN(lim - va, sz);
2613 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2615 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2617 moea_syncicache(pa, len);
2626 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2629 if (md->md_vaddr == ~0UL)
2630 return (md->md_paddr + ofs);
2632 return (md->md_vaddr + ofs);
2636 moea_scan_md(mmu_t mmu, struct pmap_md *prev)
2638 static struct pmap_md md;
2639 struct pvo_entry *pvo;
2642 if (dumpsys_minidump) {
2643 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2645 /* 1st: kernel .data and .bss. */
2647 md.md_vaddr = trunc_page((uintptr_t)_etext);
2648 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2651 switch (prev->md_index) {
2653 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2655 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2656 md.md_size = round_page(msgbufp->msg_size);
2659 /* 3rd: kernel VM. */
2660 va = prev->md_vaddr + prev->md_size;
2661 /* Find start of next chunk (from va). */
2662 while (va < virtual_end) {
2663 /* Don't dump the buffer cache. */
2664 if (va >= kmi.buffer_sva &&
2665 va < kmi.buffer_eva) {
2666 va = kmi.buffer_eva;
2669 pvo = moea_pvo_find_va(kernel_pmap,
2670 va & ~ADDR_POFF, NULL);
2672 (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2676 if (va < virtual_end) {
2679 /* Find last page in chunk. */
2680 while (va < virtual_end) {
2681 /* Don't run into the buffer cache. */
2682 if (va == kmi.buffer_sva)
2684 pvo = moea_pvo_find_va(kernel_pmap,
2685 va & ~ADDR_POFF, NULL);
2687 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2691 md.md_size = va - md.md_vaddr;
2699 } else { /* minidumps */
2700 mem_regions(&pregions, &pregions_sz,
2701 ®ions, ®ions_sz);
2704 /* first physical chunk. */
2705 md.md_paddr = pregions[0].mr_start;
2706 md.md_size = pregions[0].mr_size;
2709 } else if (md.md_index < pregions_sz) {
2710 md.md_paddr = pregions[md.md_index].mr_start;
2711 md.md_size = pregions[md.md_index].mr_size;
2715 /* There's no next physical chunk. */