2 * Copyright (c) 2001 The NetBSD Foundation, Inc.
5 * This code is derived from software contributed to The NetBSD Foundation
6 * by Matt Thomas <matt@3am-software.com> of Allegro Networks, Inc.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
18 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
19 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
20 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
21 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
22 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
23 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
24 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
25 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
26 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
27 * POSSIBILITY OF SUCH DAMAGE.
30 * Copyright (C) 1995, 1996 Wolfgang Solfrank.
31 * Copyright (C) 1995, 1996 TooLs GmbH.
32 * All rights reserved.
34 * Redistribution and use in source and binary forms, with or without
35 * modification, are permitted provided that the following conditions
37 * 1. Redistributions of source code must retain the above copyright
38 * notice, this list of conditions and the following disclaimer.
39 * 2. Redistributions in binary form must reproduce the above copyright
40 * notice, this list of conditions and the following disclaimer in the
41 * documentation and/or other materials provided with the distribution.
42 * 3. All advertising materials mentioning features or use of this software
43 * must display the following acknowledgement:
44 * This product includes software developed by TooLs GmbH.
45 * 4. The name of TooLs GmbH may not be used to endorse or promote products
46 * derived from this software without specific prior written permission.
48 * THIS SOFTWARE IS PROVIDED BY TOOLS GMBH ``AS IS'' AND ANY EXPRESS OR
49 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
50 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
51 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
52 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
53 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
54 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
55 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
56 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
57 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
59 * $NetBSD: pmap.c,v 1.28 2000/03/26 20:42:36 kleink Exp $
62 * Copyright (C) 2001 Benno Rice.
63 * All rights reserved.
65 * Redistribution and use in source and binary forms, with or without
66 * modification, are permitted provided that the following conditions
68 * 1. Redistributions of source code must retain the above copyright
69 * notice, this list of conditions and the following disclaimer.
70 * 2. Redistributions in binary form must reproduce the above copyright
71 * notice, this list of conditions and the following disclaimer in the
72 * documentation and/or other materials provided with the distribution.
74 * THIS SOFTWARE IS PROVIDED BY Benno Rice ``AS IS'' AND ANY EXPRESS OR
75 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
76 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
77 * IN NO EVENT SHALL TOOLS GMBH BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
78 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
79 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
80 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
81 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
82 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
83 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
86 #include <sys/cdefs.h>
87 __FBSDID("$FreeBSD$");
90 * Manages physical address maps.
92 * Since the information managed by this module is also stored by the
93 * logical address mapping module, this module may throw away valid virtual
94 * to physical mappings at almost any time. However, invalidations of
95 * mappings must be done as requested.
97 * In order to cope with hardware architectures which make virtual to
98 * physical map invalidates expensive, this module may delay invalidate
99 * reduced protection operations until such time as they are actually
100 * necessary. This module is given full information as to which processors
101 * are currently using which maps, and to when physical maps must be made
105 #include "opt_kstack_pages.h"
107 #include <sys/param.h>
108 #include <sys/kernel.h>
109 #include <sys/queue.h>
110 #include <sys/cpuset.h>
112 #include <sys/lock.h>
113 #include <sys/msgbuf.h>
114 #include <sys/mutex.h>
115 #include <sys/proc.h>
116 #include <sys/rwlock.h>
117 #include <sys/sched.h>
118 #include <sys/sysctl.h>
119 #include <sys/systm.h>
120 #include <sys/vmmeter.h>
122 #include <dev/ofw/openfirm.h>
125 #include <vm/vm_param.h>
126 #include <vm/vm_kern.h>
127 #include <vm/vm_page.h>
128 #include <vm/vm_map.h>
129 #include <vm/vm_object.h>
130 #include <vm/vm_extern.h>
131 #include <vm/vm_pageout.h>
134 #include <machine/cpu.h>
135 #include <machine/platform.h>
136 #include <machine/bat.h>
137 #include <machine/frame.h>
138 #include <machine/md_var.h>
139 #include <machine/psl.h>
140 #include <machine/pte.h>
141 #include <machine/smp.h>
142 #include <machine/sr.h>
143 #include <machine/mmuvar.h>
144 #include <machine/trap.h>
150 #define TODO panic("%s: not implemented", __func__);
152 #define VSID_MAKE(sr, hash) ((sr) | (((hash) & 0xfffff) << 4))
153 #define VSID_TO_SR(vsid) ((vsid) & 0xf)
154 #define VSID_TO_HASH(vsid) (((vsid) >> 4) & 0xfffff)
163 extern unsigned char _etext[];
164 extern unsigned char _end[];
166 extern int dumpsys_minidump;
169 * Map of physical memory regions.
171 static struct mem_region *regions;
172 static struct mem_region *pregions;
173 static u_int phys_avail_count;
174 static int regions_sz, pregions_sz;
175 static struct ofw_map *translations;
178 * Lock for the pteg and pvo tables.
180 struct mtx moea_table_mutex;
181 struct mtx moea_vsid_mutex;
183 /* tlbie instruction synchronization */
184 static struct mtx tlbie_mtx;
189 static struct pteg *moea_pteg_table;
190 u_int moea_pteg_count;
191 u_int moea_pteg_mask;
196 struct pvo_head *moea_pvo_table; /* pvo entries by pteg index */
197 struct pvo_head moea_pvo_kunmanaged =
198 LIST_HEAD_INITIALIZER(moea_pvo_kunmanaged); /* list of unmanaged pages */
200 static struct rwlock_padalign pvh_global_lock;
202 uma_zone_t moea_upvo_zone; /* zone for pvo entries for unmanaged pages */
203 uma_zone_t moea_mpvo_zone; /* zone for pvo entries for managed pages */
205 #define BPVO_POOL_SIZE 32768
206 static struct pvo_entry *moea_bpvo_pool;
207 static int moea_bpvo_pool_index = 0;
209 #define VSID_NBPW (sizeof(u_int32_t) * 8)
210 static u_int moea_vsid_bitmap[NPMAPS / VSID_NBPW];
212 static boolean_t moea_initialized = FALSE;
217 u_int moea_pte_valid = 0;
218 u_int moea_pte_overflow = 0;
219 u_int moea_pte_replacements = 0;
220 u_int moea_pvo_entries = 0;
221 u_int moea_pvo_enter_calls = 0;
222 u_int moea_pvo_remove_calls = 0;
223 u_int moea_pte_spills = 0;
224 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_valid, CTLFLAG_RD, &moea_pte_valid,
226 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_overflow, CTLFLAG_RD,
227 &moea_pte_overflow, 0, "");
228 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_replacements, CTLFLAG_RD,
229 &moea_pte_replacements, 0, "");
230 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_entries, CTLFLAG_RD, &moea_pvo_entries,
232 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_enter_calls, CTLFLAG_RD,
233 &moea_pvo_enter_calls, 0, "");
234 SYSCTL_INT(_machdep, OID_AUTO, moea_pvo_remove_calls, CTLFLAG_RD,
235 &moea_pvo_remove_calls, 0, "");
236 SYSCTL_INT(_machdep, OID_AUTO, moea_pte_spills, CTLFLAG_RD,
237 &moea_pte_spills, 0, "");
240 * Allocate physical memory for use in moea_bootstrap.
242 static vm_offset_t moea_bootstrap_alloc(vm_size_t, u_int);
247 static int moea_pte_insert(u_int, struct pte *);
252 static int moea_pvo_enter(pmap_t, uma_zone_t, struct pvo_head *,
253 vm_offset_t, vm_offset_t, u_int, int);
254 static void moea_pvo_remove(struct pvo_entry *, int);
255 static struct pvo_entry *moea_pvo_find_va(pmap_t, vm_offset_t, int *);
256 static struct pte *moea_pvo_to_pte(const struct pvo_entry *, int);
261 static int moea_enter_locked(pmap_t, vm_offset_t, vm_page_t,
262 vm_prot_t, u_int, int8_t);
263 static void moea_syncicache(vm_offset_t, vm_size_t);
264 static boolean_t moea_query_bit(vm_page_t, int);
265 static u_int moea_clear_bit(vm_page_t, int);
266 static void moea_kremove(mmu_t, vm_offset_t);
267 int moea_pte_spill(vm_offset_t);
270 * Kernel MMU interface
272 void moea_clear_modify(mmu_t, vm_page_t);
273 void moea_copy_page(mmu_t, vm_page_t, vm_page_t);
274 void moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
275 vm_page_t *mb, vm_offset_t b_offset, int xfersize);
276 int moea_enter(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t, u_int,
278 void moea_enter_object(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_page_t,
280 void moea_enter_quick(mmu_t, pmap_t, vm_offset_t, vm_page_t, vm_prot_t);
281 vm_paddr_t moea_extract(mmu_t, pmap_t, vm_offset_t);
282 vm_page_t moea_extract_and_hold(mmu_t, pmap_t, vm_offset_t, vm_prot_t);
283 void moea_init(mmu_t);
284 boolean_t moea_is_modified(mmu_t, vm_page_t);
285 boolean_t moea_is_prefaultable(mmu_t, pmap_t, vm_offset_t);
286 boolean_t moea_is_referenced(mmu_t, vm_page_t);
287 int moea_ts_referenced(mmu_t, vm_page_t);
288 vm_offset_t moea_map(mmu_t, vm_offset_t *, vm_paddr_t, vm_paddr_t, int);
289 boolean_t moea_page_exists_quick(mmu_t, pmap_t, vm_page_t);
290 int moea_page_wired_mappings(mmu_t, vm_page_t);
291 void moea_pinit(mmu_t, pmap_t);
292 void moea_pinit0(mmu_t, pmap_t);
293 void moea_protect(mmu_t, pmap_t, vm_offset_t, vm_offset_t, vm_prot_t);
294 void moea_qenter(mmu_t, vm_offset_t, vm_page_t *, int);
295 void moea_qremove(mmu_t, vm_offset_t, int);
296 void moea_release(mmu_t, pmap_t);
297 void moea_remove(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
298 void moea_remove_all(mmu_t, vm_page_t);
299 void moea_remove_write(mmu_t, vm_page_t);
300 void moea_unwire(mmu_t, pmap_t, vm_offset_t, vm_offset_t);
301 void moea_zero_page(mmu_t, vm_page_t);
302 void moea_zero_page_area(mmu_t, vm_page_t, int, int);
303 void moea_zero_page_idle(mmu_t, vm_page_t);
304 void moea_activate(mmu_t, struct thread *);
305 void moea_deactivate(mmu_t, struct thread *);
306 void moea_cpu_bootstrap(mmu_t, int);
307 void moea_bootstrap(mmu_t, vm_offset_t, vm_offset_t);
308 void *moea_mapdev(mmu_t, vm_paddr_t, vm_size_t);
309 void *moea_mapdev_attr(mmu_t, vm_offset_t, vm_size_t, vm_memattr_t);
310 void moea_unmapdev(mmu_t, vm_offset_t, vm_size_t);
311 vm_paddr_t moea_kextract(mmu_t, vm_offset_t);
312 void moea_kenter_attr(mmu_t, vm_offset_t, vm_offset_t, vm_memattr_t);
313 void moea_kenter(mmu_t, vm_offset_t, vm_paddr_t);
314 void moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma);
315 boolean_t moea_dev_direct_mapped(mmu_t, vm_paddr_t, vm_size_t);
316 static void moea_sync_icache(mmu_t, pmap_t, vm_offset_t, vm_size_t);
317 vm_offset_t moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
319 struct pmap_md * moea_scan_md(mmu_t mmu, struct pmap_md *prev);
321 static mmu_method_t moea_methods[] = {
322 MMUMETHOD(mmu_clear_modify, moea_clear_modify),
323 MMUMETHOD(mmu_copy_page, moea_copy_page),
324 MMUMETHOD(mmu_copy_pages, moea_copy_pages),
325 MMUMETHOD(mmu_enter, moea_enter),
326 MMUMETHOD(mmu_enter_object, moea_enter_object),
327 MMUMETHOD(mmu_enter_quick, moea_enter_quick),
328 MMUMETHOD(mmu_extract, moea_extract),
329 MMUMETHOD(mmu_extract_and_hold, moea_extract_and_hold),
330 MMUMETHOD(mmu_init, moea_init),
331 MMUMETHOD(mmu_is_modified, moea_is_modified),
332 MMUMETHOD(mmu_is_prefaultable, moea_is_prefaultable),
333 MMUMETHOD(mmu_is_referenced, moea_is_referenced),
334 MMUMETHOD(mmu_ts_referenced, moea_ts_referenced),
335 MMUMETHOD(mmu_map, moea_map),
336 MMUMETHOD(mmu_page_exists_quick,moea_page_exists_quick),
337 MMUMETHOD(mmu_page_wired_mappings,moea_page_wired_mappings),
338 MMUMETHOD(mmu_pinit, moea_pinit),
339 MMUMETHOD(mmu_pinit0, moea_pinit0),
340 MMUMETHOD(mmu_protect, moea_protect),
341 MMUMETHOD(mmu_qenter, moea_qenter),
342 MMUMETHOD(mmu_qremove, moea_qremove),
343 MMUMETHOD(mmu_release, moea_release),
344 MMUMETHOD(mmu_remove, moea_remove),
345 MMUMETHOD(mmu_remove_all, moea_remove_all),
346 MMUMETHOD(mmu_remove_write, moea_remove_write),
347 MMUMETHOD(mmu_sync_icache, moea_sync_icache),
348 MMUMETHOD(mmu_unwire, moea_unwire),
349 MMUMETHOD(mmu_zero_page, moea_zero_page),
350 MMUMETHOD(mmu_zero_page_area, moea_zero_page_area),
351 MMUMETHOD(mmu_zero_page_idle, moea_zero_page_idle),
352 MMUMETHOD(mmu_activate, moea_activate),
353 MMUMETHOD(mmu_deactivate, moea_deactivate),
354 MMUMETHOD(mmu_page_set_memattr, moea_page_set_memattr),
356 /* Internal interfaces */
357 MMUMETHOD(mmu_bootstrap, moea_bootstrap),
358 MMUMETHOD(mmu_cpu_bootstrap, moea_cpu_bootstrap),
359 MMUMETHOD(mmu_mapdev_attr, moea_mapdev_attr),
360 MMUMETHOD(mmu_mapdev, moea_mapdev),
361 MMUMETHOD(mmu_unmapdev, moea_unmapdev),
362 MMUMETHOD(mmu_kextract, moea_kextract),
363 MMUMETHOD(mmu_kenter, moea_kenter),
364 MMUMETHOD(mmu_kenter_attr, moea_kenter_attr),
365 MMUMETHOD(mmu_dev_direct_mapped,moea_dev_direct_mapped),
366 MMUMETHOD(mmu_scan_md, moea_scan_md),
367 MMUMETHOD(mmu_dumpsys_map, moea_dumpsys_map),
372 MMU_DEF(oea_mmu, MMU_TYPE_OEA, moea_methods, 0);
374 static __inline uint32_t
375 moea_calc_wimg(vm_offset_t pa, vm_memattr_t ma)
380 if (ma != VM_MEMATTR_DEFAULT) {
382 case VM_MEMATTR_UNCACHEABLE:
383 return (PTE_I | PTE_G);
384 case VM_MEMATTR_WRITE_COMBINING:
385 case VM_MEMATTR_WRITE_BACK:
386 case VM_MEMATTR_PREFETCHABLE:
388 case VM_MEMATTR_WRITE_THROUGH:
389 return (PTE_W | PTE_M);
394 * Assume the page is cache inhibited and access is guarded unless
395 * it's in our available memory array.
397 pte_lo = PTE_I | PTE_G;
398 for (i = 0; i < pregions_sz; i++) {
399 if ((pa >= pregions[i].mr_start) &&
400 (pa < (pregions[i].mr_start + pregions[i].mr_size))) {
410 tlbie(vm_offset_t va)
413 mtx_lock_spin(&tlbie_mtx);
414 __asm __volatile("ptesync");
415 __asm __volatile("tlbie %0" :: "r"(va));
416 __asm __volatile("eieio; tlbsync; ptesync");
417 mtx_unlock_spin(&tlbie_mtx);
425 for (va = 0; va < 0x00040000; va += 0x00001000) {
426 __asm __volatile("tlbie %0" :: "r"(va));
429 __asm __volatile("tlbsync");
434 va_to_sr(u_int *sr, vm_offset_t va)
436 return (sr[(uintptr_t)va >> ADDR_SR_SHFT]);
439 static __inline u_int
440 va_to_pteg(u_int sr, vm_offset_t addr)
444 hash = (sr & SR_VSID_MASK) ^ (((u_int)addr & ADDR_PIDX) >>
446 return (hash & moea_pteg_mask);
449 static __inline struct pvo_head *
450 vm_page_to_pvoh(vm_page_t m)
453 return (&m->md.mdpg_pvoh);
457 moea_attr_clear(vm_page_t m, int ptebit)
460 rw_assert(&pvh_global_lock, RA_WLOCKED);
461 m->md.mdpg_attrs &= ~ptebit;
465 moea_attr_fetch(vm_page_t m)
468 return (m->md.mdpg_attrs);
472 moea_attr_save(vm_page_t m, int ptebit)
475 rw_assert(&pvh_global_lock, RA_WLOCKED);
476 m->md.mdpg_attrs |= ptebit;
480 moea_pte_compare(const struct pte *pt, const struct pte *pvo_pt)
482 if (pt->pte_hi == pvo_pt->pte_hi)
489 moea_pte_match(struct pte *pt, u_int sr, vm_offset_t va, int which)
491 return (pt->pte_hi & ~PTE_VALID) ==
492 (((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
493 ((va >> ADDR_API_SHFT) & PTE_API) | which);
497 moea_pte_create(struct pte *pt, u_int sr, vm_offset_t va, u_int pte_lo)
500 mtx_assert(&moea_table_mutex, MA_OWNED);
503 * Construct a PTE. Default to IMB initially. Valid bit only gets
504 * set when the real pte is set in memory.
506 * Note: Don't set the valid bit for correct operation of tlb update.
508 pt->pte_hi = ((sr & SR_VSID_MASK) << PTE_VSID_SHFT) |
509 (((va & ADDR_PIDX) >> ADDR_API_SHFT) & PTE_API);
514 moea_pte_synch(struct pte *pt, struct pte *pvo_pt)
517 mtx_assert(&moea_table_mutex, MA_OWNED);
518 pvo_pt->pte_lo |= pt->pte_lo & (PTE_REF | PTE_CHG);
522 moea_pte_clear(struct pte *pt, vm_offset_t va, int ptebit)
525 mtx_assert(&moea_table_mutex, MA_OWNED);
528 * As shown in Section 7.6.3.2.3
530 pt->pte_lo &= ~ptebit;
535 moea_pte_set(struct pte *pt, struct pte *pvo_pt)
538 mtx_assert(&moea_table_mutex, MA_OWNED);
539 pvo_pt->pte_hi |= PTE_VALID;
542 * Update the PTE as defined in section 7.6.3.1.
543 * Note that the REF/CHG bits are from pvo_pt and thus should have
544 * been saved so this routine can restore them (if desired).
546 pt->pte_lo = pvo_pt->pte_lo;
548 pt->pte_hi = pvo_pt->pte_hi;
554 moea_pte_unset(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
557 mtx_assert(&moea_table_mutex, MA_OWNED);
558 pvo_pt->pte_hi &= ~PTE_VALID;
561 * Force the reg & chg bits back into the PTEs.
566 * Invalidate the pte.
568 pt->pte_hi &= ~PTE_VALID;
573 * Save the reg & chg bits.
575 moea_pte_synch(pt, pvo_pt);
580 moea_pte_change(struct pte *pt, struct pte *pvo_pt, vm_offset_t va)
586 moea_pte_unset(pt, pvo_pt, va);
587 moea_pte_set(pt, pvo_pt);
591 * Quick sort callout for comparing memory regions.
593 static int om_cmp(const void *a, const void *b);
596 om_cmp(const void *a, const void *b)
598 const struct ofw_map *mapa;
599 const struct ofw_map *mapb;
603 if (mapa->om_pa < mapb->om_pa)
605 else if (mapa->om_pa > mapb->om_pa)
612 moea_cpu_bootstrap(mmu_t mmup, int ap)
619 __asm __volatile("mtdbatu 0,%0" :: "r"(battable[0].batu));
620 __asm __volatile("mtdbatl 0,%0" :: "r"(battable[0].batl));
622 __asm __volatile("mtibatu 0,%0" :: "r"(battable[0].batu));
623 __asm __volatile("mtibatl 0,%0" :: "r"(battable[0].batl));
629 * Special case for the Wii: don't install the PCI BAT.
631 if (strcmp(installed_platform(), "wii") != 0) {
633 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
634 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
640 __asm __volatile("mtibatu 1,%0" :: "r"(0));
641 __asm __volatile("mtdbatu 2,%0" :: "r"(0));
642 __asm __volatile("mtibatu 2,%0" :: "r"(0));
643 __asm __volatile("mtdbatu 3,%0" :: "r"(0));
644 __asm __volatile("mtibatu 3,%0" :: "r"(0));
647 for (i = 0; i < 16; i++)
648 mtsrin(i << ADDR_SR_SHFT, kernel_pmap->pm_sr[i]);
651 sdr = (u_int)moea_pteg_table | (moea_pteg_mask >> 10);
652 __asm __volatile("mtsdr1 %0" :: "r"(sdr));
659 moea_bootstrap(mmu_t mmup, vm_offset_t kernelstart, vm_offset_t kernelend)
662 phandle_t chosen, mmu;
665 vm_size_t size, physsz, hwphyssz;
666 vm_offset_t pa, va, off;
671 * Set up BAT0 to map the lowest 256 MB area
673 battable[0x0].batl = BATL(0x00000000, BAT_M, BAT_PP_RW);
674 battable[0x0].batu = BATU(0x00000000, BAT_BL_256M, BAT_Vs);
677 * Map PCI memory space.
679 battable[0x8].batl = BATL(0x80000000, BAT_I|BAT_G, BAT_PP_RW);
680 battable[0x8].batu = BATU(0x80000000, BAT_BL_256M, BAT_Vs);
682 battable[0x9].batl = BATL(0x90000000, BAT_I|BAT_G, BAT_PP_RW);
683 battable[0x9].batu = BATU(0x90000000, BAT_BL_256M, BAT_Vs);
685 battable[0xa].batl = BATL(0xa0000000, BAT_I|BAT_G, BAT_PP_RW);
686 battable[0xa].batu = BATU(0xa0000000, BAT_BL_256M, BAT_Vs);
688 battable[0xb].batl = BATL(0xb0000000, BAT_I|BAT_G, BAT_PP_RW);
689 battable[0xb].batu = BATU(0xb0000000, BAT_BL_256M, BAT_Vs);
694 battable[0xf].batl = BATL(0xf0000000, BAT_I|BAT_G, BAT_PP_RW);
695 battable[0xf].batu = BATU(0xf0000000, BAT_BL_256M, BAT_Vs);
698 * Use an IBAT and a DBAT to map the bottom segment of memory
699 * where we are. Turn off instruction relocation temporarily
700 * to prevent faults while reprogramming the IBAT.
703 mtmsr(msr & ~PSL_IR);
704 __asm (".balign 32; \n"
705 "mtibatu 0,%0; mtibatl 0,%1; isync; \n"
706 "mtdbatu 0,%0; mtdbatl 0,%1; isync"
707 :: "r"(battable[0].batu), "r"(battable[0].batl));
711 if (strcmp(installed_platform(), "wii") != 0) {
714 __asm __volatile("mtdbatu 1,%0" :: "r"(battable[8].batu));
715 __asm __volatile("mtdbatl 1,%0" :: "r"(battable[8].batl));
721 /* set global direct map flag */
724 mem_regions(&pregions, &pregions_sz, ®ions, ®ions_sz);
725 CTR0(KTR_PMAP, "moea_bootstrap: physical memory");
727 for (i = 0; i < pregions_sz; i++) {
731 CTR3(KTR_PMAP, "physregion: %#x - %#x (%#x)",
732 pregions[i].mr_start,
733 pregions[i].mr_start + pregions[i].mr_size,
734 pregions[i].mr_size);
736 * Install entries into the BAT table to allow all
737 * of physmem to be convered by on-demand BAT entries.
738 * The loop will sometimes set the same battable element
739 * twice, but that's fine since they won't be used for
742 pa = pregions[i].mr_start & 0xf0000000;
743 end = pregions[i].mr_start + pregions[i].mr_size;
745 u_int n = pa >> ADDR_SR_SHFT;
747 battable[n].batl = BATL(pa, BAT_M, BAT_PP_RW);
748 battable[n].batu = BATU(pa, BAT_BL_256M, BAT_Vs);
749 pa += SEGMENT_LENGTH;
753 if (sizeof(phys_avail)/sizeof(phys_avail[0]) < regions_sz)
754 panic("moea_bootstrap: phys_avail too small");
756 phys_avail_count = 0;
759 TUNABLE_ULONG_FETCH("hw.physmem", (u_long *) &hwphyssz);
760 for (i = 0, j = 0; i < regions_sz; i++, j += 2) {
761 CTR3(KTR_PMAP, "region: %#x - %#x (%#x)", regions[i].mr_start,
762 regions[i].mr_start + regions[i].mr_size,
765 (physsz + regions[i].mr_size) >= hwphyssz) {
766 if (physsz < hwphyssz) {
767 phys_avail[j] = regions[i].mr_start;
768 phys_avail[j + 1] = regions[i].mr_start +
775 phys_avail[j] = regions[i].mr_start;
776 phys_avail[j + 1] = regions[i].mr_start + regions[i].mr_size;
778 physsz += regions[i].mr_size;
781 /* Check for overlap with the kernel and exception vectors */
782 for (j = 0; j < 2*phys_avail_count; j+=2) {
783 if (phys_avail[j] < EXC_LAST)
784 phys_avail[j] += EXC_LAST;
786 if (kernelstart >= phys_avail[j] &&
787 kernelstart < phys_avail[j+1]) {
788 if (kernelend < phys_avail[j+1]) {
789 phys_avail[2*phys_avail_count] =
790 (kernelend & ~PAGE_MASK) + PAGE_SIZE;
791 phys_avail[2*phys_avail_count + 1] =
796 phys_avail[j+1] = kernelstart & ~PAGE_MASK;
799 if (kernelend >= phys_avail[j] &&
800 kernelend < phys_avail[j+1]) {
801 if (kernelstart > phys_avail[j]) {
802 phys_avail[2*phys_avail_count] = phys_avail[j];
803 phys_avail[2*phys_avail_count + 1] =
804 kernelstart & ~PAGE_MASK;
808 phys_avail[j] = (kernelend & ~PAGE_MASK) + PAGE_SIZE;
812 physmem = btoc(physsz);
815 * Allocate PTEG table.
818 moea_pteg_count = PTEGCOUNT;
820 moea_pteg_count = 0x1000;
822 while (moea_pteg_count < physmem)
823 moea_pteg_count <<= 1;
825 moea_pteg_count >>= 1;
826 #endif /* PTEGCOUNT */
828 size = moea_pteg_count * sizeof(struct pteg);
829 CTR2(KTR_PMAP, "moea_bootstrap: %d PTEGs, %d bytes", moea_pteg_count,
831 moea_pteg_table = (struct pteg *)moea_bootstrap_alloc(size, size);
832 CTR1(KTR_PMAP, "moea_bootstrap: PTEG table at %p", moea_pteg_table);
833 bzero((void *)moea_pteg_table, moea_pteg_count * sizeof(struct pteg));
834 moea_pteg_mask = moea_pteg_count - 1;
837 * Allocate pv/overflow lists.
839 size = sizeof(struct pvo_head) * moea_pteg_count;
840 moea_pvo_table = (struct pvo_head *)moea_bootstrap_alloc(size,
842 CTR1(KTR_PMAP, "moea_bootstrap: PVO table at %p", moea_pvo_table);
843 for (i = 0; i < moea_pteg_count; i++)
844 LIST_INIT(&moea_pvo_table[i]);
847 * Initialize the lock that synchronizes access to the pteg and pvo
850 mtx_init(&moea_table_mutex, "pmap table", NULL, MTX_DEF |
852 mtx_init(&moea_vsid_mutex, "VSID table", NULL, MTX_DEF);
854 mtx_init(&tlbie_mtx, "tlbie", NULL, MTX_SPIN);
857 * Initialise the unmanaged pvo pool.
859 moea_bpvo_pool = (struct pvo_entry *)moea_bootstrap_alloc(
860 BPVO_POOL_SIZE*sizeof(struct pvo_entry), 0);
861 moea_bpvo_pool_index = 0;
864 * Make sure kernel vsid is allocated as well as VSID 0.
866 moea_vsid_bitmap[(KERNEL_VSIDBITS & (NPMAPS - 1)) / VSID_NBPW]
867 |= 1 << (KERNEL_VSIDBITS % VSID_NBPW);
868 moea_vsid_bitmap[0] |= 1;
871 * Initialize the kernel pmap (which is statically allocated).
873 PMAP_LOCK_INIT(kernel_pmap);
874 for (i = 0; i < 16; i++)
875 kernel_pmap->pm_sr[i] = EMPTY_SEGMENT + i;
876 CPU_FILL(&kernel_pmap->pm_active);
877 RB_INIT(&kernel_pmap->pmap_pvo);
880 * Initialize the global pv list lock.
882 rw_init(&pvh_global_lock, "pmap pv global");
885 * Set up the Open Firmware mappings
887 chosen = OF_finddevice("/chosen");
888 if (chosen != -1 && OF_getprop(chosen, "mmu", &mmui, 4) != -1 &&
889 (mmu = OF_instance_to_package(mmui)) != -1 &&
890 (sz = OF_getproplen(mmu, "translations")) != -1) {
892 for (i = 0; phys_avail[i] != 0; i += 2) {
893 if (phys_avail[i + 1] >= sz) {
894 translations = (struct ofw_map *)phys_avail[i];
898 if (translations == NULL)
899 panic("moea_bootstrap: no space to copy translations");
900 bzero(translations, sz);
901 if (OF_getprop(mmu, "translations", translations, sz) == -1)
902 panic("moea_bootstrap: can't get ofw translations");
903 CTR0(KTR_PMAP, "moea_bootstrap: translations");
904 sz /= sizeof(*translations);
905 qsort(translations, sz, sizeof (*translations), om_cmp);
906 for (i = 0; i < sz; i++) {
907 CTR3(KTR_PMAP, "translation: pa=%#x va=%#x len=%#x",
908 translations[i].om_pa, translations[i].om_va,
909 translations[i].om_len);
912 * If the mapping is 1:1, let the RAM and device
913 * on-demand BAT tables take care of the translation.
915 if (translations[i].om_va == translations[i].om_pa)
918 /* Enter the pages */
919 for (off = 0; off < translations[i].om_len;
921 moea_kenter(mmup, translations[i].om_va + off,
922 translations[i].om_pa + off);
927 * Calculate the last available physical address.
929 for (i = 0; phys_avail[i + 2] != 0; i += 2)
931 Maxmem = powerpc_btop(phys_avail[i + 1]);
933 moea_cpu_bootstrap(mmup,0);
938 * Set the start and end of kva.
940 virtual_avail = VM_MIN_KERNEL_ADDRESS;
941 virtual_end = VM_MAX_SAFE_KERNEL_ADDRESS;
944 * Allocate a kernel stack with a guard page for thread0 and map it
945 * into the kernel page map.
947 pa = moea_bootstrap_alloc(KSTACK_PAGES * PAGE_SIZE, PAGE_SIZE);
948 va = virtual_avail + KSTACK_GUARD_PAGES * PAGE_SIZE;
949 virtual_avail = va + KSTACK_PAGES * PAGE_SIZE;
950 CTR2(KTR_PMAP, "moea_bootstrap: kstack0 at %#x (%#x)", pa, va);
951 thread0.td_kstack = va;
952 thread0.td_kstack_pages = KSTACK_PAGES;
953 for (i = 0; i < KSTACK_PAGES; i++) {
954 moea_kenter(mmup, va, pa);
960 * Allocate virtual address space for the message buffer.
962 pa = msgbuf_phys = moea_bootstrap_alloc(msgbufsize, PAGE_SIZE);
963 msgbufp = (struct msgbuf *)virtual_avail;
965 virtual_avail += round_page(msgbufsize);
966 while (va < virtual_avail) {
967 moea_kenter(mmup, va, pa);
973 * Allocate virtual address space for the dynamic percpu area.
975 pa = moea_bootstrap_alloc(DPCPU_SIZE, PAGE_SIZE);
976 dpcpu = (void *)virtual_avail;
978 virtual_avail += DPCPU_SIZE;
979 while (va < virtual_avail) {
980 moea_kenter(mmup, va, pa);
984 dpcpu_init(dpcpu, 0);
988 * Activate a user pmap. The pmap must be activated before it's address
989 * space can be accessed in any way.
992 moea_activate(mmu_t mmu, struct thread *td)
997 * Load all the data we need up front to encourage the compiler to
998 * not issue any loads while we have interrupts disabled below.
1000 pm = &td->td_proc->p_vmspace->vm_pmap;
1001 pmr = pm->pmap_phys;
1003 CPU_SET(PCPU_GET(cpuid), &pm->pm_active);
1004 PCPU_SET(curpmap, pmr);
1008 moea_deactivate(mmu_t mmu, struct thread *td)
1012 pm = &td->td_proc->p_vmspace->vm_pmap;
1013 CPU_CLR(PCPU_GET(cpuid), &pm->pm_active);
1014 PCPU_SET(curpmap, NULL);
1018 moea_unwire(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1020 struct pvo_entry key, *pvo;
1023 key.pvo_vaddr = sva;
1024 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1025 pvo != NULL && PVO_VADDR(pvo) < eva;
1026 pvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo)) {
1027 if ((pvo->pvo_vaddr & PVO_WIRED) == 0)
1028 panic("moea_unwire: pvo %p is missing PVO_WIRED", pvo);
1029 pvo->pvo_vaddr &= ~PVO_WIRED;
1030 pm->pm_stats.wired_count--;
1036 moea_copy_page(mmu_t mmu, vm_page_t msrc, vm_page_t mdst)
1041 dst = VM_PAGE_TO_PHYS(mdst);
1042 src = VM_PAGE_TO_PHYS(msrc);
1044 bcopy((void *)src, (void *)dst, PAGE_SIZE);
1048 moea_copy_pages(mmu_t mmu, vm_page_t *ma, vm_offset_t a_offset,
1049 vm_page_t *mb, vm_offset_t b_offset, int xfersize)
1052 vm_offset_t a_pg_offset, b_pg_offset;
1055 while (xfersize > 0) {
1056 a_pg_offset = a_offset & PAGE_MASK;
1057 cnt = min(xfersize, PAGE_SIZE - a_pg_offset);
1058 a_cp = (char *)VM_PAGE_TO_PHYS(ma[a_offset >> PAGE_SHIFT]) +
1060 b_pg_offset = b_offset & PAGE_MASK;
1061 cnt = min(cnt, PAGE_SIZE - b_pg_offset);
1062 b_cp = (char *)VM_PAGE_TO_PHYS(mb[b_offset >> PAGE_SHIFT]) +
1064 bcopy(a_cp, b_cp, cnt);
1072 * Zero a page of physical memory by temporarily mapping it into the tlb.
1075 moea_zero_page(mmu_t mmu, vm_page_t m)
1077 vm_offset_t off, pa = VM_PAGE_TO_PHYS(m);
1079 for (off = 0; off < PAGE_SIZE; off += cacheline_size)
1080 __asm __volatile("dcbz 0,%0" :: "r"(pa + off));
1084 moea_zero_page_area(mmu_t mmu, vm_page_t m, int off, int size)
1086 vm_offset_t pa = VM_PAGE_TO_PHYS(m);
1087 void *va = (void *)(pa + off);
1093 moea_zero_page_idle(mmu_t mmu, vm_page_t m)
1096 moea_zero_page(mmu, m);
1100 * Map the given physical page at the specified virtual address in the
1101 * target pmap with the protection requested. If specified the page
1102 * will be wired down.
1105 moea_enter(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1106 u_int flags, int8_t psind)
1111 rw_wlock(&pvh_global_lock);
1113 error = moea_enter_locked(pmap, va, m, prot, flags, psind);
1114 rw_wunlock(&pvh_global_lock);
1116 if (error != ENOMEM)
1117 return (KERN_SUCCESS);
1118 if ((flags & PMAP_ENTER_NOSLEEP) != 0)
1119 return (KERN_RESOURCE_SHORTAGE);
1120 VM_OBJECT_ASSERT_UNLOCKED(m->object);
1126 * Map the given physical page at the specified virtual address in the
1127 * target pmap with the protection requested. If specified the page
1128 * will be wired down.
1130 * The page queues and pmap must be locked.
1133 moea_enter_locked(pmap_t pmap, vm_offset_t va, vm_page_t m, vm_prot_t prot,
1134 u_int flags, int8_t psind __unused)
1136 struct pvo_head *pvo_head;
1139 u_int pte_lo, pvo_flags;
1142 if (!moea_initialized) {
1143 pvo_head = &moea_pvo_kunmanaged;
1144 zone = moea_upvo_zone;
1148 pvo_head = vm_page_to_pvoh(m);
1150 zone = moea_mpvo_zone;
1151 pvo_flags = PVO_MANAGED;
1153 if (pmap_bootstrapped)
1154 rw_assert(&pvh_global_lock, RA_WLOCKED);
1155 PMAP_LOCK_ASSERT(pmap, MA_OWNED);
1156 if ((m->oflags & VPO_UNMANAGED) == 0 && !vm_page_xbusied(m))
1157 VM_OBJECT_ASSERT_LOCKED(m->object);
1159 /* XXX change the pvo head for fake pages */
1160 if ((m->oflags & VPO_UNMANAGED) != 0) {
1161 pvo_flags &= ~PVO_MANAGED;
1162 pvo_head = &moea_pvo_kunmanaged;
1163 zone = moea_upvo_zone;
1166 pte_lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), pmap_page_get_memattr(m));
1168 if (prot & VM_PROT_WRITE) {
1170 if (pmap_bootstrapped &&
1171 (m->oflags & VPO_UNMANAGED) == 0)
1172 vm_page_aflag_set(m, PGA_WRITEABLE);
1176 if ((flags & PMAP_ENTER_WIRED) != 0)
1177 pvo_flags |= PVO_WIRED;
1179 error = moea_pvo_enter(pmap, zone, pvo_head, va, VM_PAGE_TO_PHYS(m),
1183 * Flush the real page from the instruction cache. This has be done
1184 * for all user mappings to prevent information leakage via the
1185 * instruction cache. moea_pvo_enter() returns ENOENT for the first
1186 * mapping for a page.
1188 if (pmap != kernel_pmap && error == ENOENT &&
1189 (pte_lo & (PTE_I | PTE_G)) == 0)
1190 moea_syncicache(VM_PAGE_TO_PHYS(m), PAGE_SIZE);
1196 * Maps a sequence of resident pages belonging to the same object.
1197 * The sequence begins with the given page m_start. This page is
1198 * mapped at the given virtual address start. Each subsequent page is
1199 * mapped at a virtual address that is offset from start by the same
1200 * amount as the page is offset from m_start within the object. The
1201 * last page in the sequence is the page with the largest offset from
1202 * m_start that can be mapped at a virtual address less than the given
1203 * virtual address end. Not every virtual page between start and end
1204 * is mapped; only those for which a resident page exists with the
1205 * corresponding offset from m_start are mapped.
1208 moea_enter_object(mmu_t mmu, pmap_t pm, vm_offset_t start, vm_offset_t end,
1209 vm_page_t m_start, vm_prot_t prot)
1212 vm_pindex_t diff, psize;
1214 VM_OBJECT_ASSERT_LOCKED(m_start->object);
1216 psize = atop(end - start);
1218 rw_wlock(&pvh_global_lock);
1220 while (m != NULL && (diff = m->pindex - m_start->pindex) < psize) {
1221 moea_enter_locked(pm, start + ptoa(diff), m, prot &
1222 (VM_PROT_READ | VM_PROT_EXECUTE), 0, 0);
1223 m = TAILQ_NEXT(m, listq);
1225 rw_wunlock(&pvh_global_lock);
1230 moea_enter_quick(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_page_t m,
1234 rw_wlock(&pvh_global_lock);
1236 moea_enter_locked(pm, va, m, prot & (VM_PROT_READ | VM_PROT_EXECUTE),
1238 rw_wunlock(&pvh_global_lock);
1243 moea_extract(mmu_t mmu, pmap_t pm, vm_offset_t va)
1245 struct pvo_entry *pvo;
1249 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
1253 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1259 * Atomically extract and hold the physical page with the given
1260 * pmap and virtual address pair if that mapping permits the given
1264 moea_extract_and_hold(mmu_t mmu, pmap_t pmap, vm_offset_t va, vm_prot_t prot)
1266 struct pvo_entry *pvo;
1274 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1275 if (pvo != NULL && (pvo->pvo_pte.pte.pte_hi & PTE_VALID) &&
1276 ((pvo->pvo_pte.pte.pte_lo & PTE_PP) == PTE_RW ||
1277 (prot & VM_PROT_WRITE) == 0)) {
1278 if (vm_page_pa_tryrelock(pmap, pvo->pvo_pte.pte.pte_lo & PTE_RPGN, &pa))
1280 m = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
1289 moea_init(mmu_t mmu)
1292 moea_upvo_zone = uma_zcreate("UPVO entry", sizeof (struct pvo_entry),
1293 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1294 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1295 moea_mpvo_zone = uma_zcreate("MPVO entry", sizeof(struct pvo_entry),
1296 NULL, NULL, NULL, NULL, UMA_ALIGN_PTR,
1297 UMA_ZONE_VM | UMA_ZONE_NOFREE);
1298 moea_initialized = TRUE;
1302 moea_is_referenced(mmu_t mmu, vm_page_t m)
1306 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1307 ("moea_is_referenced: page %p is not managed", m));
1308 rw_wlock(&pvh_global_lock);
1309 rv = moea_query_bit(m, PTE_REF);
1310 rw_wunlock(&pvh_global_lock);
1315 moea_is_modified(mmu_t mmu, vm_page_t m)
1319 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1320 ("moea_is_modified: page %p is not managed", m));
1323 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1324 * concurrently set while the object is locked. Thus, if PGA_WRITEABLE
1325 * is clear, no PTEs can have PTE_CHG set.
1327 VM_OBJECT_ASSERT_WLOCKED(m->object);
1328 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1330 rw_wlock(&pvh_global_lock);
1331 rv = moea_query_bit(m, PTE_CHG);
1332 rw_wunlock(&pvh_global_lock);
1337 moea_is_prefaultable(mmu_t mmu, pmap_t pmap, vm_offset_t va)
1339 struct pvo_entry *pvo;
1343 pvo = moea_pvo_find_va(pmap, va & ~ADDR_POFF, NULL);
1344 rv = pvo == NULL || (pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0;
1350 moea_clear_modify(mmu_t mmu, vm_page_t m)
1353 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1354 ("moea_clear_modify: page %p is not managed", m));
1355 VM_OBJECT_ASSERT_WLOCKED(m->object);
1356 KASSERT(!vm_page_xbusied(m),
1357 ("moea_clear_modify: page %p is exclusive busy", m));
1360 * If the page is not PGA_WRITEABLE, then no PTEs can have PTE_CHG
1361 * set. If the object containing the page is locked and the page is
1362 * not exclusive busied, then PGA_WRITEABLE cannot be concurrently set.
1364 if ((m->aflags & PGA_WRITEABLE) == 0)
1366 rw_wlock(&pvh_global_lock);
1367 moea_clear_bit(m, PTE_CHG);
1368 rw_wunlock(&pvh_global_lock);
1372 * Clear the write and modified bits in each of the given page's mappings.
1375 moea_remove_write(mmu_t mmu, vm_page_t m)
1377 struct pvo_entry *pvo;
1382 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1383 ("moea_remove_write: page %p is not managed", m));
1386 * If the page is not exclusive busied, then PGA_WRITEABLE cannot be
1387 * set by another thread while the object is locked. Thus,
1388 * if PGA_WRITEABLE is clear, no page table entries need updating.
1390 VM_OBJECT_ASSERT_WLOCKED(m->object);
1391 if (!vm_page_xbusied(m) && (m->aflags & PGA_WRITEABLE) == 0)
1393 rw_wlock(&pvh_global_lock);
1394 lo = moea_attr_fetch(m);
1396 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1397 pmap = pvo->pvo_pmap;
1399 if ((pvo->pvo_pte.pte.pte_lo & PTE_PP) != PTE_BR) {
1400 pt = moea_pvo_to_pte(pvo, -1);
1401 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1402 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1404 moea_pte_synch(pt, &pvo->pvo_pte.pte);
1405 lo |= pvo->pvo_pte.pte.pte_lo;
1406 pvo->pvo_pte.pte.pte_lo &= ~PTE_CHG;
1407 moea_pte_change(pt, &pvo->pvo_pte.pte,
1409 mtx_unlock(&moea_table_mutex);
1414 if ((lo & PTE_CHG) != 0) {
1415 moea_attr_clear(m, PTE_CHG);
1418 vm_page_aflag_clear(m, PGA_WRITEABLE);
1419 rw_wunlock(&pvh_global_lock);
1423 * moea_ts_referenced:
1425 * Return a count of reference bits for a page, clearing those bits.
1426 * It is not necessary for every reference bit to be cleared, but it
1427 * is necessary that 0 only be returned when there are truly no
1428 * reference bits set.
1430 * XXX: The exact number of bits to check and clear is a matter that
1431 * should be tested and standardized at some point in the future for
1432 * optimal aging of shared pages.
1435 moea_ts_referenced(mmu_t mmu, vm_page_t m)
1439 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1440 ("moea_ts_referenced: page %p is not managed", m));
1441 rw_wlock(&pvh_global_lock);
1442 count = moea_clear_bit(m, PTE_REF);
1443 rw_wunlock(&pvh_global_lock);
1448 * Modify the WIMG settings of all mappings for a page.
1451 moea_page_set_memattr(mmu_t mmu, vm_page_t m, vm_memattr_t ma)
1453 struct pvo_entry *pvo;
1454 struct pvo_head *pvo_head;
1459 if ((m->oflags & VPO_UNMANAGED) != 0) {
1460 m->md.mdpg_cache_attrs = ma;
1464 rw_wlock(&pvh_global_lock);
1465 pvo_head = vm_page_to_pvoh(m);
1466 lo = moea_calc_wimg(VM_PAGE_TO_PHYS(m), ma);
1468 LIST_FOREACH(pvo, pvo_head, pvo_vlink) {
1469 pmap = pvo->pvo_pmap;
1471 pt = moea_pvo_to_pte(pvo, -1);
1472 pvo->pvo_pte.pte.pte_lo &= ~PTE_WIMG;
1473 pvo->pvo_pte.pte.pte_lo |= lo;
1475 moea_pte_change(pt, &pvo->pvo_pte.pte,
1477 if (pvo->pvo_pmap == kernel_pmap)
1480 mtx_unlock(&moea_table_mutex);
1483 m->md.mdpg_cache_attrs = ma;
1484 rw_wunlock(&pvh_global_lock);
1488 * Map a wired page into kernel virtual address space.
1491 moea_kenter(mmu_t mmu, vm_offset_t va, vm_paddr_t pa)
1494 moea_kenter_attr(mmu, va, pa, VM_MEMATTR_DEFAULT);
1498 moea_kenter_attr(mmu_t mmu, vm_offset_t va, vm_offset_t pa, vm_memattr_t ma)
1504 if (va < VM_MIN_KERNEL_ADDRESS)
1505 panic("moea_kenter: attempt to enter non-kernel address %#x",
1509 pte_lo = moea_calc_wimg(pa, ma);
1511 PMAP_LOCK(kernel_pmap);
1512 error = moea_pvo_enter(kernel_pmap, moea_upvo_zone,
1513 &moea_pvo_kunmanaged, va, pa, pte_lo, PVO_WIRED);
1515 if (error != 0 && error != ENOENT)
1516 panic("moea_kenter: failed to enter va %#x pa %#x: %d", va,
1519 PMAP_UNLOCK(kernel_pmap);
1523 * Extract the physical page address associated with the given kernel virtual
1527 moea_kextract(mmu_t mmu, vm_offset_t va)
1529 struct pvo_entry *pvo;
1533 * Allow direct mappings on 32-bit OEA
1535 if (va < VM_MIN_KERNEL_ADDRESS) {
1539 PMAP_LOCK(kernel_pmap);
1540 pvo = moea_pvo_find_va(kernel_pmap, va & ~ADDR_POFF, NULL);
1541 KASSERT(pvo != NULL, ("moea_kextract: no addr found"));
1542 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) | (va & ADDR_POFF);
1543 PMAP_UNLOCK(kernel_pmap);
1548 * Remove a wired page from kernel virtual address space.
1551 moea_kremove(mmu_t mmu, vm_offset_t va)
1554 moea_remove(mmu, kernel_pmap, va, va + PAGE_SIZE);
1558 * Map a range of physical addresses into kernel virtual address space.
1560 * The value passed in *virt is a suggested virtual address for the mapping.
1561 * Architectures which can support a direct-mapped physical to virtual region
1562 * can return the appropriate address within that region, leaving '*virt'
1563 * unchanged. We cannot and therefore do not; *virt is updated with the
1564 * first usable address after the mapped region.
1567 moea_map(mmu_t mmu, vm_offset_t *virt, vm_paddr_t pa_start,
1568 vm_paddr_t pa_end, int prot)
1570 vm_offset_t sva, va;
1574 for (; pa_start < pa_end; pa_start += PAGE_SIZE, va += PAGE_SIZE)
1575 moea_kenter(mmu, va, pa_start);
1581 * Returns true if the pmap's pv is one of the first
1582 * 16 pvs linked to from this page. This count may
1583 * be changed upwards or downwards in the future; it
1584 * is only necessary that true be returned for a small
1585 * subset of pmaps for proper page aging.
1588 moea_page_exists_quick(mmu_t mmu, pmap_t pmap, vm_page_t m)
1591 struct pvo_entry *pvo;
1594 KASSERT((m->oflags & VPO_UNMANAGED) == 0,
1595 ("moea_page_exists_quick: page %p is not managed", m));
1598 rw_wlock(&pvh_global_lock);
1599 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
1600 if (pvo->pvo_pmap == pmap) {
1607 rw_wunlock(&pvh_global_lock);
1612 * Return the number of managed mappings to the given physical page
1616 moea_page_wired_mappings(mmu_t mmu, vm_page_t m)
1618 struct pvo_entry *pvo;
1622 if ((m->oflags & VPO_UNMANAGED) != 0)
1624 rw_wlock(&pvh_global_lock);
1625 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink)
1626 if ((pvo->pvo_vaddr & PVO_WIRED) != 0)
1628 rw_wunlock(&pvh_global_lock);
1632 static u_int moea_vsidcontext;
1635 moea_pinit(mmu_t mmu, pmap_t pmap)
1640 KASSERT((int)pmap < VM_MIN_KERNEL_ADDRESS, ("moea_pinit: virt pmap"));
1641 RB_INIT(&pmap->pmap_pvo);
1644 __asm __volatile("mftb %0" : "=r"(entropy));
1646 if ((pmap->pmap_phys = (pmap_t)moea_kextract(mmu, (vm_offset_t)pmap))
1648 pmap->pmap_phys = pmap;
1652 mtx_lock(&moea_vsid_mutex);
1654 * Allocate some segment registers for this pmap.
1656 for (i = 0; i < NPMAPS; i += VSID_NBPW) {
1660 * Create a new value by mutiplying by a prime and adding in
1661 * entropy from the timebase register. This is to make the
1662 * VSID more random so that the PT hash function collides
1663 * less often. (Note that the prime casues gcc to do shifts
1664 * instead of a multiply.)
1666 moea_vsidcontext = (moea_vsidcontext * 0x1105) + entropy;
1667 hash = moea_vsidcontext & (NPMAPS - 1);
1668 if (hash == 0) /* 0 is special, avoid it */
1671 mask = 1 << (hash & (VSID_NBPW - 1));
1672 hash = (moea_vsidcontext & 0xfffff);
1673 if (moea_vsid_bitmap[n] & mask) { /* collision? */
1674 /* anything free in this bucket? */
1675 if (moea_vsid_bitmap[n] == 0xffffffff) {
1676 entropy = (moea_vsidcontext >> 20);
1679 i = ffs(~moea_vsid_bitmap[n]) - 1;
1681 hash &= 0xfffff & ~(VSID_NBPW - 1);
1684 KASSERT(!(moea_vsid_bitmap[n] & mask),
1685 ("Allocating in-use VSID group %#x\n", hash));
1686 moea_vsid_bitmap[n] |= mask;
1687 for (i = 0; i < 16; i++)
1688 pmap->pm_sr[i] = VSID_MAKE(i, hash);
1689 mtx_unlock(&moea_vsid_mutex);
1693 mtx_unlock(&moea_vsid_mutex);
1694 panic("moea_pinit: out of segments");
1698 * Initialize the pmap associated with process 0.
1701 moea_pinit0(mmu_t mmu, pmap_t pm)
1705 moea_pinit(mmu, pm);
1706 bzero(&pm->pm_stats, sizeof(pm->pm_stats));
1710 * Set the physical protection on the specified range of this map as requested.
1713 moea_protect(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva,
1716 struct pvo_entry *pvo, *tpvo, key;
1719 KASSERT(pm == &curproc->p_vmspace->vm_pmap || pm == kernel_pmap,
1720 ("moea_protect: non current pmap"));
1722 if ((prot & VM_PROT_READ) == VM_PROT_NONE) {
1723 moea_remove(mmu, pm, sva, eva);
1727 rw_wlock(&pvh_global_lock);
1729 key.pvo_vaddr = sva;
1730 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1731 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1732 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1735 * Grab the PTE pointer before we diddle with the cached PTE
1738 pt = moea_pvo_to_pte(pvo, -1);
1740 * Change the protection of the page.
1742 pvo->pvo_pte.pte.pte_lo &= ~PTE_PP;
1743 pvo->pvo_pte.pte.pte_lo |= PTE_BR;
1746 * If the PVO is in the page table, update that pte as well.
1749 moea_pte_change(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
1750 mtx_unlock(&moea_table_mutex);
1753 rw_wunlock(&pvh_global_lock);
1758 * Map a list of wired pages into kernel virtual address space. This is
1759 * intended for temporary mappings which do not need page modification or
1760 * references recorded. Existing mappings in the region are overwritten.
1763 moea_qenter(mmu_t mmu, vm_offset_t sva, vm_page_t *m, int count)
1768 while (count-- > 0) {
1769 moea_kenter(mmu, va, VM_PAGE_TO_PHYS(*m));
1776 * Remove page mappings from kernel virtual address space. Intended for
1777 * temporary mappings entered by moea_qenter.
1780 moea_qremove(mmu_t mmu, vm_offset_t sva, int count)
1785 while (count-- > 0) {
1786 moea_kremove(mmu, va);
1792 moea_release(mmu_t mmu, pmap_t pmap)
1797 * Free segment register's VSID
1799 if (pmap->pm_sr[0] == 0)
1800 panic("moea_release");
1802 mtx_lock(&moea_vsid_mutex);
1803 idx = VSID_TO_HASH(pmap->pm_sr[0]) & (NPMAPS-1);
1804 mask = 1 << (idx % VSID_NBPW);
1806 moea_vsid_bitmap[idx] &= ~mask;
1807 mtx_unlock(&moea_vsid_mutex);
1811 * Remove the given range of addresses from the specified map.
1814 moea_remove(mmu_t mmu, pmap_t pm, vm_offset_t sva, vm_offset_t eva)
1816 struct pvo_entry *pvo, *tpvo, key;
1818 rw_wlock(&pvh_global_lock);
1820 key.pvo_vaddr = sva;
1821 for (pvo = RB_NFIND(pvo_tree, &pm->pmap_pvo, &key);
1822 pvo != NULL && PVO_VADDR(pvo) < eva; pvo = tpvo) {
1823 tpvo = RB_NEXT(pvo_tree, &pm->pmap_pvo, pvo);
1824 moea_pvo_remove(pvo, -1);
1827 rw_wunlock(&pvh_global_lock);
1831 * Remove physical page from all pmaps in which it resides. moea_pvo_remove()
1832 * will reflect changes in pte's back to the vm_page.
1835 moea_remove_all(mmu_t mmu, vm_page_t m)
1837 struct pvo_head *pvo_head;
1838 struct pvo_entry *pvo, *next_pvo;
1841 rw_wlock(&pvh_global_lock);
1842 pvo_head = vm_page_to_pvoh(m);
1843 for (pvo = LIST_FIRST(pvo_head); pvo != NULL; pvo = next_pvo) {
1844 next_pvo = LIST_NEXT(pvo, pvo_vlink);
1846 pmap = pvo->pvo_pmap;
1848 moea_pvo_remove(pvo, -1);
1851 if ((m->aflags & PGA_WRITEABLE) && moea_query_bit(m, PTE_CHG)) {
1852 moea_attr_clear(m, PTE_CHG);
1855 vm_page_aflag_clear(m, PGA_WRITEABLE);
1856 rw_wunlock(&pvh_global_lock);
1860 * Allocate a physical page of memory directly from the phys_avail map.
1861 * Can only be called from moea_bootstrap before avail start and end are
1865 moea_bootstrap_alloc(vm_size_t size, u_int align)
1870 size = round_page(size);
1871 for (i = 0; phys_avail[i + 1] != 0; i += 2) {
1873 s = (phys_avail[i] + align - 1) & ~(align - 1);
1878 if (s < phys_avail[i] || e > phys_avail[i + 1])
1881 if (s == phys_avail[i]) {
1882 phys_avail[i] += size;
1883 } else if (e == phys_avail[i + 1]) {
1884 phys_avail[i + 1] -= size;
1886 for (j = phys_avail_count * 2; j > i; j -= 2) {
1887 phys_avail[j] = phys_avail[j - 2];
1888 phys_avail[j + 1] = phys_avail[j - 1];
1891 phys_avail[i + 3] = phys_avail[i + 1];
1892 phys_avail[i + 1] = s;
1893 phys_avail[i + 2] = e;
1899 panic("moea_bootstrap_alloc: could not allocate memory");
1903 moea_syncicache(vm_offset_t pa, vm_size_t len)
1905 __syncicache((void *)pa, len);
1909 moea_pvo_enter(pmap_t pm, uma_zone_t zone, struct pvo_head *pvo_head,
1910 vm_offset_t va, vm_offset_t pa, u_int pte_lo, int flags)
1912 struct pvo_entry *pvo;
1919 moea_pvo_enter_calls++;
1924 * Compute the PTE Group index.
1927 sr = va_to_sr(pm->pm_sr, va);
1928 ptegidx = va_to_pteg(sr, va);
1931 * Remove any existing mapping for this page. Reuse the pvo entry if
1932 * there is a mapping.
1934 mtx_lock(&moea_table_mutex);
1935 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
1936 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
1937 if ((pvo->pvo_pte.pte.pte_lo & PTE_RPGN) == pa &&
1938 (pvo->pvo_pte.pte.pte_lo & PTE_PP) ==
1939 (pte_lo & PTE_PP)) {
1941 * The PTE is not changing. Instead, this may
1942 * be a request to change the mapping's wired
1945 mtx_unlock(&moea_table_mutex);
1946 if ((flags & PVO_WIRED) != 0 &&
1947 (pvo->pvo_vaddr & PVO_WIRED) == 0) {
1948 pvo->pvo_vaddr |= PVO_WIRED;
1949 pm->pm_stats.wired_count++;
1950 } else if ((flags & PVO_WIRED) == 0 &&
1951 (pvo->pvo_vaddr & PVO_WIRED) != 0) {
1952 pvo->pvo_vaddr &= ~PVO_WIRED;
1953 pm->pm_stats.wired_count--;
1957 moea_pvo_remove(pvo, -1);
1963 * If we aren't overwriting a mapping, try to allocate.
1965 if (moea_initialized) {
1966 pvo = uma_zalloc(zone, M_NOWAIT);
1968 if (moea_bpvo_pool_index >= BPVO_POOL_SIZE) {
1969 panic("moea_enter: bpvo pool exhausted, %d, %d, %d",
1970 moea_bpvo_pool_index, BPVO_POOL_SIZE,
1971 BPVO_POOL_SIZE * sizeof(struct pvo_entry));
1973 pvo = &moea_bpvo_pool[moea_bpvo_pool_index];
1974 moea_bpvo_pool_index++;
1979 mtx_unlock(&moea_table_mutex);
1984 pvo->pvo_vaddr = va;
1986 LIST_INSERT_HEAD(&moea_pvo_table[ptegidx], pvo, pvo_olink);
1987 pvo->pvo_vaddr &= ~ADDR_POFF;
1988 if (flags & PVO_WIRED)
1989 pvo->pvo_vaddr |= PVO_WIRED;
1990 if (pvo_head != &moea_pvo_kunmanaged)
1991 pvo->pvo_vaddr |= PVO_MANAGED;
1993 pvo->pvo_vaddr |= PVO_BOOTSTRAP;
1995 moea_pte_create(&pvo->pvo_pte.pte, sr, va, pa | pte_lo);
2000 RB_INSERT(pvo_tree, &pm->pmap_pvo, pvo);
2003 * Remember if the list was empty and therefore will be the first
2006 if (LIST_FIRST(pvo_head) == NULL)
2008 LIST_INSERT_HEAD(pvo_head, pvo, pvo_vlink);
2010 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2011 pm->pm_stats.wired_count++;
2012 pm->pm_stats.resident_count++;
2014 i = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2015 KASSERT(i < 8, ("Invalid PTE index"));
2017 PVO_PTEGIDX_SET(pvo, i);
2019 panic("moea_pvo_enter: overflow");
2020 moea_pte_overflow++;
2022 mtx_unlock(&moea_table_mutex);
2024 return (first ? ENOENT : 0);
2028 moea_pvo_remove(struct pvo_entry *pvo, int pteidx)
2033 * If there is an active pte entry, we need to deactivate it (and
2034 * save the ref & cfg bits).
2036 pt = moea_pvo_to_pte(pvo, pteidx);
2038 moea_pte_unset(pt, &pvo->pvo_pte.pte, pvo->pvo_vaddr);
2039 mtx_unlock(&moea_table_mutex);
2040 PVO_PTEGIDX_CLR(pvo);
2042 moea_pte_overflow--;
2046 * Update our statistics.
2048 pvo->pvo_pmap->pm_stats.resident_count--;
2049 if (pvo->pvo_pte.pte.pte_lo & PVO_WIRED)
2050 pvo->pvo_pmap->pm_stats.wired_count--;
2053 * Save the REF/CHG bits into their cache if the page is managed.
2055 if ((pvo->pvo_vaddr & PVO_MANAGED) == PVO_MANAGED) {
2058 pg = PHYS_TO_VM_PAGE(pvo->pvo_pte.pte.pte_lo & PTE_RPGN);
2060 moea_attr_save(pg, pvo->pvo_pte.pte.pte_lo &
2061 (PTE_REF | PTE_CHG));
2066 * Remove this PVO from the PV and pmap lists.
2068 LIST_REMOVE(pvo, pvo_vlink);
2069 RB_REMOVE(pvo_tree, &pvo->pvo_pmap->pmap_pvo, pvo);
2072 * Remove this from the overflow list and return it to the pool
2073 * if we aren't going to reuse it.
2075 LIST_REMOVE(pvo, pvo_olink);
2076 if (!(pvo->pvo_vaddr & PVO_BOOTSTRAP))
2077 uma_zfree(pvo->pvo_vaddr & PVO_MANAGED ? moea_mpvo_zone :
2078 moea_upvo_zone, pvo);
2080 moea_pvo_remove_calls++;
2084 moea_pvo_pte_index(const struct pvo_entry *pvo, int ptegidx)
2089 * We can find the actual pte entry without searching by grabbing
2090 * the PTEG index from 3 unused bits in pte_lo[11:9] and by
2091 * noticing the HID bit.
2093 pteidx = ptegidx * 8 + PVO_PTEGIDX_GET(pvo);
2094 if (pvo->pvo_pte.pte.pte_hi & PTE_HID)
2095 pteidx ^= moea_pteg_mask * 8;
2100 static struct pvo_entry *
2101 moea_pvo_find_va(pmap_t pm, vm_offset_t va, int *pteidx_p)
2103 struct pvo_entry *pvo;
2108 sr = va_to_sr(pm->pm_sr, va);
2109 ptegidx = va_to_pteg(sr, va);
2111 mtx_lock(&moea_table_mutex);
2112 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2113 if (pvo->pvo_pmap == pm && PVO_VADDR(pvo) == va) {
2115 *pteidx_p = moea_pvo_pte_index(pvo, ptegidx);
2119 mtx_unlock(&moea_table_mutex);
2125 moea_pvo_to_pte(const struct pvo_entry *pvo, int pteidx)
2130 * If we haven't been supplied the ptegidx, calculate it.
2136 sr = va_to_sr(pvo->pvo_pmap->pm_sr, pvo->pvo_vaddr);
2137 ptegidx = va_to_pteg(sr, pvo->pvo_vaddr);
2138 pteidx = moea_pvo_pte_index(pvo, ptegidx);
2141 pt = &moea_pteg_table[pteidx >> 3].pt[pteidx & 7];
2142 mtx_lock(&moea_table_mutex);
2144 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) && !PVO_PTEGIDX_ISSET(pvo)) {
2145 panic("moea_pvo_to_pte: pvo %p has valid pte in pvo but no "
2146 "valid pte index", pvo);
2149 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0 && PVO_PTEGIDX_ISSET(pvo)) {
2150 panic("moea_pvo_to_pte: pvo %p has valid pte index in pvo "
2151 "pvo but no valid pte", pvo);
2154 if ((pt->pte_hi ^ (pvo->pvo_pte.pte.pte_hi & ~PTE_VALID)) == PTE_VALID) {
2155 if ((pvo->pvo_pte.pte.pte_hi & PTE_VALID) == 0) {
2156 panic("moea_pvo_to_pte: pvo %p has valid pte in "
2157 "moea_pteg_table %p but invalid in pvo", pvo, pt);
2160 if (((pt->pte_lo ^ pvo->pvo_pte.pte.pte_lo) & ~(PTE_CHG|PTE_REF))
2162 panic("moea_pvo_to_pte: pvo %p pte does not match "
2163 "pte %p in moea_pteg_table", pvo, pt);
2166 mtx_assert(&moea_table_mutex, MA_OWNED);
2170 if (pvo->pvo_pte.pte.pte_hi & PTE_VALID) {
2171 panic("moea_pvo_to_pte: pvo %p has invalid pte %p in "
2172 "moea_pteg_table but valid in pvo: %8x, %8x", pvo, pt, pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2175 mtx_unlock(&moea_table_mutex);
2180 * XXX: THIS STUFF SHOULD BE IN pte.c?
2183 moea_pte_spill(vm_offset_t addr)
2185 struct pvo_entry *source_pvo, *victim_pvo;
2186 struct pvo_entry *pvo;
2195 ptegidx = va_to_pteg(sr, addr);
2198 * Have to substitute some entry. Use the primary hash for this.
2199 * Use low bits of timebase as random generator.
2201 pteg = &moea_pteg_table[ptegidx];
2202 mtx_lock(&moea_table_mutex);
2203 __asm __volatile("mftb %0" : "=r"(i));
2209 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx], pvo_olink) {
2211 * We need to find a pvo entry for this address.
2213 if (source_pvo == NULL &&
2214 moea_pte_match(&pvo->pvo_pte.pte, sr, addr,
2215 pvo->pvo_pte.pte.pte_hi & PTE_HID)) {
2217 * Now found an entry to be spilled into the pteg.
2218 * The PTE is now valid, so we know it's active.
2220 j = moea_pte_insert(ptegidx, &pvo->pvo_pte.pte);
2223 PVO_PTEGIDX_SET(pvo, j);
2224 moea_pte_overflow--;
2225 mtx_unlock(&moea_table_mutex);
2231 if (victim_pvo != NULL)
2236 * We also need the pvo entry of the victim we are replacing
2237 * so save the R & C bits of the PTE.
2239 if ((pt->pte_hi & PTE_HID) == 0 && victim_pvo == NULL &&
2240 moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2242 if (source_pvo != NULL)
2247 if (source_pvo == NULL) {
2248 mtx_unlock(&moea_table_mutex);
2252 if (victim_pvo == NULL) {
2253 if ((pt->pte_hi & PTE_HID) == 0)
2254 panic("moea_pte_spill: victim p-pte (%p) has no pvo"
2258 * If this is a secondary PTE, we need to search it's primary
2259 * pvo bucket for the matching PVO.
2261 LIST_FOREACH(pvo, &moea_pvo_table[ptegidx ^ moea_pteg_mask],
2264 * We also need the pvo entry of the victim we are
2265 * replacing so save the R & C bits of the PTE.
2267 if (moea_pte_compare(pt, &pvo->pvo_pte.pte)) {
2273 if (victim_pvo == NULL)
2274 panic("moea_pte_spill: victim s-pte (%p) has no pvo"
2279 * We are invalidating the TLB entry for the EA we are replacing even
2280 * though it's valid. If we don't, we lose any ref/chg bit changes
2281 * contained in the TLB entry.
2283 source_pvo->pvo_pte.pte.pte_hi &= ~PTE_HID;
2285 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2286 moea_pte_set(pt, &source_pvo->pvo_pte.pte);
2288 PVO_PTEGIDX_CLR(victim_pvo);
2289 PVO_PTEGIDX_SET(source_pvo, i);
2290 moea_pte_replacements++;
2292 mtx_unlock(&moea_table_mutex);
2296 static __inline struct pvo_entry *
2297 moea_pte_spillable_ident(u_int ptegidx)
2300 struct pvo_entry *pvo_walk, *pvo = NULL;
2302 LIST_FOREACH(pvo_walk, &moea_pvo_table[ptegidx], pvo_olink) {
2303 if (pvo_walk->pvo_vaddr & PVO_WIRED)
2306 if (!(pvo_walk->pvo_pte.pte.pte_hi & PTE_VALID))
2309 pt = moea_pvo_to_pte(pvo_walk, -1);
2316 mtx_unlock(&moea_table_mutex);
2317 if (!(pt->pte_lo & PTE_REF))
2325 moea_pte_insert(u_int ptegidx, struct pte *pvo_pt)
2328 struct pvo_entry *victim_pvo;
2331 u_int pteg_bkpidx = ptegidx;
2333 mtx_assert(&moea_table_mutex, MA_OWNED);
2336 * First try primary hash.
2338 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2339 if ((pt->pte_hi & PTE_VALID) == 0) {
2340 pvo_pt->pte_hi &= ~PTE_HID;
2341 moea_pte_set(pt, pvo_pt);
2347 * Now try secondary hash.
2349 ptegidx ^= moea_pteg_mask;
2351 for (pt = moea_pteg_table[ptegidx].pt, i = 0; i < 8; i++, pt++) {
2352 if ((pt->pte_hi & PTE_VALID) == 0) {
2353 pvo_pt->pte_hi |= PTE_HID;
2354 moea_pte_set(pt, pvo_pt);
2359 /* Try again, but this time try to force a PTE out. */
2360 ptegidx = pteg_bkpidx;
2362 victim_pvo = moea_pte_spillable_ident(ptegidx);
2363 if (victim_pvo == NULL) {
2364 ptegidx ^= moea_pteg_mask;
2365 victim_pvo = moea_pte_spillable_ident(ptegidx);
2368 if (victim_pvo == NULL) {
2369 panic("moea_pte_insert: overflow");
2373 victim_idx = moea_pvo_pte_index(victim_pvo, ptegidx);
2375 if (pteg_bkpidx == ptegidx)
2376 pvo_pt->pte_hi &= ~PTE_HID;
2378 pvo_pt->pte_hi |= PTE_HID;
2381 * Synchronize the sacrifice PTE with its PVO, then mark both
2382 * invalid. The PVO will be reused when/if the VM system comes
2383 * here after a fault.
2385 pt = &moea_pteg_table[victim_idx >> 3].pt[victim_idx & 7];
2387 if (pt->pte_hi != victim_pvo->pvo_pte.pte.pte_hi)
2388 panic("Victim PVO doesn't match PTE! PVO: %8x, PTE: %8x", victim_pvo->pvo_pte.pte.pte_hi, pt->pte_hi);
2393 moea_pte_unset(pt, &victim_pvo->pvo_pte.pte, victim_pvo->pvo_vaddr);
2394 PVO_PTEGIDX_CLR(victim_pvo);
2395 moea_pte_overflow++;
2396 moea_pte_set(pt, pvo_pt);
2398 return (victim_idx & 7);
2402 moea_query_bit(vm_page_t m, int ptebit)
2404 struct pvo_entry *pvo;
2407 rw_assert(&pvh_global_lock, RA_WLOCKED);
2408 if (moea_attr_fetch(m) & ptebit)
2411 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2414 * See if we saved the bit off. If so, cache it and return
2417 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2418 moea_attr_save(m, ptebit);
2424 * No luck, now go through the hard part of looking at the PTEs
2425 * themselves. Sync so that any pending REF/CHG bits are flushed to
2429 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2432 * See if this pvo has a valid PTE. if so, fetch the
2433 * REF/CHG bits from the valid PTE. If the appropriate
2434 * ptebit is set, cache it and return success.
2436 pt = moea_pvo_to_pte(pvo, -1);
2438 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2439 mtx_unlock(&moea_table_mutex);
2440 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2441 moea_attr_save(m, ptebit);
2451 moea_clear_bit(vm_page_t m, int ptebit)
2454 struct pvo_entry *pvo;
2457 rw_assert(&pvh_global_lock, RA_WLOCKED);
2460 * Clear the cached value.
2462 moea_attr_clear(m, ptebit);
2465 * Sync so that any pending REF/CHG bits are flushed to the PTEs (so
2466 * we can reset the right ones). note that since the pvo entries and
2467 * list heads are accessed via BAT0 and are never placed in the page
2468 * table, we don't have to worry about further accesses setting the
2474 * For each pvo entry, clear the pvo's ptebit. If this pvo has a
2475 * valid pte clear the ptebit from the valid pte.
2478 LIST_FOREACH(pvo, vm_page_to_pvoh(m), pvo_vlink) {
2479 pt = moea_pvo_to_pte(pvo, -1);
2481 moea_pte_synch(pt, &pvo->pvo_pte.pte);
2482 if (pvo->pvo_pte.pte.pte_lo & ptebit) {
2484 moea_pte_clear(pt, PVO_VADDR(pvo), ptebit);
2486 mtx_unlock(&moea_table_mutex);
2488 pvo->pvo_pte.pte.pte_lo &= ~ptebit;
2495 * Return true if the physical range is encompassed by the battable[idx]
2498 moea_bat_mapped(int idx, vm_offset_t pa, vm_size_t size)
2506 * Return immediately if not a valid mapping
2508 if (!(battable[idx].batu & BAT_Vs))
2512 * The BAT entry must be cache-inhibited, guarded, and r/w
2513 * so it can function as an i/o page
2515 prot = battable[idx].batl & (BAT_I|BAT_G|BAT_PP_RW);
2516 if (prot != (BAT_I|BAT_G|BAT_PP_RW))
2520 * The address should be within the BAT range. Assume that the
2521 * start address in the BAT has the correct alignment (thus
2522 * not requiring masking)
2524 start = battable[idx].batl & BAT_PBS;
2525 bat_ble = (battable[idx].batu & ~(BAT_EBS)) | 0x03;
2526 end = start | (bat_ble << 15) | 0x7fff;
2528 if ((pa < start) || ((pa + size) > end))
2535 moea_dev_direct_mapped(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2540 * This currently does not work for entries that
2541 * overlap 256M BAT segments.
2544 for(i = 0; i < 16; i++)
2545 if (moea_bat_mapped(i, pa, size) == 0)
2552 * Map a set of physical memory pages into the kernel virtual
2553 * address space. Return a pointer to where it is mapped. This
2554 * routine is intended to be used for mapping device memory,
2558 moea_mapdev(mmu_t mmu, vm_paddr_t pa, vm_size_t size)
2561 return (moea_mapdev_attr(mmu, pa, size, VM_MEMATTR_DEFAULT));
2565 moea_mapdev_attr(mmu_t mmu, vm_offset_t pa, vm_size_t size, vm_memattr_t ma)
2567 vm_offset_t va, tmpva, ppa, offset;
2570 ppa = trunc_page(pa);
2571 offset = pa & PAGE_MASK;
2572 size = roundup(offset + size, PAGE_SIZE);
2575 * If the physical address lies within a valid BAT table entry,
2576 * return the 1:1 mapping. This currently doesn't work
2577 * for regions that overlap 256M BAT segments.
2579 for (i = 0; i < 16; i++) {
2580 if (moea_bat_mapped(i, pa, size) == 0)
2581 return ((void *) pa);
2584 va = kva_alloc(size);
2586 panic("moea_mapdev: Couldn't alloc kernel virtual memory");
2588 for (tmpva = va; size > 0;) {
2589 moea_kenter_attr(mmu, tmpva, ppa, ma);
2596 return ((void *)(va + offset));
2600 moea_unmapdev(mmu_t mmu, vm_offset_t va, vm_size_t size)
2602 vm_offset_t base, offset;
2605 * If this is outside kernel virtual space, then it's a
2606 * battable entry and doesn't require unmapping
2608 if ((va >= VM_MIN_KERNEL_ADDRESS) && (va <= virtual_end)) {
2609 base = trunc_page(va);
2610 offset = va & PAGE_MASK;
2611 size = roundup(offset + size, PAGE_SIZE);
2612 kva_free(base, size);
2617 moea_sync_icache(mmu_t mmu, pmap_t pm, vm_offset_t va, vm_size_t sz)
2619 struct pvo_entry *pvo;
2626 lim = round_page(va);
2627 len = MIN(lim - va, sz);
2628 pvo = moea_pvo_find_va(pm, va & ~ADDR_POFF, NULL);
2630 pa = (pvo->pvo_pte.pte.pte_lo & PTE_RPGN) |
2632 moea_syncicache(pa, len);
2641 moea_dumpsys_map(mmu_t mmu, struct pmap_md *md, vm_size_t ofs,
2644 if (md->md_vaddr == ~0UL)
2645 return (md->md_paddr + ofs);
2647 return (md->md_vaddr + ofs);
2651 moea_scan_md(mmu_t mmu, struct pmap_md *prev)
2653 static struct pmap_md md;
2654 struct pvo_entry *pvo;
2657 if (dumpsys_minidump) {
2658 md.md_paddr = ~0UL; /* Minidumps use virtual addresses. */
2660 /* 1st: kernel .data and .bss. */
2662 md.md_vaddr = trunc_page((uintptr_t)_etext);
2663 md.md_size = round_page((uintptr_t)_end) - md.md_vaddr;
2666 switch (prev->md_index) {
2668 /* 2nd: msgbuf and tables (see pmap_bootstrap()). */
2670 md.md_vaddr = (vm_offset_t)msgbufp->msg_ptr;
2671 md.md_size = round_page(msgbufp->msg_size);
2674 /* 3rd: kernel VM. */
2675 va = prev->md_vaddr + prev->md_size;
2676 /* Find start of next chunk (from va). */
2677 while (va < virtual_end) {
2678 /* Don't dump the buffer cache. */
2679 if (va >= kmi.buffer_sva &&
2680 va < kmi.buffer_eva) {
2681 va = kmi.buffer_eva;
2684 pvo = moea_pvo_find_va(kernel_pmap,
2685 va & ~ADDR_POFF, NULL);
2687 (pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2691 if (va < virtual_end) {
2694 /* Find last page in chunk. */
2695 while (va < virtual_end) {
2696 /* Don't run into the buffer cache. */
2697 if (va == kmi.buffer_sva)
2699 pvo = moea_pvo_find_va(kernel_pmap,
2700 va & ~ADDR_POFF, NULL);
2702 !(pvo->pvo_pte.pte.pte_hi & PTE_VALID))
2706 md.md_size = va - md.md_vaddr;
2714 } else { /* minidumps */
2715 mem_regions(&pregions, &pregions_sz,
2716 ®ions, ®ions_sz);
2719 /* first physical chunk. */
2720 md.md_paddr = pregions[0].mr_start;
2721 md.md_size = pregions[0].mr_size;
2724 } else if (md.md_index < pregions_sz) {
2725 md.md_paddr = pregions[md.md_index].mr_start;
2726 md.md_size = pregions[md.md_index].mr_size;
2730 /* There's no next physical chunk. */