2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
58 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
60 #define PxSIG_ATA 0x00000101 /* ATA drive */
61 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
64 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
65 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
66 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
67 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
68 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
69 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
70 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
71 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
77 #define TEST_UNIT_READY 0x00
78 #define REQUEST_SENSE 0x03
80 #define START_STOP_UNIT 0x1B
81 #define PREVENT_ALLOW 0x1E
82 #define READ_CAPACITY 0x25
84 #define POSITION_TO_ELEMENT 0x2B
86 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
87 #define MODE_SENSE_10 0x5A
92 * SCSI mode page codes
94 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
95 #define MODEPAGE_CD_CAPABILITIES 0x2A
102 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
104 #define DPRINTF(format, arg...)
106 #define WPRINTF(format, arg...) printf(format, ##arg)
109 struct blockif_req io_req;
110 struct ahci_port *io_pr;
111 STAILQ_ENTRY(ahci_ioreq) io_list;
120 struct blockif_ctxt *bctx;
121 struct pci_ahci_softc *pr_sc;
152 struct ahci_ioreq *ioreq;
154 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
157 struct ahci_cmd_hdr {
162 uint32_t reserved[4];
165 struct ahci_prdt_entry {
171 struct pci_ahci_softc {
172 struct pci_devinst *asc_pi;
186 struct ahci_port port[MAX_PORTS];
188 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
190 static inline void lba_to_msf(uint8_t *buf, int lba)
193 buf[0] = (lba / 75) / 60;
194 buf[1] = (lba / 75) % 60;
199 * generate HBA intr depending on whether or not ports within
200 * the controller have an interrupt pending.
203 ahci_generate_intr(struct pci_ahci_softc *sc)
207 for (i = 0; i < sc->ports; i++) {
208 struct ahci_port *pr;
214 DPRINTF("%s %x\n", __func__, sc->is);
216 if (sc->is && (sc->ghc & AHCI_GHC_IE))
217 pci_generate_msi(sc->asc_pi, 0);
221 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
223 int offset, len, irq;
225 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
229 case FIS_TYPE_REGD2H:
234 case FIS_TYPE_SETDEVBITS:
239 case FIS_TYPE_PIOSETUP:
245 WPRINTF("unsupported fis type %d\n", ft);
248 memcpy(p->rfis + offset, fis, len);
251 ahci_generate_intr(p->pr_sc);
256 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
261 error = (tfd >> 8) & 0xff;
262 memset(fis, 0, sizeof(fis));
265 *(uint32_t *)(fis + 4) = (1 << slot);
266 if (fis[2] & ATA_S_ERROR)
267 p->is |= AHCI_P_IX_TFE;
269 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
273 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
278 error = (tfd >> 8) & 0xff;
279 memset(fis, 0, sizeof(fis));
280 fis[0] = FIS_TYPE_REGD2H;
294 if (fis[2] & ATA_S_ERROR)
295 p->is |= AHCI_P_IX_TFE;
297 p->ci &= ~(1 << slot);
298 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
302 ahci_write_reset_fis_d2h(struct ahci_port *p)
306 memset(fis, 0, sizeof(fis));
307 fis[0] = FIS_TYPE_REGD2H;
315 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
319 ahci_port_reset(struct ahci_port *pr)
324 pr->xfermode = ATA_UDMA6;
325 pr->mult_sectors = 128;
328 pr->ssts = ATA_SS_DET_NO_DEVICE;
329 pr->sig = 0xFFFFFFFF;
333 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
335 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
338 pr->tfd |= ATA_S_READY;
340 pr->sig = PxSIG_ATAPI;
341 ahci_write_reset_fis_d2h(pr);
345 ahci_reset(struct pci_ahci_softc *sc)
349 sc->ghc = AHCI_GHC_AE;
351 for (i = 0; i < sc->ports; i++) {
354 ahci_port_reset(&sc->port[i]);
359 ata_string(uint8_t *dest, const char *src, int len)
363 for (i = 0; i < len; i++) {
365 dest[i ^ 1] = *src++;
372 atapi_string(uint8_t *dest, const char *src, int len)
376 for (i = 0; i < len; i++) {
385 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
388 struct ahci_ioreq *aior;
389 struct blockif_req *breq;
390 struct pci_ahci_softc *sc;
391 struct ahci_prdt_entry *prdt;
392 struct ahci_cmd_hdr *hdr;
395 int i, err, iovcnt, ncq, readop;
398 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
399 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
404 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
405 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
408 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
409 cfis[2] == ATA_READ_FPDMA_QUEUED) {
410 lba = ((uint64_t)cfis[10] << 40) |
411 ((uint64_t)cfis[9] << 32) |
412 ((uint64_t)cfis[8] << 24) |
413 ((uint64_t)cfis[6] << 16) |
414 ((uint64_t)cfis[5] << 8) |
416 len = cfis[11] << 8 | cfis[3];
420 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
421 lba = ((uint64_t)cfis[10] << 40) |
422 ((uint64_t)cfis[9] << 32) |
423 ((uint64_t)cfis[8] << 24) |
424 ((uint64_t)cfis[6] << 16) |
425 ((uint64_t)cfis[5] << 8) |
427 len = cfis[13] << 8 | cfis[12];
431 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
432 (cfis[5] << 8) | cfis[4];
437 lba *= blockif_sectsz(p->bctx);
438 len *= blockif_sectsz(p->bctx);
441 * Pull request off free list
443 aior = STAILQ_FIRST(&p->iofhd);
444 assert(aior != NULL);
445 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
450 breq = &aior->io_req;
451 breq->br_offset = lba + done;
452 iovcnt = hdr->prdtl - seek;
453 if (iovcnt > BLOCKIF_IOV_MAX) {
454 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
455 iovcnt = BLOCKIF_IOV_MAX;
458 breq->br_iovcnt = iovcnt;
461 * Build up the iovec based on the prdt
463 for (i = 0; i < iovcnt; i++) {
464 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
465 prdt->dba, prdt->dbc + 1);
466 breq->br_iov[i].iov_len = prdt->dbc + 1;
467 aior->done += (prdt->dbc + 1);
471 err = blockif_read(p->bctx, breq);
473 err = blockif_write(p->bctx, breq);
476 if (!aior->prdtl && ncq)
477 p->ci &= ~(1 << slot);
481 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
483 struct ahci_ioreq *aior;
484 struct blockif_req *breq;
488 * Pull request off free list
490 aior = STAILQ_FIRST(&p->iofhd);
491 assert(aior != NULL);
492 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
496 breq = &aior->io_req;
498 err = blockif_flush(p->bctx, breq);
503 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
506 struct ahci_cmd_hdr *hdr;
507 struct ahci_prdt_entry *prdt;
511 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
514 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
515 for (i = 0; i < hdr->prdtl && len; i++) {
516 uint8_t *ptr = paddr_guest2host(ahci_ctx(p->pr_sc),
517 prdt->dba, prdt->dbc + 1);
518 memcpy(ptr, from, prdt->dbc + 1);
519 len -= (prdt->dbc + 1);
520 from += (prdt->dbc + 1);
523 hdr->prdbc = size - len;
527 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
529 struct ahci_cmd_hdr *hdr;
531 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
532 if (p->atapi || hdr->prdtl == 0) {
533 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
534 p->is |= AHCI_P_IX_TFE;
539 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
540 memset(buf, 0, sizeof(buf));
542 /* TODO emulate different serial? */
543 ata_string((uint8_t *)(buf+10), "123456", 20);
544 ata_string((uint8_t *)(buf+23), "001", 8);
545 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
546 buf[47] = (0x8000 | 128);
548 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
550 buf[53] = (1 << 1 | 1 << 2);
552 buf[59] = (0x100 | p->mult_sectors);
554 buf[61] = (sectors >> 16);
556 if (p->xfermode & ATA_WDMA0)
557 buf[63] |= (1 << ((p->xfermode & 7) + 8));
564 buf[76] = (1 << 8 | 1 << 2);
567 buf[82] = (1 << 5 | 1 << 14);
568 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
570 buf[85] = (1 << 5 | 1 << 14);
571 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
574 if (p->xfermode & ATA_UDMA0)
575 buf[88] |= (1 << ((p->xfermode & 7) + 8));
576 buf[93] = (1 | 1 <<14);
578 buf[101] = (sectors >> 16);
579 buf[102] = (sectors >> 32);
580 buf[103] = (sectors >> 48);
581 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
582 p->tfd = ATA_S_DSC | ATA_S_READY;
583 p->is |= AHCI_P_IX_DP;
585 p->ci &= ~(1 << slot);
586 ahci_generate_intr(p->pr_sc);
590 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
593 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
594 p->is |= AHCI_P_IX_TFE;
598 memset(buf, 0, sizeof(buf));
599 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
600 /* TODO emulate different serial? */
601 ata_string((uint8_t *)(buf+10), "123456", 20);
602 ata_string((uint8_t *)(buf+23), "001", 8);
603 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
604 buf[49] = (1 << 9 | 1 << 8);
605 buf[50] = (1 << 14 | 1);
606 buf[53] = (1 << 2 | 1 << 1);
614 buf[76] = (1 << 2 | 1 << 1);
616 buf[80] = (0x1f << 4);
622 buf[88] = (1 << 14 | 0x7f);
623 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
624 p->tfd = ATA_S_DSC | ATA_S_READY;
625 p->is |= AHCI_P_IX_DHR;
627 p->ci &= ~(1 << slot);
628 ahci_generate_intr(p->pr_sc);
632 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
648 atapi_string(buf + 8, "BHYVE", 8);
649 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
650 atapi_string(buf + 32, "001", 4);
655 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
656 write_prdt(p, slot, cfis, buf, len);
657 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
661 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
666 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
668 be32enc(buf, sectors - 1);
669 be32enc(buf + 4, 2048);
670 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
671 write_prdt(p, slot, cfis, buf, sizeof(buf));
672 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
676 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
684 len = be16dec(acmd + 7);
685 format = acmd[9] >> 6;
691 uint8_t start_track, buf[20], *bp;
693 msf = (acmd[1] >> 1) & 1;
694 start_track = acmd[6];
695 if (start_track > 1 && start_track != 0xaa) {
697 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
699 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
700 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
701 ahci_write_fis_d2h(p, slot, cfis, tfd);
707 if (start_track <= 1) {
727 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
731 lba_to_msf(bp, sectors);
734 be32enc(bp, sectors);
738 be16enc(buf, size - 2);
741 write_prdt(p, slot, cfis, buf, len);
742 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
743 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
750 memset(buf, 0, sizeof(buf));
754 if (len > sizeof(buf))
756 write_prdt(p, slot, cfis, buf, len);
757 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
758 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
765 uint8_t start_track, *bp, buf[50];
767 msf = (acmd[1] >> 1) & 1;
768 start_track = acmd[6];
804 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
808 lba_to_msf(bp, sectors);
811 be32enc(bp, sectors);
834 be16enc(buf, size - 2);
837 write_prdt(p, slot, cfis, buf, len);
838 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
839 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
846 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
848 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
849 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
850 ahci_write_fis_d2h(p, slot, cfis, tfd);
857 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
858 uint32_t done, int seek)
860 struct ahci_ioreq *aior;
861 struct ahci_cmd_hdr *hdr;
862 struct ahci_prdt_entry *prdt;
863 struct blockif_req *breq;
864 struct pci_ahci_softc *sc;
872 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
873 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
876 lba = be32dec(acmd + 2);
877 if (acmd[0] == READ_10)
878 len = be16dec(acmd + 7);
880 len = be32dec(acmd + 6);
882 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
883 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
889 * Pull request off free list
891 aior = STAILQ_FIRST(&p->iofhd);
892 assert(aior != NULL);
893 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
898 breq = &aior->io_req;
899 breq->br_offset = lba + done;
900 iovcnt = hdr->prdtl - seek;
901 if (iovcnt > BLOCKIF_IOV_MAX) {
902 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
903 iovcnt = BLOCKIF_IOV_MAX;
906 breq->br_iovcnt = iovcnt;
909 * Build up the iovec based on the prdt
911 for (i = 0; i < hdr->prdtl; i++) {
912 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
913 prdt->dba, prdt->dbc + 1);
914 breq->br_iov[i].iov_len = prdt->dbc + 1;
915 aior->done += (prdt->dbc + 1);
918 err = blockif_read(p->bctx, breq);
923 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
931 if (len > sizeof(buf))
934 buf[0] = 0x70 | (1 << 7);
935 buf[2] = p->sense_key;
938 write_prdt(p, slot, cfis, buf, len);
939 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
940 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
944 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
946 uint8_t *acmd = cfis + 0x40;
949 switch (acmd[4] & 3) {
953 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
954 tfd = ATA_S_READY | ATA_S_DSC;
957 /* TODO eject media */
958 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
959 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
961 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
964 ahci_write_fis_d2h(p, slot, cfis, tfd);
968 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
976 len = be16dec(acmd + 7);
978 code = acmd[2] & 0x3f;
983 case MODEPAGE_RW_ERROR_RECOVERY:
987 if (len > sizeof(buf))
990 memset(buf, 0, sizeof(buf));
991 be16enc(buf, 16 - 2);
996 write_prdt(p, slot, cfis, buf, len);
997 tfd = ATA_S_READY | ATA_S_DSC;
1000 case MODEPAGE_CD_CAPABILITIES:
1004 if (len > sizeof(buf))
1007 memset(buf, 0, sizeof(buf));
1008 be16enc(buf, 30 - 2);
1014 be16enc(&buf[18], 2);
1015 be16enc(&buf[20], 512);
1016 write_prdt(p, slot, cfis, buf, len);
1017 tfd = ATA_S_READY | ATA_S_DSC;
1026 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1028 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1033 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1035 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1038 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1039 ahci_write_fis_d2h(p, slot, cfis, tfd);
1043 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1051 /* we don't support asynchronous operation */
1052 if (!(acmd[1] & 1)) {
1053 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1055 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1060 len = be16dec(acmd + 7);
1061 if (len > sizeof(buf))
1064 memset(buf, 0, sizeof(buf));
1065 be16enc(buf, 8 - 2);
1069 write_prdt(p, slot, cfis, buf, len);
1070 tfd = ATA_S_READY | ATA_S_DSC;
1072 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1073 ahci_write_fis_d2h(p, slot, cfis, tfd);
1077 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1087 for (i = 0; i < 16; i++)
1088 DPRINTF("%02x ", acmd[i]);
1094 case TEST_UNIT_READY:
1095 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1096 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1099 atapi_inquiry(p, slot, cfis);
1102 atapi_read_capacity(p, slot, cfis);
1106 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1107 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1110 atapi_read_toc(p, slot, cfis);
1114 atapi_read(p, slot, cfis, 0, 0);
1117 atapi_request_sense(p, slot, cfis);
1119 case START_STOP_UNIT:
1120 atapi_start_stop_unit(p, slot, cfis);
1123 atapi_mode_sense(p, slot, cfis);
1125 case GET_EVENT_STATUS_NOTIFICATION:
1126 atapi_get_event_status_notification(p, slot, cfis);
1129 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1130 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1132 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1133 ATA_S_READY | ATA_S_ERROR);
1139 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1143 case ATA_ATA_IDENTIFY:
1144 handle_identify(p, slot, cfis);
1146 case ATA_SETFEATURES:
1149 case ATA_SF_ENAB_WCACHE:
1150 case ATA_SF_DIS_WCACHE:
1151 case ATA_SF_ENAB_RCACHE:
1152 case ATA_SF_DIS_RCACHE:
1153 p->tfd = ATA_S_DSC | ATA_S_READY;
1155 case ATA_SF_SETXFER:
1157 switch (cfis[12] & 0xf8) {
1163 p->xfermode = (cfis[12] & 0x7);
1166 p->tfd = ATA_S_DSC | ATA_S_READY;
1170 p->tfd = ATA_S_ERROR | ATA_S_READY;
1171 p->tfd |= (ATA_ERROR_ABORT << 8);
1174 p->is |= AHCI_P_IX_DP;
1175 p->ci &= ~(1 << slot);
1176 ahci_generate_intr(p->pr_sc);
1180 if (cfis[12] != 0 &&
1181 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1182 p->tfd = ATA_S_ERROR | ATA_S_READY;
1183 p->tfd |= (ATA_ERROR_ABORT << 8);
1185 p->mult_sectors = cfis[12];
1186 p->tfd = ATA_S_DSC | ATA_S_READY;
1188 p->is |= AHCI_P_IX_DP;
1189 p->ci &= ~(1 << slot);
1190 ahci_generate_intr(p->pr_sc);
1194 case ATA_READ_DMA48:
1195 case ATA_WRITE_DMA48:
1196 case ATA_READ_FPDMA_QUEUED:
1197 case ATA_WRITE_FPDMA_QUEUED:
1198 ahci_handle_dma(p, slot, cfis, 0, 0);
1200 case ATA_FLUSHCACHE:
1201 case ATA_FLUSHCACHE48:
1202 ahci_handle_flush(p, slot, cfis);
1204 case ATA_STANDBY_CMD:
1207 case ATA_STANDBY_IMMEDIATE:
1208 case ATA_IDLE_IMMEDIATE:
1210 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1212 case ATA_ATAPI_IDENTIFY:
1213 handle_atapi_identify(p, slot, cfis);
1215 case ATA_PACKET_CMD:
1217 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1218 p->is |= AHCI_P_IX_TFE;
1219 p->ci &= ~(1 << slot);
1220 ahci_generate_intr(p->pr_sc);
1222 handle_packet_cmd(p, slot, cfis);
1225 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1226 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1227 p->is |= AHCI_P_IX_TFE;
1228 p->ci &= ~(1 << slot);
1229 ahci_generate_intr(p->pr_sc);
1235 ahci_handle_slot(struct ahci_port *p, int slot)
1237 struct ahci_cmd_hdr *hdr;
1238 struct ahci_prdt_entry *prdt;
1239 struct pci_ahci_softc *sc;
1244 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1245 cfl = (hdr->flags & 0x1f) * 4;
1246 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1247 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1248 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1252 for (i = 0; i < cfl; i++) {
1255 DPRINTF("%02x ", cfis[i]);
1259 for (i = 0; i < hdr->prdtl; i++) {
1260 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1265 if (cfis[0] != FIS_TYPE_REGH2D) {
1266 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1270 if (cfis[1] & 0x80) {
1271 ahci_handle_cmd(p, slot, cfis);
1273 if (cfis[15] & (1 << 2))
1275 else if (p->reset) {
1279 p->ci &= ~(1 << slot);
1284 ahci_handle_port(struct ahci_port *p)
1288 if (!(p->cmd & AHCI_P_CMD_ST))
1291 for (i = 0; (i < 32) && p->ci; i++) {
1292 if (p->ci & (1 << i))
1293 ahci_handle_slot(p, i);
1298 * blockif callback routine - this runs in the context of the blockif
1299 * i/o thread, so the mutex needs to be acquired.
1302 ata_ioreq_cb(struct blockif_req *br, int err)
1304 struct ahci_cmd_hdr *hdr;
1305 struct ahci_ioreq *aior;
1306 struct ahci_port *p;
1307 struct pci_ahci_softc *sc;
1310 int pending, slot, ncq;
1312 DPRINTF("%s %d\n", __func__, err);
1315 aior = br->br_param;
1319 pending = aior->prdtl;
1321 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1323 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1324 cfis[2] == ATA_READ_FPDMA_QUEUED)
1327 pthread_mutex_lock(&sc->mtx);
1330 * Move the blockif request back to the free list
1332 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1334 if (pending && !err) {
1335 ahci_handle_dma(p, slot, cfis, aior->done,
1336 hdr->prdtl - pending);
1340 if (!err && aior->done == aior->len) {
1341 tfd = ATA_S_READY | ATA_S_DSC;
1345 hdr->prdbc = aior->len;
1347 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1350 p->serr |= (1 << slot);
1354 p->sact &= ~(1 << slot);
1355 ahci_write_fis_sdb(p, slot, tfd);
1357 ahci_write_fis_d2h(p, slot, cfis, tfd);
1360 pthread_mutex_unlock(&sc->mtx);
1361 DPRINTF("%s exit\n", __func__);
1365 atapi_ioreq_cb(struct blockif_req *br, int err)
1367 struct ahci_cmd_hdr *hdr;
1368 struct ahci_ioreq *aior;
1369 struct ahci_port *p;
1370 struct pci_ahci_softc *sc;
1375 DPRINTF("%s %d\n", __func__, err);
1377 aior = br->br_param;
1381 pending = aior->prdtl;
1383 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1385 pthread_mutex_lock(&sc->mtx);
1388 * Move the blockif request back to the free list
1390 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1392 if (pending && !err) {
1393 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1397 if (!err && aior->done == aior->len) {
1398 tfd = ATA_S_READY | ATA_S_DSC;
1399 hdr->prdbc = aior->len;
1401 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1403 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1407 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1408 ahci_write_fis_d2h(p, slot, cfis, tfd);
1411 pthread_mutex_unlock(&sc->mtx);
1412 DPRINTF("%s exit\n", __func__);
1416 pci_ahci_ioreq_init(struct ahci_port *pr)
1418 struct ahci_ioreq *vr;
1421 pr->ioqsz = blockif_queuesz(pr->bctx);
1422 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1423 STAILQ_INIT(&pr->iofhd);
1426 * Add all i/o request entries to the free queue
1428 for (i = 0; i < pr->ioqsz; i++) {
1432 vr->io_req.br_callback = ata_ioreq_cb;
1434 vr->io_req.br_callback = atapi_ioreq_cb;
1435 vr->io_req.br_param = vr;
1436 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list);
1441 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1443 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1444 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1445 struct ahci_port *p = &sc->port[port];
1447 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1448 port, offset, value);
1467 p->ie = value & 0xFDC000FF;
1468 ahci_generate_intr(sc);
1474 if (!(value & AHCI_P_CMD_ST)) {
1475 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
1481 p->cmd |= AHCI_P_CMD_CR;
1482 clb = (uint64_t)p->clbu << 32 | p->clb;
1483 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1484 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1487 if (value & AHCI_P_CMD_FRE) {
1490 p->cmd |= AHCI_P_CMD_FR;
1491 fb = (uint64_t)p->fbu << 32 | p->fb;
1492 /* we don't support FBSCP, so rfis size is 256Bytes */
1493 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1495 p->cmd &= ~AHCI_P_CMD_FR;
1498 if (value & AHCI_P_CMD_CLO) {
1500 p->cmd &= ~AHCI_P_CMD_CLO;
1503 ahci_handle_port(p);
1509 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1512 if (!(p->cmd & AHCI_P_CMD_ST)) {
1513 if (value & ATA_SC_DET_RESET)
1526 ahci_handle_port(p);
1536 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1538 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1546 WPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1549 if (value & AHCI_GHC_HR)
1551 else if (value & AHCI_GHC_IE) {
1552 sc->ghc |= AHCI_GHC_IE;
1553 ahci_generate_intr(sc);
1558 ahci_generate_intr(sc);
1566 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1567 int baridx, uint64_t offset, int size, uint64_t value)
1569 struct pci_ahci_softc *sc = pi->pi_arg;
1571 assert(baridx == 5);
1574 pthread_mutex_lock(&sc->mtx);
1576 if (offset < AHCI_OFFSET)
1577 pci_ahci_host_write(sc, offset, value);
1578 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1579 pci_ahci_port_write(sc, offset, value);
1581 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1583 pthread_mutex_unlock(&sc->mtx);
1587 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1603 uint32_t *p = &sc->cap;
1604 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1612 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1619 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1622 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1623 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1643 uint32_t *p= &sc->port[port].clb;
1644 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1653 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1654 port, offset, value);
1660 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1661 uint64_t offset, int size)
1663 struct pci_ahci_softc *sc = pi->pi_arg;
1666 assert(baridx == 5);
1669 pthread_mutex_lock(&sc->mtx);
1671 if (offset < AHCI_OFFSET)
1672 value = pci_ahci_host_read(sc, offset);
1673 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1674 value = pci_ahci_port_read(sc, offset);
1677 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1680 pthread_mutex_unlock(&sc->mtx);
1686 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1688 char bident[sizeof("XX:X:X")];
1689 struct blockif_ctxt *bctxt;
1690 struct pci_ahci_softc *sc;
1696 fprintf(stderr, "pci_ahci: backing device required\n");
1701 dbg = fopen("/tmp/log", "w+");
1704 sc = malloc(sizeof(struct pci_ahci_softc));
1705 memset(sc, 0, sizeof(struct pci_ahci_softc));
1708 sc->ports = MAX_PORTS;
1711 * Only use port 0 for a backing device. All other ports will be
1714 sc->port[0].atapi = atapi;
1717 * Attempt to open the backing image. Use the PCI
1718 * slot/func/ahci_port for the identifier string
1719 * since that uniquely identifies a storage device.
1721 snprintf(bident, sizeof(bident), "%d:%d:%d", pi->pi_slot, pi->pi_func,
1723 bctxt = blockif_open(opts, bident);
1724 if (bctxt == NULL) {
1728 sc->port[0].bctx = bctxt;
1729 sc->port[0].pr_sc = sc;
1732 * Allocate blockif request structures and add them
1735 pci_ahci_ioreq_init(&sc->port[0]);
1737 pthread_mutex_init(&sc->mtx, NULL);
1739 /* Intel ICH8 AHCI */
1740 slots = sc->port[0].ioqsz;
1744 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1745 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1746 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1747 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1748 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1750 /* Only port 0 implemented */
1753 sc->cap2 = AHCI_CAP2_APST;
1756 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1757 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1758 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1759 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1760 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1761 pci_emul_add_msicap(pi, 1);
1762 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1763 AHCI_OFFSET + sc->ports * AHCI_STEP);
1767 blockif_close(sc->port[0].bctx);
1775 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1778 return (pci_ahci_init(ctx, pi, opts, 0));
1782 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1785 return (pci_ahci_init(ctx, pi, opts, 1));
1789 * Use separate emulation names to distinguish drive and atapi devices
1791 struct pci_devemu pci_de_ahci_hd = {
1792 .pe_emu = "ahci-hd",
1793 .pe_init = pci_ahci_hd_init,
1794 .pe_barwrite = pci_ahci_write,
1795 .pe_barread = pci_ahci_read
1797 PCI_EMUL_SET(pci_de_ahci_hd);
1799 struct pci_devemu pci_de_ahci_cd = {
1800 .pe_emu = "ahci-cd",
1801 .pe_init = pci_ahci_atapi_init,
1802 .pe_barwrite = pci_ahci_write,
1803 .pe_barread = pci_ahci_read
1805 PCI_EMUL_SET(pci_de_ahci_cd);