2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
58 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
60 #define PxSIG_ATA 0x00000101 /* ATA drive */
61 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
64 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
65 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
66 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
67 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
68 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
69 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
70 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
71 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
77 #define TEST_UNIT_READY 0x00
78 #define REQUEST_SENSE 0x03
80 #define START_STOP_UNIT 0x1B
81 #define PREVENT_ALLOW 0x1E
82 #define READ_CAPACITY 0x25
84 #define POSITION_TO_ELEMENT 0x2B
86 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
87 #define MODE_SENSE_10 0x5A
92 * SCSI mode page codes
94 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
95 #define MODEPAGE_CD_CAPABILITIES 0x2A
100 #define ATA_SF_ENAB_SATA_SF 0x10
101 #define ATA_SATA_SF_AN 0x05
102 #define ATA_SF_DIS_SATA_SF 0x90
109 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
111 #define DPRINTF(format, arg...)
113 #define WPRINTF(format, arg...) printf(format, ##arg)
116 struct blockif_req io_req;
117 struct ahci_port *io_pr;
118 STAILQ_ENTRY(ahci_ioreq) io_list;
127 struct blockif_ctxt *bctx;
128 struct pci_ahci_softc *pr_sc;
160 struct ahci_ioreq *ioreq;
162 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
165 struct ahci_cmd_hdr {
170 uint32_t reserved[4];
173 struct ahci_prdt_entry {
176 #define DBCMASK 0x3fffff
180 struct pci_ahci_softc {
181 struct pci_devinst *asc_pi;
195 struct ahci_port port[MAX_PORTS];
197 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
199 static inline void lba_to_msf(uint8_t *buf, int lba)
202 buf[0] = (lba / 75) / 60;
203 buf[1] = (lba / 75) % 60;
208 * generate HBA intr depending on whether or not ports within
209 * the controller have an interrupt pending.
212 ahci_generate_intr(struct pci_ahci_softc *sc)
216 for (i = 0; i < sc->ports; i++) {
217 struct ahci_port *pr;
223 DPRINTF("%s %x\n", __func__, sc->is);
225 if (sc->is && (sc->ghc & AHCI_GHC_IE))
226 pci_generate_msi(sc->asc_pi, 0);
230 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
232 int offset, len, irq;
234 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
238 case FIS_TYPE_REGD2H:
243 case FIS_TYPE_SETDEVBITS:
248 case FIS_TYPE_PIOSETUP:
254 WPRINTF("unsupported fis type %d\n", ft);
257 memcpy(p->rfis + offset, fis, len);
260 ahci_generate_intr(p->pr_sc);
265 ahci_write_fis_piosetup(struct ahci_port *p)
269 memset(fis, 0, sizeof(fis));
270 fis[0] = FIS_TYPE_PIOSETUP;
271 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
275 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
280 error = (tfd >> 8) & 0xff;
281 memset(fis, 0, sizeof(fis));
284 *(uint32_t *)(fis + 4) = (1 << slot);
285 if (fis[2] & ATA_S_ERROR)
286 p->is |= AHCI_P_IX_TFE;
288 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
292 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
297 error = (tfd >> 8) & 0xff;
298 memset(fis, 0, sizeof(fis));
299 fis[0] = FIS_TYPE_REGD2H;
313 if (fis[2] & ATA_S_ERROR)
314 p->is |= AHCI_P_IX_TFE;
316 p->ci &= ~(1 << slot);
317 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
321 ahci_write_reset_fis_d2h(struct ahci_port *p)
325 memset(fis, 0, sizeof(fis));
326 fis[0] = FIS_TYPE_REGD2H;
334 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
338 ahci_port_reset(struct ahci_port *pr)
343 pr->xfermode = ATA_UDMA6;
344 pr->mult_sectors = 128;
347 pr->ssts = ATA_SS_DET_NO_DEVICE;
348 pr->sig = 0xFFFFFFFF;
352 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
354 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
357 pr->tfd |= ATA_S_READY;
359 pr->sig = PxSIG_ATAPI;
360 ahci_write_reset_fis_d2h(pr);
364 ahci_reset(struct pci_ahci_softc *sc)
368 sc->ghc = AHCI_GHC_AE;
370 for (i = 0; i < sc->ports; i++) {
373 ahci_port_reset(&sc->port[i]);
378 ata_string(uint8_t *dest, const char *src, int len)
382 for (i = 0; i < len; i++) {
384 dest[i ^ 1] = *src++;
391 atapi_string(uint8_t *dest, const char *src, int len)
395 for (i = 0; i < len; i++) {
404 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
407 struct ahci_ioreq *aior;
408 struct blockif_req *breq;
409 struct pci_ahci_softc *sc;
410 struct ahci_prdt_entry *prdt;
411 struct ahci_cmd_hdr *hdr;
414 int i, err, iovcnt, ncq, readop;
417 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
418 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
423 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
424 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
427 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
428 cfis[2] == ATA_READ_FPDMA_QUEUED) {
429 lba = ((uint64_t)cfis[10] << 40) |
430 ((uint64_t)cfis[9] << 32) |
431 ((uint64_t)cfis[8] << 24) |
432 ((uint64_t)cfis[6] << 16) |
433 ((uint64_t)cfis[5] << 8) |
435 len = cfis[11] << 8 | cfis[3];
439 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
440 lba = ((uint64_t)cfis[10] << 40) |
441 ((uint64_t)cfis[9] << 32) |
442 ((uint64_t)cfis[8] << 24) |
443 ((uint64_t)cfis[6] << 16) |
444 ((uint64_t)cfis[5] << 8) |
446 len = cfis[13] << 8 | cfis[12];
450 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
451 (cfis[5] << 8) | cfis[4];
456 lba *= blockif_sectsz(p->bctx);
457 len *= blockif_sectsz(p->bctx);
460 * Pull request off free list
462 aior = STAILQ_FIRST(&p->iofhd);
463 assert(aior != NULL);
464 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
469 breq = &aior->io_req;
470 breq->br_offset = lba + done;
471 iovcnt = hdr->prdtl - seek;
472 if (iovcnt > BLOCKIF_IOV_MAX) {
473 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
474 iovcnt = BLOCKIF_IOV_MAX;
476 * Mark this command in-flight.
478 p->pending |= 1 << slot;
481 breq->br_iovcnt = iovcnt;
484 * Build up the iovec based on the prdt
486 for (i = 0; i < iovcnt; i++) {
489 dbcsz = (prdt->dbc & DBCMASK) + 1;
490 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
492 breq->br_iov[i].iov_len = dbcsz;
497 err = blockif_read(p->bctx, breq);
499 err = blockif_write(p->bctx, breq);
503 p->ci &= ~(1 << slot);
507 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
509 struct ahci_ioreq *aior;
510 struct blockif_req *breq;
514 * Pull request off free list
516 aior = STAILQ_FIRST(&p->iofhd);
517 assert(aior != NULL);
518 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
524 breq = &aior->io_req;
526 err = blockif_flush(p->bctx, breq);
531 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
534 struct ahci_cmd_hdr *hdr;
535 struct ahci_prdt_entry *prdt;
539 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
542 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
543 for (i = 0; i < hdr->prdtl && len; i++) {
548 dbcsz = (prdt->dbc & DBCMASK) + 1;
549 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
550 sublen = len < dbcsz ? len : dbcsz;
551 memcpy(ptr, from, sublen);
556 hdr->prdbc = size - len;
560 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
562 struct ahci_cmd_hdr *hdr;
564 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
565 if (p->atapi || hdr->prdtl == 0) {
566 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
567 p->is |= AHCI_P_IX_TFE;
572 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
573 memset(buf, 0, sizeof(buf));
575 /* TODO emulate different serial? */
576 ata_string((uint8_t *)(buf+10), "123456", 20);
577 ata_string((uint8_t *)(buf+23), "001", 8);
578 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
579 buf[47] = (0x8000 | 128);
581 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
583 buf[53] = (1 << 1 | 1 << 2);
585 buf[59] = (0x100 | p->mult_sectors);
587 buf[61] = (sectors >> 16);
589 if (p->xfermode & ATA_WDMA0)
590 buf[63] |= (1 << ((p->xfermode & 7) + 8));
597 buf[76] = (1 << 8 | 1 << 2);
600 buf[82] = (1 << 5 | 1 << 14);
601 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
603 buf[85] = (1 << 5 | 1 << 14);
604 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
607 if (p->xfermode & ATA_UDMA0)
608 buf[88] |= (1 << ((p->xfermode & 7) + 8));
609 buf[93] = (1 | 1 <<14);
611 buf[101] = (sectors >> 16);
612 buf[102] = (sectors >> 32);
613 buf[103] = (sectors >> 48);
614 ahci_write_fis_piosetup(p);
615 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
616 p->tfd = ATA_S_DSC | ATA_S_READY;
617 p->is |= AHCI_P_IX_DP;
619 p->ci &= ~(1 << slot);
620 ahci_generate_intr(p->pr_sc);
624 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
627 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
628 p->is |= AHCI_P_IX_TFE;
632 memset(buf, 0, sizeof(buf));
633 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
634 /* TODO emulate different serial? */
635 ata_string((uint8_t *)(buf+10), "123456", 20);
636 ata_string((uint8_t *)(buf+23), "001", 8);
637 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
638 buf[49] = (1 << 9 | 1 << 8);
639 buf[50] = (1 << 14 | 1);
640 buf[53] = (1 << 2 | 1 << 1);
648 buf[76] = (1 << 2 | 1 << 1);
650 buf[80] = (0x1f << 4);
656 buf[88] = (1 << 14 | 0x7f);
657 ahci_write_fis_piosetup(p);
658 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
659 p->tfd = ATA_S_DSC | ATA_S_READY;
660 p->is |= AHCI_P_IX_DHR;
662 p->ci &= ~(1 << slot);
663 ahci_generate_intr(p->pr_sc);
667 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
683 atapi_string(buf + 8, "BHYVE", 8);
684 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
685 atapi_string(buf + 32, "001", 4);
690 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
691 write_prdt(p, slot, cfis, buf, len);
692 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
696 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
701 sectors = blockif_size(p->bctx) / 2048;
702 be32enc(buf, sectors - 1);
703 be32enc(buf + 4, 2048);
704 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
705 write_prdt(p, slot, cfis, buf, sizeof(buf));
706 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
710 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
718 len = be16dec(acmd + 7);
719 format = acmd[9] >> 6;
725 uint8_t start_track, buf[20], *bp;
727 msf = (acmd[1] >> 1) & 1;
728 start_track = acmd[6];
729 if (start_track > 1 && start_track != 0xaa) {
731 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
733 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
734 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
735 ahci_write_fis_d2h(p, slot, cfis, tfd);
741 if (start_track <= 1) {
761 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
765 lba_to_msf(bp, sectors);
768 be32enc(bp, sectors);
772 be16enc(buf, size - 2);
775 write_prdt(p, slot, cfis, buf, len);
776 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
777 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
784 memset(buf, 0, sizeof(buf));
788 if (len > sizeof(buf))
790 write_prdt(p, slot, cfis, buf, len);
791 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
792 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
799 uint8_t start_track, *bp, buf[50];
801 msf = (acmd[1] >> 1) & 1;
802 start_track = acmd[6];
838 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
842 lba_to_msf(bp, sectors);
845 be32enc(bp, sectors);
868 be16enc(buf, size - 2);
871 write_prdt(p, slot, cfis, buf, len);
872 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
873 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
880 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
882 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
883 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
884 ahci_write_fis_d2h(p, slot, cfis, tfd);
891 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
892 uint32_t done, int seek)
894 struct ahci_ioreq *aior;
895 struct ahci_cmd_hdr *hdr;
896 struct ahci_prdt_entry *prdt;
897 struct blockif_req *breq;
898 struct pci_ahci_softc *sc;
906 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
907 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
910 lba = be32dec(acmd + 2);
911 if (acmd[0] == READ_10)
912 len = be16dec(acmd + 7);
914 len = be32dec(acmd + 6);
916 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
917 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
923 * Pull request off free list
925 aior = STAILQ_FIRST(&p->iofhd);
926 assert(aior != NULL);
927 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
932 breq = &aior->io_req;
933 breq->br_offset = lba + done;
934 iovcnt = hdr->prdtl - seek;
935 if (iovcnt > BLOCKIF_IOV_MAX) {
936 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
937 iovcnt = BLOCKIF_IOV_MAX;
940 breq->br_iovcnt = iovcnt;
943 * Build up the iovec based on the prdt
945 for (i = 0; i < iovcnt; i++) {
948 dbcsz = (prdt->dbc & DBCMASK) + 1;
949 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
951 breq->br_iov[i].iov_len = dbcsz;
955 err = blockif_read(p->bctx, breq);
960 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
968 if (len > sizeof(buf))
971 buf[0] = 0x70 | (1 << 7);
972 buf[2] = p->sense_key;
975 write_prdt(p, slot, cfis, buf, len);
976 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
977 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
981 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
983 uint8_t *acmd = cfis + 0x40;
986 switch (acmd[4] & 3) {
990 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
991 tfd = ATA_S_READY | ATA_S_DSC;
994 /* TODO eject media */
995 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
996 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
998 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1001 ahci_write_fis_d2h(p, slot, cfis, tfd);
1005 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1013 len = be16dec(acmd + 7);
1015 code = acmd[2] & 0x3f;
1020 case MODEPAGE_RW_ERROR_RECOVERY:
1024 if (len > sizeof(buf))
1027 memset(buf, 0, sizeof(buf));
1028 be16enc(buf, 16 - 2);
1033 write_prdt(p, slot, cfis, buf, len);
1034 tfd = ATA_S_READY | ATA_S_DSC;
1037 case MODEPAGE_CD_CAPABILITIES:
1041 if (len > sizeof(buf))
1044 memset(buf, 0, sizeof(buf));
1045 be16enc(buf, 30 - 2);
1051 be16enc(&buf[18], 2);
1052 be16enc(&buf[20], 512);
1053 write_prdt(p, slot, cfis, buf, len);
1054 tfd = ATA_S_READY | ATA_S_DSC;
1063 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1065 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1070 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1072 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1075 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1076 ahci_write_fis_d2h(p, slot, cfis, tfd);
1080 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1088 /* we don't support asynchronous operation */
1089 if (!(acmd[1] & 1)) {
1090 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1092 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1097 len = be16dec(acmd + 7);
1098 if (len > sizeof(buf))
1101 memset(buf, 0, sizeof(buf));
1102 be16enc(buf, 8 - 2);
1106 write_prdt(p, slot, cfis, buf, len);
1107 tfd = ATA_S_READY | ATA_S_DSC;
1109 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1110 ahci_write_fis_d2h(p, slot, cfis, tfd);
1114 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1124 for (i = 0; i < 16; i++)
1125 DPRINTF("%02x ", acmd[i]);
1131 case TEST_UNIT_READY:
1132 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1133 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1136 atapi_inquiry(p, slot, cfis);
1139 atapi_read_capacity(p, slot, cfis);
1143 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1144 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1147 atapi_read_toc(p, slot, cfis);
1151 atapi_read(p, slot, cfis, 0, 0);
1154 atapi_request_sense(p, slot, cfis);
1156 case START_STOP_UNIT:
1157 atapi_start_stop_unit(p, slot, cfis);
1160 atapi_mode_sense(p, slot, cfis);
1162 case GET_EVENT_STATUS_NOTIFICATION:
1163 atapi_get_event_status_notification(p, slot, cfis);
1166 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1167 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1169 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1170 ATA_S_READY | ATA_S_ERROR);
1176 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1180 case ATA_ATA_IDENTIFY:
1181 handle_identify(p, slot, cfis);
1183 case ATA_SETFEATURES:
1186 case ATA_SF_ENAB_SATA_SF:
1188 case ATA_SATA_SF_AN:
1189 p->tfd = ATA_S_DSC | ATA_S_READY;
1192 p->tfd = ATA_S_ERROR | ATA_S_READY;
1193 p->tfd |= (ATA_ERROR_ABORT << 8);
1197 case ATA_SF_ENAB_WCACHE:
1198 case ATA_SF_DIS_WCACHE:
1199 case ATA_SF_ENAB_RCACHE:
1200 case ATA_SF_DIS_RCACHE:
1201 p->tfd = ATA_S_DSC | ATA_S_READY;
1203 case ATA_SF_SETXFER:
1205 switch (cfis[12] & 0xf8) {
1211 p->xfermode = (cfis[12] & 0x7);
1214 p->tfd = ATA_S_DSC | ATA_S_READY;
1218 p->tfd = ATA_S_ERROR | ATA_S_READY;
1219 p->tfd |= (ATA_ERROR_ABORT << 8);
1222 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1226 if (cfis[12] != 0 &&
1227 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1228 p->tfd = ATA_S_ERROR | ATA_S_READY;
1229 p->tfd |= (ATA_ERROR_ABORT << 8);
1231 p->mult_sectors = cfis[12];
1232 p->tfd = ATA_S_DSC | ATA_S_READY;
1234 p->is |= AHCI_P_IX_DP;
1235 p->ci &= ~(1 << slot);
1236 ahci_generate_intr(p->pr_sc);
1240 case ATA_READ_DMA48:
1241 case ATA_WRITE_DMA48:
1242 case ATA_READ_FPDMA_QUEUED:
1243 case ATA_WRITE_FPDMA_QUEUED:
1244 ahci_handle_dma(p, slot, cfis, 0, 0);
1246 case ATA_FLUSHCACHE:
1247 case ATA_FLUSHCACHE48:
1248 ahci_handle_flush(p, slot, cfis);
1250 case ATA_STANDBY_CMD:
1253 case ATA_STANDBY_IMMEDIATE:
1254 case ATA_IDLE_IMMEDIATE:
1256 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1258 case ATA_ATAPI_IDENTIFY:
1259 handle_atapi_identify(p, slot, cfis);
1261 case ATA_PACKET_CMD:
1263 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1264 p->is |= AHCI_P_IX_TFE;
1265 p->ci &= ~(1 << slot);
1266 ahci_generate_intr(p->pr_sc);
1268 handle_packet_cmd(p, slot, cfis);
1271 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1272 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1273 p->is |= AHCI_P_IX_TFE;
1274 p->ci &= ~(1 << slot);
1275 ahci_generate_intr(p->pr_sc);
1281 ahci_handle_slot(struct ahci_port *p, int slot)
1283 struct ahci_cmd_hdr *hdr;
1284 struct ahci_prdt_entry *prdt;
1285 struct pci_ahci_softc *sc;
1290 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1291 cfl = (hdr->flags & 0x1f) * 4;
1292 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1293 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1294 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1298 for (i = 0; i < cfl; i++) {
1301 DPRINTF("%02x ", cfis[i]);
1305 for (i = 0; i < hdr->prdtl; i++) {
1306 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1311 if (cfis[0] != FIS_TYPE_REGH2D) {
1312 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1316 if (cfis[1] & 0x80) {
1317 ahci_handle_cmd(p, slot, cfis);
1319 if (cfis[15] & (1 << 2))
1321 else if (p->reset) {
1325 p->ci &= ~(1 << slot);
1330 ahci_handle_port(struct ahci_port *p)
1334 if (!(p->cmd & AHCI_P_CMD_ST))
1338 * Search for any new commands to issue ignoring those that
1339 * are already in-flight.
1341 for (i = 0; (i < 32) && p->ci; i++) {
1342 if ((p->ci & (1 << i)) && !(p->pending & (1 << i)))
1343 ahci_handle_slot(p, i);
1348 * blockif callback routine - this runs in the context of the blockif
1349 * i/o thread, so the mutex needs to be acquired.
1352 ata_ioreq_cb(struct blockif_req *br, int err)
1354 struct ahci_cmd_hdr *hdr;
1355 struct ahci_ioreq *aior;
1356 struct ahci_port *p;
1357 struct pci_ahci_softc *sc;
1360 int pending, slot, ncq;
1362 DPRINTF("%s %d\n", __func__, err);
1365 aior = br->br_param;
1369 pending = aior->prdtl;
1371 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1373 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1374 cfis[2] == ATA_READ_FPDMA_QUEUED)
1377 pthread_mutex_lock(&sc->mtx);
1380 * Move the blockif request back to the free list
1382 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1384 if (pending && !err) {
1385 ahci_handle_dma(p, slot, cfis, aior->done,
1386 hdr->prdtl - pending);
1390 if (!err && aior->done == aior->len) {
1391 tfd = ATA_S_READY | ATA_S_DSC;
1395 hdr->prdbc = aior->len;
1397 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1400 p->serr |= (1 << slot);
1404 * This command is now complete.
1406 p->pending &= ~(1 << slot);
1409 p->sact &= ~(1 << slot);
1410 ahci_write_fis_sdb(p, slot, tfd);
1412 ahci_write_fis_d2h(p, slot, cfis, tfd);
1415 pthread_mutex_unlock(&sc->mtx);
1416 DPRINTF("%s exit\n", __func__);
1420 atapi_ioreq_cb(struct blockif_req *br, int err)
1422 struct ahci_cmd_hdr *hdr;
1423 struct ahci_ioreq *aior;
1424 struct ahci_port *p;
1425 struct pci_ahci_softc *sc;
1430 DPRINTF("%s %d\n", __func__, err);
1432 aior = br->br_param;
1436 pending = aior->prdtl;
1438 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1440 pthread_mutex_lock(&sc->mtx);
1443 * Move the blockif request back to the free list
1445 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1447 if (pending && !err) {
1448 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1452 if (!err && aior->done == aior->len) {
1453 tfd = ATA_S_READY | ATA_S_DSC;
1454 hdr->prdbc = aior->len;
1456 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1458 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1462 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1463 ahci_write_fis_d2h(p, slot, cfis, tfd);
1466 pthread_mutex_unlock(&sc->mtx);
1467 DPRINTF("%s exit\n", __func__);
1471 pci_ahci_ioreq_init(struct ahci_port *pr)
1473 struct ahci_ioreq *vr;
1476 pr->ioqsz = blockif_queuesz(pr->bctx);
1477 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1478 STAILQ_INIT(&pr->iofhd);
1481 * Add all i/o request entries to the free queue
1483 for (i = 0; i < pr->ioqsz; i++) {
1487 vr->io_req.br_callback = ata_ioreq_cb;
1489 vr->io_req.br_callback = atapi_ioreq_cb;
1490 vr->io_req.br_param = vr;
1491 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list);
1496 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1498 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1499 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1500 struct ahci_port *p = &sc->port[port];
1502 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1503 port, offset, value);
1522 p->ie = value & 0xFDC000FF;
1523 ahci_generate_intr(sc);
1529 if (!(value & AHCI_P_CMD_ST)) {
1530 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
1536 p->cmd |= AHCI_P_CMD_CR;
1537 clb = (uint64_t)p->clbu << 32 | p->clb;
1538 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1539 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1542 if (value & AHCI_P_CMD_FRE) {
1545 p->cmd |= AHCI_P_CMD_FR;
1546 fb = (uint64_t)p->fbu << 32 | p->fb;
1547 /* we don't support FBSCP, so rfis size is 256Bytes */
1548 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1550 p->cmd &= ~AHCI_P_CMD_FR;
1553 if (value & AHCI_P_CMD_CLO) {
1555 p->cmd &= ~AHCI_P_CMD_CLO;
1558 ahci_handle_port(p);
1564 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1567 if (!(p->cmd & AHCI_P_CMD_ST)) {
1568 if (value & ATA_SC_DET_RESET)
1581 ahci_handle_port(p);
1591 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1593 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1601 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1604 if (value & AHCI_GHC_HR)
1606 else if (value & AHCI_GHC_IE) {
1607 sc->ghc |= AHCI_GHC_IE;
1608 ahci_generate_intr(sc);
1613 ahci_generate_intr(sc);
1621 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1622 int baridx, uint64_t offset, int size, uint64_t value)
1624 struct pci_ahci_softc *sc = pi->pi_arg;
1626 assert(baridx == 5);
1629 pthread_mutex_lock(&sc->mtx);
1631 if (offset < AHCI_OFFSET)
1632 pci_ahci_host_write(sc, offset, value);
1633 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1634 pci_ahci_port_write(sc, offset, value);
1636 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1638 pthread_mutex_unlock(&sc->mtx);
1642 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1658 uint32_t *p = &sc->cap;
1659 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1667 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1674 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1677 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1678 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1698 uint32_t *p= &sc->port[port].clb;
1699 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1708 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1709 port, offset, value);
1715 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1716 uint64_t offset, int size)
1718 struct pci_ahci_softc *sc = pi->pi_arg;
1721 assert(baridx == 5);
1724 pthread_mutex_lock(&sc->mtx);
1726 if (offset < AHCI_OFFSET)
1727 value = pci_ahci_host_read(sc, offset);
1728 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1729 value = pci_ahci_port_read(sc, offset);
1732 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1735 pthread_mutex_unlock(&sc->mtx);
1741 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1743 char bident[sizeof("XX:X:X")];
1744 struct blockif_ctxt *bctxt;
1745 struct pci_ahci_softc *sc;
1751 fprintf(stderr, "pci_ahci: backing device required\n");
1756 dbg = fopen("/tmp/log", "w+");
1759 sc = malloc(sizeof(struct pci_ahci_softc));
1760 memset(sc, 0, sizeof(struct pci_ahci_softc));
1763 sc->ports = MAX_PORTS;
1766 * Only use port 0 for a backing device. All other ports will be
1769 sc->port[0].atapi = atapi;
1772 * Attempt to open the backing image. Use the PCI
1773 * slot/func for the identifier string.
1775 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
1776 bctxt = blockif_open(opts, bident);
1777 if (bctxt == NULL) {
1781 sc->port[0].bctx = bctxt;
1782 sc->port[0].pr_sc = sc;
1785 * Allocate blockif request structures and add them
1788 pci_ahci_ioreq_init(&sc->port[0]);
1790 pthread_mutex_init(&sc->mtx, NULL);
1792 /* Intel ICH8 AHCI */
1793 slots = sc->port[0].ioqsz;
1797 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1798 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1799 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1800 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1801 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1803 /* Only port 0 implemented */
1806 sc->cap2 = AHCI_CAP2_APST;
1809 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1810 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1811 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1812 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1813 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1814 pci_emul_add_msicap(pi, 1);
1815 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1816 AHCI_OFFSET + sc->ports * AHCI_STEP);
1820 blockif_close(sc->port[0].bctx);
1828 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1831 return (pci_ahci_init(ctx, pi, opts, 0));
1835 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1838 return (pci_ahci_init(ctx, pi, opts, 1));
1842 * Use separate emulation names to distinguish drive and atapi devices
1844 struct pci_devemu pci_de_ahci_hd = {
1845 .pe_emu = "ahci-hd",
1846 .pe_init = pci_ahci_hd_init,
1847 .pe_barwrite = pci_ahci_write,
1848 .pe_barread = pci_ahci_read
1850 PCI_EMUL_SET(pci_de_ahci_hd);
1852 struct pci_devemu pci_de_ahci_cd = {
1853 .pe_emu = "ahci-cd",
1854 .pe_init = pci_ahci_atapi_init,
1855 .pe_barwrite = pci_ahci_write,
1856 .pe_barread = pci_ahci_read
1858 PCI_EMUL_SET(pci_de_ahci_cd);