2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
51 #include <pthread_np.h>
59 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
61 #define PxSIG_ATA 0x00000101 /* ATA drive */
62 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
78 #define TEST_UNIT_READY 0x00
79 #define REQUEST_SENSE 0x03
81 #define START_STOP_UNIT 0x1B
82 #define PREVENT_ALLOW 0x1E
83 #define READ_CAPACITY 0x25
85 #define POSITION_TO_ELEMENT 0x2B
87 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
88 #define MODE_SENSE_10 0x5A
93 * SCSI mode page codes
95 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
96 #define MODEPAGE_CD_CAPABILITIES 0x2A
101 #define ATA_SF_ENAB_SATA_SF 0x10
102 #define ATA_SATA_SF_AN 0x05
103 #define ATA_SF_DIS_SATA_SF 0x90
110 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
112 #define DPRINTF(format, arg...)
114 #define WPRINTF(format, arg...) printf(format, ##arg)
117 struct blockif_req io_req;
118 struct ahci_port *io_pr;
119 STAILQ_ENTRY(ahci_ioreq) io_flist;
120 TAILQ_ENTRY(ahci_ioreq) io_blist;
129 struct blockif_ctxt *bctx;
130 struct pci_ahci_softc *pr_sc;
137 uint8_t err_cfis[20];
163 struct ahci_ioreq *ioreq;
165 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
166 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
169 struct ahci_cmd_hdr {
174 uint32_t reserved[4];
177 struct ahci_prdt_entry {
180 #define DBCMASK 0x3fffff
184 struct pci_ahci_softc {
185 struct pci_devinst *asc_pi;
200 struct ahci_port port[MAX_PORTS];
202 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
204 static inline void lba_to_msf(uint8_t *buf, int lba)
207 buf[0] = (lba / 75) / 60;
208 buf[1] = (lba / 75) % 60;
213 * generate HBA intr depending on whether or not ports within
214 * the controller have an interrupt pending.
217 ahci_generate_intr(struct pci_ahci_softc *sc)
219 struct pci_devinst *pi;
224 for (i = 0; i < sc->ports; i++) {
225 struct ahci_port *pr;
231 DPRINTF("%s %x\n", __func__, sc->is);
233 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
234 if (pci_msi_enabled(pi)) {
236 * Generate an MSI interrupt on every edge
238 pci_generate_msi(pi, 0);
239 } else if (!sc->lintr) {
241 * Only generate a pin-based interrupt if one wasn't
245 pci_lintr_assert(pi);
247 } else if (sc->lintr) {
249 * No interrupts: deassert pin-based signal if it had
252 pci_lintr_deassert(pi);
258 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
260 int offset, len, irq;
262 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
266 case FIS_TYPE_REGD2H:
271 case FIS_TYPE_SETDEVBITS:
276 case FIS_TYPE_PIOSETUP:
282 WPRINTF("unsupported fis type %d\n", ft);
285 memcpy(p->rfis + offset, fis, len);
288 ahci_generate_intr(p->pr_sc);
293 ahci_write_fis_piosetup(struct ahci_port *p)
297 memset(fis, 0, sizeof(fis));
298 fis[0] = FIS_TYPE_PIOSETUP;
299 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
303 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
308 error = (tfd >> 8) & 0xff;
309 memset(fis, 0, sizeof(fis));
310 fis[0] = FIS_TYPE_SETDEVBITS;
314 if (fis[2] & ATA_S_ERROR) {
315 p->is |= AHCI_P_IX_TFE;
316 p->err_cfis[0] = slot;
317 p->err_cfis[2] = tfd & 0x77;
318 p->err_cfis[3] = error;
319 memcpy(&p->err_cfis[4], cfis + 4, 16);
321 *(uint32_t *)(fis + 4) = (1 << slot);
322 p->sact &= ~(1 << slot);
325 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
329 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
334 error = (tfd >> 8) & 0xff;
335 memset(fis, 0, sizeof(fis));
336 fis[0] = FIS_TYPE_REGD2H;
350 if (fis[2] & ATA_S_ERROR) {
351 p->is |= AHCI_P_IX_TFE;
352 p->err_cfis[0] = 0x80;
353 p->err_cfis[2] = tfd & 0xff;
354 p->err_cfis[3] = error;
355 memcpy(&p->err_cfis[4], cfis + 4, 16);
357 p->ci &= ~(1 << slot);
359 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
363 ahci_write_reset_fis_d2h(struct ahci_port *p)
367 memset(fis, 0, sizeof(fis));
368 fis[0] = FIS_TYPE_REGD2H;
376 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
380 ahci_check_stopped(struct ahci_port *p)
383 * If we are no longer processing the command list and nothing
384 * is in-flight, clear the running bit, the current command
385 * slot, the command issue and active bits.
387 if (!(p->cmd & AHCI_P_CMD_ST)) {
388 if (p->pending == 0) {
389 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
397 ahci_port_stop(struct ahci_port *p)
399 struct ahci_ioreq *aior;
405 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
407 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
409 * Try to cancel the outstanding blockif request.
411 error = blockif_cancel(p->bctx, &aior->io_req);
417 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
418 cfis[2] == ATA_READ_FPDMA_QUEUED)
422 p->sact &= ~(1 << slot);
424 p->ci &= ~(1 << slot);
427 * This command is now done.
429 p->pending &= ~(1 << slot);
432 * Delete the blockif request from the busy list
434 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
437 * Move the blockif request back to the free list
439 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
442 ahci_check_stopped(p);
446 ahci_port_reset(struct ahci_port *pr)
450 pr->xfermode = ATA_UDMA6;
451 pr->mult_sectors = 128;
454 pr->ssts = ATA_SS_DET_NO_DEVICE;
455 pr->sig = 0xFFFFFFFF;
459 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
460 if (pr->sctl & ATA_SC_SPD_MASK)
461 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
463 pr->ssts |= ATA_SS_SPD_GEN3;
464 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
467 pr->tfd |= ATA_S_READY;
469 pr->sig = PxSIG_ATAPI;
470 ahci_write_reset_fis_d2h(pr);
474 ahci_reset(struct pci_ahci_softc *sc)
478 sc->ghc = AHCI_GHC_AE;
482 pci_lintr_deassert(sc->asc_pi);
486 for (i = 0; i < sc->ports; i++) {
489 sc->port[i].sctl = 0;
490 ahci_port_reset(&sc->port[i]);
495 ata_string(uint8_t *dest, const char *src, int len)
499 for (i = 0; i < len; i++) {
501 dest[i ^ 1] = *src++;
508 atapi_string(uint8_t *dest, const char *src, int len)
512 for (i = 0; i < len; i++) {
521 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
524 struct ahci_ioreq *aior;
525 struct blockif_req *breq;
526 struct pci_ahci_softc *sc;
527 struct ahci_prdt_entry *prdt;
528 struct ahci_cmd_hdr *hdr;
531 int i, err, iovcnt, ncq, readop;
534 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
535 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
540 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
541 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
542 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
543 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
546 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
547 cfis[2] == ATA_READ_FPDMA_QUEUED) {
548 lba = ((uint64_t)cfis[10] << 40) |
549 ((uint64_t)cfis[9] << 32) |
550 ((uint64_t)cfis[8] << 24) |
551 ((uint64_t)cfis[6] << 16) |
552 ((uint64_t)cfis[5] << 8) |
554 len = cfis[11] << 8 | cfis[3];
558 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
559 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
560 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
561 lba = ((uint64_t)cfis[10] << 40) |
562 ((uint64_t)cfis[9] << 32) |
563 ((uint64_t)cfis[8] << 24) |
564 ((uint64_t)cfis[6] << 16) |
565 ((uint64_t)cfis[5] << 8) |
567 len = cfis[13] << 8 | cfis[12];
571 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
572 (cfis[5] << 8) | cfis[4];
577 lba *= blockif_sectsz(p->bctx);
578 len *= blockif_sectsz(p->bctx);
581 * Pull request off free list
583 aior = STAILQ_FIRST(&p->iofhd);
584 assert(aior != NULL);
585 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
590 breq = &aior->io_req;
591 breq->br_offset = lba + done;
592 iovcnt = hdr->prdtl - seek;
593 if (iovcnt > BLOCKIF_IOV_MAX) {
594 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
595 iovcnt = BLOCKIF_IOV_MAX;
598 breq->br_iovcnt = iovcnt;
601 * Mark this command in-flight.
603 p->pending |= 1 << slot;
606 * Stuff request onto busy list
608 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
611 * Build up the iovec based on the prdt
613 for (i = 0; i < iovcnt; i++) {
616 dbcsz = (prdt->dbc & DBCMASK) + 1;
617 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
619 breq->br_iov[i].iov_len = dbcsz;
624 err = blockif_read(p->bctx, breq);
626 err = blockif_write(p->bctx, breq);
630 p->ci &= ~(1 << slot);
634 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
636 struct ahci_ioreq *aior;
637 struct blockif_req *breq;
641 * Pull request off free list
643 aior = STAILQ_FIRST(&p->iofhd);
644 assert(aior != NULL);
645 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
651 breq = &aior->io_req;
654 * Mark this command in-flight.
656 p->pending |= 1 << slot;
659 * Stuff request onto busy list
661 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
663 err = blockif_flush(p->bctx, breq);
668 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
671 struct ahci_cmd_hdr *hdr;
672 struct ahci_prdt_entry *prdt;
676 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
679 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
680 for (i = 0; i < hdr->prdtl && len; i++) {
685 dbcsz = (prdt->dbc & DBCMASK) + 1;
686 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
687 sublen = len < dbcsz ? len : dbcsz;
688 memcpy(to, ptr, sublen);
696 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
698 struct ahci_ioreq *aior;
699 struct blockif_req *breq;
706 len = (uint16_t)cfis[13] << 8 | cfis[12];
708 read_prdt(p, slot, cfis, buf, sizeof(buf));
712 elba = ((uint64_t)entry[5] << 40) |
713 ((uint64_t)entry[4] << 32) |
714 ((uint64_t)entry[3] << 24) |
715 ((uint64_t)entry[2] << 16) |
716 ((uint64_t)entry[1] << 8) |
718 elen = (uint16_t)entry[7] << 8 | entry[6];
722 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
723 p->pending &= ~(1 << slot);
724 ahci_check_stopped(p);
731 * Pull request off free list
733 aior = STAILQ_FIRST(&p->iofhd);
734 assert(aior != NULL);
735 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
742 breq = &aior->io_req;
743 breq->br_offset = elba * blockif_sectsz(p->bctx);
745 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx);
748 * Mark this command in-flight.
750 p->pending |= 1 << slot;
753 * Stuff request onto busy list
755 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
757 err = blockif_delete(p->bctx, breq);
762 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
765 struct ahci_cmd_hdr *hdr;
766 struct ahci_prdt_entry *prdt;
770 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
773 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
774 for (i = 0; i < hdr->prdtl && len; i++) {
779 dbcsz = (prdt->dbc & DBCMASK) + 1;
780 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
781 sublen = len < dbcsz ? len : dbcsz;
782 memcpy(ptr, from, sublen);
787 hdr->prdbc = size - len;
791 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
793 struct ahci_cmd_hdr *hdr;
796 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
797 if (p->atapi || hdr->prdtl == 0 || cfis[4] != 0x10 ||
798 cfis[5] != 0 || cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
799 ahci_write_fis_d2h(p, slot, cfis,
800 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
804 memset(buf, 0, sizeof(buf));
805 memcpy(buf, p->err_cfis, sizeof(p->err_cfis));
807 if (cfis[2] == ATA_READ_LOG_EXT)
808 ahci_write_fis_piosetup(p);
809 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
810 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
814 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
816 struct ahci_cmd_hdr *hdr;
818 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
819 if (p->atapi || hdr->prdtl == 0) {
820 ahci_write_fis_d2h(p, slot, cfis,
821 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
825 int sectsz, psectsz, psectoff, candelete, ro;
829 ro = blockif_is_ro(p->bctx);
830 candelete = blockif_candelete(p->bctx);
831 sectsz = blockif_sectsz(p->bctx);
832 sectors = blockif_size(p->bctx) / sectsz;
833 blockif_chs(p->bctx, &cyl, &heads, &sech);
834 blockif_psectsz(p->bctx, &psectsz, &psectoff);
835 memset(buf, 0, sizeof(buf));
840 /* TODO emulate different serial? */
841 ata_string((uint8_t *)(buf+10), "123456", 20);
842 ata_string((uint8_t *)(buf+23), "001", 8);
843 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
844 buf[47] = (0x8000 | 128);
846 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
848 buf[53] = (1 << 1 | 1 << 2);
850 buf[59] = (0x100 | p->mult_sectors);
851 if (sectors <= 0x0fffffff) {
853 buf[61] = (sectors >> 16);
859 if (p->xfermode & ATA_WDMA0)
860 buf[63] |= (1 << ((p->xfermode & 7) + 8));
868 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
872 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
873 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
874 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
875 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
877 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
878 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
879 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
880 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
883 if (p->xfermode & ATA_UDMA0)
884 buf[88] |= (1 << ((p->xfermode & 7) + 8));
885 buf[93] = (1 | 1 <<14);
887 buf[101] = (sectors >> 16);
888 buf[102] = (sectors >> 32);
889 buf[103] = (sectors >> 48);
890 if (candelete && !ro) {
891 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
893 buf[169] = ATA_SUPPORT_DSM_TRIM;
897 if (psectsz > sectsz) {
899 buf[106] |= ffsl(psectsz / sectsz) - 1;
900 buf[209] |= (psectoff / sectsz);
904 buf[117] = sectsz / 2;
905 buf[118] = ((sectsz / 2) >> 16);
907 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
908 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
910 ahci_write_fis_piosetup(p);
911 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
912 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
917 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
920 ahci_write_fis_d2h(p, slot, cfis,
921 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
925 memset(buf, 0, sizeof(buf));
926 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
927 /* TODO emulate different serial? */
928 ata_string((uint8_t *)(buf+10), "123456", 20);
929 ata_string((uint8_t *)(buf+23), "001", 8);
930 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
931 buf[49] = (1 << 9 | 1 << 8);
932 buf[50] = (1 << 14 | 1);
933 buf[53] = (1 << 2 | 1 << 1);
941 buf[76] = (1 << 2 | 1 << 1);
943 buf[80] = (0x1f << 4);
949 buf[88] = (1 << 14 | 0x7f);
950 ahci_write_fis_piosetup(p);
951 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
952 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
957 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
973 atapi_string(buf + 8, "BHYVE", 8);
974 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
975 atapi_string(buf + 32, "001", 4);
980 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
981 write_prdt(p, slot, cfis, buf, len);
982 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
986 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
991 sectors = blockif_size(p->bctx) / 2048;
992 be32enc(buf, sectors - 1);
993 be32enc(buf + 4, 2048);
994 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
995 write_prdt(p, slot, cfis, buf, sizeof(buf));
996 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1000 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1008 len = be16dec(acmd + 7);
1009 format = acmd[9] >> 6;
1015 uint8_t start_track, buf[20], *bp;
1017 msf = (acmd[1] >> 1) & 1;
1018 start_track = acmd[6];
1019 if (start_track > 1 && start_track != 0xaa) {
1021 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1023 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1024 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1025 ahci_write_fis_d2h(p, slot, cfis, tfd);
1031 if (start_track <= 1) {
1051 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1055 lba_to_msf(bp, sectors);
1058 be32enc(bp, sectors);
1062 be16enc(buf, size - 2);
1065 write_prdt(p, slot, cfis, buf, len);
1066 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1067 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1074 memset(buf, 0, sizeof(buf));
1078 if (len > sizeof(buf))
1080 write_prdt(p, slot, cfis, buf, len);
1081 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1082 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1089 uint8_t start_track, *bp, buf[50];
1091 msf = (acmd[1] >> 1) & 1;
1092 start_track = acmd[6];
1128 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1132 lba_to_msf(bp, sectors);
1135 be32enc(bp, sectors);
1158 be16enc(buf, size - 2);
1161 write_prdt(p, slot, cfis, buf, len);
1162 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1163 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1170 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1172 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1173 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1174 ahci_write_fis_d2h(p, slot, cfis, tfd);
1181 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
1182 uint32_t done, int seek)
1184 struct ahci_ioreq *aior;
1185 struct ahci_cmd_hdr *hdr;
1186 struct ahci_prdt_entry *prdt;
1187 struct blockif_req *breq;
1188 struct pci_ahci_softc *sc;
1196 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1197 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1200 lba = be32dec(acmd + 2);
1201 if (acmd[0] == READ_10)
1202 len = be16dec(acmd + 7);
1204 len = be32dec(acmd + 6);
1206 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1207 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1213 * Pull request off free list
1215 aior = STAILQ_FIRST(&p->iofhd);
1216 assert(aior != NULL);
1217 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1222 breq = &aior->io_req;
1223 breq->br_offset = lba + done;
1224 iovcnt = hdr->prdtl - seek;
1225 if (iovcnt > BLOCKIF_IOV_MAX) {
1226 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
1227 iovcnt = BLOCKIF_IOV_MAX;
1230 breq->br_iovcnt = iovcnt;
1233 * Mark this command in-flight.
1235 p->pending |= 1 << slot;
1238 * Stuff request onto busy list
1240 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1243 * Build up the iovec based on the prdt
1245 for (i = 0; i < iovcnt; i++) {
1248 dbcsz = (prdt->dbc & DBCMASK) + 1;
1249 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
1251 breq->br_iov[i].iov_len = dbcsz;
1252 aior->done += dbcsz;
1255 err = blockif_read(p->bctx, breq);
1260 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1268 if (len > sizeof(buf))
1270 memset(buf, 0, len);
1271 buf[0] = 0x70 | (1 << 7);
1272 buf[2] = p->sense_key;
1275 write_prdt(p, slot, cfis, buf, len);
1276 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1277 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1281 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1283 uint8_t *acmd = cfis + 0x40;
1286 switch (acmd[4] & 3) {
1290 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1291 tfd = ATA_S_READY | ATA_S_DSC;
1294 /* TODO eject media */
1295 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1296 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1298 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1301 ahci_write_fis_d2h(p, slot, cfis, tfd);
1305 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1313 len = be16dec(acmd + 7);
1315 code = acmd[2] & 0x3f;
1320 case MODEPAGE_RW_ERROR_RECOVERY:
1324 if (len > sizeof(buf))
1327 memset(buf, 0, sizeof(buf));
1328 be16enc(buf, 16 - 2);
1333 write_prdt(p, slot, cfis, buf, len);
1334 tfd = ATA_S_READY | ATA_S_DSC;
1337 case MODEPAGE_CD_CAPABILITIES:
1341 if (len > sizeof(buf))
1344 memset(buf, 0, sizeof(buf));
1345 be16enc(buf, 30 - 2);
1351 be16enc(&buf[18], 2);
1352 be16enc(&buf[20], 512);
1353 write_prdt(p, slot, cfis, buf, len);
1354 tfd = ATA_S_READY | ATA_S_DSC;
1363 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1365 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1370 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1372 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1375 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1376 ahci_write_fis_d2h(p, slot, cfis, tfd);
1380 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1388 /* we don't support asynchronous operation */
1389 if (!(acmd[1] & 1)) {
1390 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1392 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1397 len = be16dec(acmd + 7);
1398 if (len > sizeof(buf))
1401 memset(buf, 0, sizeof(buf));
1402 be16enc(buf, 8 - 2);
1406 write_prdt(p, slot, cfis, buf, len);
1407 tfd = ATA_S_READY | ATA_S_DSC;
1409 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1410 ahci_write_fis_d2h(p, slot, cfis, tfd);
1414 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1424 for (i = 0; i < 16; i++)
1425 DPRINTF("%02x ", acmd[i]);
1431 case TEST_UNIT_READY:
1432 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1433 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1436 atapi_inquiry(p, slot, cfis);
1439 atapi_read_capacity(p, slot, cfis);
1443 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1444 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1447 atapi_read_toc(p, slot, cfis);
1451 atapi_read(p, slot, cfis, 0, 0);
1454 atapi_request_sense(p, slot, cfis);
1456 case START_STOP_UNIT:
1457 atapi_start_stop_unit(p, slot, cfis);
1460 atapi_mode_sense(p, slot, cfis);
1462 case GET_EVENT_STATUS_NOTIFICATION:
1463 atapi_get_event_status_notification(p, slot, cfis);
1466 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1467 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1469 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1470 ATA_S_READY | ATA_S_ERROR);
1476 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1480 case ATA_ATA_IDENTIFY:
1481 handle_identify(p, slot, cfis);
1483 case ATA_SETFEATURES:
1486 case ATA_SF_ENAB_SATA_SF:
1488 case ATA_SATA_SF_AN:
1489 p->tfd = ATA_S_DSC | ATA_S_READY;
1492 p->tfd = ATA_S_ERROR | ATA_S_READY;
1493 p->tfd |= (ATA_ERROR_ABORT << 8);
1497 case ATA_SF_ENAB_WCACHE:
1498 case ATA_SF_DIS_WCACHE:
1499 case ATA_SF_ENAB_RCACHE:
1500 case ATA_SF_DIS_RCACHE:
1501 p->tfd = ATA_S_DSC | ATA_S_READY;
1503 case ATA_SF_SETXFER:
1505 switch (cfis[12] & 0xf8) {
1511 p->xfermode = (cfis[12] & 0x7);
1514 p->tfd = ATA_S_DSC | ATA_S_READY;
1518 p->tfd = ATA_S_ERROR | ATA_S_READY;
1519 p->tfd |= (ATA_ERROR_ABORT << 8);
1522 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1526 if (cfis[12] != 0 &&
1527 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1528 p->tfd = ATA_S_ERROR | ATA_S_READY;
1529 p->tfd |= (ATA_ERROR_ABORT << 8);
1531 p->mult_sectors = cfis[12];
1532 p->tfd = ATA_S_DSC | ATA_S_READY;
1534 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1542 case ATA_READ_MUL48:
1543 case ATA_WRITE_MUL48:
1546 case ATA_READ_DMA48:
1547 case ATA_WRITE_DMA48:
1548 case ATA_READ_FPDMA_QUEUED:
1549 case ATA_WRITE_FPDMA_QUEUED:
1550 ahci_handle_dma(p, slot, cfis, 0, 0);
1552 case ATA_FLUSHCACHE:
1553 case ATA_FLUSHCACHE48:
1554 ahci_handle_flush(p, slot, cfis);
1556 case ATA_DATA_SET_MANAGEMENT:
1557 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1558 cfis[13] == 0 && cfis[12] == 1) {
1559 ahci_handle_dsm_trim(p, slot, cfis, 0);
1562 ahci_write_fis_d2h(p, slot, cfis,
1563 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1565 case ATA_READ_LOG_EXT:
1566 case ATA_READ_LOG_DMA_EXT:
1567 ahci_handle_read_log(p, slot, cfis);
1569 case ATA_STANDBY_CMD:
1572 case ATA_STANDBY_IMMEDIATE:
1573 case ATA_IDLE_IMMEDIATE:
1575 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1577 case ATA_ATAPI_IDENTIFY:
1578 handle_atapi_identify(p, slot, cfis);
1580 case ATA_PACKET_CMD:
1582 ahci_write_fis_d2h(p, slot, cfis,
1583 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1585 handle_packet_cmd(p, slot, cfis);
1588 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1589 ahci_write_fis_d2h(p, slot, cfis,
1590 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1596 ahci_handle_slot(struct ahci_port *p, int slot)
1598 struct ahci_cmd_hdr *hdr;
1599 struct ahci_prdt_entry *prdt;
1600 struct pci_ahci_softc *sc;
1605 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1606 cfl = (hdr->flags & 0x1f) * 4;
1607 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1608 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1609 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1613 for (i = 0; i < cfl; i++) {
1616 DPRINTF("%02x ", cfis[i]);
1620 for (i = 0; i < hdr->prdtl; i++) {
1621 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1626 if (cfis[0] != FIS_TYPE_REGH2D) {
1627 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1631 if (cfis[1] & 0x80) {
1632 ahci_handle_cmd(p, slot, cfis);
1634 if (cfis[15] & (1 << 2))
1636 else if (p->reset) {
1640 p->ci &= ~(1 << slot);
1645 ahci_handle_port(struct ahci_port *p)
1649 if (!(p->cmd & AHCI_P_CMD_ST))
1653 * Search for any new commands to issue ignoring those that
1654 * are already in-flight.
1656 for (i = 0; (i < 32) && p->ci; i++) {
1657 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1658 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1659 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1660 ahci_handle_slot(p, i);
1666 * blockif callback routine - this runs in the context of the blockif
1667 * i/o thread, so the mutex needs to be acquired.
1670 ata_ioreq_cb(struct blockif_req *br, int err)
1672 struct ahci_cmd_hdr *hdr;
1673 struct ahci_ioreq *aior;
1674 struct ahci_port *p;
1675 struct pci_ahci_softc *sc;
1678 int pending, slot, ncq, dsm;
1680 DPRINTF("%s %d\n", __func__, err);
1683 aior = br->br_param;
1687 pending = aior->prdtl;
1689 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1691 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1692 cfis[2] == ATA_READ_FPDMA_QUEUED)
1694 if (cfis[2] == ATA_DATA_SET_MANAGEMENT)
1697 pthread_mutex_lock(&sc->mtx);
1700 * Delete the blockif request from the busy list
1702 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1705 * Move the blockif request back to the free list
1707 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1710 hdr->prdbc = aior->done;
1713 if (aior->done != aior->len && !err) {
1714 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1718 if (pending && !err) {
1719 ahci_handle_dma(p, slot, cfis, aior->done,
1720 hdr->prdtl - pending);
1725 if (!err && aior->done == aior->len) {
1726 tfd = ATA_S_READY | ATA_S_DSC;
1728 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1732 ahci_write_fis_sdb(p, slot, cfis, tfd);
1734 ahci_write_fis_d2h(p, slot, cfis, tfd);
1737 * This command is now complete.
1739 p->pending &= ~(1 << slot);
1741 ahci_check_stopped(p);
1743 pthread_mutex_unlock(&sc->mtx);
1744 DPRINTF("%s exit\n", __func__);
1748 atapi_ioreq_cb(struct blockif_req *br, int err)
1750 struct ahci_cmd_hdr *hdr;
1751 struct ahci_ioreq *aior;
1752 struct ahci_port *p;
1753 struct pci_ahci_softc *sc;
1758 DPRINTF("%s %d\n", __func__, err);
1760 aior = br->br_param;
1764 pending = aior->prdtl;
1766 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1768 pthread_mutex_lock(&sc->mtx);
1771 * Delete the blockif request from the busy list
1773 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1776 * Move the blockif request back to the free list
1778 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1781 hdr->prdbc = aior->done;
1783 if (pending && !err) {
1784 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1788 if (!err && aior->done == aior->len) {
1789 tfd = ATA_S_READY | ATA_S_DSC;
1791 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1793 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1796 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1797 ahci_write_fis_d2h(p, slot, cfis, tfd);
1800 * This command is now complete.
1802 p->pending &= ~(1 << slot);
1804 ahci_check_stopped(p);
1806 pthread_mutex_unlock(&sc->mtx);
1807 DPRINTF("%s exit\n", __func__);
1811 pci_ahci_ioreq_init(struct ahci_port *pr)
1813 struct ahci_ioreq *vr;
1816 pr->ioqsz = blockif_queuesz(pr->bctx);
1817 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1818 STAILQ_INIT(&pr->iofhd);
1821 * Add all i/o request entries to the free queue
1823 for (i = 0; i < pr->ioqsz; i++) {
1827 vr->io_req.br_callback = ata_ioreq_cb;
1829 vr->io_req.br_callback = atapi_ioreq_cb;
1830 vr->io_req.br_param = vr;
1831 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
1834 TAILQ_INIT(&pr->iobhd);
1838 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1840 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1841 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1842 struct ahci_port *p = &sc->port[port];
1844 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1845 port, offset, value);
1864 p->ie = value & 0xFDC000FF;
1865 ahci_generate_intr(sc);
1871 if (!(value & AHCI_P_CMD_ST)) {
1876 p->cmd |= AHCI_P_CMD_CR;
1877 clb = (uint64_t)p->clbu << 32 | p->clb;
1878 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1879 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1882 if (value & AHCI_P_CMD_FRE) {
1885 p->cmd |= AHCI_P_CMD_FR;
1886 fb = (uint64_t)p->fbu << 32 | p->fb;
1887 /* we don't support FBSCP, so rfis size is 256Bytes */
1888 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1890 p->cmd &= ~AHCI_P_CMD_FR;
1893 if (value & AHCI_P_CMD_CLO) {
1895 p->cmd &= ~AHCI_P_CMD_CLO;
1898 ahci_handle_port(p);
1904 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1908 if (!(p->cmd & AHCI_P_CMD_ST)) {
1909 if (value & ATA_SC_DET_RESET)
1921 ahci_handle_port(p);
1931 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1933 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1941 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1944 if (value & AHCI_GHC_HR)
1946 else if (value & AHCI_GHC_IE) {
1947 sc->ghc |= AHCI_GHC_IE;
1948 ahci_generate_intr(sc);
1953 ahci_generate_intr(sc);
1961 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1962 int baridx, uint64_t offset, int size, uint64_t value)
1964 struct pci_ahci_softc *sc = pi->pi_arg;
1966 assert(baridx == 5);
1969 pthread_mutex_lock(&sc->mtx);
1971 if (offset < AHCI_OFFSET)
1972 pci_ahci_host_write(sc, offset, value);
1973 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1974 pci_ahci_port_write(sc, offset, value);
1976 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1978 pthread_mutex_unlock(&sc->mtx);
1982 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1998 uint32_t *p = &sc->cap;
1999 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2007 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
2014 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2017 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2018 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2038 uint32_t *p= &sc->port[port].clb;
2039 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2048 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
2049 port, offset, value);
2055 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2056 uint64_t offset, int size)
2058 struct pci_ahci_softc *sc = pi->pi_arg;
2061 assert(baridx == 5);
2064 pthread_mutex_lock(&sc->mtx);
2066 if (offset < AHCI_OFFSET)
2067 value = pci_ahci_host_read(sc, offset);
2068 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2069 value = pci_ahci_port_read(sc, offset);
2072 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
2075 pthread_mutex_unlock(&sc->mtx);
2081 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2083 char bident[sizeof("XX:X:X")];
2084 struct blockif_ctxt *bctxt;
2085 struct pci_ahci_softc *sc;
2091 fprintf(stderr, "pci_ahci: backing device required\n");
2096 dbg = fopen("/tmp/log", "w+");
2099 sc = calloc(1, sizeof(struct pci_ahci_softc));
2102 sc->ports = MAX_PORTS;
2105 * Only use port 0 for a backing device. All other ports will be
2108 sc->port[0].atapi = atapi;
2111 * Attempt to open the backing image. Use the PCI
2112 * slot/func for the identifier string.
2114 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
2115 bctxt = blockif_open(opts, bident);
2116 if (bctxt == NULL) {
2120 sc->port[0].bctx = bctxt;
2121 sc->port[0].pr_sc = sc;
2124 * Allocate blockif request structures and add them
2127 pci_ahci_ioreq_init(&sc->port[0]);
2129 pthread_mutex_init(&sc->mtx, NULL);
2131 /* Intel ICH8 AHCI */
2132 slots = sc->port[0].ioqsz;
2136 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2137 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2138 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2139 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2140 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2142 /* Only port 0 implemented */
2145 sc->cap2 = AHCI_CAP2_APST;
2148 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2149 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2150 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2151 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2152 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2153 pci_emul_add_msicap(pi, 1);
2154 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2155 AHCI_OFFSET + sc->ports * AHCI_STEP);
2157 pci_lintr_request(pi);
2161 blockif_close(sc->port[0].bctx);
2169 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2172 return (pci_ahci_init(ctx, pi, opts, 0));
2176 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2179 return (pci_ahci_init(ctx, pi, opts, 1));
2183 * Use separate emulation names to distinguish drive and atapi devices
2185 struct pci_devemu pci_de_ahci_hd = {
2186 .pe_emu = "ahci-hd",
2187 .pe_init = pci_ahci_hd_init,
2188 .pe_barwrite = pci_ahci_write,
2189 .pe_barread = pci_ahci_read
2191 PCI_EMUL_SET(pci_de_ahci_hd);
2193 struct pci_devemu pci_de_ahci_cd = {
2194 .pe_emu = "ahci-cd",
2195 .pe_init = pci_ahci_atapi_init,
2196 .pe_barwrite = pci_ahci_write,
2197 .pe_barread = pci_ahci_read
2199 PCI_EMUL_SET(pci_de_ahci_cd);