2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
51 #include <pthread_np.h>
59 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
61 #define PxSIG_ATA 0x00000101 /* ATA drive */
62 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
78 #define TEST_UNIT_READY 0x00
79 #define REQUEST_SENSE 0x03
81 #define START_STOP_UNIT 0x1B
82 #define PREVENT_ALLOW 0x1E
83 #define READ_CAPACITY 0x25
85 #define POSITION_TO_ELEMENT 0x2B
87 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
88 #define MODE_SENSE_10 0x5A
93 * SCSI mode page codes
95 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
96 #define MODEPAGE_CD_CAPABILITIES 0x2A
101 #define ATA_SF_ENAB_SATA_SF 0x10
102 #define ATA_SATA_SF_AN 0x05
103 #define ATA_SF_DIS_SATA_SF 0x90
110 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
112 #define DPRINTF(format, arg...)
114 #define WPRINTF(format, arg...) printf(format, ##arg)
117 struct blockif_req io_req;
118 struct ahci_port *io_pr;
119 STAILQ_ENTRY(ahci_ioreq) io_flist;
120 TAILQ_ENTRY(ahci_ioreq) io_blist;
129 struct blockif_ctxt *bctx;
130 struct pci_ahci_softc *pr_sc;
162 struct ahci_ioreq *ioreq;
164 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
165 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
168 struct ahci_cmd_hdr {
173 uint32_t reserved[4];
176 struct ahci_prdt_entry {
179 #define DBCMASK 0x3fffff
183 struct pci_ahci_softc {
184 struct pci_devinst *asc_pi;
199 struct ahci_port port[MAX_PORTS];
201 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
203 static inline void lba_to_msf(uint8_t *buf, int lba)
206 buf[0] = (lba / 75) / 60;
207 buf[1] = (lba / 75) % 60;
212 * generate HBA intr depending on whether or not ports within
213 * the controller have an interrupt pending.
216 ahci_generate_intr(struct pci_ahci_softc *sc)
218 struct pci_devinst *pi;
223 for (i = 0; i < sc->ports; i++) {
224 struct ahci_port *pr;
230 DPRINTF("%s %x\n", __func__, sc->is);
232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
233 if (pci_msi_enabled(pi)) {
235 * Generate an MSI interrupt on every edge
237 pci_generate_msi(pi, 0);
238 } else if (!sc->lintr) {
240 * Only generate a pin-based interrupt if one wasn't
244 pci_lintr_assert(pi);
246 } else if (sc->lintr) {
248 * No interrupts: deassert pin-based signal if it had
251 pci_lintr_deassert(pi);
257 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
259 int offset, len, irq;
261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
265 case FIS_TYPE_REGD2H:
270 case FIS_TYPE_SETDEVBITS:
275 case FIS_TYPE_PIOSETUP:
281 WPRINTF("unsupported fis type %d\n", ft);
284 memcpy(p->rfis + offset, fis, len);
287 ahci_generate_intr(p->pr_sc);
292 ahci_write_fis_piosetup(struct ahci_port *p)
296 memset(fis, 0, sizeof(fis));
297 fis[0] = FIS_TYPE_PIOSETUP;
298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
302 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
307 error = (tfd >> 8) & 0xff;
308 memset(fis, 0, sizeof(fis));
311 *(uint32_t *)(fis + 4) = (1 << slot);
312 if (fis[2] & ATA_S_ERROR)
313 p->is |= AHCI_P_IX_TFE;
315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
319 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
324 error = (tfd >> 8) & 0xff;
325 memset(fis, 0, sizeof(fis));
326 fis[0] = FIS_TYPE_REGD2H;
340 if (fis[2] & ATA_S_ERROR)
341 p->is |= AHCI_P_IX_TFE;
343 p->ci &= ~(1 << slot);
345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
349 ahci_write_reset_fis_d2h(struct ahci_port *p)
353 memset(fis, 0, sizeof(fis));
354 fis[0] = FIS_TYPE_REGD2H;
362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
366 ahci_check_stopped(struct ahci_port *p)
369 * If we are no longer processing the command list and nothing
370 * is in-flight, clear the running bit, the current command
371 * slot, the command issue and active bits.
373 if (!(p->cmd & AHCI_P_CMD_ST)) {
374 if (p->pending == 0) {
375 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
383 ahci_port_stop(struct ahci_port *p)
385 struct ahci_ioreq *aior;
391 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
393 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
395 * Try to cancel the outstanding blockif request.
397 error = blockif_cancel(p->bctx, &aior->io_req);
403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
404 cfis[2] == ATA_READ_FPDMA_QUEUED)
408 p->sact &= ~(1 << slot);
410 p->ci &= ~(1 << slot);
413 * This command is now done.
415 p->pending &= ~(1 << slot);
418 * Delete the blockif request from the busy list
420 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
423 * Move the blockif request back to the free list
425 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
428 ahci_check_stopped(p);
432 ahci_port_reset(struct ahci_port *pr)
437 pr->xfermode = ATA_UDMA6;
438 pr->mult_sectors = 128;
441 pr->ssts = ATA_SS_DET_NO_DEVICE;
442 pr->sig = 0xFFFFFFFF;
446 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
448 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
451 pr->tfd |= ATA_S_READY;
453 pr->sig = PxSIG_ATAPI;
454 ahci_write_reset_fis_d2h(pr);
458 ahci_reset(struct pci_ahci_softc *sc)
462 sc->ghc = AHCI_GHC_AE;
466 pci_lintr_deassert(sc->asc_pi);
470 for (i = 0; i < sc->ports; i++) {
473 ahci_port_reset(&sc->port[i]);
478 ata_string(uint8_t *dest, const char *src, int len)
482 for (i = 0; i < len; i++) {
484 dest[i ^ 1] = *src++;
491 atapi_string(uint8_t *dest, const char *src, int len)
495 for (i = 0; i < len; i++) {
504 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
507 struct ahci_ioreq *aior;
508 struct blockif_req *breq;
509 struct pci_ahci_softc *sc;
510 struct ahci_prdt_entry *prdt;
511 struct ahci_cmd_hdr *hdr;
514 int i, err, iovcnt, ncq, readop;
517 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
518 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
523 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
524 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
525 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
526 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
529 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
530 cfis[2] == ATA_READ_FPDMA_QUEUED) {
531 lba = ((uint64_t)cfis[10] << 40) |
532 ((uint64_t)cfis[9] << 32) |
533 ((uint64_t)cfis[8] << 24) |
534 ((uint64_t)cfis[6] << 16) |
535 ((uint64_t)cfis[5] << 8) |
537 len = cfis[11] << 8 | cfis[3];
541 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
542 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
543 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
544 lba = ((uint64_t)cfis[10] << 40) |
545 ((uint64_t)cfis[9] << 32) |
546 ((uint64_t)cfis[8] << 24) |
547 ((uint64_t)cfis[6] << 16) |
548 ((uint64_t)cfis[5] << 8) |
550 len = cfis[13] << 8 | cfis[12];
554 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
555 (cfis[5] << 8) | cfis[4];
560 lba *= blockif_sectsz(p->bctx);
561 len *= blockif_sectsz(p->bctx);
564 * Pull request off free list
566 aior = STAILQ_FIRST(&p->iofhd);
567 assert(aior != NULL);
568 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
573 breq = &aior->io_req;
574 breq->br_offset = lba + done;
575 iovcnt = hdr->prdtl - seek;
576 if (iovcnt > BLOCKIF_IOV_MAX) {
577 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
578 iovcnt = BLOCKIF_IOV_MAX;
581 breq->br_iovcnt = iovcnt;
584 * Mark this command in-flight.
586 p->pending |= 1 << slot;
589 * Stuff request onto busy list
591 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
594 * Build up the iovec based on the prdt
596 for (i = 0; i < iovcnt; i++) {
599 dbcsz = (prdt->dbc & DBCMASK) + 1;
600 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
602 breq->br_iov[i].iov_len = dbcsz;
607 err = blockif_read(p->bctx, breq);
609 err = blockif_write(p->bctx, breq);
613 p->ci &= ~(1 << slot);
617 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
619 struct ahci_ioreq *aior;
620 struct blockif_req *breq;
624 * Pull request off free list
626 aior = STAILQ_FIRST(&p->iofhd);
627 assert(aior != NULL);
628 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
634 breq = &aior->io_req;
637 * Mark this command in-flight.
639 p->pending |= 1 << slot;
642 * Stuff request onto busy list
644 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
646 err = blockif_flush(p->bctx, breq);
651 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
654 struct ahci_cmd_hdr *hdr;
655 struct ahci_prdt_entry *prdt;
659 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
662 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
663 for (i = 0; i < hdr->prdtl && len; i++) {
668 dbcsz = (prdt->dbc & DBCMASK) + 1;
669 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
670 sublen = len < dbcsz ? len : dbcsz;
671 memcpy(to, ptr, sublen);
679 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
681 struct ahci_ioreq *aior;
682 struct blockif_req *breq;
689 len = (uint16_t)cfis[13] << 8 | cfis[12];
691 read_prdt(p, slot, cfis, buf, sizeof(buf));
695 elba = ((uint64_t)entry[5] << 40) |
696 ((uint64_t)entry[4] << 32) |
697 ((uint64_t)entry[3] << 24) |
698 ((uint64_t)entry[2] << 16) |
699 ((uint64_t)entry[1] << 8) |
701 elen = (uint16_t)entry[7] << 8 | entry[6];
705 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
706 p->pending &= ~(1 << slot);
707 ahci_check_stopped(p);
714 * Pull request off free list
716 aior = STAILQ_FIRST(&p->iofhd);
717 assert(aior != NULL);
718 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
725 breq = &aior->io_req;
726 breq->br_offset = elba * blockif_sectsz(p->bctx);
728 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx);
731 * Mark this command in-flight.
733 p->pending |= 1 << slot;
736 * Stuff request onto busy list
738 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
740 err = blockif_delete(p->bctx, breq);
745 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
748 struct ahci_cmd_hdr *hdr;
749 struct ahci_prdt_entry *prdt;
753 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
756 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
757 for (i = 0; i < hdr->prdtl && len; i++) {
762 dbcsz = (prdt->dbc & DBCMASK) + 1;
763 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
764 sublen = len < dbcsz ? len : dbcsz;
765 memcpy(ptr, from, sublen);
770 hdr->prdbc = size - len;
774 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
776 struct ahci_cmd_hdr *hdr;
778 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
779 if (p->atapi || hdr->prdtl == 0) {
780 ahci_write_fis_d2h(p, slot, cfis,
781 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
785 int sectsz, psectsz, psectoff, candelete, ro;
789 ro = blockif_is_ro(p->bctx);
790 candelete = blockif_candelete(p->bctx);
791 sectsz = blockif_sectsz(p->bctx);
792 sectors = blockif_size(p->bctx) / sectsz;
793 blockif_chs(p->bctx, &cyl, &heads, &sech);
794 blockif_psectsz(p->bctx, &psectsz, &psectoff);
795 memset(buf, 0, sizeof(buf));
800 /* TODO emulate different serial? */
801 ata_string((uint8_t *)(buf+10), "123456", 20);
802 ata_string((uint8_t *)(buf+23), "001", 8);
803 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
804 buf[47] = (0x8000 | 128);
806 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
808 buf[53] = (1 << 1 | 1 << 2);
810 buf[59] = (0x100 | p->mult_sectors);
812 buf[61] = (sectors >> 16);
814 if (p->xfermode & ATA_WDMA0)
815 buf[63] |= (1 << ((p->xfermode & 7) + 8));
823 buf[76] = (1 << 8 | 1 << 2);
826 buf[82] = (1 << 5 | 1 << 14);
827 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
829 buf[85] = (1 << 5 | 1 << 14);
830 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
833 if (p->xfermode & ATA_UDMA0)
834 buf[88] |= (1 << ((p->xfermode & 7) + 8));
835 buf[93] = (1 | 1 <<14);
837 buf[101] = (sectors >> 16);
838 buf[102] = (sectors >> 32);
839 buf[103] = (sectors >> 48);
840 if (candelete && !ro) {
841 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
843 buf[169] = ATA_SUPPORT_DSM_TRIM;
847 if (psectsz > sectsz) {
849 buf[106] |= ffsl(psectsz / sectsz) - 1;
850 buf[209] |= (psectoff / sectsz);
854 buf[117] = sectsz / 2;
855 buf[118] = ((sectsz / 2) >> 16);
857 ahci_write_fis_piosetup(p);
858 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
859 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
864 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
867 ahci_write_fis_d2h(p, slot, cfis,
868 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
872 memset(buf, 0, sizeof(buf));
873 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
874 /* TODO emulate different serial? */
875 ata_string((uint8_t *)(buf+10), "123456", 20);
876 ata_string((uint8_t *)(buf+23), "001", 8);
877 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
878 buf[49] = (1 << 9 | 1 << 8);
879 buf[50] = (1 << 14 | 1);
880 buf[53] = (1 << 2 | 1 << 1);
888 buf[76] = (1 << 2 | 1 << 1);
890 buf[80] = (0x1f << 4);
896 buf[88] = (1 << 14 | 0x7f);
897 ahci_write_fis_piosetup(p);
898 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
899 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
904 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
920 atapi_string(buf + 8, "BHYVE", 8);
921 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
922 atapi_string(buf + 32, "001", 4);
927 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
928 write_prdt(p, slot, cfis, buf, len);
929 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
933 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
938 sectors = blockif_size(p->bctx) / 2048;
939 be32enc(buf, sectors - 1);
940 be32enc(buf + 4, 2048);
941 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
942 write_prdt(p, slot, cfis, buf, sizeof(buf));
943 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
947 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
955 len = be16dec(acmd + 7);
956 format = acmd[9] >> 6;
962 uint8_t start_track, buf[20], *bp;
964 msf = (acmd[1] >> 1) & 1;
965 start_track = acmd[6];
966 if (start_track > 1 && start_track != 0xaa) {
968 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
970 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
971 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
972 ahci_write_fis_d2h(p, slot, cfis, tfd);
978 if (start_track <= 1) {
998 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1002 lba_to_msf(bp, sectors);
1005 be32enc(bp, sectors);
1009 be16enc(buf, size - 2);
1012 write_prdt(p, slot, cfis, buf, len);
1013 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1014 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1021 memset(buf, 0, sizeof(buf));
1025 if (len > sizeof(buf))
1027 write_prdt(p, slot, cfis, buf, len);
1028 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1029 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1036 uint8_t start_track, *bp, buf[50];
1038 msf = (acmd[1] >> 1) & 1;
1039 start_track = acmd[6];
1075 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1079 lba_to_msf(bp, sectors);
1082 be32enc(bp, sectors);
1105 be16enc(buf, size - 2);
1108 write_prdt(p, slot, cfis, buf, len);
1109 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1110 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1117 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1119 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1120 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1121 ahci_write_fis_d2h(p, slot, cfis, tfd);
1128 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
1129 uint32_t done, int seek)
1131 struct ahci_ioreq *aior;
1132 struct ahci_cmd_hdr *hdr;
1133 struct ahci_prdt_entry *prdt;
1134 struct blockif_req *breq;
1135 struct pci_ahci_softc *sc;
1143 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1144 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1147 lba = be32dec(acmd + 2);
1148 if (acmd[0] == READ_10)
1149 len = be16dec(acmd + 7);
1151 len = be32dec(acmd + 6);
1153 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1154 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1160 * Pull request off free list
1162 aior = STAILQ_FIRST(&p->iofhd);
1163 assert(aior != NULL);
1164 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1169 breq = &aior->io_req;
1170 breq->br_offset = lba + done;
1171 iovcnt = hdr->prdtl - seek;
1172 if (iovcnt > BLOCKIF_IOV_MAX) {
1173 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
1174 iovcnt = BLOCKIF_IOV_MAX;
1177 breq->br_iovcnt = iovcnt;
1180 * Mark this command in-flight.
1182 p->pending |= 1 << slot;
1185 * Stuff request onto busy list
1187 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1190 * Build up the iovec based on the prdt
1192 for (i = 0; i < iovcnt; i++) {
1195 dbcsz = (prdt->dbc & DBCMASK) + 1;
1196 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
1198 breq->br_iov[i].iov_len = dbcsz;
1199 aior->done += dbcsz;
1202 err = blockif_read(p->bctx, breq);
1207 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1215 if (len > sizeof(buf))
1217 memset(buf, 0, len);
1218 buf[0] = 0x70 | (1 << 7);
1219 buf[2] = p->sense_key;
1222 write_prdt(p, slot, cfis, buf, len);
1223 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1224 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1228 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1230 uint8_t *acmd = cfis + 0x40;
1233 switch (acmd[4] & 3) {
1237 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1238 tfd = ATA_S_READY | ATA_S_DSC;
1241 /* TODO eject media */
1242 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1243 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1245 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1248 ahci_write_fis_d2h(p, slot, cfis, tfd);
1252 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1260 len = be16dec(acmd + 7);
1262 code = acmd[2] & 0x3f;
1267 case MODEPAGE_RW_ERROR_RECOVERY:
1271 if (len > sizeof(buf))
1274 memset(buf, 0, sizeof(buf));
1275 be16enc(buf, 16 - 2);
1280 write_prdt(p, slot, cfis, buf, len);
1281 tfd = ATA_S_READY | ATA_S_DSC;
1284 case MODEPAGE_CD_CAPABILITIES:
1288 if (len > sizeof(buf))
1291 memset(buf, 0, sizeof(buf));
1292 be16enc(buf, 30 - 2);
1298 be16enc(&buf[18], 2);
1299 be16enc(&buf[20], 512);
1300 write_prdt(p, slot, cfis, buf, len);
1301 tfd = ATA_S_READY | ATA_S_DSC;
1310 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1312 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1317 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1319 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1322 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1323 ahci_write_fis_d2h(p, slot, cfis, tfd);
1327 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1335 /* we don't support asynchronous operation */
1336 if (!(acmd[1] & 1)) {
1337 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1339 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1344 len = be16dec(acmd + 7);
1345 if (len > sizeof(buf))
1348 memset(buf, 0, sizeof(buf));
1349 be16enc(buf, 8 - 2);
1353 write_prdt(p, slot, cfis, buf, len);
1354 tfd = ATA_S_READY | ATA_S_DSC;
1356 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1357 ahci_write_fis_d2h(p, slot, cfis, tfd);
1361 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1371 for (i = 0; i < 16; i++)
1372 DPRINTF("%02x ", acmd[i]);
1378 case TEST_UNIT_READY:
1379 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1380 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1383 atapi_inquiry(p, slot, cfis);
1386 atapi_read_capacity(p, slot, cfis);
1390 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1391 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1394 atapi_read_toc(p, slot, cfis);
1398 atapi_read(p, slot, cfis, 0, 0);
1401 atapi_request_sense(p, slot, cfis);
1403 case START_STOP_UNIT:
1404 atapi_start_stop_unit(p, slot, cfis);
1407 atapi_mode_sense(p, slot, cfis);
1409 case GET_EVENT_STATUS_NOTIFICATION:
1410 atapi_get_event_status_notification(p, slot, cfis);
1413 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1414 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1416 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1417 ATA_S_READY | ATA_S_ERROR);
1423 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1427 case ATA_ATA_IDENTIFY:
1428 handle_identify(p, slot, cfis);
1430 case ATA_SETFEATURES:
1433 case ATA_SF_ENAB_SATA_SF:
1435 case ATA_SATA_SF_AN:
1436 p->tfd = ATA_S_DSC | ATA_S_READY;
1439 p->tfd = ATA_S_ERROR | ATA_S_READY;
1440 p->tfd |= (ATA_ERROR_ABORT << 8);
1444 case ATA_SF_ENAB_WCACHE:
1445 case ATA_SF_DIS_WCACHE:
1446 case ATA_SF_ENAB_RCACHE:
1447 case ATA_SF_DIS_RCACHE:
1448 p->tfd = ATA_S_DSC | ATA_S_READY;
1450 case ATA_SF_SETXFER:
1452 switch (cfis[12] & 0xf8) {
1458 p->xfermode = (cfis[12] & 0x7);
1461 p->tfd = ATA_S_DSC | ATA_S_READY;
1465 p->tfd = ATA_S_ERROR | ATA_S_READY;
1466 p->tfd |= (ATA_ERROR_ABORT << 8);
1469 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1473 if (cfis[12] != 0 &&
1474 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1475 p->tfd = ATA_S_ERROR | ATA_S_READY;
1476 p->tfd |= (ATA_ERROR_ABORT << 8);
1478 p->mult_sectors = cfis[12];
1479 p->tfd = ATA_S_DSC | ATA_S_READY;
1481 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1489 case ATA_READ_MUL48:
1490 case ATA_WRITE_MUL48:
1493 case ATA_READ_DMA48:
1494 case ATA_WRITE_DMA48:
1495 case ATA_READ_FPDMA_QUEUED:
1496 case ATA_WRITE_FPDMA_QUEUED:
1497 ahci_handle_dma(p, slot, cfis, 0, 0);
1499 case ATA_FLUSHCACHE:
1500 case ATA_FLUSHCACHE48:
1501 ahci_handle_flush(p, slot, cfis);
1503 case ATA_DATA_SET_MANAGEMENT:
1504 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1505 cfis[13] == 0 && cfis[12] == 1) {
1506 ahci_handle_dsm_trim(p, slot, cfis, 0);
1509 ahci_write_fis_d2h(p, slot, cfis,
1510 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1512 case ATA_STANDBY_CMD:
1515 case ATA_STANDBY_IMMEDIATE:
1516 case ATA_IDLE_IMMEDIATE:
1518 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1520 case ATA_ATAPI_IDENTIFY:
1521 handle_atapi_identify(p, slot, cfis);
1523 case ATA_PACKET_CMD:
1525 ahci_write_fis_d2h(p, slot, cfis,
1526 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1528 handle_packet_cmd(p, slot, cfis);
1531 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1532 ahci_write_fis_d2h(p, slot, cfis,
1533 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1539 ahci_handle_slot(struct ahci_port *p, int slot)
1541 struct ahci_cmd_hdr *hdr;
1542 struct ahci_prdt_entry *prdt;
1543 struct pci_ahci_softc *sc;
1548 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1549 cfl = (hdr->flags & 0x1f) * 4;
1550 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1551 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1552 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1556 for (i = 0; i < cfl; i++) {
1559 DPRINTF("%02x ", cfis[i]);
1563 for (i = 0; i < hdr->prdtl; i++) {
1564 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1569 if (cfis[0] != FIS_TYPE_REGH2D) {
1570 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1574 if (cfis[1] & 0x80) {
1575 ahci_handle_cmd(p, slot, cfis);
1577 if (cfis[15] & (1 << 2))
1579 else if (p->reset) {
1583 p->ci &= ~(1 << slot);
1588 ahci_handle_port(struct ahci_port *p)
1592 if (!(p->cmd & AHCI_P_CMD_ST))
1596 * Search for any new commands to issue ignoring those that
1597 * are already in-flight.
1599 for (i = 0; (i < 32) && p->ci; i++) {
1600 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1601 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1602 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1603 ahci_handle_slot(p, i);
1609 * blockif callback routine - this runs in the context of the blockif
1610 * i/o thread, so the mutex needs to be acquired.
1613 ata_ioreq_cb(struct blockif_req *br, int err)
1615 struct ahci_cmd_hdr *hdr;
1616 struct ahci_ioreq *aior;
1617 struct ahci_port *p;
1618 struct pci_ahci_softc *sc;
1621 int pending, slot, ncq, dsm;
1623 DPRINTF("%s %d\n", __func__, err);
1626 aior = br->br_param;
1630 pending = aior->prdtl;
1632 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1634 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1635 cfis[2] == ATA_READ_FPDMA_QUEUED)
1637 if (cfis[2] == ATA_DATA_SET_MANAGEMENT)
1640 pthread_mutex_lock(&sc->mtx);
1643 * Delete the blockif request from the busy list
1645 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1648 * Move the blockif request back to the free list
1650 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1653 if (aior->done != aior->len && !err) {
1654 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1658 if (pending && !err) {
1659 ahci_handle_dma(p, slot, cfis, aior->done,
1660 hdr->prdtl - pending);
1665 if (!err && aior->done == aior->len) {
1666 tfd = ATA_S_READY | ATA_S_DSC;
1670 hdr->prdbc = aior->len;
1672 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1675 p->serr |= (1 << slot);
1679 p->sact &= ~(1 << slot);
1680 ahci_write_fis_sdb(p, slot, tfd);
1682 ahci_write_fis_d2h(p, slot, cfis, tfd);
1685 * This command is now complete.
1687 p->pending &= ~(1 << slot);
1689 ahci_check_stopped(p);
1691 pthread_mutex_unlock(&sc->mtx);
1692 DPRINTF("%s exit\n", __func__);
1696 atapi_ioreq_cb(struct blockif_req *br, int err)
1698 struct ahci_cmd_hdr *hdr;
1699 struct ahci_ioreq *aior;
1700 struct ahci_port *p;
1701 struct pci_ahci_softc *sc;
1706 DPRINTF("%s %d\n", __func__, err);
1708 aior = br->br_param;
1712 pending = aior->prdtl;
1714 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1716 pthread_mutex_lock(&sc->mtx);
1719 * Delete the blockif request from the busy list
1721 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1724 * Move the blockif request back to the free list
1726 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1728 if (pending && !err) {
1729 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1733 if (!err && aior->done == aior->len) {
1734 tfd = ATA_S_READY | ATA_S_DSC;
1735 hdr->prdbc = aior->len;
1737 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1739 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1743 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1744 ahci_write_fis_d2h(p, slot, cfis, tfd);
1747 * This command is now complete.
1749 p->pending &= ~(1 << slot);
1751 ahci_check_stopped(p);
1753 pthread_mutex_unlock(&sc->mtx);
1754 DPRINTF("%s exit\n", __func__);
1758 pci_ahci_ioreq_init(struct ahci_port *pr)
1760 struct ahci_ioreq *vr;
1763 pr->ioqsz = blockif_queuesz(pr->bctx);
1764 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1765 STAILQ_INIT(&pr->iofhd);
1768 * Add all i/o request entries to the free queue
1770 for (i = 0; i < pr->ioqsz; i++) {
1774 vr->io_req.br_callback = ata_ioreq_cb;
1776 vr->io_req.br_callback = atapi_ioreq_cb;
1777 vr->io_req.br_param = vr;
1778 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
1781 TAILQ_INIT(&pr->iobhd);
1785 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1787 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1788 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1789 struct ahci_port *p = &sc->port[port];
1791 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1792 port, offset, value);
1811 p->ie = value & 0xFDC000FF;
1812 ahci_generate_intr(sc);
1818 if (!(value & AHCI_P_CMD_ST)) {
1823 p->cmd |= AHCI_P_CMD_CR;
1824 clb = (uint64_t)p->clbu << 32 | p->clb;
1825 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1826 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1829 if (value & AHCI_P_CMD_FRE) {
1832 p->cmd |= AHCI_P_CMD_FR;
1833 fb = (uint64_t)p->fbu << 32 | p->fb;
1834 /* we don't support FBSCP, so rfis size is 256Bytes */
1835 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1837 p->cmd &= ~AHCI_P_CMD_FR;
1840 if (value & AHCI_P_CMD_CLO) {
1842 p->cmd &= ~AHCI_P_CMD_CLO;
1845 ahci_handle_port(p);
1851 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1854 if (!(p->cmd & AHCI_P_CMD_ST)) {
1855 if (value & ATA_SC_DET_RESET)
1868 ahci_handle_port(p);
1878 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1880 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1888 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1891 if (value & AHCI_GHC_HR)
1893 else if (value & AHCI_GHC_IE) {
1894 sc->ghc |= AHCI_GHC_IE;
1895 ahci_generate_intr(sc);
1900 ahci_generate_intr(sc);
1908 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1909 int baridx, uint64_t offset, int size, uint64_t value)
1911 struct pci_ahci_softc *sc = pi->pi_arg;
1913 assert(baridx == 5);
1916 pthread_mutex_lock(&sc->mtx);
1918 if (offset < AHCI_OFFSET)
1919 pci_ahci_host_write(sc, offset, value);
1920 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1921 pci_ahci_port_write(sc, offset, value);
1923 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1925 pthread_mutex_unlock(&sc->mtx);
1929 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1945 uint32_t *p = &sc->cap;
1946 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1954 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1961 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1964 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1965 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1985 uint32_t *p= &sc->port[port].clb;
1986 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1995 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1996 port, offset, value);
2002 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2003 uint64_t offset, int size)
2005 struct pci_ahci_softc *sc = pi->pi_arg;
2008 assert(baridx == 5);
2011 pthread_mutex_lock(&sc->mtx);
2013 if (offset < AHCI_OFFSET)
2014 value = pci_ahci_host_read(sc, offset);
2015 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2016 value = pci_ahci_port_read(sc, offset);
2019 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
2022 pthread_mutex_unlock(&sc->mtx);
2028 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2030 char bident[sizeof("XX:X:X")];
2031 struct blockif_ctxt *bctxt;
2032 struct pci_ahci_softc *sc;
2038 fprintf(stderr, "pci_ahci: backing device required\n");
2043 dbg = fopen("/tmp/log", "w+");
2046 sc = calloc(1, sizeof(struct pci_ahci_softc));
2049 sc->ports = MAX_PORTS;
2052 * Only use port 0 for a backing device. All other ports will be
2055 sc->port[0].atapi = atapi;
2058 * Attempt to open the backing image. Use the PCI
2059 * slot/func for the identifier string.
2061 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
2062 bctxt = blockif_open(opts, bident);
2063 if (bctxt == NULL) {
2067 sc->port[0].bctx = bctxt;
2068 sc->port[0].pr_sc = sc;
2071 * Allocate blockif request structures and add them
2074 pci_ahci_ioreq_init(&sc->port[0]);
2076 pthread_mutex_init(&sc->mtx, NULL);
2078 /* Intel ICH8 AHCI */
2079 slots = sc->port[0].ioqsz;
2083 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2084 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2085 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2086 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2087 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2089 /* Only port 0 implemented */
2092 sc->cap2 = AHCI_CAP2_APST;
2095 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2096 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2097 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2098 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2099 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2100 pci_emul_add_msicap(pi, 1);
2101 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2102 AHCI_OFFSET + sc->ports * AHCI_STEP);
2104 pci_lintr_request(pi);
2108 blockif_close(sc->port[0].bctx);
2116 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2119 return (pci_ahci_init(ctx, pi, opts, 0));
2123 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2126 return (pci_ahci_init(ctx, pi, opts, 1));
2130 * Use separate emulation names to distinguish drive and atapi devices
2132 struct pci_devemu pci_de_ahci_hd = {
2133 .pe_emu = "ahci-hd",
2134 .pe_init = pci_ahci_hd_init,
2135 .pe_barwrite = pci_ahci_write,
2136 .pe_barread = pci_ahci_read
2138 PCI_EMUL_SET(pci_de_ahci_hd);
2140 struct pci_devemu pci_de_ahci_cd = {
2141 .pe_emu = "ahci-cd",
2142 .pe_init = pci_ahci_atapi_init,
2143 .pe_barwrite = pci_ahci_write,
2144 .pe_barread = pci_ahci_read
2146 PCI_EMUL_SET(pci_de_ahci_cd);