2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
51 #include <pthread_np.h>
59 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
61 #define PxSIG_ATA 0x00000101 /* ATA drive */
62 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
78 #define TEST_UNIT_READY 0x00
79 #define REQUEST_SENSE 0x03
81 #define START_STOP_UNIT 0x1B
82 #define PREVENT_ALLOW 0x1E
83 #define READ_CAPACITY 0x25
85 #define POSITION_TO_ELEMENT 0x2B
87 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
88 #define MODE_SENSE_10 0x5A
93 * SCSI mode page codes
95 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
96 #define MODEPAGE_CD_CAPABILITIES 0x2A
101 #define ATA_SF_ENAB_SATA_SF 0x10
102 #define ATA_SATA_SF_AN 0x05
103 #define ATA_SF_DIS_SATA_SF 0x90
110 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
112 #define DPRINTF(format, arg...)
114 #define WPRINTF(format, arg...) printf(format, ##arg)
117 struct blockif_req io_req;
118 struct ahci_port *io_pr;
119 STAILQ_ENTRY(ahci_ioreq) io_flist;
120 TAILQ_ENTRY(ahci_ioreq) io_blist;
129 struct blockif_ctxt *bctx;
130 struct pci_ahci_softc *pr_sc;
137 uint8_t err_cfis[20];
163 struct ahci_ioreq *ioreq;
165 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
166 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
169 struct ahci_cmd_hdr {
174 uint32_t reserved[4];
177 struct ahci_prdt_entry {
180 #define DBCMASK 0x3fffff
184 struct pci_ahci_softc {
185 struct pci_devinst *asc_pi;
200 struct ahci_port port[MAX_PORTS];
202 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
204 static inline void lba_to_msf(uint8_t *buf, int lba)
207 buf[0] = (lba / 75) / 60;
208 buf[1] = (lba / 75) % 60;
213 * generate HBA intr depending on whether or not ports within
214 * the controller have an interrupt pending.
217 ahci_generate_intr(struct pci_ahci_softc *sc)
219 struct pci_devinst *pi;
224 for (i = 0; i < sc->ports; i++) {
225 struct ahci_port *pr;
231 DPRINTF("%s %x\n", __func__, sc->is);
233 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
234 if (pci_msi_enabled(pi)) {
236 * Generate an MSI interrupt on every edge
238 pci_generate_msi(pi, 0);
239 } else if (!sc->lintr) {
241 * Only generate a pin-based interrupt if one wasn't
245 pci_lintr_assert(pi);
247 } else if (sc->lintr) {
249 * No interrupts: deassert pin-based signal if it had
252 pci_lintr_deassert(pi);
258 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
260 int offset, len, irq;
262 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
266 case FIS_TYPE_REGD2H:
271 case FIS_TYPE_SETDEVBITS:
276 case FIS_TYPE_PIOSETUP:
282 WPRINTF("unsupported fis type %d\n", ft);
285 memcpy(p->rfis + offset, fis, len);
288 ahci_generate_intr(p->pr_sc);
293 ahci_write_fis_piosetup(struct ahci_port *p)
297 memset(fis, 0, sizeof(fis));
298 fis[0] = FIS_TYPE_PIOSETUP;
299 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
303 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
308 error = (tfd >> 8) & 0xff;
309 memset(fis, 0, sizeof(fis));
310 fis[0] = FIS_TYPE_SETDEVBITS;
314 if (fis[2] & ATA_S_ERROR) {
315 p->is |= AHCI_P_IX_TFE;
316 p->err_cfis[0] = slot;
317 p->err_cfis[2] = tfd & 0x77;
318 p->err_cfis[3] = error;
319 memcpy(&p->err_cfis[4], cfis + 4, 16);
321 *(uint32_t *)(fis + 4) = (1 << slot);
322 p->sact &= ~(1 << slot);
325 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
329 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
334 error = (tfd >> 8) & 0xff;
335 memset(fis, 0, sizeof(fis));
336 fis[0] = FIS_TYPE_REGD2H;
350 if (fis[2] & ATA_S_ERROR) {
351 p->is |= AHCI_P_IX_TFE;
352 p->err_cfis[0] = 0x80;
353 p->err_cfis[2] = tfd & 0xff;
354 p->err_cfis[3] = error;
355 memcpy(&p->err_cfis[4], cfis + 4, 16);
357 p->ci &= ~(1 << slot);
359 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
363 ahci_write_reset_fis_d2h(struct ahci_port *p)
367 memset(fis, 0, sizeof(fis));
368 fis[0] = FIS_TYPE_REGD2H;
376 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
380 ahci_check_stopped(struct ahci_port *p)
383 * If we are no longer processing the command list and nothing
384 * is in-flight, clear the running bit, the current command
385 * slot, the command issue and active bits.
387 if (!(p->cmd & AHCI_P_CMD_ST)) {
388 if (p->pending == 0) {
389 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
397 ahci_port_stop(struct ahci_port *p)
399 struct ahci_ioreq *aior;
405 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
407 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
409 * Try to cancel the outstanding blockif request.
411 error = blockif_cancel(p->bctx, &aior->io_req);
417 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
418 cfis[2] == ATA_READ_FPDMA_QUEUED)
422 p->sact &= ~(1 << slot);
424 p->ci &= ~(1 << slot);
427 * This command is now done.
429 p->pending &= ~(1 << slot);
432 * Delete the blockif request from the busy list
434 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
437 * Move the blockif request back to the free list
439 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
442 ahci_check_stopped(p);
446 ahci_port_reset(struct ahci_port *pr)
450 pr->xfermode = ATA_UDMA6;
451 pr->mult_sectors = 128;
454 pr->ssts = ATA_SS_DET_NO_DEVICE;
455 pr->sig = 0xFFFFFFFF;
459 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
460 if (pr->sctl & ATA_SC_SPD_MASK)
461 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
463 pr->ssts |= ATA_SS_SPD_GEN3;
464 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
467 pr->tfd |= ATA_S_READY;
469 pr->sig = PxSIG_ATAPI;
470 ahci_write_reset_fis_d2h(pr);
474 ahci_reset(struct pci_ahci_softc *sc)
478 sc->ghc = AHCI_GHC_AE;
482 pci_lintr_deassert(sc->asc_pi);
486 for (i = 0; i < sc->ports; i++) {
489 sc->port[i].sctl = 0;
490 ahci_port_reset(&sc->port[i]);
495 ata_string(uint8_t *dest, const char *src, int len)
499 for (i = 0; i < len; i++) {
501 dest[i ^ 1] = *src++;
508 atapi_string(uint8_t *dest, const char *src, int len)
512 for (i = 0; i < len; i++) {
521 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
524 struct ahci_ioreq *aior;
525 struct blockif_req *breq;
526 struct pci_ahci_softc *sc;
527 struct ahci_prdt_entry *prdt;
528 struct ahci_cmd_hdr *hdr;
531 int i, err, iovcnt, ncq, readop;
534 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
535 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
540 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
541 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
542 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
543 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
546 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
547 cfis[2] == ATA_READ_FPDMA_QUEUED) {
548 lba = ((uint64_t)cfis[10] << 40) |
549 ((uint64_t)cfis[9] << 32) |
550 ((uint64_t)cfis[8] << 24) |
551 ((uint64_t)cfis[6] << 16) |
552 ((uint64_t)cfis[5] << 8) |
554 len = cfis[11] << 8 | cfis[3];
558 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
559 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
560 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
561 lba = ((uint64_t)cfis[10] << 40) |
562 ((uint64_t)cfis[9] << 32) |
563 ((uint64_t)cfis[8] << 24) |
564 ((uint64_t)cfis[6] << 16) |
565 ((uint64_t)cfis[5] << 8) |
567 len = cfis[13] << 8 | cfis[12];
571 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
572 (cfis[5] << 8) | cfis[4];
577 lba *= blockif_sectsz(p->bctx);
578 len *= blockif_sectsz(p->bctx);
581 * Pull request off free list
583 aior = STAILQ_FIRST(&p->iofhd);
584 assert(aior != NULL);
585 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
590 breq = &aior->io_req;
591 breq->br_offset = lba + done;
592 iovcnt = hdr->prdtl - seek;
593 if (iovcnt > BLOCKIF_IOV_MAX) {
594 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
595 iovcnt = BLOCKIF_IOV_MAX;
598 breq->br_iovcnt = iovcnt;
601 * Mark this command in-flight.
603 p->pending |= 1 << slot;
606 * Stuff request onto busy list
608 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
611 * Build up the iovec based on the prdt
613 for (i = 0; i < iovcnt; i++) {
616 dbcsz = (prdt->dbc & DBCMASK) + 1;
617 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
619 breq->br_iov[i].iov_len = dbcsz;
624 err = blockif_read(p->bctx, breq);
626 err = blockif_write(p->bctx, breq);
630 p->ci &= ~(1 << slot);
634 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
636 struct ahci_ioreq *aior;
637 struct blockif_req *breq;
641 * Pull request off free list
643 aior = STAILQ_FIRST(&p->iofhd);
644 assert(aior != NULL);
645 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
651 breq = &aior->io_req;
654 * Mark this command in-flight.
656 p->pending |= 1 << slot;
659 * Stuff request onto busy list
661 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
663 err = blockif_flush(p->bctx, breq);
668 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
671 struct ahci_cmd_hdr *hdr;
672 struct ahci_prdt_entry *prdt;
676 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
679 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
680 for (i = 0; i < hdr->prdtl && len; i++) {
685 dbcsz = (prdt->dbc & DBCMASK) + 1;
686 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
687 sublen = len < dbcsz ? len : dbcsz;
688 memcpy(to, ptr, sublen);
696 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
698 struct ahci_ioreq *aior;
699 struct blockif_req *breq;
706 if (cfis[2] == ATA_DATA_SET_MANAGEMENT) {
707 len = (uint16_t)cfis[13] << 8 | cfis[12];
709 } else { /* ATA_SEND_FPDMA_QUEUED */
710 len = (uint16_t)cfis[11] << 8 | cfis[3];
713 read_prdt(p, slot, cfis, buf, sizeof(buf));
717 elba = ((uint64_t)entry[5] << 40) |
718 ((uint64_t)entry[4] << 32) |
719 ((uint64_t)entry[3] << 24) |
720 ((uint64_t)entry[2] << 16) |
721 ((uint64_t)entry[1] << 8) |
723 elen = (uint16_t)entry[7] << 8 | entry[6];
727 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
728 p->pending &= ~(1 << slot);
729 ahci_check_stopped(p);
736 * Pull request off free list
738 aior = STAILQ_FIRST(&p->iofhd);
739 assert(aior != NULL);
740 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
747 breq = &aior->io_req;
748 breq->br_offset = elba * blockif_sectsz(p->bctx);
750 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx);
753 * Mark this command in-flight.
755 p->pending |= 1 << slot;
758 * Stuff request onto busy list
760 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
762 err = blockif_delete(p->bctx, breq);
767 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
770 struct ahci_cmd_hdr *hdr;
771 struct ahci_prdt_entry *prdt;
775 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
778 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
779 for (i = 0; i < hdr->prdtl && len; i++) {
784 dbcsz = (prdt->dbc & DBCMASK) + 1;
785 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
786 sublen = len < dbcsz ? len : dbcsz;
787 memcpy(ptr, from, sublen);
792 hdr->prdbc = size - len;
796 ahci_handle_read_log(struct ahci_port *p, int slot, uint8_t *cfis)
798 struct ahci_cmd_hdr *hdr;
801 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
802 if (p->atapi || hdr->prdtl == 0 || cfis[4] != 0x10 ||
803 cfis[5] != 0 || cfis[9] != 0 || cfis[12] != 1 || cfis[13] != 0) {
804 ahci_write_fis_d2h(p, slot, cfis,
805 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
809 memset(buf, 0, sizeof(buf));
810 memcpy(buf, p->err_cfis, sizeof(p->err_cfis));
812 if (cfis[2] == ATA_READ_LOG_EXT)
813 ahci_write_fis_piosetup(p);
814 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
815 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
819 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
821 struct ahci_cmd_hdr *hdr;
823 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
824 if (p->atapi || hdr->prdtl == 0) {
825 ahci_write_fis_d2h(p, slot, cfis,
826 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
830 int sectsz, psectsz, psectoff, candelete, ro;
834 ro = blockif_is_ro(p->bctx);
835 candelete = blockif_candelete(p->bctx);
836 sectsz = blockif_sectsz(p->bctx);
837 sectors = blockif_size(p->bctx) / sectsz;
838 blockif_chs(p->bctx, &cyl, &heads, &sech);
839 blockif_psectsz(p->bctx, &psectsz, &psectoff);
840 memset(buf, 0, sizeof(buf));
845 /* TODO emulate different serial? */
846 ata_string((uint8_t *)(buf+10), "123456", 20);
847 ata_string((uint8_t *)(buf+23), "001", 8);
848 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
849 buf[47] = (0x8000 | 128);
851 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
853 buf[53] = (1 << 1 | 1 << 2);
855 buf[59] = (0x100 | p->mult_sectors);
856 if (sectors <= 0x0fffffff) {
858 buf[61] = (sectors >> 16);
864 if (p->xfermode & ATA_WDMA0)
865 buf[63] |= (1 << ((p->xfermode & 7) + 8));
873 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
875 buf[77] = (ATA_SUPPORT_RCVSND_FPDMA_QUEUED |
876 (p->ssts & ATA_SS_SPD_MASK) >> 3);
879 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
880 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
881 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
882 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
884 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
885 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
886 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
887 ATA_SUPPORT_FLUSHCACHE48 | 1 << 15);
890 if (p->xfermode & ATA_UDMA0)
891 buf[88] |= (1 << ((p->xfermode & 7) + 8));
892 buf[93] = (1 | 1 <<14);
894 buf[101] = (sectors >> 16);
895 buf[102] = (sectors >> 32);
896 buf[103] = (sectors >> 48);
897 if (candelete && !ro) {
898 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
900 buf[169] = ATA_SUPPORT_DSM_TRIM;
904 if (psectsz > sectsz) {
906 buf[106] |= ffsl(psectsz / sectsz) - 1;
907 buf[209] |= (psectoff / sectsz);
911 buf[117] = sectsz / 2;
912 buf[118] = ((sectsz / 2) >> 16);
914 buf[119] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
915 buf[120] = (ATA_SUPPORT_RWLOGDMAEXT | 1 << 14);
917 ahci_write_fis_piosetup(p);
918 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
919 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
924 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
927 ahci_write_fis_d2h(p, slot, cfis,
928 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
932 memset(buf, 0, sizeof(buf));
933 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
934 /* TODO emulate different serial? */
935 ata_string((uint8_t *)(buf+10), "123456", 20);
936 ata_string((uint8_t *)(buf+23), "001", 8);
937 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
938 buf[49] = (1 << 9 | 1 << 8);
939 buf[50] = (1 << 14 | 1);
940 buf[53] = (1 << 2 | 1 << 1);
948 buf[76] = (1 << 2 | 1 << 1);
950 buf[80] = (0x1f << 4);
956 buf[88] = (1 << 14 | 0x7f);
957 ahci_write_fis_piosetup(p);
958 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
959 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
964 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
980 atapi_string(buf + 8, "BHYVE", 8);
981 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
982 atapi_string(buf + 32, "001", 4);
987 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
988 write_prdt(p, slot, cfis, buf, len);
989 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
993 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
998 sectors = blockif_size(p->bctx) / 2048;
999 be32enc(buf, sectors - 1);
1000 be32enc(buf + 4, 2048);
1001 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1002 write_prdt(p, slot, cfis, buf, sizeof(buf));
1003 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1007 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
1015 len = be16dec(acmd + 7);
1016 format = acmd[9] >> 6;
1022 uint8_t start_track, buf[20], *bp;
1024 msf = (acmd[1] >> 1) & 1;
1025 start_track = acmd[6];
1026 if (start_track > 1 && start_track != 0xaa) {
1028 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1030 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1031 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1032 ahci_write_fis_d2h(p, slot, cfis, tfd);
1038 if (start_track <= 1) {
1058 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1062 lba_to_msf(bp, sectors);
1065 be32enc(bp, sectors);
1069 be16enc(buf, size - 2);
1072 write_prdt(p, slot, cfis, buf, len);
1073 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1074 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1081 memset(buf, 0, sizeof(buf));
1085 if (len > sizeof(buf))
1087 write_prdt(p, slot, cfis, buf, len);
1088 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1089 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1096 uint8_t start_track, *bp, buf[50];
1098 msf = (acmd[1] >> 1) & 1;
1099 start_track = acmd[6];
1135 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1139 lba_to_msf(bp, sectors);
1142 be32enc(bp, sectors);
1165 be16enc(buf, size - 2);
1168 write_prdt(p, slot, cfis, buf, len);
1169 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1170 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1177 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1179 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1180 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1181 ahci_write_fis_d2h(p, slot, cfis, tfd);
1188 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
1189 uint32_t done, int seek)
1191 struct ahci_ioreq *aior;
1192 struct ahci_cmd_hdr *hdr;
1193 struct ahci_prdt_entry *prdt;
1194 struct blockif_req *breq;
1195 struct pci_ahci_softc *sc;
1203 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1204 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1207 lba = be32dec(acmd + 2);
1208 if (acmd[0] == READ_10)
1209 len = be16dec(acmd + 7);
1211 len = be32dec(acmd + 6);
1213 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1214 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1220 * Pull request off free list
1222 aior = STAILQ_FIRST(&p->iofhd);
1223 assert(aior != NULL);
1224 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1229 breq = &aior->io_req;
1230 breq->br_offset = lba + done;
1231 iovcnt = hdr->prdtl - seek;
1232 if (iovcnt > BLOCKIF_IOV_MAX) {
1233 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
1234 iovcnt = BLOCKIF_IOV_MAX;
1237 breq->br_iovcnt = iovcnt;
1240 * Mark this command in-flight.
1242 p->pending |= 1 << slot;
1245 * Stuff request onto busy list
1247 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1250 * Build up the iovec based on the prdt
1252 for (i = 0; i < iovcnt; i++) {
1255 dbcsz = (prdt->dbc & DBCMASK) + 1;
1256 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
1258 breq->br_iov[i].iov_len = dbcsz;
1259 aior->done += dbcsz;
1262 err = blockif_read(p->bctx, breq);
1267 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1275 if (len > sizeof(buf))
1277 memset(buf, 0, len);
1278 buf[0] = 0x70 | (1 << 7);
1279 buf[2] = p->sense_key;
1282 write_prdt(p, slot, cfis, buf, len);
1283 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1284 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1288 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1290 uint8_t *acmd = cfis + 0x40;
1293 switch (acmd[4] & 3) {
1297 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1298 tfd = ATA_S_READY | ATA_S_DSC;
1301 /* TODO eject media */
1302 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1303 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1305 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1308 ahci_write_fis_d2h(p, slot, cfis, tfd);
1312 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1320 len = be16dec(acmd + 7);
1322 code = acmd[2] & 0x3f;
1327 case MODEPAGE_RW_ERROR_RECOVERY:
1331 if (len > sizeof(buf))
1334 memset(buf, 0, sizeof(buf));
1335 be16enc(buf, 16 - 2);
1340 write_prdt(p, slot, cfis, buf, len);
1341 tfd = ATA_S_READY | ATA_S_DSC;
1344 case MODEPAGE_CD_CAPABILITIES:
1348 if (len > sizeof(buf))
1351 memset(buf, 0, sizeof(buf));
1352 be16enc(buf, 30 - 2);
1358 be16enc(&buf[18], 2);
1359 be16enc(&buf[20], 512);
1360 write_prdt(p, slot, cfis, buf, len);
1361 tfd = ATA_S_READY | ATA_S_DSC;
1370 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1372 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1377 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1379 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1382 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1383 ahci_write_fis_d2h(p, slot, cfis, tfd);
1387 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1395 /* we don't support asynchronous operation */
1396 if (!(acmd[1] & 1)) {
1397 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1399 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1404 len = be16dec(acmd + 7);
1405 if (len > sizeof(buf))
1408 memset(buf, 0, sizeof(buf));
1409 be16enc(buf, 8 - 2);
1413 write_prdt(p, slot, cfis, buf, len);
1414 tfd = ATA_S_READY | ATA_S_DSC;
1416 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1417 ahci_write_fis_d2h(p, slot, cfis, tfd);
1421 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1431 for (i = 0; i < 16; i++)
1432 DPRINTF("%02x ", acmd[i]);
1438 case TEST_UNIT_READY:
1439 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1440 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1443 atapi_inquiry(p, slot, cfis);
1446 atapi_read_capacity(p, slot, cfis);
1450 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1451 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1454 atapi_read_toc(p, slot, cfis);
1458 atapi_read(p, slot, cfis, 0, 0);
1461 atapi_request_sense(p, slot, cfis);
1463 case START_STOP_UNIT:
1464 atapi_start_stop_unit(p, slot, cfis);
1467 atapi_mode_sense(p, slot, cfis);
1469 case GET_EVENT_STATUS_NOTIFICATION:
1470 atapi_get_event_status_notification(p, slot, cfis);
1473 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1474 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1476 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1477 ATA_S_READY | ATA_S_ERROR);
1483 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1487 case ATA_ATA_IDENTIFY:
1488 handle_identify(p, slot, cfis);
1490 case ATA_SETFEATURES:
1493 case ATA_SF_ENAB_SATA_SF:
1495 case ATA_SATA_SF_AN:
1496 p->tfd = ATA_S_DSC | ATA_S_READY;
1499 p->tfd = ATA_S_ERROR | ATA_S_READY;
1500 p->tfd |= (ATA_ERROR_ABORT << 8);
1504 case ATA_SF_ENAB_WCACHE:
1505 case ATA_SF_DIS_WCACHE:
1506 case ATA_SF_ENAB_RCACHE:
1507 case ATA_SF_DIS_RCACHE:
1508 p->tfd = ATA_S_DSC | ATA_S_READY;
1510 case ATA_SF_SETXFER:
1512 switch (cfis[12] & 0xf8) {
1518 p->xfermode = (cfis[12] & 0x7);
1521 p->tfd = ATA_S_DSC | ATA_S_READY;
1525 p->tfd = ATA_S_ERROR | ATA_S_READY;
1526 p->tfd |= (ATA_ERROR_ABORT << 8);
1529 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1533 if (cfis[12] != 0 &&
1534 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1535 p->tfd = ATA_S_ERROR | ATA_S_READY;
1536 p->tfd |= (ATA_ERROR_ABORT << 8);
1538 p->mult_sectors = cfis[12];
1539 p->tfd = ATA_S_DSC | ATA_S_READY;
1541 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1549 case ATA_READ_MUL48:
1550 case ATA_WRITE_MUL48:
1553 case ATA_READ_DMA48:
1554 case ATA_WRITE_DMA48:
1555 case ATA_READ_FPDMA_QUEUED:
1556 case ATA_WRITE_FPDMA_QUEUED:
1557 ahci_handle_dma(p, slot, cfis, 0, 0);
1559 case ATA_FLUSHCACHE:
1560 case ATA_FLUSHCACHE48:
1561 ahci_handle_flush(p, slot, cfis);
1563 case ATA_DATA_SET_MANAGEMENT:
1564 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1565 cfis[13] == 0 && cfis[12] == 1) {
1566 ahci_handle_dsm_trim(p, slot, cfis, 0);
1569 ahci_write_fis_d2h(p, slot, cfis,
1570 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1572 case ATA_SEND_FPDMA_QUEUED:
1573 if ((cfis[13] & 0x1f) == ATA_SFPDMA_DSM &&
1574 cfis[17] == 0 && cfis[16] == ATA_DSM_TRIM &&
1575 cfis[11] == 0 && cfis[13] == 1) {
1576 ahci_handle_dsm_trim(p, slot, cfis, 0);
1579 ahci_write_fis_d2h(p, slot, cfis,
1580 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1582 case ATA_READ_LOG_EXT:
1583 case ATA_READ_LOG_DMA_EXT:
1584 ahci_handle_read_log(p, slot, cfis);
1586 case ATA_STANDBY_CMD:
1589 case ATA_STANDBY_IMMEDIATE:
1590 case ATA_IDLE_IMMEDIATE:
1592 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1594 case ATA_ATAPI_IDENTIFY:
1595 handle_atapi_identify(p, slot, cfis);
1597 case ATA_PACKET_CMD:
1599 ahci_write_fis_d2h(p, slot, cfis,
1600 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1602 handle_packet_cmd(p, slot, cfis);
1605 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1606 ahci_write_fis_d2h(p, slot, cfis,
1607 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1613 ahci_handle_slot(struct ahci_port *p, int slot)
1615 struct ahci_cmd_hdr *hdr;
1616 struct ahci_prdt_entry *prdt;
1617 struct pci_ahci_softc *sc;
1622 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1623 cfl = (hdr->flags & 0x1f) * 4;
1624 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1625 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1626 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1630 for (i = 0; i < cfl; i++) {
1633 DPRINTF("%02x ", cfis[i]);
1637 for (i = 0; i < hdr->prdtl; i++) {
1638 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1643 if (cfis[0] != FIS_TYPE_REGH2D) {
1644 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1648 if (cfis[1] & 0x80) {
1649 ahci_handle_cmd(p, slot, cfis);
1651 if (cfis[15] & (1 << 2))
1653 else if (p->reset) {
1657 p->ci &= ~(1 << slot);
1662 ahci_handle_port(struct ahci_port *p)
1666 if (!(p->cmd & AHCI_P_CMD_ST))
1670 * Search for any new commands to issue ignoring those that
1671 * are already in-flight.
1673 for (i = 0; (i < 32) && p->ci; i++) {
1674 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1675 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1676 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1677 ahci_handle_slot(p, i);
1683 * blockif callback routine - this runs in the context of the blockif
1684 * i/o thread, so the mutex needs to be acquired.
1687 ata_ioreq_cb(struct blockif_req *br, int err)
1689 struct ahci_cmd_hdr *hdr;
1690 struct ahci_ioreq *aior;
1691 struct ahci_port *p;
1692 struct pci_ahci_softc *sc;
1695 int pending, slot, ncq, dsm;
1697 DPRINTF("%s %d\n", __func__, err);
1700 aior = br->br_param;
1704 pending = aior->prdtl;
1706 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1708 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1709 cfis[2] == ATA_READ_FPDMA_QUEUED ||
1710 cfis[2] == ATA_SEND_FPDMA_QUEUED)
1712 if (cfis[2] == ATA_DATA_SET_MANAGEMENT ||
1713 (cfis[2] == ATA_SEND_FPDMA_QUEUED &&
1714 (cfis[13] & 0x1f) == ATA_SFPDMA_DSM))
1717 pthread_mutex_lock(&sc->mtx);
1720 * Delete the blockif request from the busy list
1722 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1725 * Move the blockif request back to the free list
1727 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1730 hdr->prdbc = aior->done;
1733 if (aior->done != aior->len && !err) {
1734 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1738 if (pending && !err) {
1739 ahci_handle_dma(p, slot, cfis, aior->done,
1740 hdr->prdtl - pending);
1745 if (!err && aior->done == aior->len) {
1746 tfd = ATA_S_READY | ATA_S_DSC;
1748 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1752 ahci_write_fis_sdb(p, slot, cfis, tfd);
1754 ahci_write_fis_d2h(p, slot, cfis, tfd);
1757 * This command is now complete.
1759 p->pending &= ~(1 << slot);
1761 ahci_check_stopped(p);
1763 pthread_mutex_unlock(&sc->mtx);
1764 DPRINTF("%s exit\n", __func__);
1768 atapi_ioreq_cb(struct blockif_req *br, int err)
1770 struct ahci_cmd_hdr *hdr;
1771 struct ahci_ioreq *aior;
1772 struct ahci_port *p;
1773 struct pci_ahci_softc *sc;
1778 DPRINTF("%s %d\n", __func__, err);
1780 aior = br->br_param;
1784 pending = aior->prdtl;
1786 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1788 pthread_mutex_lock(&sc->mtx);
1791 * Delete the blockif request from the busy list
1793 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1796 * Move the blockif request back to the free list
1798 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1801 hdr->prdbc = aior->done;
1803 if (pending && !err) {
1804 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1808 if (!err && aior->done == aior->len) {
1809 tfd = ATA_S_READY | ATA_S_DSC;
1811 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1813 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1816 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1817 ahci_write_fis_d2h(p, slot, cfis, tfd);
1820 * This command is now complete.
1822 p->pending &= ~(1 << slot);
1824 ahci_check_stopped(p);
1826 pthread_mutex_unlock(&sc->mtx);
1827 DPRINTF("%s exit\n", __func__);
1831 pci_ahci_ioreq_init(struct ahci_port *pr)
1833 struct ahci_ioreq *vr;
1836 pr->ioqsz = blockif_queuesz(pr->bctx);
1837 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1838 STAILQ_INIT(&pr->iofhd);
1841 * Add all i/o request entries to the free queue
1843 for (i = 0; i < pr->ioqsz; i++) {
1847 vr->io_req.br_callback = ata_ioreq_cb;
1849 vr->io_req.br_callback = atapi_ioreq_cb;
1850 vr->io_req.br_param = vr;
1851 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
1854 TAILQ_INIT(&pr->iobhd);
1858 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1860 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1861 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1862 struct ahci_port *p = &sc->port[port];
1864 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1865 port, offset, value);
1884 p->ie = value & 0xFDC000FF;
1885 ahci_generate_intr(sc);
1891 if (!(value & AHCI_P_CMD_ST)) {
1896 p->cmd |= AHCI_P_CMD_CR;
1897 clb = (uint64_t)p->clbu << 32 | p->clb;
1898 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1899 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1902 if (value & AHCI_P_CMD_FRE) {
1905 p->cmd |= AHCI_P_CMD_FR;
1906 fb = (uint64_t)p->fbu << 32 | p->fb;
1907 /* we don't support FBSCP, so rfis size is 256Bytes */
1908 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1910 p->cmd &= ~AHCI_P_CMD_FR;
1913 if (value & AHCI_P_CMD_CLO) {
1915 p->cmd &= ~AHCI_P_CMD_CLO;
1918 ahci_handle_port(p);
1924 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1928 if (!(p->cmd & AHCI_P_CMD_ST)) {
1929 if (value & ATA_SC_DET_RESET)
1941 ahci_handle_port(p);
1951 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1953 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1961 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1964 if (value & AHCI_GHC_HR)
1966 else if (value & AHCI_GHC_IE) {
1967 sc->ghc |= AHCI_GHC_IE;
1968 ahci_generate_intr(sc);
1973 ahci_generate_intr(sc);
1981 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1982 int baridx, uint64_t offset, int size, uint64_t value)
1984 struct pci_ahci_softc *sc = pi->pi_arg;
1986 assert(baridx == 5);
1989 pthread_mutex_lock(&sc->mtx);
1991 if (offset < AHCI_OFFSET)
1992 pci_ahci_host_write(sc, offset, value);
1993 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1994 pci_ahci_port_write(sc, offset, value);
1996 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1998 pthread_mutex_unlock(&sc->mtx);
2002 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
2018 uint32_t *p = &sc->cap;
2019 p += (offset - AHCI_CAP) / sizeof(uint32_t);
2027 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
2034 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
2037 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
2038 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
2058 uint32_t *p= &sc->port[port].clb;
2059 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2068 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
2069 port, offset, value);
2075 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2076 uint64_t offset, int size)
2078 struct pci_ahci_softc *sc = pi->pi_arg;
2081 assert(baridx == 5);
2084 pthread_mutex_lock(&sc->mtx);
2086 if (offset < AHCI_OFFSET)
2087 value = pci_ahci_host_read(sc, offset);
2088 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2089 value = pci_ahci_port_read(sc, offset);
2092 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
2095 pthread_mutex_unlock(&sc->mtx);
2101 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2103 char bident[sizeof("XX:X:X")];
2104 struct blockif_ctxt *bctxt;
2105 struct pci_ahci_softc *sc;
2111 fprintf(stderr, "pci_ahci: backing device required\n");
2116 dbg = fopen("/tmp/log", "w+");
2119 sc = calloc(1, sizeof(struct pci_ahci_softc));
2122 sc->ports = MAX_PORTS;
2125 * Only use port 0 for a backing device. All other ports will be
2128 sc->port[0].atapi = atapi;
2131 * Attempt to open the backing image. Use the PCI
2132 * slot/func for the identifier string.
2134 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
2135 bctxt = blockif_open(opts, bident);
2136 if (bctxt == NULL) {
2140 sc->port[0].bctx = bctxt;
2141 sc->port[0].pr_sc = sc;
2144 * Allocate blockif request structures and add them
2147 pci_ahci_ioreq_init(&sc->port[0]);
2149 pthread_mutex_init(&sc->mtx, NULL);
2151 /* Intel ICH8 AHCI */
2152 slots = sc->port[0].ioqsz;
2156 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2157 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2158 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2159 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2160 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2162 /* Only port 0 implemented */
2165 sc->cap2 = AHCI_CAP2_APST;
2168 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2169 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2170 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2171 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2172 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2173 pci_emul_add_msicap(pi, 1);
2174 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2175 AHCI_OFFSET + sc->ports * AHCI_STEP);
2177 pci_lintr_request(pi);
2181 blockif_close(sc->port[0].bctx);
2189 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2192 return (pci_ahci_init(ctx, pi, opts, 0));
2196 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2199 return (pci_ahci_init(ctx, pi, opts, 1));
2203 * Use separate emulation names to distinguish drive and atapi devices
2205 struct pci_devemu pci_de_ahci_hd = {
2206 .pe_emu = "ahci-hd",
2207 .pe_init = pci_ahci_hd_init,
2208 .pe_barwrite = pci_ahci_write,
2209 .pe_barread = pci_ahci_read
2211 PCI_EMUL_SET(pci_de_ahci_hd);
2213 struct pci_devemu pci_de_ahci_cd = {
2214 .pe_emu = "ahci-cd",
2215 .pe_init = pci_ahci_atapi_init,
2216 .pe_barwrite = pci_ahci_write,
2217 .pe_barread = pci_ahci_read
2219 PCI_EMUL_SET(pci_de_ahci_cd);