2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
51 #include <pthread_np.h>
59 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
61 #define PxSIG_ATA 0x00000101 /* ATA drive */
62 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
78 #define TEST_UNIT_READY 0x00
79 #define REQUEST_SENSE 0x03
81 #define START_STOP_UNIT 0x1B
82 #define PREVENT_ALLOW 0x1E
83 #define READ_CAPACITY 0x25
85 #define POSITION_TO_ELEMENT 0x2B
87 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
88 #define MODE_SENSE_10 0x5A
93 * SCSI mode page codes
95 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
96 #define MODEPAGE_CD_CAPABILITIES 0x2A
101 #define ATA_SF_ENAB_SATA_SF 0x10
102 #define ATA_SATA_SF_AN 0x05
103 #define ATA_SF_DIS_SATA_SF 0x90
110 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
112 #define DPRINTF(format, arg...)
114 #define WPRINTF(format, arg...) printf(format, ##arg)
117 struct blockif_req io_req;
118 struct ahci_port *io_pr;
119 STAILQ_ENTRY(ahci_ioreq) io_flist;
120 TAILQ_ENTRY(ahci_ioreq) io_blist;
129 struct blockif_ctxt *bctx;
130 struct pci_ahci_softc *pr_sc;
162 struct ahci_ioreq *ioreq;
164 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
165 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
168 struct ahci_cmd_hdr {
173 uint32_t reserved[4];
176 struct ahci_prdt_entry {
179 #define DBCMASK 0x3fffff
183 struct pci_ahci_softc {
184 struct pci_devinst *asc_pi;
199 struct ahci_port port[MAX_PORTS];
201 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
203 static inline void lba_to_msf(uint8_t *buf, int lba)
206 buf[0] = (lba / 75) / 60;
207 buf[1] = (lba / 75) % 60;
212 * generate HBA intr depending on whether or not ports within
213 * the controller have an interrupt pending.
216 ahci_generate_intr(struct pci_ahci_softc *sc)
218 struct pci_devinst *pi;
223 for (i = 0; i < sc->ports; i++) {
224 struct ahci_port *pr;
230 DPRINTF("%s %x\n", __func__, sc->is);
232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
233 if (pci_msi_enabled(pi)) {
235 * Generate an MSI interrupt on every edge
237 pci_generate_msi(pi, 0);
238 } else if (!sc->lintr) {
240 * Only generate a pin-based interrupt if one wasn't
244 pci_lintr_assert(pi);
246 } else if (sc->lintr) {
248 * No interrupts: deassert pin-based signal if it had
251 pci_lintr_deassert(pi);
257 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
259 int offset, len, irq;
261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
265 case FIS_TYPE_REGD2H:
270 case FIS_TYPE_SETDEVBITS:
275 case FIS_TYPE_PIOSETUP:
281 WPRINTF("unsupported fis type %d\n", ft);
284 memcpy(p->rfis + offset, fis, len);
287 ahci_generate_intr(p->pr_sc);
292 ahci_write_fis_piosetup(struct ahci_port *p)
296 memset(fis, 0, sizeof(fis));
297 fis[0] = FIS_TYPE_PIOSETUP;
298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
302 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
307 error = (tfd >> 8) & 0xff;
308 memset(fis, 0, sizeof(fis));
311 *(uint32_t *)(fis + 4) = (1 << slot);
312 if (fis[2] & ATA_S_ERROR)
313 p->is |= AHCI_P_IX_TFE;
315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
319 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
324 error = (tfd >> 8) & 0xff;
325 memset(fis, 0, sizeof(fis));
326 fis[0] = FIS_TYPE_REGD2H;
340 if (fis[2] & ATA_S_ERROR)
341 p->is |= AHCI_P_IX_TFE;
343 p->ci &= ~(1 << slot);
345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
349 ahci_write_reset_fis_d2h(struct ahci_port *p)
353 memset(fis, 0, sizeof(fis));
354 fis[0] = FIS_TYPE_REGD2H;
362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
366 ahci_check_stopped(struct ahci_port *p)
369 * If we are no longer processing the command list and nothing
370 * is in-flight, clear the running bit.
372 if (!(p->cmd & AHCI_P_CMD_ST)) {
374 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
379 ahci_port_stop(struct ahci_port *p)
381 struct ahci_ioreq *aior;
387 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
389 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
391 * Try to cancel the outstanding blockif request.
393 error = blockif_cancel(p->bctx, &aior->io_req);
399 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
400 cfis[2] == ATA_READ_FPDMA_QUEUED)
404 p->sact &= ~(1 << slot);
406 p->ci &= ~(1 << slot);
409 * This command is now done.
411 p->pending &= ~(1 << slot);
414 * Delete the blockif request from the busy list
416 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
419 * Move the blockif request back to the free list
421 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
424 ahci_check_stopped(p);
428 ahci_port_reset(struct ahci_port *pr)
433 pr->xfermode = ATA_UDMA6;
434 pr->mult_sectors = 128;
437 pr->ssts = ATA_SS_DET_NO_DEVICE;
438 pr->sig = 0xFFFFFFFF;
442 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
444 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
447 pr->tfd |= ATA_S_READY;
449 pr->sig = PxSIG_ATAPI;
450 ahci_write_reset_fis_d2h(pr);
454 ahci_reset(struct pci_ahci_softc *sc)
458 sc->ghc = AHCI_GHC_AE;
462 pci_lintr_deassert(sc->asc_pi);
466 for (i = 0; i < sc->ports; i++) {
469 ahci_port_reset(&sc->port[i]);
474 ata_string(uint8_t *dest, const char *src, int len)
478 for (i = 0; i < len; i++) {
480 dest[i ^ 1] = *src++;
487 atapi_string(uint8_t *dest, const char *src, int len)
491 for (i = 0; i < len; i++) {
500 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
503 struct ahci_ioreq *aior;
504 struct blockif_req *breq;
505 struct pci_ahci_softc *sc;
506 struct ahci_prdt_entry *prdt;
507 struct ahci_cmd_hdr *hdr;
510 int i, err, iovcnt, ncq, readop;
513 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
514 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
519 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
520 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
523 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
524 cfis[2] == ATA_READ_FPDMA_QUEUED) {
525 lba = ((uint64_t)cfis[10] << 40) |
526 ((uint64_t)cfis[9] << 32) |
527 ((uint64_t)cfis[8] << 24) |
528 ((uint64_t)cfis[6] << 16) |
529 ((uint64_t)cfis[5] << 8) |
531 len = cfis[11] << 8 | cfis[3];
535 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
536 lba = ((uint64_t)cfis[10] << 40) |
537 ((uint64_t)cfis[9] << 32) |
538 ((uint64_t)cfis[8] << 24) |
539 ((uint64_t)cfis[6] << 16) |
540 ((uint64_t)cfis[5] << 8) |
542 len = cfis[13] << 8 | cfis[12];
546 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
547 (cfis[5] << 8) | cfis[4];
552 lba *= blockif_sectsz(p->bctx);
553 len *= blockif_sectsz(p->bctx);
556 * Pull request off free list
558 aior = STAILQ_FIRST(&p->iofhd);
559 assert(aior != NULL);
560 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
565 breq = &aior->io_req;
566 breq->br_offset = lba + done;
567 iovcnt = hdr->prdtl - seek;
568 if (iovcnt > BLOCKIF_IOV_MAX) {
569 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
570 iovcnt = BLOCKIF_IOV_MAX;
573 breq->br_iovcnt = iovcnt;
576 * Mark this command in-flight.
578 p->pending |= 1 << slot;
581 * Stuff request onto busy list
583 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
586 * Build up the iovec based on the prdt
588 for (i = 0; i < iovcnt; i++) {
591 dbcsz = (prdt->dbc & DBCMASK) + 1;
592 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
594 breq->br_iov[i].iov_len = dbcsz;
599 err = blockif_read(p->bctx, breq);
601 err = blockif_write(p->bctx, breq);
605 p->ci &= ~(1 << slot);
609 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
611 struct ahci_ioreq *aior;
612 struct blockif_req *breq;
616 * Pull request off free list
618 aior = STAILQ_FIRST(&p->iofhd);
619 assert(aior != NULL);
620 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
626 breq = &aior->io_req;
629 * Mark this command in-flight.
631 p->pending |= 1 << slot;
634 * Stuff request onto busy list
636 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
638 err = blockif_flush(p->bctx, breq);
643 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
646 struct ahci_cmd_hdr *hdr;
647 struct ahci_prdt_entry *prdt;
651 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
654 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
655 for (i = 0; i < hdr->prdtl && len; i++) {
660 dbcsz = (prdt->dbc & DBCMASK) + 1;
661 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
662 sublen = len < dbcsz ? len : dbcsz;
663 memcpy(ptr, from, sublen);
668 hdr->prdbc = size - len;
672 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
674 struct ahci_cmd_hdr *hdr;
676 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
677 if (p->atapi || hdr->prdtl == 0) {
678 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
679 p->is |= AHCI_P_IX_TFE;
686 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
687 blockif_chs(p->bctx, &cyl, &heads, &sech);
688 memset(buf, 0, sizeof(buf));
693 /* TODO emulate different serial? */
694 ata_string((uint8_t *)(buf+10), "123456", 20);
695 ata_string((uint8_t *)(buf+23), "001", 8);
696 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
697 buf[47] = (0x8000 | 128);
699 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
701 buf[53] = (1 << 1 | 1 << 2);
703 buf[59] = (0x100 | p->mult_sectors);
705 buf[61] = (sectors >> 16);
707 if (p->xfermode & ATA_WDMA0)
708 buf[63] |= (1 << ((p->xfermode & 7) + 8));
715 buf[76] = (1 << 8 | 1 << 2);
718 buf[82] = (1 << 5 | 1 << 14);
719 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
721 buf[85] = (1 << 5 | 1 << 14);
722 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
725 if (p->xfermode & ATA_UDMA0)
726 buf[88] |= (1 << ((p->xfermode & 7) + 8));
727 buf[93] = (1 | 1 <<14);
729 buf[101] = (sectors >> 16);
730 buf[102] = (sectors >> 32);
731 buf[103] = (sectors >> 48);
732 ahci_write_fis_piosetup(p);
733 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
734 p->tfd = ATA_S_DSC | ATA_S_READY;
735 p->is |= AHCI_P_IX_DP;
736 p->ci &= ~(1 << slot);
738 ahci_generate_intr(p->pr_sc);
742 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
745 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
746 p->is |= AHCI_P_IX_TFE;
750 memset(buf, 0, sizeof(buf));
751 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
752 /* TODO emulate different serial? */
753 ata_string((uint8_t *)(buf+10), "123456", 20);
754 ata_string((uint8_t *)(buf+23), "001", 8);
755 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
756 buf[49] = (1 << 9 | 1 << 8);
757 buf[50] = (1 << 14 | 1);
758 buf[53] = (1 << 2 | 1 << 1);
766 buf[76] = (1 << 2 | 1 << 1);
768 buf[80] = (0x1f << 4);
774 buf[88] = (1 << 14 | 0x7f);
775 ahci_write_fis_piosetup(p);
776 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
777 p->tfd = ATA_S_DSC | ATA_S_READY;
778 p->is |= AHCI_P_IX_DHR;
779 p->ci &= ~(1 << slot);
781 ahci_generate_intr(p->pr_sc);
785 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
801 atapi_string(buf + 8, "BHYVE", 8);
802 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
803 atapi_string(buf + 32, "001", 4);
808 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
809 write_prdt(p, slot, cfis, buf, len);
810 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
814 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
819 sectors = blockif_size(p->bctx) / 2048;
820 be32enc(buf, sectors - 1);
821 be32enc(buf + 4, 2048);
822 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
823 write_prdt(p, slot, cfis, buf, sizeof(buf));
824 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
828 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
836 len = be16dec(acmd + 7);
837 format = acmd[9] >> 6;
843 uint8_t start_track, buf[20], *bp;
845 msf = (acmd[1] >> 1) & 1;
846 start_track = acmd[6];
847 if (start_track > 1 && start_track != 0xaa) {
849 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
851 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
852 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
853 ahci_write_fis_d2h(p, slot, cfis, tfd);
859 if (start_track <= 1) {
879 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
883 lba_to_msf(bp, sectors);
886 be32enc(bp, sectors);
890 be16enc(buf, size - 2);
893 write_prdt(p, slot, cfis, buf, len);
894 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
895 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
902 memset(buf, 0, sizeof(buf));
906 if (len > sizeof(buf))
908 write_prdt(p, slot, cfis, buf, len);
909 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
910 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
917 uint8_t start_track, *bp, buf[50];
919 msf = (acmd[1] >> 1) & 1;
920 start_track = acmd[6];
956 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
960 lba_to_msf(bp, sectors);
963 be32enc(bp, sectors);
986 be16enc(buf, size - 2);
989 write_prdt(p, slot, cfis, buf, len);
990 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
991 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
998 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1000 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1001 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1002 ahci_write_fis_d2h(p, slot, cfis, tfd);
1009 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
1010 uint32_t done, int seek)
1012 struct ahci_ioreq *aior;
1013 struct ahci_cmd_hdr *hdr;
1014 struct ahci_prdt_entry *prdt;
1015 struct blockif_req *breq;
1016 struct pci_ahci_softc *sc;
1024 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1025 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1028 lba = be32dec(acmd + 2);
1029 if (acmd[0] == READ_10)
1030 len = be16dec(acmd + 7);
1032 len = be32dec(acmd + 6);
1034 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1035 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1041 * Pull request off free list
1043 aior = STAILQ_FIRST(&p->iofhd);
1044 assert(aior != NULL);
1045 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1050 breq = &aior->io_req;
1051 breq->br_offset = lba + done;
1052 iovcnt = hdr->prdtl - seek;
1053 if (iovcnt > BLOCKIF_IOV_MAX) {
1054 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
1055 iovcnt = BLOCKIF_IOV_MAX;
1058 breq->br_iovcnt = iovcnt;
1061 * Mark this command in-flight.
1063 p->pending |= 1 << slot;
1066 * Stuff request onto busy list
1068 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1071 * Build up the iovec based on the prdt
1073 for (i = 0; i < iovcnt; i++) {
1076 dbcsz = (prdt->dbc & DBCMASK) + 1;
1077 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
1079 breq->br_iov[i].iov_len = dbcsz;
1080 aior->done += dbcsz;
1083 err = blockif_read(p->bctx, breq);
1088 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1096 if (len > sizeof(buf))
1098 memset(buf, 0, len);
1099 buf[0] = 0x70 | (1 << 7);
1100 buf[2] = p->sense_key;
1103 write_prdt(p, slot, cfis, buf, len);
1104 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1105 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1109 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1111 uint8_t *acmd = cfis + 0x40;
1114 switch (acmd[4] & 3) {
1118 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1119 tfd = ATA_S_READY | ATA_S_DSC;
1122 /* TODO eject media */
1123 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1124 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1126 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1129 ahci_write_fis_d2h(p, slot, cfis, tfd);
1133 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1141 len = be16dec(acmd + 7);
1143 code = acmd[2] & 0x3f;
1148 case MODEPAGE_RW_ERROR_RECOVERY:
1152 if (len > sizeof(buf))
1155 memset(buf, 0, sizeof(buf));
1156 be16enc(buf, 16 - 2);
1161 write_prdt(p, slot, cfis, buf, len);
1162 tfd = ATA_S_READY | ATA_S_DSC;
1165 case MODEPAGE_CD_CAPABILITIES:
1169 if (len > sizeof(buf))
1172 memset(buf, 0, sizeof(buf));
1173 be16enc(buf, 30 - 2);
1179 be16enc(&buf[18], 2);
1180 be16enc(&buf[20], 512);
1181 write_prdt(p, slot, cfis, buf, len);
1182 tfd = ATA_S_READY | ATA_S_DSC;
1191 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1193 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1198 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1200 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1203 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1204 ahci_write_fis_d2h(p, slot, cfis, tfd);
1208 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1216 /* we don't support asynchronous operation */
1217 if (!(acmd[1] & 1)) {
1218 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1220 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1225 len = be16dec(acmd + 7);
1226 if (len > sizeof(buf))
1229 memset(buf, 0, sizeof(buf));
1230 be16enc(buf, 8 - 2);
1234 write_prdt(p, slot, cfis, buf, len);
1235 tfd = ATA_S_READY | ATA_S_DSC;
1237 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1238 ahci_write_fis_d2h(p, slot, cfis, tfd);
1242 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1252 for (i = 0; i < 16; i++)
1253 DPRINTF("%02x ", acmd[i]);
1259 case TEST_UNIT_READY:
1260 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1261 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1264 atapi_inquiry(p, slot, cfis);
1267 atapi_read_capacity(p, slot, cfis);
1271 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1272 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1275 atapi_read_toc(p, slot, cfis);
1279 atapi_read(p, slot, cfis, 0, 0);
1282 atapi_request_sense(p, slot, cfis);
1284 case START_STOP_UNIT:
1285 atapi_start_stop_unit(p, slot, cfis);
1288 atapi_mode_sense(p, slot, cfis);
1290 case GET_EVENT_STATUS_NOTIFICATION:
1291 atapi_get_event_status_notification(p, slot, cfis);
1294 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1295 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1297 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1298 ATA_S_READY | ATA_S_ERROR);
1304 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1308 case ATA_ATA_IDENTIFY:
1309 handle_identify(p, slot, cfis);
1311 case ATA_SETFEATURES:
1314 case ATA_SF_ENAB_SATA_SF:
1316 case ATA_SATA_SF_AN:
1317 p->tfd = ATA_S_DSC | ATA_S_READY;
1320 p->tfd = ATA_S_ERROR | ATA_S_READY;
1321 p->tfd |= (ATA_ERROR_ABORT << 8);
1325 case ATA_SF_ENAB_WCACHE:
1326 case ATA_SF_DIS_WCACHE:
1327 case ATA_SF_ENAB_RCACHE:
1328 case ATA_SF_DIS_RCACHE:
1329 p->tfd = ATA_S_DSC | ATA_S_READY;
1331 case ATA_SF_SETXFER:
1333 switch (cfis[12] & 0xf8) {
1339 p->xfermode = (cfis[12] & 0x7);
1342 p->tfd = ATA_S_DSC | ATA_S_READY;
1346 p->tfd = ATA_S_ERROR | ATA_S_READY;
1347 p->tfd |= (ATA_ERROR_ABORT << 8);
1350 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1354 if (cfis[12] != 0 &&
1355 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1356 p->tfd = ATA_S_ERROR | ATA_S_READY;
1357 p->tfd |= (ATA_ERROR_ABORT << 8);
1359 p->mult_sectors = cfis[12];
1360 p->tfd = ATA_S_DSC | ATA_S_READY;
1362 p->is |= AHCI_P_IX_DP;
1363 p->ci &= ~(1 << slot);
1364 ahci_generate_intr(p->pr_sc);
1368 case ATA_READ_DMA48:
1369 case ATA_WRITE_DMA48:
1370 case ATA_READ_FPDMA_QUEUED:
1371 case ATA_WRITE_FPDMA_QUEUED:
1372 ahci_handle_dma(p, slot, cfis, 0, 0);
1374 case ATA_FLUSHCACHE:
1375 case ATA_FLUSHCACHE48:
1376 ahci_handle_flush(p, slot, cfis);
1378 case ATA_STANDBY_CMD:
1381 case ATA_STANDBY_IMMEDIATE:
1382 case ATA_IDLE_IMMEDIATE:
1384 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1386 case ATA_ATAPI_IDENTIFY:
1387 handle_atapi_identify(p, slot, cfis);
1389 case ATA_PACKET_CMD:
1391 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1392 p->is |= AHCI_P_IX_TFE;
1393 ahci_generate_intr(p->pr_sc);
1395 handle_packet_cmd(p, slot, cfis);
1398 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1399 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1400 p->is |= AHCI_P_IX_TFE;
1401 ahci_generate_intr(p->pr_sc);
1407 ahci_handle_slot(struct ahci_port *p, int slot)
1409 struct ahci_cmd_hdr *hdr;
1410 struct ahci_prdt_entry *prdt;
1411 struct pci_ahci_softc *sc;
1416 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1417 cfl = (hdr->flags & 0x1f) * 4;
1418 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1419 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1420 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1424 for (i = 0; i < cfl; i++) {
1427 DPRINTF("%02x ", cfis[i]);
1431 for (i = 0; i < hdr->prdtl; i++) {
1432 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1437 if (cfis[0] != FIS_TYPE_REGH2D) {
1438 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1442 if (cfis[1] & 0x80) {
1443 ahci_handle_cmd(p, slot, cfis);
1445 if (cfis[15] & (1 << 2))
1447 else if (p->reset) {
1451 p->ci &= ~(1 << slot);
1456 ahci_handle_port(struct ahci_port *p)
1460 if (!(p->cmd & AHCI_P_CMD_ST))
1464 * Search for any new commands to issue ignoring those that
1465 * are already in-flight.
1467 for (i = 0; (i < 32) && p->ci; i++) {
1468 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1469 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1470 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1471 ahci_handle_slot(p, i);
1477 * blockif callback routine - this runs in the context of the blockif
1478 * i/o thread, so the mutex needs to be acquired.
1481 ata_ioreq_cb(struct blockif_req *br, int err)
1483 struct ahci_cmd_hdr *hdr;
1484 struct ahci_ioreq *aior;
1485 struct ahci_port *p;
1486 struct pci_ahci_softc *sc;
1489 int pending, slot, ncq;
1491 DPRINTF("%s %d\n", __func__, err);
1494 aior = br->br_param;
1498 pending = aior->prdtl;
1500 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1502 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1503 cfis[2] == ATA_READ_FPDMA_QUEUED)
1506 pthread_mutex_lock(&sc->mtx);
1509 * Delete the blockif request from the busy list
1511 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1514 * Move the blockif request back to the free list
1516 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1518 if (pending && !err) {
1519 ahci_handle_dma(p, slot, cfis, aior->done,
1520 hdr->prdtl - pending);
1524 if (!err && aior->done == aior->len) {
1525 tfd = ATA_S_READY | ATA_S_DSC;
1529 hdr->prdbc = aior->len;
1531 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1534 p->serr |= (1 << slot);
1538 p->sact &= ~(1 << slot);
1539 ahci_write_fis_sdb(p, slot, tfd);
1541 ahci_write_fis_d2h(p, slot, cfis, tfd);
1544 * This command is now complete.
1546 p->pending &= ~(1 << slot);
1548 ahci_check_stopped(p);
1550 pthread_mutex_unlock(&sc->mtx);
1551 DPRINTF("%s exit\n", __func__);
1555 atapi_ioreq_cb(struct blockif_req *br, int err)
1557 struct ahci_cmd_hdr *hdr;
1558 struct ahci_ioreq *aior;
1559 struct ahci_port *p;
1560 struct pci_ahci_softc *sc;
1565 DPRINTF("%s %d\n", __func__, err);
1567 aior = br->br_param;
1571 pending = aior->prdtl;
1573 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1575 pthread_mutex_lock(&sc->mtx);
1578 * Delete the blockif request from the busy list
1580 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1583 * Move the blockif request back to the free list
1585 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1587 if (pending && !err) {
1588 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1592 if (!err && aior->done == aior->len) {
1593 tfd = ATA_S_READY | ATA_S_DSC;
1594 hdr->prdbc = aior->len;
1596 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1598 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1602 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1603 ahci_write_fis_d2h(p, slot, cfis, tfd);
1606 * This command is now complete.
1608 p->pending &= ~(1 << slot);
1610 ahci_check_stopped(p);
1612 pthread_mutex_unlock(&sc->mtx);
1613 DPRINTF("%s exit\n", __func__);
1617 pci_ahci_ioreq_init(struct ahci_port *pr)
1619 struct ahci_ioreq *vr;
1622 pr->ioqsz = blockif_queuesz(pr->bctx);
1623 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1624 STAILQ_INIT(&pr->iofhd);
1627 * Add all i/o request entries to the free queue
1629 for (i = 0; i < pr->ioqsz; i++) {
1633 vr->io_req.br_callback = ata_ioreq_cb;
1635 vr->io_req.br_callback = atapi_ioreq_cb;
1636 vr->io_req.br_param = vr;
1637 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
1640 TAILQ_INIT(&pr->iobhd);
1644 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1646 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1647 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1648 struct ahci_port *p = &sc->port[port];
1650 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1651 port, offset, value);
1670 p->ie = value & 0xFDC000FF;
1671 ahci_generate_intr(sc);
1677 if (!(value & AHCI_P_CMD_ST)) {
1682 p->cmd |= AHCI_P_CMD_CR;
1683 clb = (uint64_t)p->clbu << 32 | p->clb;
1684 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1685 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1688 if (value & AHCI_P_CMD_FRE) {
1691 p->cmd |= AHCI_P_CMD_FR;
1692 fb = (uint64_t)p->fbu << 32 | p->fb;
1693 /* we don't support FBSCP, so rfis size is 256Bytes */
1694 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1696 p->cmd &= ~AHCI_P_CMD_FR;
1699 if (value & AHCI_P_CMD_CLO) {
1701 p->cmd &= ~AHCI_P_CMD_CLO;
1704 ahci_handle_port(p);
1710 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1713 if (!(p->cmd & AHCI_P_CMD_ST)) {
1714 if (value & ATA_SC_DET_RESET)
1727 ahci_handle_port(p);
1737 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1739 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1747 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1750 if (value & AHCI_GHC_HR)
1752 else if (value & AHCI_GHC_IE) {
1753 sc->ghc |= AHCI_GHC_IE;
1754 ahci_generate_intr(sc);
1759 ahci_generate_intr(sc);
1767 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1768 int baridx, uint64_t offset, int size, uint64_t value)
1770 struct pci_ahci_softc *sc = pi->pi_arg;
1772 assert(baridx == 5);
1775 pthread_mutex_lock(&sc->mtx);
1777 if (offset < AHCI_OFFSET)
1778 pci_ahci_host_write(sc, offset, value);
1779 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1780 pci_ahci_port_write(sc, offset, value);
1782 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1784 pthread_mutex_unlock(&sc->mtx);
1788 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1804 uint32_t *p = &sc->cap;
1805 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1813 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1820 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1823 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1824 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1844 uint32_t *p= &sc->port[port].clb;
1845 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1854 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1855 port, offset, value);
1861 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1862 uint64_t offset, int size)
1864 struct pci_ahci_softc *sc = pi->pi_arg;
1867 assert(baridx == 5);
1870 pthread_mutex_lock(&sc->mtx);
1872 if (offset < AHCI_OFFSET)
1873 value = pci_ahci_host_read(sc, offset);
1874 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1875 value = pci_ahci_port_read(sc, offset);
1878 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1881 pthread_mutex_unlock(&sc->mtx);
1887 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1889 char bident[sizeof("XX:X:X")];
1890 struct blockif_ctxt *bctxt;
1891 struct pci_ahci_softc *sc;
1897 fprintf(stderr, "pci_ahci: backing device required\n");
1902 dbg = fopen("/tmp/log", "w+");
1905 sc = calloc(1, sizeof(struct pci_ahci_softc));
1908 sc->ports = MAX_PORTS;
1911 * Only use port 0 for a backing device. All other ports will be
1914 sc->port[0].atapi = atapi;
1917 * Attempt to open the backing image. Use the PCI
1918 * slot/func for the identifier string.
1920 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
1921 bctxt = blockif_open(opts, bident);
1922 if (bctxt == NULL) {
1926 sc->port[0].bctx = bctxt;
1927 sc->port[0].pr_sc = sc;
1930 * Allocate blockif request structures and add them
1933 pci_ahci_ioreq_init(&sc->port[0]);
1935 pthread_mutex_init(&sc->mtx, NULL);
1937 /* Intel ICH8 AHCI */
1938 slots = sc->port[0].ioqsz;
1942 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1943 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1944 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1945 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1946 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1948 /* Only port 0 implemented */
1951 sc->cap2 = AHCI_CAP2_APST;
1954 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1955 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1956 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1957 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1958 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1959 pci_emul_add_msicap(pi, 1);
1960 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1961 AHCI_OFFSET + sc->ports * AHCI_STEP);
1963 pci_lintr_request(pi);
1967 blockif_close(sc->port[0].bctx);
1975 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1978 return (pci_ahci_init(ctx, pi, opts, 0));
1982 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1985 return (pci_ahci_init(ctx, pi, opts, 1));
1989 * Use separate emulation names to distinguish drive and atapi devices
1991 struct pci_devemu pci_de_ahci_hd = {
1992 .pe_emu = "ahci-hd",
1993 .pe_init = pci_ahci_hd_init,
1994 .pe_barwrite = pci_ahci_write,
1995 .pe_barread = pci_ahci_read
1997 PCI_EMUL_SET(pci_de_ahci_hd);
1999 struct pci_devemu pci_de_ahci_cd = {
2000 .pe_emu = "ahci-cd",
2001 .pe_init = pci_ahci_atapi_init,
2002 .pe_barwrite = pci_ahci_write,
2003 .pe_barread = pci_ahci_read
2005 PCI_EMUL_SET(pci_de_ahci_cd);