2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
58 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
60 #define PxSIG_ATA 0x00000101 /* ATA drive */
61 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
64 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
65 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
66 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
67 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
68 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
69 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
70 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
71 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
77 #define TEST_UNIT_READY 0x00
78 #define REQUEST_SENSE 0x03
80 #define START_STOP_UNIT 0x1B
81 #define PREVENT_ALLOW 0x1E
82 #define READ_CAPACITY 0x25
84 #define POSITION_TO_ELEMENT 0x2B
86 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
87 #define MODE_SENSE_10 0x5A
92 * SCSI mode page codes
94 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
95 #define MODEPAGE_CD_CAPABILITIES 0x2A
100 #define ATA_SF_ENAB_SATA_SF 0x10
101 #define ATA_SATA_SF_AN 0x05
102 #define ATA_SF_DIS_SATA_SF 0x90
109 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
111 #define DPRINTF(format, arg...)
113 #define WPRINTF(format, arg...) printf(format, ##arg)
116 struct blockif_req io_req;
117 struct ahci_port *io_pr;
118 STAILQ_ENTRY(ahci_ioreq) io_list;
127 struct blockif_ctxt *bctx;
128 struct pci_ahci_softc *pr_sc;
160 struct ahci_ioreq *ioreq;
162 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
165 struct ahci_cmd_hdr {
170 uint32_t reserved[4];
173 struct ahci_prdt_entry {
176 #define DBCMASK 0x3fffff
180 struct pci_ahci_softc {
181 struct pci_devinst *asc_pi;
196 struct ahci_port port[MAX_PORTS];
198 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
200 static inline void lba_to_msf(uint8_t *buf, int lba)
203 buf[0] = (lba / 75) / 60;
204 buf[1] = (lba / 75) % 60;
209 * generate HBA intr depending on whether or not ports within
210 * the controller have an interrupt pending.
213 ahci_generate_intr(struct pci_ahci_softc *sc)
215 struct pci_devinst *pi;
220 for (i = 0; i < sc->ports; i++) {
221 struct ahci_port *pr;
227 DPRINTF("%s %x\n", __func__, sc->is);
229 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
230 if (pci_msi_enabled(pi)) {
232 * Generate an MSI interrupt on every edge
234 pci_generate_msi(pi, 0);
235 } else if (!sc->lintr) {
237 * Only generate a pin-based interrupt if one wasn't
241 pci_lintr_assert(pi);
243 } else if (sc->lintr) {
245 * No interrupts: deassert pin-based signal if it had
248 pci_lintr_deassert(pi);
254 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
256 int offset, len, irq;
258 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
262 case FIS_TYPE_REGD2H:
267 case FIS_TYPE_SETDEVBITS:
272 case FIS_TYPE_PIOSETUP:
278 WPRINTF("unsupported fis type %d\n", ft);
281 memcpy(p->rfis + offset, fis, len);
284 ahci_generate_intr(p->pr_sc);
289 ahci_write_fis_piosetup(struct ahci_port *p)
293 memset(fis, 0, sizeof(fis));
294 fis[0] = FIS_TYPE_PIOSETUP;
295 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
299 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
304 error = (tfd >> 8) & 0xff;
305 memset(fis, 0, sizeof(fis));
308 *(uint32_t *)(fis + 4) = (1 << slot);
309 if (fis[2] & ATA_S_ERROR)
310 p->is |= AHCI_P_IX_TFE;
312 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
316 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
321 error = (tfd >> 8) & 0xff;
322 memset(fis, 0, sizeof(fis));
323 fis[0] = FIS_TYPE_REGD2H;
337 if (fis[2] & ATA_S_ERROR)
338 p->is |= AHCI_P_IX_TFE;
340 p->ci &= ~(1 << slot);
342 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
346 ahci_write_reset_fis_d2h(struct ahci_port *p)
350 memset(fis, 0, sizeof(fis));
351 fis[0] = FIS_TYPE_REGD2H;
359 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
363 ahci_port_reset(struct ahci_port *pr)
368 pr->xfermode = ATA_UDMA6;
369 pr->mult_sectors = 128;
372 pr->ssts = ATA_SS_DET_NO_DEVICE;
373 pr->sig = 0xFFFFFFFF;
377 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
379 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
382 pr->tfd |= ATA_S_READY;
384 pr->sig = PxSIG_ATAPI;
385 ahci_write_reset_fis_d2h(pr);
389 ahci_reset(struct pci_ahci_softc *sc)
393 sc->ghc = AHCI_GHC_AE;
397 pci_lintr_deassert(sc->asc_pi);
401 for (i = 0; i < sc->ports; i++) {
404 ahci_port_reset(&sc->port[i]);
409 ata_string(uint8_t *dest, const char *src, int len)
413 for (i = 0; i < len; i++) {
415 dest[i ^ 1] = *src++;
422 atapi_string(uint8_t *dest, const char *src, int len)
426 for (i = 0; i < len; i++) {
435 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
438 struct ahci_ioreq *aior;
439 struct blockif_req *breq;
440 struct pci_ahci_softc *sc;
441 struct ahci_prdt_entry *prdt;
442 struct ahci_cmd_hdr *hdr;
445 int i, err, iovcnt, ncq, readop;
448 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
449 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
454 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
455 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
458 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
459 cfis[2] == ATA_READ_FPDMA_QUEUED) {
460 lba = ((uint64_t)cfis[10] << 40) |
461 ((uint64_t)cfis[9] << 32) |
462 ((uint64_t)cfis[8] << 24) |
463 ((uint64_t)cfis[6] << 16) |
464 ((uint64_t)cfis[5] << 8) |
466 len = cfis[11] << 8 | cfis[3];
470 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
471 lba = ((uint64_t)cfis[10] << 40) |
472 ((uint64_t)cfis[9] << 32) |
473 ((uint64_t)cfis[8] << 24) |
474 ((uint64_t)cfis[6] << 16) |
475 ((uint64_t)cfis[5] << 8) |
477 len = cfis[13] << 8 | cfis[12];
481 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
482 (cfis[5] << 8) | cfis[4];
487 lba *= blockif_sectsz(p->bctx);
488 len *= blockif_sectsz(p->bctx);
491 * Pull request off free list
493 aior = STAILQ_FIRST(&p->iofhd);
494 assert(aior != NULL);
495 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
500 breq = &aior->io_req;
501 breq->br_offset = lba + done;
502 iovcnt = hdr->prdtl - seek;
503 if (iovcnt > BLOCKIF_IOV_MAX) {
504 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
505 iovcnt = BLOCKIF_IOV_MAX;
507 * Mark this command in-flight.
509 p->pending |= 1 << slot;
512 breq->br_iovcnt = iovcnt;
515 * Build up the iovec based on the prdt
517 for (i = 0; i < iovcnt; i++) {
520 dbcsz = (prdt->dbc & DBCMASK) + 1;
521 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
523 breq->br_iov[i].iov_len = dbcsz;
528 err = blockif_read(p->bctx, breq);
530 err = blockif_write(p->bctx, breq);
534 p->ci &= ~(1 << slot);
538 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
540 struct ahci_ioreq *aior;
541 struct blockif_req *breq;
545 * Pull request off free list
547 aior = STAILQ_FIRST(&p->iofhd);
548 assert(aior != NULL);
549 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
555 breq = &aior->io_req;
557 err = blockif_flush(p->bctx, breq);
562 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
565 struct ahci_cmd_hdr *hdr;
566 struct ahci_prdt_entry *prdt;
570 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
573 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
574 for (i = 0; i < hdr->prdtl && len; i++) {
579 dbcsz = (prdt->dbc & DBCMASK) + 1;
580 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
581 sublen = len < dbcsz ? len : dbcsz;
582 memcpy(ptr, from, sublen);
587 hdr->prdbc = size - len;
591 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
593 struct ahci_cmd_hdr *hdr;
595 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
596 if (p->atapi || hdr->prdtl == 0) {
597 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
598 p->is |= AHCI_P_IX_TFE;
605 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
606 blockif_chs(p->bctx, &cyl, &heads, &sech);
607 memset(buf, 0, sizeof(buf));
612 /* TODO emulate different serial? */
613 ata_string((uint8_t *)(buf+10), "123456", 20);
614 ata_string((uint8_t *)(buf+23), "001", 8);
615 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
616 buf[47] = (0x8000 | 128);
618 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
620 buf[53] = (1 << 1 | 1 << 2);
622 buf[59] = (0x100 | p->mult_sectors);
624 buf[61] = (sectors >> 16);
626 if (p->xfermode & ATA_WDMA0)
627 buf[63] |= (1 << ((p->xfermode & 7) + 8));
634 buf[76] = (1 << 8 | 1 << 2);
637 buf[82] = (1 << 5 | 1 << 14);
638 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
640 buf[85] = (1 << 5 | 1 << 14);
641 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
644 if (p->xfermode & ATA_UDMA0)
645 buf[88] |= (1 << ((p->xfermode & 7) + 8));
646 buf[93] = (1 | 1 <<14);
648 buf[101] = (sectors >> 16);
649 buf[102] = (sectors >> 32);
650 buf[103] = (sectors >> 48);
651 ahci_write_fis_piosetup(p);
652 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
653 p->tfd = ATA_S_DSC | ATA_S_READY;
654 p->is |= AHCI_P_IX_DP;
655 p->ci &= ~(1 << slot);
657 ahci_generate_intr(p->pr_sc);
661 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
664 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
665 p->is |= AHCI_P_IX_TFE;
669 memset(buf, 0, sizeof(buf));
670 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
671 /* TODO emulate different serial? */
672 ata_string((uint8_t *)(buf+10), "123456", 20);
673 ata_string((uint8_t *)(buf+23), "001", 8);
674 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
675 buf[49] = (1 << 9 | 1 << 8);
676 buf[50] = (1 << 14 | 1);
677 buf[53] = (1 << 2 | 1 << 1);
685 buf[76] = (1 << 2 | 1 << 1);
687 buf[80] = (0x1f << 4);
693 buf[88] = (1 << 14 | 0x7f);
694 ahci_write_fis_piosetup(p);
695 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
696 p->tfd = ATA_S_DSC | ATA_S_READY;
697 p->is |= AHCI_P_IX_DHR;
698 p->ci &= ~(1 << slot);
700 ahci_generate_intr(p->pr_sc);
704 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
720 atapi_string(buf + 8, "BHYVE", 8);
721 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
722 atapi_string(buf + 32, "001", 4);
727 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
728 write_prdt(p, slot, cfis, buf, len);
729 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
733 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
738 sectors = blockif_size(p->bctx) / 2048;
739 be32enc(buf, sectors - 1);
740 be32enc(buf + 4, 2048);
741 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
742 write_prdt(p, slot, cfis, buf, sizeof(buf));
743 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
747 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
755 len = be16dec(acmd + 7);
756 format = acmd[9] >> 6;
762 uint8_t start_track, buf[20], *bp;
764 msf = (acmd[1] >> 1) & 1;
765 start_track = acmd[6];
766 if (start_track > 1 && start_track != 0xaa) {
768 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
770 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
771 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
772 ahci_write_fis_d2h(p, slot, cfis, tfd);
778 if (start_track <= 1) {
798 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
802 lba_to_msf(bp, sectors);
805 be32enc(bp, sectors);
809 be16enc(buf, size - 2);
812 write_prdt(p, slot, cfis, buf, len);
813 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
814 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
821 memset(buf, 0, sizeof(buf));
825 if (len > sizeof(buf))
827 write_prdt(p, slot, cfis, buf, len);
828 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
829 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
836 uint8_t start_track, *bp, buf[50];
838 msf = (acmd[1] >> 1) & 1;
839 start_track = acmd[6];
875 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
879 lba_to_msf(bp, sectors);
882 be32enc(bp, sectors);
905 be16enc(buf, size - 2);
908 write_prdt(p, slot, cfis, buf, len);
909 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
910 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
917 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
919 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
920 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
921 ahci_write_fis_d2h(p, slot, cfis, tfd);
928 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
929 uint32_t done, int seek)
931 struct ahci_ioreq *aior;
932 struct ahci_cmd_hdr *hdr;
933 struct ahci_prdt_entry *prdt;
934 struct blockif_req *breq;
935 struct pci_ahci_softc *sc;
943 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
944 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
947 lba = be32dec(acmd + 2);
948 if (acmd[0] == READ_10)
949 len = be16dec(acmd + 7);
951 len = be32dec(acmd + 6);
953 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
954 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
960 * Pull request off free list
962 aior = STAILQ_FIRST(&p->iofhd);
963 assert(aior != NULL);
964 STAILQ_REMOVE_HEAD(&p->iofhd, io_list);
969 breq = &aior->io_req;
970 breq->br_offset = lba + done;
971 iovcnt = hdr->prdtl - seek;
972 if (iovcnt > BLOCKIF_IOV_MAX) {
973 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
974 iovcnt = BLOCKIF_IOV_MAX;
977 breq->br_iovcnt = iovcnt;
980 * Build up the iovec based on the prdt
982 for (i = 0; i < iovcnt; i++) {
985 dbcsz = (prdt->dbc & DBCMASK) + 1;
986 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
988 breq->br_iov[i].iov_len = dbcsz;
992 err = blockif_read(p->bctx, breq);
997 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1005 if (len > sizeof(buf))
1007 memset(buf, 0, len);
1008 buf[0] = 0x70 | (1 << 7);
1009 buf[2] = p->sense_key;
1012 write_prdt(p, slot, cfis, buf, len);
1013 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1014 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1018 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1020 uint8_t *acmd = cfis + 0x40;
1023 switch (acmd[4] & 3) {
1027 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1028 tfd = ATA_S_READY | ATA_S_DSC;
1031 /* TODO eject media */
1032 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1033 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1035 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1038 ahci_write_fis_d2h(p, slot, cfis, tfd);
1042 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1050 len = be16dec(acmd + 7);
1052 code = acmd[2] & 0x3f;
1057 case MODEPAGE_RW_ERROR_RECOVERY:
1061 if (len > sizeof(buf))
1064 memset(buf, 0, sizeof(buf));
1065 be16enc(buf, 16 - 2);
1070 write_prdt(p, slot, cfis, buf, len);
1071 tfd = ATA_S_READY | ATA_S_DSC;
1074 case MODEPAGE_CD_CAPABILITIES:
1078 if (len > sizeof(buf))
1081 memset(buf, 0, sizeof(buf));
1082 be16enc(buf, 30 - 2);
1088 be16enc(&buf[18], 2);
1089 be16enc(&buf[20], 512);
1090 write_prdt(p, slot, cfis, buf, len);
1091 tfd = ATA_S_READY | ATA_S_DSC;
1100 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1102 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1107 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1109 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1112 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1113 ahci_write_fis_d2h(p, slot, cfis, tfd);
1117 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1125 /* we don't support asynchronous operation */
1126 if (!(acmd[1] & 1)) {
1127 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1129 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1134 len = be16dec(acmd + 7);
1135 if (len > sizeof(buf))
1138 memset(buf, 0, sizeof(buf));
1139 be16enc(buf, 8 - 2);
1143 write_prdt(p, slot, cfis, buf, len);
1144 tfd = ATA_S_READY | ATA_S_DSC;
1146 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1147 ahci_write_fis_d2h(p, slot, cfis, tfd);
1151 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1161 for (i = 0; i < 16; i++)
1162 DPRINTF("%02x ", acmd[i]);
1168 case TEST_UNIT_READY:
1169 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1170 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1173 atapi_inquiry(p, slot, cfis);
1176 atapi_read_capacity(p, slot, cfis);
1180 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1181 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1184 atapi_read_toc(p, slot, cfis);
1188 atapi_read(p, slot, cfis, 0, 0);
1191 atapi_request_sense(p, slot, cfis);
1193 case START_STOP_UNIT:
1194 atapi_start_stop_unit(p, slot, cfis);
1197 atapi_mode_sense(p, slot, cfis);
1199 case GET_EVENT_STATUS_NOTIFICATION:
1200 atapi_get_event_status_notification(p, slot, cfis);
1203 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1204 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1206 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1207 ATA_S_READY | ATA_S_ERROR);
1213 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1217 case ATA_ATA_IDENTIFY:
1218 handle_identify(p, slot, cfis);
1220 case ATA_SETFEATURES:
1223 case ATA_SF_ENAB_SATA_SF:
1225 case ATA_SATA_SF_AN:
1226 p->tfd = ATA_S_DSC | ATA_S_READY;
1229 p->tfd = ATA_S_ERROR | ATA_S_READY;
1230 p->tfd |= (ATA_ERROR_ABORT << 8);
1234 case ATA_SF_ENAB_WCACHE:
1235 case ATA_SF_DIS_WCACHE:
1236 case ATA_SF_ENAB_RCACHE:
1237 case ATA_SF_DIS_RCACHE:
1238 p->tfd = ATA_S_DSC | ATA_S_READY;
1240 case ATA_SF_SETXFER:
1242 switch (cfis[12] & 0xf8) {
1248 p->xfermode = (cfis[12] & 0x7);
1251 p->tfd = ATA_S_DSC | ATA_S_READY;
1255 p->tfd = ATA_S_ERROR | ATA_S_READY;
1256 p->tfd |= (ATA_ERROR_ABORT << 8);
1259 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1263 if (cfis[12] != 0 &&
1264 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1265 p->tfd = ATA_S_ERROR | ATA_S_READY;
1266 p->tfd |= (ATA_ERROR_ABORT << 8);
1268 p->mult_sectors = cfis[12];
1269 p->tfd = ATA_S_DSC | ATA_S_READY;
1271 p->is |= AHCI_P_IX_DP;
1272 p->ci &= ~(1 << slot);
1273 ahci_generate_intr(p->pr_sc);
1277 case ATA_READ_DMA48:
1278 case ATA_WRITE_DMA48:
1279 case ATA_READ_FPDMA_QUEUED:
1280 case ATA_WRITE_FPDMA_QUEUED:
1281 ahci_handle_dma(p, slot, cfis, 0, 0);
1283 case ATA_FLUSHCACHE:
1284 case ATA_FLUSHCACHE48:
1285 ahci_handle_flush(p, slot, cfis);
1287 case ATA_STANDBY_CMD:
1290 case ATA_STANDBY_IMMEDIATE:
1291 case ATA_IDLE_IMMEDIATE:
1293 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1295 case ATA_ATAPI_IDENTIFY:
1296 handle_atapi_identify(p, slot, cfis);
1298 case ATA_PACKET_CMD:
1300 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1301 p->is |= AHCI_P_IX_TFE;
1302 ahci_generate_intr(p->pr_sc);
1304 handle_packet_cmd(p, slot, cfis);
1307 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1308 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1309 p->is |= AHCI_P_IX_TFE;
1310 ahci_generate_intr(p->pr_sc);
1316 ahci_handle_slot(struct ahci_port *p, int slot)
1318 struct ahci_cmd_hdr *hdr;
1319 struct ahci_prdt_entry *prdt;
1320 struct pci_ahci_softc *sc;
1325 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1326 cfl = (hdr->flags & 0x1f) * 4;
1327 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1328 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1329 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1333 for (i = 0; i < cfl; i++) {
1336 DPRINTF("%02x ", cfis[i]);
1340 for (i = 0; i < hdr->prdtl; i++) {
1341 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1346 if (cfis[0] != FIS_TYPE_REGH2D) {
1347 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1351 if (cfis[1] & 0x80) {
1352 ahci_handle_cmd(p, slot, cfis);
1354 if (cfis[15] & (1 << 2))
1356 else if (p->reset) {
1360 p->ci &= ~(1 << slot);
1365 ahci_handle_port(struct ahci_port *p)
1369 if (!(p->cmd & AHCI_P_CMD_ST))
1373 * Search for any new commands to issue ignoring those that
1374 * are already in-flight.
1376 for (i = 0; (i < 32) && p->ci; i++) {
1377 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1378 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1379 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1380 ahci_handle_slot(p, i);
1386 * blockif callback routine - this runs in the context of the blockif
1387 * i/o thread, so the mutex needs to be acquired.
1390 ata_ioreq_cb(struct blockif_req *br, int err)
1392 struct ahci_cmd_hdr *hdr;
1393 struct ahci_ioreq *aior;
1394 struct ahci_port *p;
1395 struct pci_ahci_softc *sc;
1398 int pending, slot, ncq;
1400 DPRINTF("%s %d\n", __func__, err);
1403 aior = br->br_param;
1407 pending = aior->prdtl;
1409 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1411 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1412 cfis[2] == ATA_READ_FPDMA_QUEUED)
1415 pthread_mutex_lock(&sc->mtx);
1418 * Move the blockif request back to the free list
1420 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1422 if (pending && !err) {
1423 ahci_handle_dma(p, slot, cfis, aior->done,
1424 hdr->prdtl - pending);
1428 if (!err && aior->done == aior->len) {
1429 tfd = ATA_S_READY | ATA_S_DSC;
1433 hdr->prdbc = aior->len;
1435 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1438 p->serr |= (1 << slot);
1442 * This command is now complete.
1444 p->pending &= ~(1 << slot);
1447 p->sact &= ~(1 << slot);
1448 ahci_write_fis_sdb(p, slot, tfd);
1450 ahci_write_fis_d2h(p, slot, cfis, tfd);
1453 pthread_mutex_unlock(&sc->mtx);
1454 DPRINTF("%s exit\n", __func__);
1458 atapi_ioreq_cb(struct blockif_req *br, int err)
1460 struct ahci_cmd_hdr *hdr;
1461 struct ahci_ioreq *aior;
1462 struct ahci_port *p;
1463 struct pci_ahci_softc *sc;
1468 DPRINTF("%s %d\n", __func__, err);
1470 aior = br->br_param;
1474 pending = aior->prdtl;
1476 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1478 pthread_mutex_lock(&sc->mtx);
1481 * Move the blockif request back to the free list
1483 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_list);
1485 if (pending && !err) {
1486 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1490 if (!err && aior->done == aior->len) {
1491 tfd = ATA_S_READY | ATA_S_DSC;
1492 hdr->prdbc = aior->len;
1494 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1496 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1500 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1501 ahci_write_fis_d2h(p, slot, cfis, tfd);
1504 pthread_mutex_unlock(&sc->mtx);
1505 DPRINTF("%s exit\n", __func__);
1509 pci_ahci_ioreq_init(struct ahci_port *pr)
1511 struct ahci_ioreq *vr;
1514 pr->ioqsz = blockif_queuesz(pr->bctx);
1515 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1516 STAILQ_INIT(&pr->iofhd);
1519 * Add all i/o request entries to the free queue
1521 for (i = 0; i < pr->ioqsz; i++) {
1525 vr->io_req.br_callback = ata_ioreq_cb;
1527 vr->io_req.br_callback = atapi_ioreq_cb;
1528 vr->io_req.br_param = vr;
1529 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_list);
1534 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1536 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1537 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1538 struct ahci_port *p = &sc->port[port];
1540 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1541 port, offset, value);
1560 p->ie = value & 0xFDC000FF;
1561 ahci_generate_intr(sc);
1567 if (!(value & AHCI_P_CMD_ST)) {
1568 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
1574 p->cmd |= AHCI_P_CMD_CR;
1575 clb = (uint64_t)p->clbu << 32 | p->clb;
1576 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1577 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1580 if (value & AHCI_P_CMD_FRE) {
1583 p->cmd |= AHCI_P_CMD_FR;
1584 fb = (uint64_t)p->fbu << 32 | p->fb;
1585 /* we don't support FBSCP, so rfis size is 256Bytes */
1586 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1588 p->cmd &= ~AHCI_P_CMD_FR;
1591 if (value & AHCI_P_CMD_CLO) {
1593 p->cmd &= ~AHCI_P_CMD_CLO;
1596 ahci_handle_port(p);
1602 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1605 if (!(p->cmd & AHCI_P_CMD_ST)) {
1606 if (value & ATA_SC_DET_RESET)
1619 ahci_handle_port(p);
1629 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1631 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1639 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1642 if (value & AHCI_GHC_HR)
1644 else if (value & AHCI_GHC_IE) {
1645 sc->ghc |= AHCI_GHC_IE;
1646 ahci_generate_intr(sc);
1651 ahci_generate_intr(sc);
1659 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1660 int baridx, uint64_t offset, int size, uint64_t value)
1662 struct pci_ahci_softc *sc = pi->pi_arg;
1664 assert(baridx == 5);
1667 pthread_mutex_lock(&sc->mtx);
1669 if (offset < AHCI_OFFSET)
1670 pci_ahci_host_write(sc, offset, value);
1671 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1672 pci_ahci_port_write(sc, offset, value);
1674 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1676 pthread_mutex_unlock(&sc->mtx);
1680 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1696 uint32_t *p = &sc->cap;
1697 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1705 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1712 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1715 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1716 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1736 uint32_t *p= &sc->port[port].clb;
1737 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1746 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1747 port, offset, value);
1753 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1754 uint64_t offset, int size)
1756 struct pci_ahci_softc *sc = pi->pi_arg;
1759 assert(baridx == 5);
1762 pthread_mutex_lock(&sc->mtx);
1764 if (offset < AHCI_OFFSET)
1765 value = pci_ahci_host_read(sc, offset);
1766 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1767 value = pci_ahci_port_read(sc, offset);
1770 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
1773 pthread_mutex_unlock(&sc->mtx);
1779 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
1781 char bident[sizeof("XX:X:X")];
1782 struct blockif_ctxt *bctxt;
1783 struct pci_ahci_softc *sc;
1789 fprintf(stderr, "pci_ahci: backing device required\n");
1794 dbg = fopen("/tmp/log", "w+");
1797 sc = calloc(1, sizeof(struct pci_ahci_softc));
1800 sc->ports = MAX_PORTS;
1803 * Only use port 0 for a backing device. All other ports will be
1806 sc->port[0].atapi = atapi;
1809 * Attempt to open the backing image. Use the PCI
1810 * slot/func for the identifier string.
1812 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
1813 bctxt = blockif_open(opts, bident);
1814 if (bctxt == NULL) {
1818 sc->port[0].bctx = bctxt;
1819 sc->port[0].pr_sc = sc;
1822 * Allocate blockif request structures and add them
1825 pci_ahci_ioreq_init(&sc->port[0]);
1827 pthread_mutex_init(&sc->mtx, NULL);
1829 /* Intel ICH8 AHCI */
1830 slots = sc->port[0].ioqsz;
1834 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
1835 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
1836 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
1837 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
1838 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
1840 /* Only port 0 implemented */
1843 sc->cap2 = AHCI_CAP2_APST;
1846 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
1847 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
1848 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
1849 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
1850 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
1851 pci_emul_add_msicap(pi, 1);
1852 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
1853 AHCI_OFFSET + sc->ports * AHCI_STEP);
1855 pci_lintr_request(pi);
1859 blockif_close(sc->port[0].bctx);
1867 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1870 return (pci_ahci_init(ctx, pi, opts, 0));
1874 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
1877 return (pci_ahci_init(ctx, pi, opts, 1));
1881 * Use separate emulation names to distinguish drive and atapi devices
1883 struct pci_devemu pci_de_ahci_hd = {
1884 .pe_emu = "ahci-hd",
1885 .pe_init = pci_ahci_hd_init,
1886 .pe_barwrite = pci_ahci_write,
1887 .pe_barread = pci_ahci_read
1889 PCI_EMUL_SET(pci_de_ahci_hd);
1891 struct pci_devemu pci_de_ahci_cd = {
1892 .pe_emu = "ahci-cd",
1893 .pe_init = pci_ahci_atapi_init,
1894 .pe_barwrite = pci_ahci_write,
1895 .pe_barread = pci_ahci_read
1897 PCI_EMUL_SET(pci_de_ahci_cd);