2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
51 #include <pthread_np.h>
59 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
61 #define PxSIG_ATA 0x00000101 /* ATA drive */
62 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
78 #define TEST_UNIT_READY 0x00
79 #define REQUEST_SENSE 0x03
81 #define START_STOP_UNIT 0x1B
82 #define PREVENT_ALLOW 0x1E
83 #define READ_CAPACITY 0x25
85 #define POSITION_TO_ELEMENT 0x2B
87 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
88 #define MODE_SENSE_10 0x5A
93 * SCSI mode page codes
95 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
96 #define MODEPAGE_CD_CAPABILITIES 0x2A
101 #define ATA_SF_ENAB_SATA_SF 0x10
102 #define ATA_SATA_SF_AN 0x05
103 #define ATA_SF_DIS_SATA_SF 0x90
110 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
112 #define DPRINTF(format, arg...)
114 #define WPRINTF(format, arg...) printf(format, ##arg)
117 struct blockif_req io_req;
118 struct ahci_port *io_pr;
119 STAILQ_ENTRY(ahci_ioreq) io_flist;
120 TAILQ_ENTRY(ahci_ioreq) io_blist;
129 struct blockif_ctxt *bctx;
130 struct pci_ahci_softc *pr_sc;
162 struct ahci_ioreq *ioreq;
164 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
165 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
168 struct ahci_cmd_hdr {
173 uint32_t reserved[4];
176 struct ahci_prdt_entry {
179 #define DBCMASK 0x3fffff
183 struct pci_ahci_softc {
184 struct pci_devinst *asc_pi;
199 struct ahci_port port[MAX_PORTS];
201 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
203 static inline void lba_to_msf(uint8_t *buf, int lba)
206 buf[0] = (lba / 75) / 60;
207 buf[1] = (lba / 75) % 60;
212 * generate HBA intr depending on whether or not ports within
213 * the controller have an interrupt pending.
216 ahci_generate_intr(struct pci_ahci_softc *sc)
218 struct pci_devinst *pi;
223 for (i = 0; i < sc->ports; i++) {
224 struct ahci_port *pr;
230 DPRINTF("%s %x\n", __func__, sc->is);
232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
233 if (pci_msi_enabled(pi)) {
235 * Generate an MSI interrupt on every edge
237 pci_generate_msi(pi, 0);
238 } else if (!sc->lintr) {
240 * Only generate a pin-based interrupt if one wasn't
244 pci_lintr_assert(pi);
246 } else if (sc->lintr) {
248 * No interrupts: deassert pin-based signal if it had
251 pci_lintr_deassert(pi);
257 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
259 int offset, len, irq;
261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
265 case FIS_TYPE_REGD2H:
270 case FIS_TYPE_SETDEVBITS:
275 case FIS_TYPE_PIOSETUP:
281 WPRINTF("unsupported fis type %d\n", ft);
284 memcpy(p->rfis + offset, fis, len);
287 ahci_generate_intr(p->pr_sc);
292 ahci_write_fis_piosetup(struct ahci_port *p)
296 memset(fis, 0, sizeof(fis));
297 fis[0] = FIS_TYPE_PIOSETUP;
298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
302 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
307 error = (tfd >> 8) & 0xff;
308 memset(fis, 0, sizeof(fis));
311 *(uint32_t *)(fis + 4) = (1 << slot);
312 if (fis[2] & ATA_S_ERROR)
313 p->is |= AHCI_P_IX_TFE;
315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
319 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
324 error = (tfd >> 8) & 0xff;
325 memset(fis, 0, sizeof(fis));
326 fis[0] = FIS_TYPE_REGD2H;
340 if (fis[2] & ATA_S_ERROR)
341 p->is |= AHCI_P_IX_TFE;
343 p->ci &= ~(1 << slot);
345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
349 ahci_write_reset_fis_d2h(struct ahci_port *p)
353 memset(fis, 0, sizeof(fis));
354 fis[0] = FIS_TYPE_REGD2H;
362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
366 ahci_check_stopped(struct ahci_port *p)
369 * If we are no longer processing the command list and nothing
370 * is in-flight, clear the running bit, the current command
371 * slot, the command issue and active bits.
373 if (!(p->cmd & AHCI_P_CMD_ST)) {
374 if (p->pending == 0) {
375 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
383 ahci_port_stop(struct ahci_port *p)
385 struct ahci_ioreq *aior;
391 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
393 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
395 * Try to cancel the outstanding blockif request.
397 error = blockif_cancel(p->bctx, &aior->io_req);
403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
404 cfis[2] == ATA_READ_FPDMA_QUEUED)
408 p->sact &= ~(1 << slot);
410 p->ci &= ~(1 << slot);
413 * This command is now done.
415 p->pending &= ~(1 << slot);
418 * Delete the blockif request from the busy list
420 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
423 * Move the blockif request back to the free list
425 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
428 ahci_check_stopped(p);
432 ahci_port_reset(struct ahci_port *pr)
437 pr->xfermode = ATA_UDMA6;
438 pr->mult_sectors = 128;
441 pr->ssts = ATA_SS_DET_NO_DEVICE;
442 pr->sig = 0xFFFFFFFF;
446 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
448 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
451 pr->tfd |= ATA_S_READY;
453 pr->sig = PxSIG_ATAPI;
454 ahci_write_reset_fis_d2h(pr);
458 ahci_reset(struct pci_ahci_softc *sc)
462 sc->ghc = AHCI_GHC_AE;
466 pci_lintr_deassert(sc->asc_pi);
470 for (i = 0; i < sc->ports; i++) {
473 ahci_port_reset(&sc->port[i]);
478 ata_string(uint8_t *dest, const char *src, int len)
482 for (i = 0; i < len; i++) {
484 dest[i ^ 1] = *src++;
491 atapi_string(uint8_t *dest, const char *src, int len)
495 for (i = 0; i < len; i++) {
504 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
507 struct ahci_ioreq *aior;
508 struct blockif_req *breq;
509 struct pci_ahci_softc *sc;
510 struct ahci_prdt_entry *prdt;
511 struct ahci_cmd_hdr *hdr;
514 int i, err, iovcnt, ncq, readop;
517 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
518 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
523 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
524 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
527 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
528 cfis[2] == ATA_READ_FPDMA_QUEUED) {
529 lba = ((uint64_t)cfis[10] << 40) |
530 ((uint64_t)cfis[9] << 32) |
531 ((uint64_t)cfis[8] << 24) |
532 ((uint64_t)cfis[6] << 16) |
533 ((uint64_t)cfis[5] << 8) |
535 len = cfis[11] << 8 | cfis[3];
539 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
540 lba = ((uint64_t)cfis[10] << 40) |
541 ((uint64_t)cfis[9] << 32) |
542 ((uint64_t)cfis[8] << 24) |
543 ((uint64_t)cfis[6] << 16) |
544 ((uint64_t)cfis[5] << 8) |
546 len = cfis[13] << 8 | cfis[12];
550 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
551 (cfis[5] << 8) | cfis[4];
556 lba *= blockif_sectsz(p->bctx);
557 len *= blockif_sectsz(p->bctx);
560 * Pull request off free list
562 aior = STAILQ_FIRST(&p->iofhd);
563 assert(aior != NULL);
564 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
569 breq = &aior->io_req;
570 breq->br_offset = lba + done;
571 iovcnt = hdr->prdtl - seek;
572 if (iovcnt > BLOCKIF_IOV_MAX) {
573 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
574 iovcnt = BLOCKIF_IOV_MAX;
577 breq->br_iovcnt = iovcnt;
580 * Mark this command in-flight.
582 p->pending |= 1 << slot;
585 * Stuff request onto busy list
587 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
590 * Build up the iovec based on the prdt
592 for (i = 0; i < iovcnt; i++) {
595 dbcsz = (prdt->dbc & DBCMASK) + 1;
596 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
598 breq->br_iov[i].iov_len = dbcsz;
603 err = blockif_read(p->bctx, breq);
605 err = blockif_write(p->bctx, breq);
609 p->ci &= ~(1 << slot);
613 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
615 struct ahci_ioreq *aior;
616 struct blockif_req *breq;
620 * Pull request off free list
622 aior = STAILQ_FIRST(&p->iofhd);
623 assert(aior != NULL);
624 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
630 breq = &aior->io_req;
633 * Mark this command in-flight.
635 p->pending |= 1 << slot;
638 * Stuff request onto busy list
640 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
642 err = blockif_flush(p->bctx, breq);
647 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
650 struct ahci_cmd_hdr *hdr;
651 struct ahci_prdt_entry *prdt;
655 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
658 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
659 for (i = 0; i < hdr->prdtl && len; i++) {
664 dbcsz = (prdt->dbc & DBCMASK) + 1;
665 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
666 sublen = len < dbcsz ? len : dbcsz;
667 memcpy(to, ptr, sublen);
675 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
677 struct ahci_ioreq *aior;
678 struct blockif_req *breq;
685 len = (uint16_t)cfis[13] << 8 | cfis[12];
687 read_prdt(p, slot, cfis, buf, sizeof(buf));
691 elba = ((uint64_t)entry[5] << 40) |
692 ((uint64_t)entry[4] << 32) |
693 ((uint64_t)entry[3] << 24) |
694 ((uint64_t)entry[2] << 16) |
695 ((uint64_t)entry[1] << 8) |
697 elen = (uint16_t)entry[7] << 8 | entry[6];
701 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
702 p->pending &= ~(1 << slot);
703 ahci_check_stopped(p);
710 * Pull request off free list
712 aior = STAILQ_FIRST(&p->iofhd);
713 assert(aior != NULL);
714 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
721 breq = &aior->io_req;
722 breq->br_offset = elba * blockif_sectsz(p->bctx);
724 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx);
727 * Mark this command in-flight.
729 p->pending |= 1 << slot;
732 * Stuff request onto busy list
734 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
736 err = blockif_delete(p->bctx, breq);
741 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
744 struct ahci_cmd_hdr *hdr;
745 struct ahci_prdt_entry *prdt;
749 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
752 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
753 for (i = 0; i < hdr->prdtl && len; i++) {
758 dbcsz = (prdt->dbc & DBCMASK) + 1;
759 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
760 sublen = len < dbcsz ? len : dbcsz;
761 memcpy(ptr, from, sublen);
766 hdr->prdbc = size - len;
770 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
772 struct ahci_cmd_hdr *hdr;
774 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
775 if (p->atapi || hdr->prdtl == 0) {
776 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
777 p->is |= AHCI_P_IX_TFE;
781 int sectsz, psectsz, psectoff, candelete, ro;
785 ro = blockif_is_ro(p->bctx);
786 candelete = blockif_candelete(p->bctx);
787 sectsz = blockif_sectsz(p->bctx);
788 sectors = blockif_size(p->bctx) / sectsz;
789 blockif_chs(p->bctx, &cyl, &heads, &sech);
790 blockif_psectsz(p->bctx, &psectsz, &psectoff);
791 memset(buf, 0, sizeof(buf));
796 /* TODO emulate different serial? */
797 ata_string((uint8_t *)(buf+10), "123456", 20);
798 ata_string((uint8_t *)(buf+23), "001", 8);
799 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
800 buf[47] = (0x8000 | 128);
802 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
804 buf[53] = (1 << 1 | 1 << 2);
806 buf[59] = (0x100 | p->mult_sectors);
808 buf[61] = (sectors >> 16);
810 if (p->xfermode & ATA_WDMA0)
811 buf[63] |= (1 << ((p->xfermode & 7) + 8));
819 buf[76] = (1 << 8 | 1 << 2);
822 buf[82] = (1 << 5 | 1 << 14);
823 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
825 buf[85] = (1 << 5 | 1 << 14);
826 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
829 if (p->xfermode & ATA_UDMA0)
830 buf[88] |= (1 << ((p->xfermode & 7) + 8));
831 buf[93] = (1 | 1 <<14);
833 buf[101] = (sectors >> 16);
834 buf[102] = (sectors >> 32);
835 buf[103] = (sectors >> 48);
836 if (candelete && !ro) {
837 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
839 buf[169] = ATA_SUPPORT_DSM_TRIM;
843 if (psectsz > sectsz) {
845 buf[106] |= ffsl(psectsz / sectsz) - 1;
846 buf[209] |= (psectoff / sectsz);
850 buf[117] = sectsz / 2;
851 buf[118] = ((sectsz / 2) >> 16);
853 ahci_write_fis_piosetup(p);
854 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
855 p->tfd = ATA_S_DSC | ATA_S_READY;
856 p->is |= AHCI_P_IX_DP;
857 p->ci &= ~(1 << slot);
859 ahci_generate_intr(p->pr_sc);
863 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
866 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
867 p->is |= AHCI_P_IX_TFE;
871 memset(buf, 0, sizeof(buf));
872 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
873 /* TODO emulate different serial? */
874 ata_string((uint8_t *)(buf+10), "123456", 20);
875 ata_string((uint8_t *)(buf+23), "001", 8);
876 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
877 buf[49] = (1 << 9 | 1 << 8);
878 buf[50] = (1 << 14 | 1);
879 buf[53] = (1 << 2 | 1 << 1);
887 buf[76] = (1 << 2 | 1 << 1);
889 buf[80] = (0x1f << 4);
895 buf[88] = (1 << 14 | 0x7f);
896 ahci_write_fis_piosetup(p);
897 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
898 p->tfd = ATA_S_DSC | ATA_S_READY;
899 p->is |= AHCI_P_IX_DHR;
900 p->ci &= ~(1 << slot);
902 ahci_generate_intr(p->pr_sc);
906 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
922 atapi_string(buf + 8, "BHYVE", 8);
923 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
924 atapi_string(buf + 32, "001", 4);
929 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
930 write_prdt(p, slot, cfis, buf, len);
931 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
935 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
940 sectors = blockif_size(p->bctx) / 2048;
941 be32enc(buf, sectors - 1);
942 be32enc(buf + 4, 2048);
943 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
944 write_prdt(p, slot, cfis, buf, sizeof(buf));
945 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
949 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
957 len = be16dec(acmd + 7);
958 format = acmd[9] >> 6;
964 uint8_t start_track, buf[20], *bp;
966 msf = (acmd[1] >> 1) & 1;
967 start_track = acmd[6];
968 if (start_track > 1 && start_track != 0xaa) {
970 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
972 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
973 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
974 ahci_write_fis_d2h(p, slot, cfis, tfd);
980 if (start_track <= 1) {
1000 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1004 lba_to_msf(bp, sectors);
1007 be32enc(bp, sectors);
1011 be16enc(buf, size - 2);
1014 write_prdt(p, slot, cfis, buf, len);
1015 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1016 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1023 memset(buf, 0, sizeof(buf));
1027 if (len > sizeof(buf))
1029 write_prdt(p, slot, cfis, buf, len);
1030 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1031 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1038 uint8_t start_track, *bp, buf[50];
1040 msf = (acmd[1] >> 1) & 1;
1041 start_track = acmd[6];
1077 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1081 lba_to_msf(bp, sectors);
1084 be32enc(bp, sectors);
1107 be16enc(buf, size - 2);
1110 write_prdt(p, slot, cfis, buf, len);
1111 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1112 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1119 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1121 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1122 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1123 ahci_write_fis_d2h(p, slot, cfis, tfd);
1130 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
1131 uint32_t done, int seek)
1133 struct ahci_ioreq *aior;
1134 struct ahci_cmd_hdr *hdr;
1135 struct ahci_prdt_entry *prdt;
1136 struct blockif_req *breq;
1137 struct pci_ahci_softc *sc;
1145 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1146 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1149 lba = be32dec(acmd + 2);
1150 if (acmd[0] == READ_10)
1151 len = be16dec(acmd + 7);
1153 len = be32dec(acmd + 6);
1155 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1156 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1162 * Pull request off free list
1164 aior = STAILQ_FIRST(&p->iofhd);
1165 assert(aior != NULL);
1166 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1171 breq = &aior->io_req;
1172 breq->br_offset = lba + done;
1173 iovcnt = hdr->prdtl - seek;
1174 if (iovcnt > BLOCKIF_IOV_MAX) {
1175 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
1176 iovcnt = BLOCKIF_IOV_MAX;
1179 breq->br_iovcnt = iovcnt;
1182 * Mark this command in-flight.
1184 p->pending |= 1 << slot;
1187 * Stuff request onto busy list
1189 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1192 * Build up the iovec based on the prdt
1194 for (i = 0; i < iovcnt; i++) {
1197 dbcsz = (prdt->dbc & DBCMASK) + 1;
1198 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
1200 breq->br_iov[i].iov_len = dbcsz;
1201 aior->done += dbcsz;
1204 err = blockif_read(p->bctx, breq);
1209 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1217 if (len > sizeof(buf))
1219 memset(buf, 0, len);
1220 buf[0] = 0x70 | (1 << 7);
1221 buf[2] = p->sense_key;
1224 write_prdt(p, slot, cfis, buf, len);
1225 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1226 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1230 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1232 uint8_t *acmd = cfis + 0x40;
1235 switch (acmd[4] & 3) {
1239 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1240 tfd = ATA_S_READY | ATA_S_DSC;
1243 /* TODO eject media */
1244 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1245 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1247 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1250 ahci_write_fis_d2h(p, slot, cfis, tfd);
1254 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1262 len = be16dec(acmd + 7);
1264 code = acmd[2] & 0x3f;
1269 case MODEPAGE_RW_ERROR_RECOVERY:
1273 if (len > sizeof(buf))
1276 memset(buf, 0, sizeof(buf));
1277 be16enc(buf, 16 - 2);
1282 write_prdt(p, slot, cfis, buf, len);
1283 tfd = ATA_S_READY | ATA_S_DSC;
1286 case MODEPAGE_CD_CAPABILITIES:
1290 if (len > sizeof(buf))
1293 memset(buf, 0, sizeof(buf));
1294 be16enc(buf, 30 - 2);
1300 be16enc(&buf[18], 2);
1301 be16enc(&buf[20], 512);
1302 write_prdt(p, slot, cfis, buf, len);
1303 tfd = ATA_S_READY | ATA_S_DSC;
1312 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1314 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1319 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1321 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1324 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1325 ahci_write_fis_d2h(p, slot, cfis, tfd);
1329 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1337 /* we don't support asynchronous operation */
1338 if (!(acmd[1] & 1)) {
1339 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1341 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1346 len = be16dec(acmd + 7);
1347 if (len > sizeof(buf))
1350 memset(buf, 0, sizeof(buf));
1351 be16enc(buf, 8 - 2);
1355 write_prdt(p, slot, cfis, buf, len);
1356 tfd = ATA_S_READY | ATA_S_DSC;
1358 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1359 ahci_write_fis_d2h(p, slot, cfis, tfd);
1363 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1373 for (i = 0; i < 16; i++)
1374 DPRINTF("%02x ", acmd[i]);
1380 case TEST_UNIT_READY:
1381 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1382 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1385 atapi_inquiry(p, slot, cfis);
1388 atapi_read_capacity(p, slot, cfis);
1392 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1393 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1396 atapi_read_toc(p, slot, cfis);
1400 atapi_read(p, slot, cfis, 0, 0);
1403 atapi_request_sense(p, slot, cfis);
1405 case START_STOP_UNIT:
1406 atapi_start_stop_unit(p, slot, cfis);
1409 atapi_mode_sense(p, slot, cfis);
1411 case GET_EVENT_STATUS_NOTIFICATION:
1412 atapi_get_event_status_notification(p, slot, cfis);
1415 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1416 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1418 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1419 ATA_S_READY | ATA_S_ERROR);
1425 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1429 case ATA_ATA_IDENTIFY:
1430 handle_identify(p, slot, cfis);
1432 case ATA_SETFEATURES:
1435 case ATA_SF_ENAB_SATA_SF:
1437 case ATA_SATA_SF_AN:
1438 p->tfd = ATA_S_DSC | ATA_S_READY;
1441 p->tfd = ATA_S_ERROR | ATA_S_READY;
1442 p->tfd |= (ATA_ERROR_ABORT << 8);
1446 case ATA_SF_ENAB_WCACHE:
1447 case ATA_SF_DIS_WCACHE:
1448 case ATA_SF_ENAB_RCACHE:
1449 case ATA_SF_DIS_RCACHE:
1450 p->tfd = ATA_S_DSC | ATA_S_READY;
1452 case ATA_SF_SETXFER:
1454 switch (cfis[12] & 0xf8) {
1460 p->xfermode = (cfis[12] & 0x7);
1463 p->tfd = ATA_S_DSC | ATA_S_READY;
1467 p->tfd = ATA_S_ERROR | ATA_S_READY;
1468 p->tfd |= (ATA_ERROR_ABORT << 8);
1471 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1475 if (cfis[12] != 0 &&
1476 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1477 p->tfd = ATA_S_ERROR | ATA_S_READY;
1478 p->tfd |= (ATA_ERROR_ABORT << 8);
1480 p->mult_sectors = cfis[12];
1481 p->tfd = ATA_S_DSC | ATA_S_READY;
1483 p->is |= AHCI_P_IX_DP;
1484 p->ci &= ~(1 << slot);
1485 ahci_generate_intr(p->pr_sc);
1489 case ATA_READ_DMA48:
1490 case ATA_WRITE_DMA48:
1491 case ATA_READ_FPDMA_QUEUED:
1492 case ATA_WRITE_FPDMA_QUEUED:
1493 ahci_handle_dma(p, slot, cfis, 0, 0);
1495 case ATA_FLUSHCACHE:
1496 case ATA_FLUSHCACHE48:
1497 ahci_handle_flush(p, slot, cfis);
1499 case ATA_DATA_SET_MANAGEMENT:
1500 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1501 cfis[13] == 0 && cfis[12] == 1) {
1502 ahci_handle_dsm_trim(p, slot, cfis, 0);
1505 ahci_write_fis_d2h(p, slot, cfis,
1506 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1508 case ATA_STANDBY_CMD:
1511 case ATA_STANDBY_IMMEDIATE:
1512 case ATA_IDLE_IMMEDIATE:
1514 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1516 case ATA_ATAPI_IDENTIFY:
1517 handle_atapi_identify(p, slot, cfis);
1519 case ATA_PACKET_CMD:
1521 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1522 p->is |= AHCI_P_IX_TFE;
1523 ahci_generate_intr(p->pr_sc);
1525 handle_packet_cmd(p, slot, cfis);
1528 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1529 p->tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1530 p->is |= AHCI_P_IX_TFE;
1531 ahci_generate_intr(p->pr_sc);
1537 ahci_handle_slot(struct ahci_port *p, int slot)
1539 struct ahci_cmd_hdr *hdr;
1540 struct ahci_prdt_entry *prdt;
1541 struct pci_ahci_softc *sc;
1546 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1547 cfl = (hdr->flags & 0x1f) * 4;
1548 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1549 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1550 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1554 for (i = 0; i < cfl; i++) {
1557 DPRINTF("%02x ", cfis[i]);
1561 for (i = 0; i < hdr->prdtl; i++) {
1562 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1567 if (cfis[0] != FIS_TYPE_REGH2D) {
1568 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1572 if (cfis[1] & 0x80) {
1573 ahci_handle_cmd(p, slot, cfis);
1575 if (cfis[15] & (1 << 2))
1577 else if (p->reset) {
1581 p->ci &= ~(1 << slot);
1586 ahci_handle_port(struct ahci_port *p)
1590 if (!(p->cmd & AHCI_P_CMD_ST))
1594 * Search for any new commands to issue ignoring those that
1595 * are already in-flight.
1597 for (i = 0; (i < 32) && p->ci; i++) {
1598 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1599 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1600 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1601 ahci_handle_slot(p, i);
1607 * blockif callback routine - this runs in the context of the blockif
1608 * i/o thread, so the mutex needs to be acquired.
1611 ata_ioreq_cb(struct blockif_req *br, int err)
1613 struct ahci_cmd_hdr *hdr;
1614 struct ahci_ioreq *aior;
1615 struct ahci_port *p;
1616 struct pci_ahci_softc *sc;
1619 int pending, slot, ncq, dsm;
1621 DPRINTF("%s %d\n", __func__, err);
1624 aior = br->br_param;
1628 pending = aior->prdtl;
1630 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1632 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1633 cfis[2] == ATA_READ_FPDMA_QUEUED)
1635 if (cfis[2] == ATA_DATA_SET_MANAGEMENT)
1638 pthread_mutex_lock(&sc->mtx);
1641 * Delete the blockif request from the busy list
1643 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1646 * Move the blockif request back to the free list
1648 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1651 if (aior->done != aior->len && !err) {
1652 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1656 if (pending && !err) {
1657 ahci_handle_dma(p, slot, cfis, aior->done,
1658 hdr->prdtl - pending);
1663 if (!err && aior->done == aior->len) {
1664 tfd = ATA_S_READY | ATA_S_DSC;
1668 hdr->prdbc = aior->len;
1670 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1673 p->serr |= (1 << slot);
1677 p->sact &= ~(1 << slot);
1678 ahci_write_fis_sdb(p, slot, tfd);
1680 ahci_write_fis_d2h(p, slot, cfis, tfd);
1683 * This command is now complete.
1685 p->pending &= ~(1 << slot);
1687 ahci_check_stopped(p);
1689 pthread_mutex_unlock(&sc->mtx);
1690 DPRINTF("%s exit\n", __func__);
1694 atapi_ioreq_cb(struct blockif_req *br, int err)
1696 struct ahci_cmd_hdr *hdr;
1697 struct ahci_ioreq *aior;
1698 struct ahci_port *p;
1699 struct pci_ahci_softc *sc;
1704 DPRINTF("%s %d\n", __func__, err);
1706 aior = br->br_param;
1710 pending = aior->prdtl;
1712 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1714 pthread_mutex_lock(&sc->mtx);
1717 * Delete the blockif request from the busy list
1719 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1722 * Move the blockif request back to the free list
1724 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1726 if (pending && !err) {
1727 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1731 if (!err && aior->done == aior->len) {
1732 tfd = ATA_S_READY | ATA_S_DSC;
1733 hdr->prdbc = aior->len;
1735 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1737 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1741 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1742 ahci_write_fis_d2h(p, slot, cfis, tfd);
1745 * This command is now complete.
1747 p->pending &= ~(1 << slot);
1749 ahci_check_stopped(p);
1751 pthread_mutex_unlock(&sc->mtx);
1752 DPRINTF("%s exit\n", __func__);
1756 pci_ahci_ioreq_init(struct ahci_port *pr)
1758 struct ahci_ioreq *vr;
1761 pr->ioqsz = blockif_queuesz(pr->bctx);
1762 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1763 STAILQ_INIT(&pr->iofhd);
1766 * Add all i/o request entries to the free queue
1768 for (i = 0; i < pr->ioqsz; i++) {
1772 vr->io_req.br_callback = ata_ioreq_cb;
1774 vr->io_req.br_callback = atapi_ioreq_cb;
1775 vr->io_req.br_param = vr;
1776 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
1779 TAILQ_INIT(&pr->iobhd);
1783 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1785 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1786 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1787 struct ahci_port *p = &sc->port[port];
1789 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1790 port, offset, value);
1809 p->ie = value & 0xFDC000FF;
1810 ahci_generate_intr(sc);
1816 if (!(value & AHCI_P_CMD_ST)) {
1821 p->cmd |= AHCI_P_CMD_CR;
1822 clb = (uint64_t)p->clbu << 32 | p->clb;
1823 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1824 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1827 if (value & AHCI_P_CMD_FRE) {
1830 p->cmd |= AHCI_P_CMD_FR;
1831 fb = (uint64_t)p->fbu << 32 | p->fb;
1832 /* we don't support FBSCP, so rfis size is 256Bytes */
1833 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1835 p->cmd &= ~AHCI_P_CMD_FR;
1838 if (value & AHCI_P_CMD_CLO) {
1840 p->cmd &= ~AHCI_P_CMD_CLO;
1843 ahci_handle_port(p);
1849 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1852 if (!(p->cmd & AHCI_P_CMD_ST)) {
1853 if (value & ATA_SC_DET_RESET)
1866 ahci_handle_port(p);
1876 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1878 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1886 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1889 if (value & AHCI_GHC_HR)
1891 else if (value & AHCI_GHC_IE) {
1892 sc->ghc |= AHCI_GHC_IE;
1893 ahci_generate_intr(sc);
1898 ahci_generate_intr(sc);
1906 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1907 int baridx, uint64_t offset, int size, uint64_t value)
1909 struct pci_ahci_softc *sc = pi->pi_arg;
1911 assert(baridx == 5);
1914 pthread_mutex_lock(&sc->mtx);
1916 if (offset < AHCI_OFFSET)
1917 pci_ahci_host_write(sc, offset, value);
1918 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1919 pci_ahci_port_write(sc, offset, value);
1921 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1923 pthread_mutex_unlock(&sc->mtx);
1927 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1943 uint32_t *p = &sc->cap;
1944 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1952 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1959 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1962 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1963 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1983 uint32_t *p= &sc->port[port].clb;
1984 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1993 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1994 port, offset, value);
2000 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2001 uint64_t offset, int size)
2003 struct pci_ahci_softc *sc = pi->pi_arg;
2006 assert(baridx == 5);
2009 pthread_mutex_lock(&sc->mtx);
2011 if (offset < AHCI_OFFSET)
2012 value = pci_ahci_host_read(sc, offset);
2013 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2014 value = pci_ahci_port_read(sc, offset);
2017 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
2020 pthread_mutex_unlock(&sc->mtx);
2026 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2028 char bident[sizeof("XX:X:X")];
2029 struct blockif_ctxt *bctxt;
2030 struct pci_ahci_softc *sc;
2036 fprintf(stderr, "pci_ahci: backing device required\n");
2041 dbg = fopen("/tmp/log", "w+");
2044 sc = calloc(1, sizeof(struct pci_ahci_softc));
2047 sc->ports = MAX_PORTS;
2050 * Only use port 0 for a backing device. All other ports will be
2053 sc->port[0].atapi = atapi;
2056 * Attempt to open the backing image. Use the PCI
2057 * slot/func for the identifier string.
2059 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
2060 bctxt = blockif_open(opts, bident);
2061 if (bctxt == NULL) {
2065 sc->port[0].bctx = bctxt;
2066 sc->port[0].pr_sc = sc;
2069 * Allocate blockif request structures and add them
2072 pci_ahci_ioreq_init(&sc->port[0]);
2074 pthread_mutex_init(&sc->mtx, NULL);
2076 /* Intel ICH8 AHCI */
2077 slots = sc->port[0].ioqsz;
2081 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2082 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2083 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2084 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2085 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2087 /* Only port 0 implemented */
2090 sc->cap2 = AHCI_CAP2_APST;
2093 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2094 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2095 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2096 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2097 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2098 pci_emul_add_msicap(pi, 1);
2099 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2100 AHCI_OFFSET + sc->ports * AHCI_STEP);
2102 pci_lintr_request(pi);
2106 blockif_close(sc->port[0].bctx);
2114 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2117 return (pci_ahci_init(ctx, pi, opts, 0));
2121 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2124 return (pci_ahci_init(ctx, pi, opts, 1));
2128 * Use separate emulation names to distinguish drive and atapi devices
2130 struct pci_devemu pci_de_ahci_hd = {
2131 .pe_emu = "ahci-hd",
2132 .pe_init = pci_ahci_hd_init,
2133 .pe_barwrite = pci_ahci_write,
2134 .pe_barread = pci_ahci_read
2136 PCI_EMUL_SET(pci_de_ahci_hd);
2138 struct pci_devemu pci_de_ahci_cd = {
2139 .pe_emu = "ahci-cd",
2140 .pe_init = pci_ahci_atapi_init,
2141 .pe_barwrite = pci_ahci_write,
2142 .pe_barread = pci_ahci_read
2144 PCI_EMUL_SET(pci_de_ahci_cd);