2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
51 #include <pthread_np.h>
59 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
61 #define PxSIG_ATA 0x00000101 /* ATA drive */
62 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
78 #define TEST_UNIT_READY 0x00
79 #define REQUEST_SENSE 0x03
81 #define START_STOP_UNIT 0x1B
82 #define PREVENT_ALLOW 0x1E
83 #define READ_CAPACITY 0x25
85 #define POSITION_TO_ELEMENT 0x2B
87 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
88 #define MODE_SENSE_10 0x5A
93 * SCSI mode page codes
95 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
96 #define MODEPAGE_CD_CAPABILITIES 0x2A
101 #define ATA_SF_ENAB_SATA_SF 0x10
102 #define ATA_SATA_SF_AN 0x05
103 #define ATA_SF_DIS_SATA_SF 0x90
110 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
112 #define DPRINTF(format, arg...)
114 #define WPRINTF(format, arg...) printf(format, ##arg)
117 struct blockif_req io_req;
118 struct ahci_port *io_pr;
119 STAILQ_ENTRY(ahci_ioreq) io_flist;
120 TAILQ_ENTRY(ahci_ioreq) io_blist;
129 struct blockif_ctxt *bctx;
130 struct pci_ahci_softc *pr_sc;
162 struct ahci_ioreq *ioreq;
164 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
165 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
168 struct ahci_cmd_hdr {
173 uint32_t reserved[4];
176 struct ahci_prdt_entry {
179 #define DBCMASK 0x3fffff
183 struct pci_ahci_softc {
184 struct pci_devinst *asc_pi;
199 struct ahci_port port[MAX_PORTS];
201 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
203 static inline void lba_to_msf(uint8_t *buf, int lba)
206 buf[0] = (lba / 75) / 60;
207 buf[1] = (lba / 75) % 60;
212 * generate HBA intr depending on whether or not ports within
213 * the controller have an interrupt pending.
216 ahci_generate_intr(struct pci_ahci_softc *sc)
218 struct pci_devinst *pi;
223 for (i = 0; i < sc->ports; i++) {
224 struct ahci_port *pr;
230 DPRINTF("%s %x\n", __func__, sc->is);
232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
233 if (pci_msi_enabled(pi)) {
235 * Generate an MSI interrupt on every edge
237 pci_generate_msi(pi, 0);
238 } else if (!sc->lintr) {
240 * Only generate a pin-based interrupt if one wasn't
244 pci_lintr_assert(pi);
246 } else if (sc->lintr) {
248 * No interrupts: deassert pin-based signal if it had
251 pci_lintr_deassert(pi);
257 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
259 int offset, len, irq;
261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
265 case FIS_TYPE_REGD2H:
270 case FIS_TYPE_SETDEVBITS:
275 case FIS_TYPE_PIOSETUP:
281 WPRINTF("unsupported fis type %d\n", ft);
284 memcpy(p->rfis + offset, fis, len);
287 ahci_generate_intr(p->pr_sc);
292 ahci_write_fis_piosetup(struct ahci_port *p)
296 memset(fis, 0, sizeof(fis));
297 fis[0] = FIS_TYPE_PIOSETUP;
298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
302 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
307 error = (tfd >> 8) & 0xff;
308 memset(fis, 0, sizeof(fis));
311 *(uint32_t *)(fis + 4) = (1 << slot);
312 if (fis[2] & ATA_S_ERROR)
313 p->is |= AHCI_P_IX_TFE;
315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
319 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
324 error = (tfd >> 8) & 0xff;
325 memset(fis, 0, sizeof(fis));
326 fis[0] = FIS_TYPE_REGD2H;
340 if (fis[2] & ATA_S_ERROR)
341 p->is |= AHCI_P_IX_TFE;
343 p->ci &= ~(1 << slot);
345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
349 ahci_write_reset_fis_d2h(struct ahci_port *p)
353 memset(fis, 0, sizeof(fis));
354 fis[0] = FIS_TYPE_REGD2H;
362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
366 ahci_check_stopped(struct ahci_port *p)
369 * If we are no longer processing the command list and nothing
370 * is in-flight, clear the running bit, the current command
371 * slot, the command issue and active bits.
373 if (!(p->cmd & AHCI_P_CMD_ST)) {
374 if (p->pending == 0) {
375 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
383 ahci_port_stop(struct ahci_port *p)
385 struct ahci_ioreq *aior;
391 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
393 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
395 * Try to cancel the outstanding blockif request.
397 error = blockif_cancel(p->bctx, &aior->io_req);
403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
404 cfis[2] == ATA_READ_FPDMA_QUEUED)
408 p->sact &= ~(1 << slot);
410 p->ci &= ~(1 << slot);
413 * This command is now done.
415 p->pending &= ~(1 << slot);
418 * Delete the blockif request from the busy list
420 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
423 * Move the blockif request back to the free list
425 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
428 ahci_check_stopped(p);
432 ahci_port_reset(struct ahci_port *pr)
436 pr->xfermode = ATA_UDMA6;
437 pr->mult_sectors = 128;
440 pr->ssts = ATA_SS_DET_NO_DEVICE;
441 pr->sig = 0xFFFFFFFF;
445 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_IPM_ACTIVE;
446 if (pr->sctl & ATA_SC_SPD_MASK)
447 pr->ssts |= (pr->sctl & ATA_SC_SPD_MASK);
449 pr->ssts |= ATA_SS_SPD_GEN3;
450 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
453 pr->tfd |= ATA_S_READY;
455 pr->sig = PxSIG_ATAPI;
456 ahci_write_reset_fis_d2h(pr);
460 ahci_reset(struct pci_ahci_softc *sc)
464 sc->ghc = AHCI_GHC_AE;
468 pci_lintr_deassert(sc->asc_pi);
472 for (i = 0; i < sc->ports; i++) {
475 sc->port[i].sctl = 0;
476 ahci_port_reset(&sc->port[i]);
481 ata_string(uint8_t *dest, const char *src, int len)
485 for (i = 0; i < len; i++) {
487 dest[i ^ 1] = *src++;
494 atapi_string(uint8_t *dest, const char *src, int len)
498 for (i = 0; i < len; i++) {
507 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
510 struct ahci_ioreq *aior;
511 struct blockif_req *breq;
512 struct pci_ahci_softc *sc;
513 struct ahci_prdt_entry *prdt;
514 struct ahci_cmd_hdr *hdr;
517 int i, err, iovcnt, ncq, readop;
520 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
521 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
526 if (cfis[2] == ATA_WRITE || cfis[2] == ATA_WRITE48 ||
527 cfis[2] == ATA_WRITE_MUL || cfis[2] == ATA_WRITE_MUL48 ||
528 cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
529 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
532 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
533 cfis[2] == ATA_READ_FPDMA_QUEUED) {
534 lba = ((uint64_t)cfis[10] << 40) |
535 ((uint64_t)cfis[9] << 32) |
536 ((uint64_t)cfis[8] << 24) |
537 ((uint64_t)cfis[6] << 16) |
538 ((uint64_t)cfis[5] << 8) |
540 len = cfis[11] << 8 | cfis[3];
544 } else if (cfis[2] == ATA_READ48 || cfis[2] == ATA_WRITE48 ||
545 cfis[2] == ATA_READ_MUL48 || cfis[2] == ATA_WRITE_MUL48 ||
546 cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
547 lba = ((uint64_t)cfis[10] << 40) |
548 ((uint64_t)cfis[9] << 32) |
549 ((uint64_t)cfis[8] << 24) |
550 ((uint64_t)cfis[6] << 16) |
551 ((uint64_t)cfis[5] << 8) |
553 len = cfis[13] << 8 | cfis[12];
557 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
558 (cfis[5] << 8) | cfis[4];
563 lba *= blockif_sectsz(p->bctx);
564 len *= blockif_sectsz(p->bctx);
567 * Pull request off free list
569 aior = STAILQ_FIRST(&p->iofhd);
570 assert(aior != NULL);
571 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
576 breq = &aior->io_req;
577 breq->br_offset = lba + done;
578 iovcnt = hdr->prdtl - seek;
579 if (iovcnt > BLOCKIF_IOV_MAX) {
580 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
581 iovcnt = BLOCKIF_IOV_MAX;
584 breq->br_iovcnt = iovcnt;
587 * Mark this command in-flight.
589 p->pending |= 1 << slot;
592 * Stuff request onto busy list
594 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
597 * Build up the iovec based on the prdt
599 for (i = 0; i < iovcnt; i++) {
602 dbcsz = (prdt->dbc & DBCMASK) + 1;
603 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
605 breq->br_iov[i].iov_len = dbcsz;
610 err = blockif_read(p->bctx, breq);
612 err = blockif_write(p->bctx, breq);
616 p->ci &= ~(1 << slot);
620 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
622 struct ahci_ioreq *aior;
623 struct blockif_req *breq;
627 * Pull request off free list
629 aior = STAILQ_FIRST(&p->iofhd);
630 assert(aior != NULL);
631 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
637 breq = &aior->io_req;
640 * Mark this command in-flight.
642 p->pending |= 1 << slot;
645 * Stuff request onto busy list
647 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
649 err = blockif_flush(p->bctx, breq);
654 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
657 struct ahci_cmd_hdr *hdr;
658 struct ahci_prdt_entry *prdt;
662 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
665 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
666 for (i = 0; i < hdr->prdtl && len; i++) {
671 dbcsz = (prdt->dbc & DBCMASK) + 1;
672 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
673 sublen = len < dbcsz ? len : dbcsz;
674 memcpy(to, ptr, sublen);
682 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
684 struct ahci_ioreq *aior;
685 struct blockif_req *breq;
692 len = (uint16_t)cfis[13] << 8 | cfis[12];
694 read_prdt(p, slot, cfis, buf, sizeof(buf));
698 elba = ((uint64_t)entry[5] << 40) |
699 ((uint64_t)entry[4] << 32) |
700 ((uint64_t)entry[3] << 24) |
701 ((uint64_t)entry[2] << 16) |
702 ((uint64_t)entry[1] << 8) |
704 elen = (uint16_t)entry[7] << 8 | entry[6];
708 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
709 p->pending &= ~(1 << slot);
710 ahci_check_stopped(p);
717 * Pull request off free list
719 aior = STAILQ_FIRST(&p->iofhd);
720 assert(aior != NULL);
721 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
728 breq = &aior->io_req;
729 breq->br_offset = elba * blockif_sectsz(p->bctx);
731 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx);
734 * Mark this command in-flight.
736 p->pending |= 1 << slot;
739 * Stuff request onto busy list
741 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
743 err = blockif_delete(p->bctx, breq);
748 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
751 struct ahci_cmd_hdr *hdr;
752 struct ahci_prdt_entry *prdt;
756 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
759 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
760 for (i = 0; i < hdr->prdtl && len; i++) {
765 dbcsz = (prdt->dbc & DBCMASK) + 1;
766 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
767 sublen = len < dbcsz ? len : dbcsz;
768 memcpy(ptr, from, sublen);
773 hdr->prdbc = size - len;
777 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
779 struct ahci_cmd_hdr *hdr;
781 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
782 if (p->atapi || hdr->prdtl == 0) {
783 ahci_write_fis_d2h(p, slot, cfis,
784 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
788 int sectsz, psectsz, psectoff, candelete, ro;
792 ro = blockif_is_ro(p->bctx);
793 candelete = blockif_candelete(p->bctx);
794 sectsz = blockif_sectsz(p->bctx);
795 sectors = blockif_size(p->bctx) / sectsz;
796 blockif_chs(p->bctx, &cyl, &heads, &sech);
797 blockif_psectsz(p->bctx, &psectsz, &psectoff);
798 memset(buf, 0, sizeof(buf));
803 /* TODO emulate different serial? */
804 ata_string((uint8_t *)(buf+10), "123456", 20);
805 ata_string((uint8_t *)(buf+23), "001", 8);
806 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
807 buf[47] = (0x8000 | 128);
809 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
811 buf[53] = (1 << 1 | 1 << 2);
813 buf[59] = (0x100 | p->mult_sectors);
814 if (sectors <= 0x0fffffff) {
816 buf[61] = (sectors >> 16);
822 if (p->xfermode & ATA_WDMA0)
823 buf[63] |= (1 << ((p->xfermode & 7) + 8));
831 buf[76] = (ATA_SATA_GEN1 | ATA_SATA_GEN2 | ATA_SATA_GEN3 |
835 buf[82] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
836 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
837 buf[83] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
838 ATA_SUPPORT_FLUSHCACHE48 | 1 << 14);
840 buf[85] = (ATA_SUPPORT_POWERMGT | ATA_SUPPORT_WRITECACHE|
841 ATA_SUPPORT_LOOKAHEAD | ATA_SUPPORT_NOP);
842 buf[86] = (ATA_SUPPORT_ADDRESS48 | ATA_SUPPORT_FLUSHCACHE |
843 ATA_SUPPORT_FLUSHCACHE48);
846 if (p->xfermode & ATA_UDMA0)
847 buf[88] |= (1 << ((p->xfermode & 7) + 8));
848 buf[93] = (1 | 1 <<14);
850 buf[101] = (sectors >> 16);
851 buf[102] = (sectors >> 32);
852 buf[103] = (sectors >> 48);
853 if (candelete && !ro) {
854 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
856 buf[169] = ATA_SUPPORT_DSM_TRIM;
860 if (psectsz > sectsz) {
862 buf[106] |= ffsl(psectsz / sectsz) - 1;
863 buf[209] |= (psectoff / sectsz);
867 buf[117] = sectsz / 2;
868 buf[118] = ((sectsz / 2) >> 16);
871 ahci_write_fis_piosetup(p);
872 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
873 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
878 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
881 ahci_write_fis_d2h(p, slot, cfis,
882 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
886 memset(buf, 0, sizeof(buf));
887 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
888 /* TODO emulate different serial? */
889 ata_string((uint8_t *)(buf+10), "123456", 20);
890 ata_string((uint8_t *)(buf+23), "001", 8);
891 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
892 buf[49] = (1 << 9 | 1 << 8);
893 buf[50] = (1 << 14 | 1);
894 buf[53] = (1 << 2 | 1 << 1);
902 buf[76] = (1 << 2 | 1 << 1);
904 buf[80] = (0x1f << 4);
910 buf[88] = (1 << 14 | 0x7f);
911 ahci_write_fis_piosetup(p);
912 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
913 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
918 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
934 atapi_string(buf + 8, "BHYVE", 8);
935 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
936 atapi_string(buf + 32, "001", 4);
941 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
942 write_prdt(p, slot, cfis, buf, len);
943 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
947 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
952 sectors = blockif_size(p->bctx) / 2048;
953 be32enc(buf, sectors - 1);
954 be32enc(buf + 4, 2048);
955 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
956 write_prdt(p, slot, cfis, buf, sizeof(buf));
957 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
961 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
969 len = be16dec(acmd + 7);
970 format = acmd[9] >> 6;
976 uint8_t start_track, buf[20], *bp;
978 msf = (acmd[1] >> 1) & 1;
979 start_track = acmd[6];
980 if (start_track > 1 && start_track != 0xaa) {
982 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
984 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
985 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
986 ahci_write_fis_d2h(p, slot, cfis, tfd);
992 if (start_track <= 1) {
1012 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1016 lba_to_msf(bp, sectors);
1019 be32enc(bp, sectors);
1023 be16enc(buf, size - 2);
1026 write_prdt(p, slot, cfis, buf, len);
1027 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1028 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1035 memset(buf, 0, sizeof(buf));
1039 if (len > sizeof(buf))
1041 write_prdt(p, slot, cfis, buf, len);
1042 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1043 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1050 uint8_t start_track, *bp, buf[50];
1052 msf = (acmd[1] >> 1) & 1;
1053 start_track = acmd[6];
1089 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1093 lba_to_msf(bp, sectors);
1096 be32enc(bp, sectors);
1119 be16enc(buf, size - 2);
1122 write_prdt(p, slot, cfis, buf, len);
1123 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1124 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1131 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1133 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1134 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1135 ahci_write_fis_d2h(p, slot, cfis, tfd);
1142 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
1143 uint32_t done, int seek)
1145 struct ahci_ioreq *aior;
1146 struct ahci_cmd_hdr *hdr;
1147 struct ahci_prdt_entry *prdt;
1148 struct blockif_req *breq;
1149 struct pci_ahci_softc *sc;
1157 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1158 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1161 lba = be32dec(acmd + 2);
1162 if (acmd[0] == READ_10)
1163 len = be16dec(acmd + 7);
1165 len = be32dec(acmd + 6);
1167 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1168 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1174 * Pull request off free list
1176 aior = STAILQ_FIRST(&p->iofhd);
1177 assert(aior != NULL);
1178 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1183 breq = &aior->io_req;
1184 breq->br_offset = lba + done;
1185 iovcnt = hdr->prdtl - seek;
1186 if (iovcnt > BLOCKIF_IOV_MAX) {
1187 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
1188 iovcnt = BLOCKIF_IOV_MAX;
1191 breq->br_iovcnt = iovcnt;
1194 * Mark this command in-flight.
1196 p->pending |= 1 << slot;
1199 * Stuff request onto busy list
1201 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1204 * Build up the iovec based on the prdt
1206 for (i = 0; i < iovcnt; i++) {
1209 dbcsz = (prdt->dbc & DBCMASK) + 1;
1210 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
1212 breq->br_iov[i].iov_len = dbcsz;
1213 aior->done += dbcsz;
1216 err = blockif_read(p->bctx, breq);
1221 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1229 if (len > sizeof(buf))
1231 memset(buf, 0, len);
1232 buf[0] = 0x70 | (1 << 7);
1233 buf[2] = p->sense_key;
1236 write_prdt(p, slot, cfis, buf, len);
1237 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1238 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1242 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1244 uint8_t *acmd = cfis + 0x40;
1247 switch (acmd[4] & 3) {
1251 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1252 tfd = ATA_S_READY | ATA_S_DSC;
1255 /* TODO eject media */
1256 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1257 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1259 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1262 ahci_write_fis_d2h(p, slot, cfis, tfd);
1266 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1274 len = be16dec(acmd + 7);
1276 code = acmd[2] & 0x3f;
1281 case MODEPAGE_RW_ERROR_RECOVERY:
1285 if (len > sizeof(buf))
1288 memset(buf, 0, sizeof(buf));
1289 be16enc(buf, 16 - 2);
1294 write_prdt(p, slot, cfis, buf, len);
1295 tfd = ATA_S_READY | ATA_S_DSC;
1298 case MODEPAGE_CD_CAPABILITIES:
1302 if (len > sizeof(buf))
1305 memset(buf, 0, sizeof(buf));
1306 be16enc(buf, 30 - 2);
1312 be16enc(&buf[18], 2);
1313 be16enc(&buf[20], 512);
1314 write_prdt(p, slot, cfis, buf, len);
1315 tfd = ATA_S_READY | ATA_S_DSC;
1324 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1326 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1331 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1333 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1336 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1337 ahci_write_fis_d2h(p, slot, cfis, tfd);
1341 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1349 /* we don't support asynchronous operation */
1350 if (!(acmd[1] & 1)) {
1351 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1353 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1358 len = be16dec(acmd + 7);
1359 if (len > sizeof(buf))
1362 memset(buf, 0, sizeof(buf));
1363 be16enc(buf, 8 - 2);
1367 write_prdt(p, slot, cfis, buf, len);
1368 tfd = ATA_S_READY | ATA_S_DSC;
1370 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1371 ahci_write_fis_d2h(p, slot, cfis, tfd);
1375 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1385 for (i = 0; i < 16; i++)
1386 DPRINTF("%02x ", acmd[i]);
1392 case TEST_UNIT_READY:
1393 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1394 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1397 atapi_inquiry(p, slot, cfis);
1400 atapi_read_capacity(p, slot, cfis);
1404 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1405 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1408 atapi_read_toc(p, slot, cfis);
1412 atapi_read(p, slot, cfis, 0, 0);
1415 atapi_request_sense(p, slot, cfis);
1417 case START_STOP_UNIT:
1418 atapi_start_stop_unit(p, slot, cfis);
1421 atapi_mode_sense(p, slot, cfis);
1423 case GET_EVENT_STATUS_NOTIFICATION:
1424 atapi_get_event_status_notification(p, slot, cfis);
1427 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1428 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1430 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1431 ATA_S_READY | ATA_S_ERROR);
1437 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1441 case ATA_ATA_IDENTIFY:
1442 handle_identify(p, slot, cfis);
1444 case ATA_SETFEATURES:
1447 case ATA_SF_ENAB_SATA_SF:
1449 case ATA_SATA_SF_AN:
1450 p->tfd = ATA_S_DSC | ATA_S_READY;
1453 p->tfd = ATA_S_ERROR | ATA_S_READY;
1454 p->tfd |= (ATA_ERROR_ABORT << 8);
1458 case ATA_SF_ENAB_WCACHE:
1459 case ATA_SF_DIS_WCACHE:
1460 case ATA_SF_ENAB_RCACHE:
1461 case ATA_SF_DIS_RCACHE:
1462 p->tfd = ATA_S_DSC | ATA_S_READY;
1464 case ATA_SF_SETXFER:
1466 switch (cfis[12] & 0xf8) {
1472 p->xfermode = (cfis[12] & 0x7);
1475 p->tfd = ATA_S_DSC | ATA_S_READY;
1479 p->tfd = ATA_S_ERROR | ATA_S_READY;
1480 p->tfd |= (ATA_ERROR_ABORT << 8);
1483 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1487 if (cfis[12] != 0 &&
1488 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1489 p->tfd = ATA_S_ERROR | ATA_S_READY;
1490 p->tfd |= (ATA_ERROR_ABORT << 8);
1492 p->mult_sectors = cfis[12];
1493 p->tfd = ATA_S_DSC | ATA_S_READY;
1495 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1503 case ATA_READ_MUL48:
1504 case ATA_WRITE_MUL48:
1507 case ATA_READ_DMA48:
1508 case ATA_WRITE_DMA48:
1509 case ATA_READ_FPDMA_QUEUED:
1510 case ATA_WRITE_FPDMA_QUEUED:
1511 ahci_handle_dma(p, slot, cfis, 0, 0);
1513 case ATA_FLUSHCACHE:
1514 case ATA_FLUSHCACHE48:
1515 ahci_handle_flush(p, slot, cfis);
1517 case ATA_DATA_SET_MANAGEMENT:
1518 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1519 cfis[13] == 0 && cfis[12] == 1) {
1520 ahci_handle_dsm_trim(p, slot, cfis, 0);
1523 ahci_write_fis_d2h(p, slot, cfis,
1524 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1526 case ATA_STANDBY_CMD:
1529 case ATA_STANDBY_IMMEDIATE:
1530 case ATA_IDLE_IMMEDIATE:
1532 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1534 case ATA_ATAPI_IDENTIFY:
1535 handle_atapi_identify(p, slot, cfis);
1537 case ATA_PACKET_CMD:
1539 ahci_write_fis_d2h(p, slot, cfis,
1540 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1542 handle_packet_cmd(p, slot, cfis);
1545 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1546 ahci_write_fis_d2h(p, slot, cfis,
1547 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1553 ahci_handle_slot(struct ahci_port *p, int slot)
1555 struct ahci_cmd_hdr *hdr;
1556 struct ahci_prdt_entry *prdt;
1557 struct pci_ahci_softc *sc;
1562 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1563 cfl = (hdr->flags & 0x1f) * 4;
1564 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1565 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1566 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1570 for (i = 0; i < cfl; i++) {
1573 DPRINTF("%02x ", cfis[i]);
1577 for (i = 0; i < hdr->prdtl; i++) {
1578 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1583 if (cfis[0] != FIS_TYPE_REGH2D) {
1584 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1588 if (cfis[1] & 0x80) {
1589 ahci_handle_cmd(p, slot, cfis);
1591 if (cfis[15] & (1 << 2))
1593 else if (p->reset) {
1597 p->ci &= ~(1 << slot);
1602 ahci_handle_port(struct ahci_port *p)
1606 if (!(p->cmd & AHCI_P_CMD_ST))
1610 * Search for any new commands to issue ignoring those that
1611 * are already in-flight.
1613 for (i = 0; (i < 32) && p->ci; i++) {
1614 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1615 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1616 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1617 ahci_handle_slot(p, i);
1623 * blockif callback routine - this runs in the context of the blockif
1624 * i/o thread, so the mutex needs to be acquired.
1627 ata_ioreq_cb(struct blockif_req *br, int err)
1629 struct ahci_cmd_hdr *hdr;
1630 struct ahci_ioreq *aior;
1631 struct ahci_port *p;
1632 struct pci_ahci_softc *sc;
1635 int pending, slot, ncq, dsm;
1637 DPRINTF("%s %d\n", __func__, err);
1640 aior = br->br_param;
1644 pending = aior->prdtl;
1646 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1648 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1649 cfis[2] == ATA_READ_FPDMA_QUEUED)
1651 if (cfis[2] == ATA_DATA_SET_MANAGEMENT)
1654 pthread_mutex_lock(&sc->mtx);
1657 * Delete the blockif request from the busy list
1659 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1662 * Move the blockif request back to the free list
1664 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1667 if (aior->done != aior->len && !err) {
1668 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1672 if (pending && !err) {
1673 ahci_handle_dma(p, slot, cfis, aior->done,
1674 hdr->prdtl - pending);
1679 if (!err && aior->done == aior->len) {
1680 tfd = ATA_S_READY | ATA_S_DSC;
1684 hdr->prdbc = aior->len;
1686 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1689 p->serr |= (1 << slot);
1693 p->sact &= ~(1 << slot);
1694 ahci_write_fis_sdb(p, slot, tfd);
1696 ahci_write_fis_d2h(p, slot, cfis, tfd);
1699 * This command is now complete.
1701 p->pending &= ~(1 << slot);
1703 ahci_check_stopped(p);
1705 pthread_mutex_unlock(&sc->mtx);
1706 DPRINTF("%s exit\n", __func__);
1710 atapi_ioreq_cb(struct blockif_req *br, int err)
1712 struct ahci_cmd_hdr *hdr;
1713 struct ahci_ioreq *aior;
1714 struct ahci_port *p;
1715 struct pci_ahci_softc *sc;
1720 DPRINTF("%s %d\n", __func__, err);
1722 aior = br->br_param;
1726 pending = aior->prdtl;
1728 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1730 pthread_mutex_lock(&sc->mtx);
1733 * Delete the blockif request from the busy list
1735 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1738 * Move the blockif request back to the free list
1740 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1742 if (pending && !err) {
1743 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1747 if (!err && aior->done == aior->len) {
1748 tfd = ATA_S_READY | ATA_S_DSC;
1749 hdr->prdbc = aior->len;
1751 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1753 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1757 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1758 ahci_write_fis_d2h(p, slot, cfis, tfd);
1761 * This command is now complete.
1763 p->pending &= ~(1 << slot);
1765 ahci_check_stopped(p);
1767 pthread_mutex_unlock(&sc->mtx);
1768 DPRINTF("%s exit\n", __func__);
1772 pci_ahci_ioreq_init(struct ahci_port *pr)
1774 struct ahci_ioreq *vr;
1777 pr->ioqsz = blockif_queuesz(pr->bctx);
1778 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1779 STAILQ_INIT(&pr->iofhd);
1782 * Add all i/o request entries to the free queue
1784 for (i = 0; i < pr->ioqsz; i++) {
1788 vr->io_req.br_callback = ata_ioreq_cb;
1790 vr->io_req.br_callback = atapi_ioreq_cb;
1791 vr->io_req.br_param = vr;
1792 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
1795 TAILQ_INIT(&pr->iobhd);
1799 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1801 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1802 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1803 struct ahci_port *p = &sc->port[port];
1805 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1806 port, offset, value);
1825 p->ie = value & 0xFDC000FF;
1826 ahci_generate_intr(sc);
1832 if (!(value & AHCI_P_CMD_ST)) {
1837 p->cmd |= AHCI_P_CMD_CR;
1838 clb = (uint64_t)p->clbu << 32 | p->clb;
1839 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1840 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1843 if (value & AHCI_P_CMD_FRE) {
1846 p->cmd |= AHCI_P_CMD_FR;
1847 fb = (uint64_t)p->fbu << 32 | p->fb;
1848 /* we don't support FBSCP, so rfis size is 256Bytes */
1849 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1851 p->cmd &= ~AHCI_P_CMD_FR;
1854 if (value & AHCI_P_CMD_CLO) {
1856 p->cmd &= ~AHCI_P_CMD_CLO;
1859 ahci_handle_port(p);
1865 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1869 if (!(p->cmd & AHCI_P_CMD_ST)) {
1870 if (value & ATA_SC_DET_RESET)
1882 ahci_handle_port(p);
1892 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1894 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1902 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1905 if (value & AHCI_GHC_HR)
1907 else if (value & AHCI_GHC_IE) {
1908 sc->ghc |= AHCI_GHC_IE;
1909 ahci_generate_intr(sc);
1914 ahci_generate_intr(sc);
1922 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1923 int baridx, uint64_t offset, int size, uint64_t value)
1925 struct pci_ahci_softc *sc = pi->pi_arg;
1927 assert(baridx == 5);
1930 pthread_mutex_lock(&sc->mtx);
1932 if (offset < AHCI_OFFSET)
1933 pci_ahci_host_write(sc, offset, value);
1934 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1935 pci_ahci_port_write(sc, offset, value);
1937 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1939 pthread_mutex_unlock(&sc->mtx);
1943 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1959 uint32_t *p = &sc->cap;
1960 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1968 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1975 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1978 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1979 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1999 uint32_t *p= &sc->port[port].clb;
2000 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
2009 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
2010 port, offset, value);
2016 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
2017 uint64_t offset, int size)
2019 struct pci_ahci_softc *sc = pi->pi_arg;
2022 assert(baridx == 5);
2025 pthread_mutex_lock(&sc->mtx);
2027 if (offset < AHCI_OFFSET)
2028 value = pci_ahci_host_read(sc, offset);
2029 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2030 value = pci_ahci_port_read(sc, offset);
2033 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
2036 pthread_mutex_unlock(&sc->mtx);
2042 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2044 char bident[sizeof("XX:X:X")];
2045 struct blockif_ctxt *bctxt;
2046 struct pci_ahci_softc *sc;
2052 fprintf(stderr, "pci_ahci: backing device required\n");
2057 dbg = fopen("/tmp/log", "w+");
2060 sc = calloc(1, sizeof(struct pci_ahci_softc));
2063 sc->ports = MAX_PORTS;
2066 * Only use port 0 for a backing device. All other ports will be
2069 sc->port[0].atapi = atapi;
2072 * Attempt to open the backing image. Use the PCI
2073 * slot/func for the identifier string.
2075 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
2076 bctxt = blockif_open(opts, bident);
2077 if (bctxt == NULL) {
2081 sc->port[0].bctx = bctxt;
2082 sc->port[0].pr_sc = sc;
2085 * Allocate blockif request structures and add them
2088 pci_ahci_ioreq_init(&sc->port[0]);
2090 pthread_mutex_init(&sc->mtx, NULL);
2092 /* Intel ICH8 AHCI */
2093 slots = sc->port[0].ioqsz;
2097 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2098 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2099 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2100 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2101 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2103 /* Only port 0 implemented */
2106 sc->cap2 = AHCI_CAP2_APST;
2109 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2110 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2111 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2112 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2113 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2114 pci_emul_add_msicap(pi, 1);
2115 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2116 AHCI_OFFSET + sc->ports * AHCI_STEP);
2118 pci_lintr_request(pi);
2122 blockif_close(sc->port[0].bctx);
2130 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2133 return (pci_ahci_init(ctx, pi, opts, 0));
2137 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2140 return (pci_ahci_init(ctx, pi, opts, 1));
2144 * Use separate emulation names to distinguish drive and atapi devices
2146 struct pci_devemu pci_de_ahci_hd = {
2147 .pe_emu = "ahci-hd",
2148 .pe_init = pci_ahci_hd_init,
2149 .pe_barwrite = pci_ahci_write,
2150 .pe_barread = pci_ahci_read
2152 PCI_EMUL_SET(pci_de_ahci_hd);
2154 struct pci_devemu pci_de_ahci_cd = {
2155 .pe_emu = "ahci-cd",
2156 .pe_init = pci_ahci_atapi_init,
2157 .pe_barwrite = pci_ahci_write,
2158 .pe_barread = pci_ahci_read
2160 PCI_EMUL_SET(pci_de_ahci_cd);