2 * Copyright (c) 2013 Zhixiang Yu <zcore@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
29 #include <sys/cdefs.h>
30 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/linker_set.h>
36 #include <sys/ioctl.h>
39 #include <sys/endian.h>
51 #include <pthread_np.h>
59 #define MAX_PORTS 6 /* Intel ICH8 AHCI supports 6 ports */
61 #define PxSIG_ATA 0x00000101 /* ATA drive */
62 #define PxSIG_ATAPI 0xeb140101 /* ATAPI drive */
65 FIS_TYPE_REGH2D = 0x27, /* Register FIS - host to device */
66 FIS_TYPE_REGD2H = 0x34, /* Register FIS - device to host */
67 FIS_TYPE_DMAACT = 0x39, /* DMA activate FIS - device to host */
68 FIS_TYPE_DMASETUP = 0x41, /* DMA setup FIS - bidirectional */
69 FIS_TYPE_DATA = 0x46, /* Data FIS - bidirectional */
70 FIS_TYPE_BIST = 0x58, /* BIST activate FIS - bidirectional */
71 FIS_TYPE_PIOSETUP = 0x5F, /* PIO setup FIS - device to host */
72 FIS_TYPE_SETDEVBITS = 0xA1, /* Set dev bits FIS - device to host */
78 #define TEST_UNIT_READY 0x00
79 #define REQUEST_SENSE 0x03
81 #define START_STOP_UNIT 0x1B
82 #define PREVENT_ALLOW 0x1E
83 #define READ_CAPACITY 0x25
85 #define POSITION_TO_ELEMENT 0x2B
87 #define GET_EVENT_STATUS_NOTIFICATION 0x4A
88 #define MODE_SENSE_10 0x5A
93 * SCSI mode page codes
95 #define MODEPAGE_RW_ERROR_RECOVERY 0x01
96 #define MODEPAGE_CD_CAPABILITIES 0x2A
101 #define ATA_SF_ENAB_SATA_SF 0x10
102 #define ATA_SATA_SF_AN 0x05
103 #define ATA_SF_DIS_SATA_SF 0x90
110 #define DPRINTF(format, arg...) do{fprintf(dbg, format, ##arg);fflush(dbg);}while(0)
112 #define DPRINTF(format, arg...)
114 #define WPRINTF(format, arg...) printf(format, ##arg)
117 struct blockif_req io_req;
118 struct ahci_port *io_pr;
119 STAILQ_ENTRY(ahci_ioreq) io_flist;
120 TAILQ_ENTRY(ahci_ioreq) io_blist;
129 struct blockif_ctxt *bctx;
130 struct pci_ahci_softc *pr_sc;
162 struct ahci_ioreq *ioreq;
164 STAILQ_HEAD(ahci_fhead, ahci_ioreq) iofhd;
165 TAILQ_HEAD(ahci_bhead, ahci_ioreq) iobhd;
168 struct ahci_cmd_hdr {
173 uint32_t reserved[4];
176 struct ahci_prdt_entry {
179 #define DBCMASK 0x3fffff
183 struct pci_ahci_softc {
184 struct pci_devinst *asc_pi;
199 struct ahci_port port[MAX_PORTS];
201 #define ahci_ctx(sc) ((sc)->asc_pi->pi_vmctx)
203 static inline void lba_to_msf(uint8_t *buf, int lba)
206 buf[0] = (lba / 75) / 60;
207 buf[1] = (lba / 75) % 60;
212 * generate HBA intr depending on whether or not ports within
213 * the controller have an interrupt pending.
216 ahci_generate_intr(struct pci_ahci_softc *sc)
218 struct pci_devinst *pi;
223 for (i = 0; i < sc->ports; i++) {
224 struct ahci_port *pr;
230 DPRINTF("%s %x\n", __func__, sc->is);
232 if (sc->is && (sc->ghc & AHCI_GHC_IE)) {
233 if (pci_msi_enabled(pi)) {
235 * Generate an MSI interrupt on every edge
237 pci_generate_msi(pi, 0);
238 } else if (!sc->lintr) {
240 * Only generate a pin-based interrupt if one wasn't
244 pci_lintr_assert(pi);
246 } else if (sc->lintr) {
248 * No interrupts: deassert pin-based signal if it had
251 pci_lintr_deassert(pi);
257 ahci_write_fis(struct ahci_port *p, enum sata_fis_type ft, uint8_t *fis)
259 int offset, len, irq;
261 if (p->rfis == NULL || !(p->cmd & AHCI_P_CMD_FRE))
265 case FIS_TYPE_REGD2H:
270 case FIS_TYPE_SETDEVBITS:
275 case FIS_TYPE_PIOSETUP:
281 WPRINTF("unsupported fis type %d\n", ft);
284 memcpy(p->rfis + offset, fis, len);
287 ahci_generate_intr(p->pr_sc);
292 ahci_write_fis_piosetup(struct ahci_port *p)
296 memset(fis, 0, sizeof(fis));
297 fis[0] = FIS_TYPE_PIOSETUP;
298 ahci_write_fis(p, FIS_TYPE_PIOSETUP, fis);
302 ahci_write_fis_sdb(struct ahci_port *p, int slot, uint32_t tfd)
307 error = (tfd >> 8) & 0xff;
308 memset(fis, 0, sizeof(fis));
311 *(uint32_t *)(fis + 4) = (1 << slot);
312 if (fis[2] & ATA_S_ERROR)
313 p->is |= AHCI_P_IX_TFE;
315 ahci_write_fis(p, FIS_TYPE_SETDEVBITS, fis);
319 ahci_write_fis_d2h(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t tfd)
324 error = (tfd >> 8) & 0xff;
325 memset(fis, 0, sizeof(fis));
326 fis[0] = FIS_TYPE_REGD2H;
340 if (fis[2] & ATA_S_ERROR)
341 p->is |= AHCI_P_IX_TFE;
343 p->ci &= ~(1 << slot);
345 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
349 ahci_write_reset_fis_d2h(struct ahci_port *p)
353 memset(fis, 0, sizeof(fis));
354 fis[0] = FIS_TYPE_REGD2H;
362 ahci_write_fis(p, FIS_TYPE_REGD2H, fis);
366 ahci_check_stopped(struct ahci_port *p)
369 * If we are no longer processing the command list and nothing
370 * is in-flight, clear the running bit, the current command
371 * slot, the command issue and active bits.
373 if (!(p->cmd & AHCI_P_CMD_ST)) {
374 if (p->pending == 0) {
375 p->cmd &= ~(AHCI_P_CMD_CR | AHCI_P_CMD_CCS_MASK);
383 ahci_port_stop(struct ahci_port *p)
385 struct ahci_ioreq *aior;
391 assert(pthread_mutex_isowned_np(&p->pr_sc->mtx));
393 TAILQ_FOREACH(aior, &p->iobhd, io_blist) {
395 * Try to cancel the outstanding blockif request.
397 error = blockif_cancel(p->bctx, &aior->io_req);
403 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
404 cfis[2] == ATA_READ_FPDMA_QUEUED)
408 p->sact &= ~(1 << slot);
410 p->ci &= ~(1 << slot);
413 * This command is now done.
415 p->pending &= ~(1 << slot);
418 * Delete the blockif request from the busy list
420 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
423 * Move the blockif request back to the free list
425 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
428 ahci_check_stopped(p);
432 ahci_port_reset(struct ahci_port *pr)
437 pr->xfermode = ATA_UDMA6;
438 pr->mult_sectors = 128;
441 pr->ssts = ATA_SS_DET_NO_DEVICE;
442 pr->sig = 0xFFFFFFFF;
446 pr->ssts = ATA_SS_DET_PHY_ONLINE | ATA_SS_SPD_GEN2 |
448 pr->tfd = (1 << 8) | ATA_S_DSC | ATA_S_DMA;
451 pr->tfd |= ATA_S_READY;
453 pr->sig = PxSIG_ATAPI;
454 ahci_write_reset_fis_d2h(pr);
458 ahci_reset(struct pci_ahci_softc *sc)
462 sc->ghc = AHCI_GHC_AE;
466 pci_lintr_deassert(sc->asc_pi);
470 for (i = 0; i < sc->ports; i++) {
473 ahci_port_reset(&sc->port[i]);
478 ata_string(uint8_t *dest, const char *src, int len)
482 for (i = 0; i < len; i++) {
484 dest[i ^ 1] = *src++;
491 atapi_string(uint8_t *dest, const char *src, int len)
495 for (i = 0; i < len; i++) {
504 ahci_handle_dma(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done,
507 struct ahci_ioreq *aior;
508 struct blockif_req *breq;
509 struct pci_ahci_softc *sc;
510 struct ahci_prdt_entry *prdt;
511 struct ahci_cmd_hdr *hdr;
514 int i, err, iovcnt, ncq, readop;
517 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
518 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
523 if (cfis[2] == ATA_WRITE_DMA || cfis[2] == ATA_WRITE_DMA48 ||
524 cfis[2] == ATA_WRITE_FPDMA_QUEUED)
527 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
528 cfis[2] == ATA_READ_FPDMA_QUEUED) {
529 lba = ((uint64_t)cfis[10] << 40) |
530 ((uint64_t)cfis[9] << 32) |
531 ((uint64_t)cfis[8] << 24) |
532 ((uint64_t)cfis[6] << 16) |
533 ((uint64_t)cfis[5] << 8) |
535 len = cfis[11] << 8 | cfis[3];
539 } else if (cfis[2] == ATA_READ_DMA48 || cfis[2] == ATA_WRITE_DMA48) {
540 lba = ((uint64_t)cfis[10] << 40) |
541 ((uint64_t)cfis[9] << 32) |
542 ((uint64_t)cfis[8] << 24) |
543 ((uint64_t)cfis[6] << 16) |
544 ((uint64_t)cfis[5] << 8) |
546 len = cfis[13] << 8 | cfis[12];
550 lba = ((cfis[7] & 0xf) << 24) | (cfis[6] << 16) |
551 (cfis[5] << 8) | cfis[4];
556 lba *= blockif_sectsz(p->bctx);
557 len *= blockif_sectsz(p->bctx);
560 * Pull request off free list
562 aior = STAILQ_FIRST(&p->iofhd);
563 assert(aior != NULL);
564 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
569 breq = &aior->io_req;
570 breq->br_offset = lba + done;
571 iovcnt = hdr->prdtl - seek;
572 if (iovcnt > BLOCKIF_IOV_MAX) {
573 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
574 iovcnt = BLOCKIF_IOV_MAX;
577 breq->br_iovcnt = iovcnt;
580 * Mark this command in-flight.
582 p->pending |= 1 << slot;
585 * Stuff request onto busy list
587 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
590 * Build up the iovec based on the prdt
592 for (i = 0; i < iovcnt; i++) {
595 dbcsz = (prdt->dbc & DBCMASK) + 1;
596 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
598 breq->br_iov[i].iov_len = dbcsz;
603 err = blockif_read(p->bctx, breq);
605 err = blockif_write(p->bctx, breq);
609 p->ci &= ~(1 << slot);
613 ahci_handle_flush(struct ahci_port *p, int slot, uint8_t *cfis)
615 struct ahci_ioreq *aior;
616 struct blockif_req *breq;
620 * Pull request off free list
622 aior = STAILQ_FIRST(&p->iofhd);
623 assert(aior != NULL);
624 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
630 breq = &aior->io_req;
633 * Mark this command in-flight.
635 p->pending |= 1 << slot;
638 * Stuff request onto busy list
640 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
642 err = blockif_flush(p->bctx, breq);
647 read_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
650 struct ahci_cmd_hdr *hdr;
651 struct ahci_prdt_entry *prdt;
655 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
658 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
659 for (i = 0; i < hdr->prdtl && len; i++) {
664 dbcsz = (prdt->dbc & DBCMASK) + 1;
665 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
666 sublen = len < dbcsz ? len : dbcsz;
667 memcpy(to, ptr, sublen);
675 ahci_handle_dsm_trim(struct ahci_port *p, int slot, uint8_t *cfis, uint32_t done)
677 struct ahci_ioreq *aior;
678 struct blockif_req *breq;
685 len = (uint16_t)cfis[13] << 8 | cfis[12];
687 read_prdt(p, slot, cfis, buf, sizeof(buf));
691 elba = ((uint64_t)entry[5] << 40) |
692 ((uint64_t)entry[4] << 32) |
693 ((uint64_t)entry[3] << 24) |
694 ((uint64_t)entry[2] << 16) |
695 ((uint64_t)entry[1] << 8) |
697 elen = (uint16_t)entry[7] << 8 | entry[6];
701 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
702 p->pending &= ~(1 << slot);
703 ahci_check_stopped(p);
710 * Pull request off free list
712 aior = STAILQ_FIRST(&p->iofhd);
713 assert(aior != NULL);
714 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
721 breq = &aior->io_req;
722 breq->br_offset = elba * blockif_sectsz(p->bctx);
724 breq->br_iov[0].iov_len = elen * blockif_sectsz(p->bctx);
727 * Mark this command in-flight.
729 p->pending |= 1 << slot;
732 * Stuff request onto busy list
734 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
736 err = blockif_delete(p->bctx, breq);
741 write_prdt(struct ahci_port *p, int slot, uint8_t *cfis,
744 struct ahci_cmd_hdr *hdr;
745 struct ahci_prdt_entry *prdt;
749 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
752 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
753 for (i = 0; i < hdr->prdtl && len; i++) {
758 dbcsz = (prdt->dbc & DBCMASK) + 1;
759 ptr = paddr_guest2host(ahci_ctx(p->pr_sc), prdt->dba, dbcsz);
760 sublen = len < dbcsz ? len : dbcsz;
761 memcpy(ptr, from, sublen);
766 hdr->prdbc = size - len;
770 handle_identify(struct ahci_port *p, int slot, uint8_t *cfis)
772 struct ahci_cmd_hdr *hdr;
774 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
775 if (p->atapi || hdr->prdtl == 0) {
776 ahci_write_fis_d2h(p, slot, cfis,
777 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
781 int sectsz, psectsz, psectoff, candelete, ro;
785 ro = blockif_is_ro(p->bctx);
786 candelete = blockif_candelete(p->bctx);
787 sectsz = blockif_sectsz(p->bctx);
788 sectors = blockif_size(p->bctx) / sectsz;
789 blockif_chs(p->bctx, &cyl, &heads, &sech);
790 blockif_psectsz(p->bctx, &psectsz, &psectoff);
791 memset(buf, 0, sizeof(buf));
796 /* TODO emulate different serial? */
797 ata_string((uint8_t *)(buf+10), "123456", 20);
798 ata_string((uint8_t *)(buf+23), "001", 8);
799 ata_string((uint8_t *)(buf+27), "BHYVE SATA DISK", 40);
800 buf[47] = (0x8000 | 128);
802 buf[49] = (1 << 8 | 1 << 9 | 1 << 11);
804 buf[53] = (1 << 1 | 1 << 2);
806 buf[59] = (0x100 | p->mult_sectors);
808 buf[61] = (sectors >> 16);
810 if (p->xfermode & ATA_WDMA0)
811 buf[63] |= (1 << ((p->xfermode & 7) + 8));
819 buf[76] = (1 << 8 | 1 << 2);
822 buf[82] = (1 << 5 | 1 << 14);
823 buf[83] = (1 << 10 | 1 << 12 | 1 << 13 | 1 << 14);
825 buf[85] = (1 << 5 | 1 << 14);
826 buf[86] = (1 << 10 | 1 << 12 | 1 << 13);
829 if (p->xfermode & ATA_UDMA0)
830 buf[88] |= (1 << ((p->xfermode & 7) + 8));
831 buf[93] = (1 | 1 <<14);
833 buf[101] = (sectors >> 16);
834 buf[102] = (sectors >> 32);
835 buf[103] = (sectors >> 48);
836 if (candelete && !ro) {
837 buf[69] |= ATA_SUPPORT_RZAT | ATA_SUPPORT_DRAT;
839 buf[169] = ATA_SUPPORT_DSM_TRIM;
843 if (psectsz > sectsz) {
845 buf[106] |= ffsl(psectsz / sectsz) - 1;
846 buf[209] |= (psectoff / sectsz);
850 buf[117] = sectsz / 2;
851 buf[118] = ((sectsz / 2) >> 16);
853 ahci_write_fis_piosetup(p);
854 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
855 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
860 handle_atapi_identify(struct ahci_port *p, int slot, uint8_t *cfis)
863 ahci_write_fis_d2h(p, slot, cfis,
864 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
868 memset(buf, 0, sizeof(buf));
869 buf[0] = (2 << 14 | 5 << 8 | 1 << 7 | 2 << 5);
870 /* TODO emulate different serial? */
871 ata_string((uint8_t *)(buf+10), "123456", 20);
872 ata_string((uint8_t *)(buf+23), "001", 8);
873 ata_string((uint8_t *)(buf+27), "BHYVE SATA DVD ROM", 40);
874 buf[49] = (1 << 9 | 1 << 8);
875 buf[50] = (1 << 14 | 1);
876 buf[53] = (1 << 2 | 1 << 1);
884 buf[76] = (1 << 2 | 1 << 1);
886 buf[80] = (0x1f << 4);
892 buf[88] = (1 << 14 | 0x7f);
893 ahci_write_fis_piosetup(p);
894 write_prdt(p, slot, cfis, (void *)buf, sizeof(buf));
895 ahci_write_fis_d2h(p, slot, cfis, ATA_S_DSC | ATA_S_READY);
900 atapi_inquiry(struct ahci_port *p, int slot, uint8_t *cfis)
916 atapi_string(buf + 8, "BHYVE", 8);
917 atapi_string(buf + 16, "BHYVE DVD-ROM", 16);
918 atapi_string(buf + 32, "001", 4);
923 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
924 write_prdt(p, slot, cfis, buf, len);
925 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
929 atapi_read_capacity(struct ahci_port *p, int slot, uint8_t *cfis)
934 sectors = blockif_size(p->bctx) / 2048;
935 be32enc(buf, sectors - 1);
936 be32enc(buf + 4, 2048);
937 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
938 write_prdt(p, slot, cfis, buf, sizeof(buf));
939 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
943 atapi_read_toc(struct ahci_port *p, int slot, uint8_t *cfis)
951 len = be16dec(acmd + 7);
952 format = acmd[9] >> 6;
958 uint8_t start_track, buf[20], *bp;
960 msf = (acmd[1] >> 1) & 1;
961 start_track = acmd[6];
962 if (start_track > 1 && start_track != 0xaa) {
964 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
966 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
967 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
968 ahci_write_fis_d2h(p, slot, cfis, tfd);
974 if (start_track <= 1) {
994 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
998 lba_to_msf(bp, sectors);
1001 be32enc(bp, sectors);
1005 be16enc(buf, size - 2);
1008 write_prdt(p, slot, cfis, buf, len);
1009 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1010 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1017 memset(buf, 0, sizeof(buf));
1021 if (len > sizeof(buf))
1023 write_prdt(p, slot, cfis, buf, len);
1024 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1025 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1032 uint8_t start_track, *bp, buf[50];
1034 msf = (acmd[1] >> 1) & 1;
1035 start_track = acmd[6];
1071 sectors = blockif_size(p->bctx) / blockif_sectsz(p->bctx);
1075 lba_to_msf(bp, sectors);
1078 be32enc(bp, sectors);
1101 be16enc(buf, size - 2);
1104 write_prdt(p, slot, cfis, buf, len);
1105 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1106 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1113 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1115 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1116 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1117 ahci_write_fis_d2h(p, slot, cfis, tfd);
1124 atapi_read(struct ahci_port *p, int slot, uint8_t *cfis,
1125 uint32_t done, int seek)
1127 struct ahci_ioreq *aior;
1128 struct ahci_cmd_hdr *hdr;
1129 struct ahci_prdt_entry *prdt;
1130 struct blockif_req *breq;
1131 struct pci_ahci_softc *sc;
1139 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1140 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1143 lba = be32dec(acmd + 2);
1144 if (acmd[0] == READ_10)
1145 len = be16dec(acmd + 7);
1147 len = be32dec(acmd + 6);
1149 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1150 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1156 * Pull request off free list
1158 aior = STAILQ_FIRST(&p->iofhd);
1159 assert(aior != NULL);
1160 STAILQ_REMOVE_HEAD(&p->iofhd, io_flist);
1165 breq = &aior->io_req;
1166 breq->br_offset = lba + done;
1167 iovcnt = hdr->prdtl - seek;
1168 if (iovcnt > BLOCKIF_IOV_MAX) {
1169 aior->prdtl = iovcnt - BLOCKIF_IOV_MAX;
1170 iovcnt = BLOCKIF_IOV_MAX;
1173 breq->br_iovcnt = iovcnt;
1176 * Mark this command in-flight.
1178 p->pending |= 1 << slot;
1181 * Stuff request onto busy list
1183 TAILQ_INSERT_HEAD(&p->iobhd, aior, io_blist);
1186 * Build up the iovec based on the prdt
1188 for (i = 0; i < iovcnt; i++) {
1191 dbcsz = (prdt->dbc & DBCMASK) + 1;
1192 breq->br_iov[i].iov_base = paddr_guest2host(ahci_ctx(sc),
1194 breq->br_iov[i].iov_len = dbcsz;
1195 aior->done += dbcsz;
1198 err = blockif_read(p->bctx, breq);
1203 atapi_request_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1211 if (len > sizeof(buf))
1213 memset(buf, 0, len);
1214 buf[0] = 0x70 | (1 << 7);
1215 buf[2] = p->sense_key;
1218 write_prdt(p, slot, cfis, buf, len);
1219 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1220 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1224 atapi_start_stop_unit(struct ahci_port *p, int slot, uint8_t *cfis)
1226 uint8_t *acmd = cfis + 0x40;
1229 switch (acmd[4] & 3) {
1233 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1234 tfd = ATA_S_READY | ATA_S_DSC;
1237 /* TODO eject media */
1238 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1239 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1241 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1244 ahci_write_fis_d2h(p, slot, cfis, tfd);
1248 atapi_mode_sense(struct ahci_port *p, int slot, uint8_t *cfis)
1256 len = be16dec(acmd + 7);
1258 code = acmd[2] & 0x3f;
1263 case MODEPAGE_RW_ERROR_RECOVERY:
1267 if (len > sizeof(buf))
1270 memset(buf, 0, sizeof(buf));
1271 be16enc(buf, 16 - 2);
1276 write_prdt(p, slot, cfis, buf, len);
1277 tfd = ATA_S_READY | ATA_S_DSC;
1280 case MODEPAGE_CD_CAPABILITIES:
1284 if (len > sizeof(buf))
1287 memset(buf, 0, sizeof(buf));
1288 be16enc(buf, 30 - 2);
1294 be16enc(&buf[18], 2);
1295 be16enc(&buf[20], 512);
1296 write_prdt(p, slot, cfis, buf, len);
1297 tfd = ATA_S_READY | ATA_S_DSC;
1306 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1308 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1313 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1315 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1318 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1319 ahci_write_fis_d2h(p, slot, cfis, tfd);
1323 atapi_get_event_status_notification(struct ahci_port *p, int slot,
1331 /* we don't support asynchronous operation */
1332 if (!(acmd[1] & 1)) {
1333 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1335 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1340 len = be16dec(acmd + 7);
1341 if (len > sizeof(buf))
1344 memset(buf, 0, sizeof(buf));
1345 be16enc(buf, 8 - 2);
1349 write_prdt(p, slot, cfis, buf, len);
1350 tfd = ATA_S_READY | ATA_S_DSC;
1352 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1353 ahci_write_fis_d2h(p, slot, cfis, tfd);
1357 handle_packet_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1367 for (i = 0; i < 16; i++)
1368 DPRINTF("%02x ", acmd[i]);
1374 case TEST_UNIT_READY:
1375 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1376 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1379 atapi_inquiry(p, slot, cfis);
1382 atapi_read_capacity(p, slot, cfis);
1386 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1387 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1390 atapi_read_toc(p, slot, cfis);
1394 atapi_read(p, slot, cfis, 0, 0);
1397 atapi_request_sense(p, slot, cfis);
1399 case START_STOP_UNIT:
1400 atapi_start_stop_unit(p, slot, cfis);
1403 atapi_mode_sense(p, slot, cfis);
1405 case GET_EVENT_STATUS_NOTIFICATION:
1406 atapi_get_event_status_notification(p, slot, cfis);
1409 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1410 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1412 ahci_write_fis_d2h(p, slot, cfis, (p->sense_key << 12) |
1413 ATA_S_READY | ATA_S_ERROR);
1419 ahci_handle_cmd(struct ahci_port *p, int slot, uint8_t *cfis)
1423 case ATA_ATA_IDENTIFY:
1424 handle_identify(p, slot, cfis);
1426 case ATA_SETFEATURES:
1429 case ATA_SF_ENAB_SATA_SF:
1431 case ATA_SATA_SF_AN:
1432 p->tfd = ATA_S_DSC | ATA_S_READY;
1435 p->tfd = ATA_S_ERROR | ATA_S_READY;
1436 p->tfd |= (ATA_ERROR_ABORT << 8);
1440 case ATA_SF_ENAB_WCACHE:
1441 case ATA_SF_DIS_WCACHE:
1442 case ATA_SF_ENAB_RCACHE:
1443 case ATA_SF_DIS_RCACHE:
1444 p->tfd = ATA_S_DSC | ATA_S_READY;
1446 case ATA_SF_SETXFER:
1448 switch (cfis[12] & 0xf8) {
1454 p->xfermode = (cfis[12] & 0x7);
1457 p->tfd = ATA_S_DSC | ATA_S_READY;
1461 p->tfd = ATA_S_ERROR | ATA_S_READY;
1462 p->tfd |= (ATA_ERROR_ABORT << 8);
1465 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1469 if (cfis[12] != 0 &&
1470 (cfis[12] > 128 || (cfis[12] & (cfis[12] - 1)))) {
1471 p->tfd = ATA_S_ERROR | ATA_S_READY;
1472 p->tfd |= (ATA_ERROR_ABORT << 8);
1474 p->mult_sectors = cfis[12];
1475 p->tfd = ATA_S_DSC | ATA_S_READY;
1477 ahci_write_fis_d2h(p, slot, cfis, p->tfd);
1481 case ATA_READ_DMA48:
1482 case ATA_WRITE_DMA48:
1483 case ATA_READ_FPDMA_QUEUED:
1484 case ATA_WRITE_FPDMA_QUEUED:
1485 ahci_handle_dma(p, slot, cfis, 0, 0);
1487 case ATA_FLUSHCACHE:
1488 case ATA_FLUSHCACHE48:
1489 ahci_handle_flush(p, slot, cfis);
1491 case ATA_DATA_SET_MANAGEMENT:
1492 if (cfis[11] == 0 && cfis[3] == ATA_DSM_TRIM &&
1493 cfis[13] == 0 && cfis[12] == 1) {
1494 ahci_handle_dsm_trim(p, slot, cfis, 0);
1497 ahci_write_fis_d2h(p, slot, cfis,
1498 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1500 case ATA_STANDBY_CMD:
1503 case ATA_STANDBY_IMMEDIATE:
1504 case ATA_IDLE_IMMEDIATE:
1506 ahci_write_fis_d2h(p, slot, cfis, ATA_S_READY | ATA_S_DSC);
1508 case ATA_ATAPI_IDENTIFY:
1509 handle_atapi_identify(p, slot, cfis);
1511 case ATA_PACKET_CMD:
1513 ahci_write_fis_d2h(p, slot, cfis,
1514 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1516 handle_packet_cmd(p, slot, cfis);
1519 WPRINTF("Unsupported cmd:%02x\n", cfis[2]);
1520 ahci_write_fis_d2h(p, slot, cfis,
1521 (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR);
1527 ahci_handle_slot(struct ahci_port *p, int slot)
1529 struct ahci_cmd_hdr *hdr;
1530 struct ahci_prdt_entry *prdt;
1531 struct pci_ahci_softc *sc;
1536 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1537 cfl = (hdr->flags & 0x1f) * 4;
1538 cfis = paddr_guest2host(ahci_ctx(sc), hdr->ctba,
1539 0x80 + hdr->prdtl * sizeof(struct ahci_prdt_entry));
1540 prdt = (struct ahci_prdt_entry *)(cfis + 0x80);
1544 for (i = 0; i < cfl; i++) {
1547 DPRINTF("%02x ", cfis[i]);
1551 for (i = 0; i < hdr->prdtl; i++) {
1552 DPRINTF("%d@%08"PRIx64"\n", prdt->dbc & 0x3fffff, prdt->dba);
1557 if (cfis[0] != FIS_TYPE_REGH2D) {
1558 WPRINTF("Not a H2D FIS:%02x\n", cfis[0]);
1562 if (cfis[1] & 0x80) {
1563 ahci_handle_cmd(p, slot, cfis);
1565 if (cfis[15] & (1 << 2))
1567 else if (p->reset) {
1571 p->ci &= ~(1 << slot);
1576 ahci_handle_port(struct ahci_port *p)
1580 if (!(p->cmd & AHCI_P_CMD_ST))
1584 * Search for any new commands to issue ignoring those that
1585 * are already in-flight.
1587 for (i = 0; (i < 32) && p->ci; i++) {
1588 if ((p->ci & (1 << i)) && !(p->pending & (1 << i))) {
1589 p->cmd &= ~AHCI_P_CMD_CCS_MASK;
1590 p->cmd |= i << AHCI_P_CMD_CCS_SHIFT;
1591 ahci_handle_slot(p, i);
1597 * blockif callback routine - this runs in the context of the blockif
1598 * i/o thread, so the mutex needs to be acquired.
1601 ata_ioreq_cb(struct blockif_req *br, int err)
1603 struct ahci_cmd_hdr *hdr;
1604 struct ahci_ioreq *aior;
1605 struct ahci_port *p;
1606 struct pci_ahci_softc *sc;
1609 int pending, slot, ncq, dsm;
1611 DPRINTF("%s %d\n", __func__, err);
1614 aior = br->br_param;
1618 pending = aior->prdtl;
1620 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + slot * AHCI_CL_SIZE);
1622 if (cfis[2] == ATA_WRITE_FPDMA_QUEUED ||
1623 cfis[2] == ATA_READ_FPDMA_QUEUED)
1625 if (cfis[2] == ATA_DATA_SET_MANAGEMENT)
1628 pthread_mutex_lock(&sc->mtx);
1631 * Delete the blockif request from the busy list
1633 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1636 * Move the blockif request back to the free list
1638 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1641 if (aior->done != aior->len && !err) {
1642 ahci_handle_dsm_trim(p, slot, cfis, aior->done);
1646 if (pending && !err) {
1647 ahci_handle_dma(p, slot, cfis, aior->done,
1648 hdr->prdtl - pending);
1653 if (!err && aior->done == aior->len) {
1654 tfd = ATA_S_READY | ATA_S_DSC;
1658 hdr->prdbc = aior->len;
1660 tfd = (ATA_E_ABORT << 8) | ATA_S_READY | ATA_S_ERROR;
1663 p->serr |= (1 << slot);
1667 p->sact &= ~(1 << slot);
1668 ahci_write_fis_sdb(p, slot, tfd);
1670 ahci_write_fis_d2h(p, slot, cfis, tfd);
1673 * This command is now complete.
1675 p->pending &= ~(1 << slot);
1677 ahci_check_stopped(p);
1679 pthread_mutex_unlock(&sc->mtx);
1680 DPRINTF("%s exit\n", __func__);
1684 atapi_ioreq_cb(struct blockif_req *br, int err)
1686 struct ahci_cmd_hdr *hdr;
1687 struct ahci_ioreq *aior;
1688 struct ahci_port *p;
1689 struct pci_ahci_softc *sc;
1694 DPRINTF("%s %d\n", __func__, err);
1696 aior = br->br_param;
1700 pending = aior->prdtl;
1702 hdr = (struct ahci_cmd_hdr *)(p->cmd_lst + aior->slot * AHCI_CL_SIZE);
1704 pthread_mutex_lock(&sc->mtx);
1707 * Delete the blockif request from the busy list
1709 TAILQ_REMOVE(&p->iobhd, aior, io_blist);
1712 * Move the blockif request back to the free list
1714 STAILQ_INSERT_TAIL(&p->iofhd, aior, io_flist);
1716 if (pending && !err) {
1717 atapi_read(p, slot, cfis, aior->done, hdr->prdtl - pending);
1721 if (!err && aior->done == aior->len) {
1722 tfd = ATA_S_READY | ATA_S_DSC;
1723 hdr->prdbc = aior->len;
1725 p->sense_key = ATA_SENSE_ILLEGAL_REQUEST;
1727 tfd = (p->sense_key << 12) | ATA_S_READY | ATA_S_ERROR;
1731 cfis[4] = (cfis[4] & ~7) | ATA_I_CMD | ATA_I_IN;
1732 ahci_write_fis_d2h(p, slot, cfis, tfd);
1735 * This command is now complete.
1737 p->pending &= ~(1 << slot);
1739 ahci_check_stopped(p);
1741 pthread_mutex_unlock(&sc->mtx);
1742 DPRINTF("%s exit\n", __func__);
1746 pci_ahci_ioreq_init(struct ahci_port *pr)
1748 struct ahci_ioreq *vr;
1751 pr->ioqsz = blockif_queuesz(pr->bctx);
1752 pr->ioreq = calloc(pr->ioqsz, sizeof(struct ahci_ioreq));
1753 STAILQ_INIT(&pr->iofhd);
1756 * Add all i/o request entries to the free queue
1758 for (i = 0; i < pr->ioqsz; i++) {
1762 vr->io_req.br_callback = ata_ioreq_cb;
1764 vr->io_req.br_callback = atapi_ioreq_cb;
1765 vr->io_req.br_param = vr;
1766 STAILQ_INSERT_TAIL(&pr->iofhd, vr, io_flist);
1769 TAILQ_INIT(&pr->iobhd);
1773 pci_ahci_port_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1775 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1776 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1777 struct ahci_port *p = &sc->port[port];
1779 DPRINTF("pci_ahci_port %d: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1780 port, offset, value);
1799 p->ie = value & 0xFDC000FF;
1800 ahci_generate_intr(sc);
1806 if (!(value & AHCI_P_CMD_ST)) {
1811 p->cmd |= AHCI_P_CMD_CR;
1812 clb = (uint64_t)p->clbu << 32 | p->clb;
1813 p->cmd_lst = paddr_guest2host(ahci_ctx(sc), clb,
1814 AHCI_CL_SIZE * AHCI_MAX_SLOTS);
1817 if (value & AHCI_P_CMD_FRE) {
1820 p->cmd |= AHCI_P_CMD_FR;
1821 fb = (uint64_t)p->fbu << 32 | p->fb;
1822 /* we don't support FBSCP, so rfis size is 256Bytes */
1823 p->rfis = paddr_guest2host(ahci_ctx(sc), fb, 256);
1825 p->cmd &= ~AHCI_P_CMD_FR;
1828 if (value & AHCI_P_CMD_CLO) {
1830 p->cmd &= ~AHCI_P_CMD_CLO;
1833 ahci_handle_port(p);
1839 WPRINTF("pci_ahci_port: read only registers 0x%"PRIx64"\n", offset);
1842 if (!(p->cmd & AHCI_P_CMD_ST)) {
1843 if (value & ATA_SC_DET_RESET)
1856 ahci_handle_port(p);
1866 pci_ahci_host_write(struct pci_ahci_softc *sc, uint64_t offset, uint64_t value)
1868 DPRINTF("pci_ahci_host: write offset 0x%"PRIx64" value 0x%"PRIx64"\n",
1876 DPRINTF("pci_ahci_host: read only registers 0x%"PRIx64"\n", offset);
1879 if (value & AHCI_GHC_HR)
1881 else if (value & AHCI_GHC_IE) {
1882 sc->ghc |= AHCI_GHC_IE;
1883 ahci_generate_intr(sc);
1888 ahci_generate_intr(sc);
1896 pci_ahci_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
1897 int baridx, uint64_t offset, int size, uint64_t value)
1899 struct pci_ahci_softc *sc = pi->pi_arg;
1901 assert(baridx == 5);
1904 pthread_mutex_lock(&sc->mtx);
1906 if (offset < AHCI_OFFSET)
1907 pci_ahci_host_write(sc, offset, value);
1908 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
1909 pci_ahci_port_write(sc, offset, value);
1911 WPRINTF("pci_ahci: unknown i/o write offset 0x%"PRIx64"\n", offset);
1913 pthread_mutex_unlock(&sc->mtx);
1917 pci_ahci_host_read(struct pci_ahci_softc *sc, uint64_t offset)
1933 uint32_t *p = &sc->cap;
1934 p += (offset - AHCI_CAP) / sizeof(uint32_t);
1942 DPRINTF("pci_ahci_host: read offset 0x%"PRIx64" value 0x%x\n",
1949 pci_ahci_port_read(struct pci_ahci_softc *sc, uint64_t offset)
1952 int port = (offset - AHCI_OFFSET) / AHCI_STEP;
1953 offset = (offset - AHCI_OFFSET) % AHCI_STEP;
1973 uint32_t *p= &sc->port[port].clb;
1974 p += (offset - AHCI_P_CLB) / sizeof(uint32_t);
1983 DPRINTF("pci_ahci_port %d: read offset 0x%"PRIx64" value 0x%x\n",
1984 port, offset, value);
1990 pci_ahci_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi, int baridx,
1991 uint64_t offset, int size)
1993 struct pci_ahci_softc *sc = pi->pi_arg;
1996 assert(baridx == 5);
1999 pthread_mutex_lock(&sc->mtx);
2001 if (offset < AHCI_OFFSET)
2002 value = pci_ahci_host_read(sc, offset);
2003 else if (offset < AHCI_OFFSET + sc->ports * AHCI_STEP)
2004 value = pci_ahci_port_read(sc, offset);
2007 WPRINTF("pci_ahci: unknown i/o read offset 0x%"PRIx64"\n", offset);
2010 pthread_mutex_unlock(&sc->mtx);
2016 pci_ahci_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts, int atapi)
2018 char bident[sizeof("XX:X:X")];
2019 struct blockif_ctxt *bctxt;
2020 struct pci_ahci_softc *sc;
2026 fprintf(stderr, "pci_ahci: backing device required\n");
2031 dbg = fopen("/tmp/log", "w+");
2034 sc = calloc(1, sizeof(struct pci_ahci_softc));
2037 sc->ports = MAX_PORTS;
2040 * Only use port 0 for a backing device. All other ports will be
2043 sc->port[0].atapi = atapi;
2046 * Attempt to open the backing image. Use the PCI
2047 * slot/func for the identifier string.
2049 snprintf(bident, sizeof(bident), "%d:%d", pi->pi_slot, pi->pi_func);
2050 bctxt = blockif_open(opts, bident);
2051 if (bctxt == NULL) {
2055 sc->port[0].bctx = bctxt;
2056 sc->port[0].pr_sc = sc;
2059 * Allocate blockif request structures and add them
2062 pci_ahci_ioreq_init(&sc->port[0]);
2064 pthread_mutex_init(&sc->mtx, NULL);
2066 /* Intel ICH8 AHCI */
2067 slots = sc->port[0].ioqsz;
2071 sc->cap = AHCI_CAP_64BIT | AHCI_CAP_SNCQ | AHCI_CAP_SSNTF |
2072 AHCI_CAP_SMPS | AHCI_CAP_SSS | AHCI_CAP_SALP |
2073 AHCI_CAP_SAL | AHCI_CAP_SCLO | (0x3 << AHCI_CAP_ISS_SHIFT)|
2074 AHCI_CAP_PMD | AHCI_CAP_SSC | AHCI_CAP_PSC |
2075 (slots << AHCI_CAP_NCS_SHIFT) | AHCI_CAP_SXS | (sc->ports - 1);
2077 /* Only port 0 implemented */
2080 sc->cap2 = AHCI_CAP2_APST;
2083 pci_set_cfgdata16(pi, PCIR_DEVICE, 0x2821);
2084 pci_set_cfgdata16(pi, PCIR_VENDOR, 0x8086);
2085 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_STORAGE);
2086 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_STORAGE_SATA);
2087 pci_set_cfgdata8(pi, PCIR_PROGIF, PCIP_STORAGE_SATA_AHCI_1_0);
2088 pci_emul_add_msicap(pi, 1);
2089 pci_emul_alloc_bar(pi, 5, PCIBAR_MEM32,
2090 AHCI_OFFSET + sc->ports * AHCI_STEP);
2092 pci_lintr_request(pi);
2096 blockif_close(sc->port[0].bctx);
2104 pci_ahci_hd_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2107 return (pci_ahci_init(ctx, pi, opts, 0));
2111 pci_ahci_atapi_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
2114 return (pci_ahci_init(ctx, pi, opts, 1));
2118 * Use separate emulation names to distinguish drive and atapi devices
2120 struct pci_devemu pci_de_ahci_hd = {
2121 .pe_emu = "ahci-hd",
2122 .pe_init = pci_ahci_hd_init,
2123 .pe_barwrite = pci_ahci_write,
2124 .pe_barread = pci_ahci_read
2126 PCI_EMUL_SET(pci_de_ahci_hd);
2128 struct pci_devemu pci_de_ahci_cd = {
2129 .pe_emu = "ahci-cd",
2130 .pe_init = pci_ahci_atapi_init,
2131 .pe_barwrite = pci_ahci_write,
2132 .pe_barread = pci_ahci_read
2134 PCI_EMUL_SET(pci_de_ahci_cd);