2 * Copyright (c) 2013 Neel Natu <neel@freebsd.org>
3 * Copyright (c) 2013 Tycho Nightingale <tycho.nightingale@pluribusnetworks.com>
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
9 * 1. Redistributions of source code must retain the above copyright
10 * notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY NETAPP, INC ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED. IN NO EVENT SHALL NETAPP, INC OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
30 #include <sys/cdefs.h>
31 __FBSDID("$FreeBSD$");
33 #include <sys/types.h>
34 #include <machine/vmm.h>
48 #include "uart_emul.h"
53 SET_DECLARE(lpc_dsdt_set, struct lpc_dsdt);
54 SET_DECLARE(lpc_sysres_set, struct lpc_sysres);
56 #define ELCR_PORT 0x4d0
57 SYSRES_IO(ELCR_PORT, 2);
59 #define IO_TIMER1_PORT 0x40
61 #define NMISC_PORT 0x61
62 SYSRES_IO(NMISC_PORT, 1);
64 static struct pci_devinst *lpc_bridge;
66 static const char *romfile;
68 #define LPC_UART_NUM 2
69 static struct lpc_uart_softc {
70 struct uart_softc *uart_softc;
75 } lpc_uart_softc[LPC_UART_NUM];
77 static const char *lpc_uart_names[LPC_UART_NUM] = { "COM1", "COM2" };
80 * LPC device configuration is in the following form:
81 * <lpc_device_name>[,<options>]
82 * For e.g. "com1,stdio" or "bootrom,/var/romfile"
85 lpc_device_parse(const char *opts)
88 char *str, *cpy, *lpcdev;
91 str = cpy = strdup(opts);
92 lpcdev = strsep(&str, ",");
94 if (strcasecmp(lpcdev, "bootrom") == 0) {
99 for (unit = 0; unit < LPC_UART_NUM; unit++) {
100 if (strcasecmp(lpcdev, lpc_uart_names[unit]) == 0) {
101 lpc_uart_softc[unit].opts = str;
123 lpc_uart_intr_assert(void *arg)
125 struct lpc_uart_softc *sc = arg;
127 assert(sc->irq >= 0);
129 vm_isa_pulse_irq(lpc_bridge->pi_vmctx, sc->irq, sc->irq);
133 lpc_uart_intr_deassert(void *arg)
136 * The COM devices on the LPC bus generate edge triggered interrupts,
137 * so nothing more to do here.
142 lpc_uart_io_handler(struct vmctx *ctx, int vcpu, int in, int port, int bytes,
143 uint32_t *eax, void *arg)
146 struct lpc_uart_softc *sc = arg;
148 offset = port - sc->iobase;
153 *eax = uart_read(sc->uart_softc, offset);
155 uart_write(sc->uart_softc, offset, *eax);
159 *eax = uart_read(sc->uart_softc, offset);
160 *eax |= uart_read(sc->uart_softc, offset + 1) << 8;
162 uart_write(sc->uart_softc, offset, *eax);
163 uart_write(sc->uart_softc, offset + 1, *eax >> 8);
174 lpc_init(struct vmctx *ctx)
176 struct lpc_uart_softc *sc;
177 struct inout_port iop;
181 if (romfile != NULL) {
182 error = bootrom_init(ctx, romfile);
188 for (unit = 0; unit < LPC_UART_NUM; unit++) {
189 sc = &lpc_uart_softc[unit];
190 name = lpc_uart_names[unit];
192 if (uart_legacy_alloc(unit, &sc->iobase, &sc->irq) != 0) {
193 fprintf(stderr, "Unable to allocate resources for "
194 "LPC device %s\n", name);
197 pci_irq_reserve(sc->irq);
199 sc->uart_softc = uart_init(lpc_uart_intr_assert,
200 lpc_uart_intr_deassert, sc);
202 if (uart_set_backend(sc->uart_softc, sc->opts) != 0) {
203 fprintf(stderr, "Unable to initialize backend '%s' "
204 "for LPC device %s\n", sc->opts, name);
208 bzero(&iop, sizeof(struct inout_port));
210 iop.port = sc->iobase;
211 iop.size = UART_IO_BAR_SIZE;
212 iop.flags = IOPORT_F_INOUT;
213 iop.handler = lpc_uart_io_handler;
216 error = register_inout(&iop);
225 pci_lpc_write_dsdt(struct pci_devinst *pi)
227 struct lpc_dsdt **ldpp, *ldp;
230 dsdt_line("Device (ISA)");
232 dsdt_line(" Name (_ADR, 0x%04X%04X)", pi->pi_slot, pi->pi_func);
233 dsdt_line(" OperationRegion (LPCR, PCI_Config, 0x00, 0x100)");
234 dsdt_line(" Field (LPCR, AnyAcc, NoLock, Preserve)");
236 dsdt_line(" Offset (0x60),");
237 dsdt_line(" PIRA, 8,");
238 dsdt_line(" PIRB, 8,");
239 dsdt_line(" PIRC, 8,");
240 dsdt_line(" PIRD, 8,");
241 dsdt_line(" Offset (0x68),");
242 dsdt_line(" PIRE, 8,");
243 dsdt_line(" PIRF, 8,");
244 dsdt_line(" PIRG, 8,");
245 dsdt_line(" PIRH, 8");
250 SET_FOREACH(ldpp, lpc_dsdt_set) {
256 dsdt_line("Device (PIC)");
258 dsdt_line(" Name (_HID, EisaId (\"PNP0000\"))");
259 dsdt_line(" Name (_CRS, ResourceTemplate ()");
262 dsdt_fixed_ioport(IO_ICU1, 2);
263 dsdt_fixed_ioport(IO_ICU2, 2);
270 dsdt_line("Device (TIMR)");
272 dsdt_line(" Name (_HID, EisaId (\"PNP0100\"))");
273 dsdt_line(" Name (_CRS, ResourceTemplate ()");
276 dsdt_fixed_ioport(IO_TIMER1_PORT, 4);
287 pci_lpc_sysres_dsdt(void)
289 struct lpc_sysres **lspp, *lsp;
292 dsdt_line("Device (SIO)");
294 dsdt_line(" Name (_HID, EisaId (\"PNP0C02\"))");
295 dsdt_line(" Name (_CRS, ResourceTemplate ()");
299 SET_FOREACH(lspp, lpc_sysres_set) {
303 dsdt_fixed_ioport(lsp->base, lsp->length);
306 dsdt_fixed_mem32(lsp->base, lsp->length);
315 LPC_DSDT(pci_lpc_sysres_dsdt);
318 pci_lpc_uart_dsdt(void)
320 struct lpc_uart_softc *sc;
323 for (unit = 0; unit < LPC_UART_NUM; unit++) {
324 sc = &lpc_uart_softc[unit];
328 dsdt_line("Device (%s)", lpc_uart_names[unit]);
330 dsdt_line(" Name (_HID, EisaId (\"PNP0501\"))");
331 dsdt_line(" Name (_UID, %d)", unit + 1);
332 dsdt_line(" Name (_CRS, ResourceTemplate ()");
335 dsdt_fixed_ioport(sc->iobase, UART_IO_BAR_SIZE);
336 dsdt_fixed_irq(sc->irq);
342 LPC_DSDT(pci_lpc_uart_dsdt);
345 pci_lpc_cfgwrite(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
346 int coff, int bytes, uint32_t val)
352 if (coff >= 0x60 && coff <= 0x63)
353 pirq_pin = coff - 0x60 + 1;
354 if (coff >= 0x68 && coff <= 0x6b)
355 pirq_pin = coff - 0x68 + 5;
357 pirq_write(ctx, pirq_pin, val);
358 pci_set_cfgdata8(pi, coff, pirq_read(pirq_pin));
366 pci_lpc_write(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
367 int baridx, uint64_t offset, int size, uint64_t value)
372 pci_lpc_read(struct vmctx *ctx, int vcpu, struct pci_devinst *pi,
373 int baridx, uint64_t offset, int size)
378 #define LPC_DEV 0x7000
379 #define LPC_VENDOR 0x8086
382 pci_lpc_init(struct vmctx *ctx, struct pci_devinst *pi, char *opts)
386 * Do not allow more than one LPC bridge to be configured.
388 if (lpc_bridge != NULL) {
389 fprintf(stderr, "Only one LPC bridge is allowed.\n");
394 * Enforce that the LPC can only be configured on bus 0. This
395 * simplifies the ACPI DSDT because it can provide a decode for
396 * all legacy i/o ports behind bus 0.
398 if (pi->pi_bus != 0) {
399 fprintf(stderr, "LPC bridge can be present only on bus 0.\n");
403 if (lpc_init(ctx) != 0)
406 /* initialize config space */
407 pci_set_cfgdata16(pi, PCIR_DEVICE, LPC_DEV);
408 pci_set_cfgdata16(pi, PCIR_VENDOR, LPC_VENDOR);
409 pci_set_cfgdata8(pi, PCIR_CLASS, PCIC_BRIDGE);
410 pci_set_cfgdata8(pi, PCIR_SUBCLASS, PCIS_BRIDGE_ISA);
418 lpc_pirq_name(int pin)
422 if (lpc_bridge == NULL)
424 asprintf(&name, "\\_SB.PC00.ISA.LNK%c,", 'A' + pin - 1);
429 lpc_pirq_routed(void)
433 if (lpc_bridge == NULL)
436 for (pin = 0; pin < 4; pin++)
437 pci_set_cfgdata8(lpc_bridge, 0x60 + pin, pirq_read(pin + 1));
438 for (pin = 0; pin < 4; pin++)
439 pci_set_cfgdata8(lpc_bridge, 0x68 + pin, pirq_read(pin + 5));
442 struct pci_devemu pci_de_lpc = {
444 .pe_init = pci_lpc_init,
445 .pe_write_dsdt = pci_lpc_write_dsdt,
446 .pe_cfgwrite = pci_lpc_cfgwrite,
447 .pe_barwrite = pci_lpc_write,
448 .pe_barread = pci_lpc_read
450 PCI_EMUL_SET(pci_de_lpc);