1 /* i386.c -- Assemble code for the Intel 80386
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003, 2004
4 Free Software Foundation, Inc.
6 This file is part of GAS, the GNU Assembler.
8 GAS is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2, or (at your option)
13 GAS is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with GAS; see the file COPYING. If not, write to the Free
20 Software Foundation, 59 Temple Place - Suite 330, Boston, MA
23 /* Intel 80386 machine specific gas.
24 Written by Eliot Dresselhaus (eliot@mgm.mit.edu).
25 x86_64 support by Jan Hubicka (jh@suse.cz)
26 VIA PadLock support by Michal Ludvig (mludvig@suse.cz)
27 Bugs & suggestions are completely welcome. This is free software.
28 Please help us make it better. */
31 #include "safe-ctype.h"
33 #include "dwarf2dbg.h"
34 #include "dw2gencfi.h"
35 #include "opcode/i386.h"
37 #ifndef REGISTER_WARNINGS
38 #define REGISTER_WARNINGS 1
41 #ifndef INFER_ADDR_PREFIX
42 #define INFER_ADDR_PREFIX 1
45 #ifndef SCALE1_WHEN_NO_INDEX
46 /* Specifying a scale factor besides 1 when there is no index is
47 futile. eg. `mov (%ebx,2),%al' does exactly the same as
48 `mov (%ebx),%al'. To slavishly follow what the programmer
49 specified, set SCALE1_WHEN_NO_INDEX to 0. */
50 #define SCALE1_WHEN_NO_INDEX 1
54 #define DEFAULT_ARCH "i386"
59 #define INLINE __inline__
65 static INLINE unsigned int mode_from_disp_size PARAMS ((unsigned int));
66 static INLINE int fits_in_signed_byte PARAMS ((offsetT));
67 static INLINE int fits_in_unsigned_byte PARAMS ((offsetT));
68 static INLINE int fits_in_unsigned_word PARAMS ((offsetT));
69 static INLINE int fits_in_signed_word PARAMS ((offsetT));
70 static INLINE int fits_in_unsigned_long PARAMS ((offsetT));
71 static INLINE int fits_in_signed_long PARAMS ((offsetT));
72 static int smallest_imm_type PARAMS ((offsetT));
73 static offsetT offset_in_range PARAMS ((offsetT, int));
74 static int add_prefix PARAMS ((unsigned int));
75 static void set_code_flag PARAMS ((int));
76 static void set_16bit_gcc_code_flag PARAMS ((int));
77 static void set_intel_syntax PARAMS ((int));
78 static void set_cpu_arch PARAMS ((int));
79 static char *output_invalid PARAMS ((int c));
80 static int i386_operand PARAMS ((char *operand_string));
81 static int i386_intel_operand PARAMS ((char *operand_string, int got_a_float));
82 static const reg_entry *parse_register PARAMS ((char *reg_string,
84 static char *parse_insn PARAMS ((char *, char *));
85 static char *parse_operands PARAMS ((char *, const char *));
86 static void swap_operands PARAMS ((void));
87 static void optimize_imm PARAMS ((void));
88 static void optimize_disp PARAMS ((void));
89 static int match_template PARAMS ((void));
90 static int check_string PARAMS ((void));
91 static int process_suffix PARAMS ((void));
92 static int check_byte_reg PARAMS ((void));
93 static int check_long_reg PARAMS ((void));
94 static int check_qword_reg PARAMS ((void));
95 static int check_word_reg PARAMS ((void));
96 static int finalize_imm PARAMS ((void));
97 static int process_operands PARAMS ((void));
98 static const seg_entry *build_modrm_byte PARAMS ((void));
99 static void output_insn PARAMS ((void));
100 static void output_branch PARAMS ((void));
101 static void output_jump PARAMS ((void));
102 static void output_interseg_jump PARAMS ((void));
103 static void output_imm PARAMS ((fragS *insn_start_frag,
104 offsetT insn_start_off));
105 static void output_disp PARAMS ((fragS *insn_start_frag,
106 offsetT insn_start_off));
108 static void s_bss PARAMS ((int));
111 static const char *default_arch = DEFAULT_ARCH;
113 /* 'md_assemble ()' gathers together information and puts it into a
120 const reg_entry *regs;
125 /* TM holds the template for the insn were currently assembling. */
128 /* SUFFIX holds the instruction mnemonic suffix if given.
129 (e.g. 'l' for 'movl') */
132 /* OPERANDS gives the number of given operands. */
133 unsigned int operands;
135 /* REG_OPERANDS, DISP_OPERANDS, MEM_OPERANDS, IMM_OPERANDS give the number
136 of given register, displacement, memory operands and immediate
138 unsigned int reg_operands, disp_operands, mem_operands, imm_operands;
140 /* TYPES [i] is the type (see above #defines) which tells us how to
141 use OP[i] for the corresponding operand. */
142 unsigned int types[MAX_OPERANDS];
144 /* Displacement expression, immediate expression, or register for each
146 union i386_op op[MAX_OPERANDS];
148 /* Flags for operands. */
149 unsigned int flags[MAX_OPERANDS];
150 #define Operand_PCrel 1
152 /* Relocation type for operand */
153 enum bfd_reloc_code_real reloc[MAX_OPERANDS];
155 /* BASE_REG, INDEX_REG, and LOG2_SCALE_FACTOR are used to encode
156 the base index byte below. */
157 const reg_entry *base_reg;
158 const reg_entry *index_reg;
159 unsigned int log2_scale_factor;
161 /* SEG gives the seg_entries of this insn. They are zero unless
162 explicit segment overrides are given. */
163 const seg_entry *seg[2];
165 /* PREFIX holds all the given prefix opcodes (usually null).
166 PREFIXES is the number of prefix opcodes. */
167 unsigned int prefixes;
168 unsigned char prefix[MAX_PREFIXES];
170 /* RM and SIB are the modrm byte and the sib byte where the
171 addressing modes of this insn are encoded. */
178 typedef struct _i386_insn i386_insn;
180 /* List of chars besides those in app.c:symbol_chars that can start an
181 operand. Used to prevent the scrubber eating vital white-space. */
183 const char extra_symbol_chars[] = "*%-(@[";
185 const char extra_symbol_chars[] = "*%-([";
188 #if (defined (TE_I386AIX) \
189 || ((defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)) \
190 && !defined (TE_LINUX) \
191 && !defined (TE_FreeBSD) \
192 && !defined (TE_NetBSD)))
193 /* This array holds the chars that always start a comment. If the
194 pre-processor is disabled, these aren't very useful. */
195 const char comment_chars[] = "#/";
196 #define PREFIX_SEPARATOR '\\'
198 /* This array holds the chars that only start a comment at the beginning of
199 a line. If the line seems to have the form '# 123 filename'
200 .line and .file directives will appear in the pre-processed output.
201 Note that input_file.c hand checks for '#' at the beginning of the
202 first line of the input file. This is because the compiler outputs
203 #NO_APP at the beginning of its output.
204 Also note that comments started like this one will always work if
205 '/' isn't otherwise defined. */
206 const char line_comment_chars[] = "#";
209 /* Putting '/' here makes it impossible to use the divide operator.
210 However, we need it for compatibility with SVR4 systems. */
211 const char comment_chars[] = "#";
212 #define PREFIX_SEPARATOR '/'
214 const char line_comment_chars[] = "/#";
217 const char line_separator_chars[] = ";";
219 /* Chars that can be used to separate mant from exp in floating point
221 const char EXP_CHARS[] = "eE";
223 /* Chars that mean this number is a floating point constant
226 const char FLT_CHARS[] = "fFdDxX";
228 /* Tables for lexical analysis. */
229 static char mnemonic_chars[256];
230 static char register_chars[256];
231 static char operand_chars[256];
232 static char identifier_chars[256];
233 static char digit_chars[256];
235 /* Lexical macros. */
236 #define is_mnemonic_char(x) (mnemonic_chars[(unsigned char) x])
237 #define is_operand_char(x) (operand_chars[(unsigned char) x])
238 #define is_register_char(x) (register_chars[(unsigned char) x])
239 #define is_space_char(x) ((x) == ' ')
240 #define is_identifier_char(x) (identifier_chars[(unsigned char) x])
241 #define is_digit_char(x) (digit_chars[(unsigned char) x])
243 /* All non-digit non-letter characters that may occur in an operand. */
244 static char operand_special_chars[] = "%$-+(,)*._~/<>|&^!:[@]";
246 /* md_assemble() always leaves the strings it's passed unaltered. To
247 effect this we maintain a stack of saved characters that we've smashed
248 with '\0's (indicating end of strings for various sub-fields of the
249 assembler instruction). */
250 static char save_stack[32];
251 static char *save_stack_p;
252 #define END_STRING_AND_SAVE(s) \
253 do { *save_stack_p++ = *(s); *(s) = '\0'; } while (0)
254 #define RESTORE_END_STRING(s) \
255 do { *(s) = *--save_stack_p; } while (0)
257 /* The instruction we're assembling. */
260 /* Possible templates for current insn. */
261 static const templates *current_templates;
263 /* Per instruction expressionS buffers: 2 displacements & 2 immediate max. */
264 static expressionS disp_expressions[2], im_expressions[2];
266 /* Current operand we are working on. */
267 static int this_operand;
269 /* We support four different modes. FLAG_CODE variable is used to distinguish
276 #define NUM_FLAG_CODE ((int) CODE_64BIT + 1)
278 static enum flag_code flag_code;
279 static int use_rela_relocations = 0;
281 /* The names used to print error messages. */
282 static const char *flag_code_names[] =
289 /* 1 for intel syntax,
291 static int intel_syntax = 0;
293 /* 1 if register prefix % not required. */
294 static int allow_naked_reg = 0;
296 /* Used in 16 bit gcc mode to add an l suffix to call, ret, enter,
297 leave, push, and pop instructions so that gcc has the same stack
298 frame as in 32 bit mode. */
299 static char stackop_size = '\0';
301 /* Non-zero to optimize code alignment. */
302 int optimize_align_code = 1;
304 /* Non-zero to quieten some warnings. */
305 static int quiet_warnings = 0;
308 static const char *cpu_arch_name = NULL;
310 /* CPU feature flags. */
311 static unsigned int cpu_arch_flags = CpuUnknownFlags | CpuNo64;
313 /* If set, conditional jumps are not automatically promoted to handle
314 larger than a byte offset. */
315 static unsigned int no_cond_jump_promotion = 0;
317 /* Pre-defined "_GLOBAL_OFFSET_TABLE_". */
320 /* The dwarf2 return column, adjusted for 32 or 64 bit. */
321 unsigned int x86_dwarf2_return_column;
323 /* The dwarf2 data alignment, adjusted for 32 or 64 bit. */
324 int x86_cie_data_alignment;
326 /* Interface to relax_segment.
327 There are 3 major relax states for 386 jump insns because the
328 different types of jumps add different sizes to frags when we're
329 figuring out what sort of jump to choose to reach a given label. */
332 #define UNCOND_JUMP 0
334 #define COND_JUMP86 2
339 #define SMALL16 (SMALL | CODE16)
341 #define BIG16 (BIG | CODE16)
345 #define INLINE __inline__
351 #define ENCODE_RELAX_STATE(type, size) \
352 ((relax_substateT) (((type) << 2) | (size)))
353 #define TYPE_FROM_RELAX_STATE(s) \
355 #define DISP_SIZE_FROM_RELAX_STATE(s) \
356 ((((s) & 3) == BIG ? 4 : (((s) & 3) == BIG16 ? 2 : 1)))
358 /* This table is used by relax_frag to promote short jumps to long
359 ones where necessary. SMALL (short) jumps may be promoted to BIG
360 (32 bit long) ones, and SMALL16 jumps to BIG16 (16 bit long). We
361 don't allow a short jump in a 32 bit code segment to be promoted to
362 a 16 bit offset jump because it's slower (requires data size
363 prefix), and doesn't work, unless the destination is in the bottom
364 64k of the code segment (The top 16 bits of eip are zeroed). */
366 const relax_typeS md_relax_table[] =
369 1) most positive reach of this state,
370 2) most negative reach of this state,
371 3) how many bytes this mode will have in the variable part of the frag
372 4) which index into the table to try if we can't fit into this one. */
374 /* UNCOND_JUMP states. */
375 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG)},
376 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16)},
377 /* dword jmp adds 4 bytes to frag:
378 0 extra opcode bytes, 4 displacement bytes. */
380 /* word jmp adds 2 byte2 to frag:
381 0 extra opcode bytes, 2 displacement bytes. */
384 /* COND_JUMP states. */
385 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG)},
386 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP, BIG16)},
387 /* dword conditionals adds 5 bytes to frag:
388 1 extra opcode byte, 4 displacement bytes. */
390 /* word conditionals add 3 bytes to frag:
391 1 extra opcode byte, 2 displacement bytes. */
394 /* COND_JUMP86 states. */
395 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG)},
396 {127 + 1, -128 + 1, 1, ENCODE_RELAX_STATE (COND_JUMP86, BIG16)},
397 /* dword conditionals adds 5 bytes to frag:
398 1 extra opcode byte, 4 displacement bytes. */
400 /* word conditionals add 4 bytes to frag:
401 1 displacement byte and a 3 byte long branch insn. */
405 static const arch_entry cpu_arch[] = {
407 {"i186", Cpu086|Cpu186 },
408 {"i286", Cpu086|Cpu186|Cpu286 },
409 {"i386", Cpu086|Cpu186|Cpu286|Cpu386 },
410 {"i486", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486 },
411 {"i586", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
412 {"i686", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
413 {"pentium", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuMMX },
414 {"pentiumpro",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuMMX|CpuSSE },
415 {"pentium4", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuP4|CpuMMX|CpuSSE|CpuSSE2 },
416 {"k6", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|CpuK6|CpuMMX|Cpu3dnow },
417 {"athlon", Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuMMX|Cpu3dnow },
418 {"sledgehammer",Cpu086|Cpu186|Cpu286|Cpu386|Cpu486|Cpu586|Cpu686|CpuK6|CpuAthlon|CpuSledgehammer|CpuMMX|Cpu3dnow|CpuSSE|CpuSSE2 },
422 const pseudo_typeS md_pseudo_table[] =
424 #if !defined(OBJ_AOUT) && !defined(USE_ALIGN_PTWO)
425 {"align", s_align_bytes, 0},
427 {"align", s_align_ptwo, 0},
429 {"arch", set_cpu_arch, 0},
433 {"ffloat", float_cons, 'f'},
434 {"dfloat", float_cons, 'd'},
435 {"tfloat", float_cons, 'x'},
437 {"noopt", s_ignore, 0},
438 {"optim", s_ignore, 0},
439 {"code16gcc", set_16bit_gcc_code_flag, CODE_16BIT},
440 {"code16", set_code_flag, CODE_16BIT},
441 {"code32", set_code_flag, CODE_32BIT},
442 {"code64", set_code_flag, CODE_64BIT},
443 {"intel_syntax", set_intel_syntax, 1},
444 {"att_syntax", set_intel_syntax, 0},
445 {"file", (void (*) PARAMS ((int))) dwarf2_directive_file, 0},
446 {"loc", dwarf2_directive_loc, 0},
450 /* For interface with expression (). */
451 extern char *input_line_pointer;
453 /* Hash table for instruction mnemonic lookup. */
454 static struct hash_control *op_hash;
456 /* Hash table for register lookup. */
457 static struct hash_control *reg_hash;
460 i386_align_code (fragP, count)
464 /* Various efficient no-op patterns for aligning code labels.
465 Note: Don't try to assemble the instructions in the comments.
466 0L and 0w are not legal. */
467 static const char f32_1[] =
469 static const char f32_2[] =
470 {0x89,0xf6}; /* movl %esi,%esi */
471 static const char f32_3[] =
472 {0x8d,0x76,0x00}; /* leal 0(%esi),%esi */
473 static const char f32_4[] =
474 {0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
475 static const char f32_5[] =
477 0x8d,0x74,0x26,0x00}; /* leal 0(%esi,1),%esi */
478 static const char f32_6[] =
479 {0x8d,0xb6,0x00,0x00,0x00,0x00}; /* leal 0L(%esi),%esi */
480 static const char f32_7[] =
481 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
482 static const char f32_8[] =
484 0x8d,0xb4,0x26,0x00,0x00,0x00,0x00}; /* leal 0L(%esi,1),%esi */
485 static const char f32_9[] =
486 {0x89,0xf6, /* movl %esi,%esi */
487 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
488 static const char f32_10[] =
489 {0x8d,0x76,0x00, /* leal 0(%esi),%esi */
490 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
491 static const char f32_11[] =
492 {0x8d,0x74,0x26,0x00, /* leal 0(%esi,1),%esi */
493 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
494 static const char f32_12[] =
495 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
496 0x8d,0xbf,0x00,0x00,0x00,0x00}; /* leal 0L(%edi),%edi */
497 static const char f32_13[] =
498 {0x8d,0xb6,0x00,0x00,0x00,0x00, /* leal 0L(%esi),%esi */
499 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
500 static const char f32_14[] =
501 {0x8d,0xb4,0x26,0x00,0x00,0x00,0x00, /* leal 0L(%esi,1),%esi */
502 0x8d,0xbc,0x27,0x00,0x00,0x00,0x00}; /* leal 0L(%edi,1),%edi */
503 static const char f32_15[] =
504 {0xeb,0x0d,0x90,0x90,0x90,0x90,0x90, /* jmp .+15; lotsa nops */
505 0x90,0x90,0x90,0x90,0x90,0x90,0x90,0x90};
506 static const char f16_3[] =
507 {0x8d,0x74,0x00}; /* lea 0(%esi),%esi */
508 static const char f16_4[] =
509 {0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
510 static const char f16_5[] =
512 0x8d,0xb4,0x00,0x00}; /* lea 0w(%si),%si */
513 static const char f16_6[] =
514 {0x89,0xf6, /* mov %si,%si */
515 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
516 static const char f16_7[] =
517 {0x8d,0x74,0x00, /* lea 0(%si),%si */
518 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
519 static const char f16_8[] =
520 {0x8d,0xb4,0x00,0x00, /* lea 0w(%si),%si */
521 0x8d,0xbd,0x00,0x00}; /* lea 0w(%di),%di */
522 static const char *const f32_patt[] = {
523 f32_1, f32_2, f32_3, f32_4, f32_5, f32_6, f32_7, f32_8,
524 f32_9, f32_10, f32_11, f32_12, f32_13, f32_14, f32_15
526 static const char *const f16_patt[] = {
527 f32_1, f32_2, f16_3, f16_4, f16_5, f16_6, f16_7, f16_8,
528 f32_15, f32_15, f32_15, f32_15, f32_15, f32_15, f32_15
531 if (count <= 0 || count > 15)
534 /* The recommended way to pad 64bit code is to use NOPs preceded by
535 maximally four 0x66 prefixes. Balance the size of nops. */
536 if (flag_code == CODE_64BIT)
539 int nnops = (count + 3) / 4;
540 int len = count / nnops;
541 int remains = count - nnops * len;
544 for (i = 0; i < remains; i++)
546 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len);
547 fragP->fr_literal[fragP->fr_fix + pos + len] = 0x90;
550 for (; i < nnops; i++)
552 memset (fragP->fr_literal + fragP->fr_fix + pos, 0x66, len - 1);
553 fragP->fr_literal[fragP->fr_fix + pos + len - 1] = 0x90;
558 if (flag_code == CODE_16BIT)
560 memcpy (fragP->fr_literal + fragP->fr_fix,
561 f16_patt[count - 1], count);
563 /* Adjust jump offset. */
564 fragP->fr_literal[fragP->fr_fix + 1] = count - 2;
567 memcpy (fragP->fr_literal + fragP->fr_fix,
568 f32_patt[count - 1], count);
569 fragP->fr_var = count;
572 static INLINE unsigned int
573 mode_from_disp_size (t)
576 return (t & Disp8) ? 1 : (t & (Disp16 | Disp32 | Disp32S)) ? 2 : 0;
580 fits_in_signed_byte (num)
583 return (num >= -128) && (num <= 127);
587 fits_in_unsigned_byte (num)
590 return (num & 0xff) == num;
594 fits_in_unsigned_word (num)
597 return (num & 0xffff) == num;
601 fits_in_signed_word (num)
604 return (-32768 <= num) && (num <= 32767);
607 fits_in_signed_long (num)
608 offsetT num ATTRIBUTE_UNUSED;
613 return (!(-((offsetT) 1 << 31) & num)
614 || (-((offsetT) 1 << 31) & num) == -((offsetT) 1 << 31));
616 } /* fits_in_signed_long() */
618 fits_in_unsigned_long (num)
619 offsetT num ATTRIBUTE_UNUSED;
624 return (num & (((offsetT) 2 << 31) - 1)) == num;
626 } /* fits_in_unsigned_long() */
629 smallest_imm_type (num)
632 if (cpu_arch_flags != (Cpu086 | Cpu186 | Cpu286 | Cpu386 | Cpu486 | CpuNo64))
634 /* This code is disabled on the 486 because all the Imm1 forms
635 in the opcode table are slower on the i486. They're the
636 versions with the implicitly specified single-position
637 displacement, which has another syntax if you really want to
640 return Imm1 | Imm8 | Imm8S | Imm16 | Imm32 | Imm32S | Imm64;
642 return (fits_in_signed_byte (num)
643 ? (Imm8S | Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
644 : fits_in_unsigned_byte (num)
645 ? (Imm8 | Imm16 | Imm32 | Imm32S | Imm64)
646 : (fits_in_signed_word (num) || fits_in_unsigned_word (num))
647 ? (Imm16 | Imm32 | Imm32S | Imm64)
648 : fits_in_signed_long (num)
649 ? (Imm32 | Imm32S | Imm64)
650 : fits_in_unsigned_long (num)
656 offset_in_range (val, size)
664 case 1: mask = ((addressT) 1 << 8) - 1; break;
665 case 2: mask = ((addressT) 1 << 16) - 1; break;
666 case 4: mask = ((addressT) 2 << 31) - 1; break;
668 case 8: mask = ((addressT) 2 << 63) - 1; break;
673 /* If BFD64, sign extend val. */
674 if (!use_rela_relocations)
675 if ((val & ~(((addressT) 2 << 31) - 1)) == 0)
676 val = (val ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
678 if ((val & ~mask) != 0 && (val & ~mask) != ~mask)
680 char buf1[40], buf2[40];
682 sprint_value (buf1, val);
683 sprint_value (buf2, val & mask);
684 as_warn (_("%s shortened to %s"), buf1, buf2);
689 /* Returns 0 if attempting to add a prefix where one from the same
690 class already exists, 1 if non rep/repne added, 2 if rep/repne
699 if (prefix >= REX_OPCODE && prefix < REX_OPCODE + 16
700 && flag_code == CODE_64BIT)
708 case CS_PREFIX_OPCODE:
709 case DS_PREFIX_OPCODE:
710 case ES_PREFIX_OPCODE:
711 case FS_PREFIX_OPCODE:
712 case GS_PREFIX_OPCODE:
713 case SS_PREFIX_OPCODE:
717 case REPNE_PREFIX_OPCODE:
718 case REPE_PREFIX_OPCODE:
721 case LOCK_PREFIX_OPCODE:
729 case ADDR_PREFIX_OPCODE:
733 case DATA_PREFIX_OPCODE:
738 if (i.prefix[q] != 0)
740 as_bad (_("same type of prefix used twice"));
745 i.prefix[q] = prefix;
750 set_code_flag (value)
754 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
755 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
756 if (value == CODE_64BIT && !(cpu_arch_flags & CpuSledgehammer))
758 as_bad (_("64bit mode not supported on this CPU."));
760 if (value == CODE_32BIT && !(cpu_arch_flags & Cpu386))
762 as_bad (_("32bit mode not supported on this CPU."));
768 set_16bit_gcc_code_flag (new_code_flag)
771 flag_code = new_code_flag;
772 cpu_arch_flags &= ~(Cpu64 | CpuNo64);
773 cpu_arch_flags |= (flag_code == CODE_64BIT ? Cpu64 : CpuNo64);
778 set_intel_syntax (syntax_flag)
781 /* Find out if register prefixing is specified. */
782 int ask_naked_reg = 0;
785 if (!is_end_of_line[(unsigned char) *input_line_pointer])
787 char *string = input_line_pointer;
788 int e = get_symbol_end ();
790 if (strcmp (string, "prefix") == 0)
792 else if (strcmp (string, "noprefix") == 0)
795 as_bad (_("bad argument to syntax directive."));
796 *input_line_pointer = e;
798 demand_empty_rest_of_line ();
800 intel_syntax = syntax_flag;
802 if (ask_naked_reg == 0)
803 allow_naked_reg = (intel_syntax
804 && (bfd_get_symbol_leading_char (stdoutput) != '\0'));
806 allow_naked_reg = (ask_naked_reg < 0);
811 int dummy ATTRIBUTE_UNUSED;
815 if (!is_end_of_line[(unsigned char) *input_line_pointer])
817 char *string = input_line_pointer;
818 int e = get_symbol_end ();
821 for (i = 0; cpu_arch[i].name; i++)
823 if (strcmp (string, cpu_arch[i].name) == 0)
825 cpu_arch_name = cpu_arch[i].name;
826 cpu_arch_flags = (cpu_arch[i].flags
827 | (flag_code == CODE_64BIT ? Cpu64 : CpuNo64));
831 if (!cpu_arch[i].name)
832 as_bad (_("no such architecture: `%s'"), string);
834 *input_line_pointer = e;
837 as_bad (_("missing cpu architecture"));
839 no_cond_jump_promotion = 0;
840 if (*input_line_pointer == ','
841 && !is_end_of_line[(unsigned char) input_line_pointer[1]])
843 char *string = ++input_line_pointer;
844 int e = get_symbol_end ();
846 if (strcmp (string, "nojumps") == 0)
847 no_cond_jump_promotion = 1;
848 else if (strcmp (string, "jumps") == 0)
851 as_bad (_("no such architecture modifier: `%s'"), string);
853 *input_line_pointer = e;
856 demand_empty_rest_of_line ();
862 if (!strcmp (default_arch, "x86_64"))
863 return bfd_mach_x86_64;
864 else if (!strcmp (default_arch, "i386"))
865 return bfd_mach_i386_i386;
867 as_fatal (_("Unknown architecture"));
873 const char *hash_err;
875 /* Initialize op_hash hash table. */
876 op_hash = hash_new ();
879 const template *optab;
880 templates *core_optab;
882 /* Setup for loop. */
884 core_optab = (templates *) xmalloc (sizeof (templates));
885 core_optab->start = optab;
890 if (optab->name == NULL
891 || strcmp (optab->name, (optab - 1)->name) != 0)
893 /* different name --> ship out current template list;
894 add to hash table; & begin anew. */
895 core_optab->end = optab;
896 hash_err = hash_insert (op_hash,
901 as_fatal (_("Internal Error: Can't hash %s: %s"),
905 if (optab->name == NULL)
907 core_optab = (templates *) xmalloc (sizeof (templates));
908 core_optab->start = optab;
913 /* Initialize reg_hash hash table. */
914 reg_hash = hash_new ();
916 const reg_entry *regtab;
918 for (regtab = i386_regtab;
919 regtab < i386_regtab + sizeof (i386_regtab) / sizeof (i386_regtab[0]);
922 hash_err = hash_insert (reg_hash, regtab->reg_name, (PTR) regtab);
924 as_fatal (_("Internal Error: Can't hash %s: %s"),
930 /* Fill in lexical tables: mnemonic_chars, operand_chars. */
935 for (c = 0; c < 256; c++)
940 mnemonic_chars[c] = c;
941 register_chars[c] = c;
942 operand_chars[c] = c;
944 else if (ISLOWER (c))
946 mnemonic_chars[c] = c;
947 register_chars[c] = c;
948 operand_chars[c] = c;
950 else if (ISUPPER (c))
952 mnemonic_chars[c] = TOLOWER (c);
953 register_chars[c] = mnemonic_chars[c];
954 operand_chars[c] = c;
957 if (ISALPHA (c) || ISDIGIT (c))
958 identifier_chars[c] = c;
961 identifier_chars[c] = c;
962 operand_chars[c] = c;
967 identifier_chars['@'] = '@';
969 digit_chars['-'] = '-';
970 identifier_chars['_'] = '_';
971 identifier_chars['.'] = '.';
973 for (p = operand_special_chars; *p != '\0'; p++)
974 operand_chars[(unsigned char) *p] = *p;
977 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
978 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
980 record_alignment (text_section, 2);
981 record_alignment (data_section, 2);
982 record_alignment (bss_section, 2);
986 if (flag_code == CODE_64BIT)
988 x86_dwarf2_return_column = 16;
989 x86_cie_data_alignment = -8;
993 x86_dwarf2_return_column = 8;
994 x86_cie_data_alignment = -4;
999 i386_print_statistics (file)
1002 hash_print_statistics (file, "i386 opcode", op_hash);
1003 hash_print_statistics (file, "i386 register", reg_hash);
1008 /* Debugging routines for md_assemble. */
1009 static void pi PARAMS ((char *, i386_insn *));
1010 static void pte PARAMS ((template *));
1011 static void pt PARAMS ((unsigned int));
1012 static void pe PARAMS ((expressionS *));
1013 static void ps PARAMS ((symbolS *));
1022 fprintf (stdout, "%s: template ", line);
1024 fprintf (stdout, " address: base %s index %s scale %x\n",
1025 x->base_reg ? x->base_reg->reg_name : "none",
1026 x->index_reg ? x->index_reg->reg_name : "none",
1027 x->log2_scale_factor);
1028 fprintf (stdout, " modrm: mode %x reg %x reg/mem %x\n",
1029 x->rm.mode, x->rm.reg, x->rm.regmem);
1030 fprintf (stdout, " sib: base %x index %x scale %x\n",
1031 x->sib.base, x->sib.index, x->sib.scale);
1032 fprintf (stdout, " rex: 64bit %x extX %x extY %x extZ %x\n",
1033 (x->rex & REX_MODE64) != 0,
1034 (x->rex & REX_EXTX) != 0,
1035 (x->rex & REX_EXTY) != 0,
1036 (x->rex & REX_EXTZ) != 0);
1037 for (i = 0; i < x->operands; i++)
1039 fprintf (stdout, " #%d: ", i + 1);
1041 fprintf (stdout, "\n");
1043 & (Reg | SReg2 | SReg3 | Control | Debug | Test | RegMMX | RegXMM))
1044 fprintf (stdout, "%s\n", x->op[i].regs->reg_name);
1045 if (x->types[i] & Imm)
1047 if (x->types[i] & Disp)
1048 pe (x->op[i].disps);
1057 fprintf (stdout, " %d operands ", t->operands);
1058 fprintf (stdout, "opcode %x ", t->base_opcode);
1059 if (t->extension_opcode != None)
1060 fprintf (stdout, "ext %x ", t->extension_opcode);
1061 if (t->opcode_modifier & D)
1062 fprintf (stdout, "D");
1063 if (t->opcode_modifier & W)
1064 fprintf (stdout, "W");
1065 fprintf (stdout, "\n");
1066 for (i = 0; i < t->operands; i++)
1068 fprintf (stdout, " #%d type ", i + 1);
1069 pt (t->operand_types[i]);
1070 fprintf (stdout, "\n");
1078 fprintf (stdout, " operation %d\n", e->X_op);
1079 fprintf (stdout, " add_number %ld (%lx)\n",
1080 (long) e->X_add_number, (long) e->X_add_number);
1081 if (e->X_add_symbol)
1083 fprintf (stdout, " add_symbol ");
1084 ps (e->X_add_symbol);
1085 fprintf (stdout, "\n");
1089 fprintf (stdout, " op_symbol ");
1090 ps (e->X_op_symbol);
1091 fprintf (stdout, "\n");
1099 fprintf (stdout, "%s type %s%s",
1101 S_IS_EXTERNAL (s) ? "EXTERNAL " : "",
1102 segment_name (S_GET_SEGMENT (s)));
1111 static const type_names[] =
1124 { BaseIndex, "BaseIndex" },
1128 { Disp32S, "d32s" },
1130 { InOutPortReg, "InOutPortReg" },
1131 { ShiftCount, "ShiftCount" },
1132 { Control, "control reg" },
1133 { Test, "test reg" },
1134 { Debug, "debug reg" },
1135 { FloatReg, "FReg" },
1136 { FloatAcc, "FAcc" },
1140 { JumpAbsolute, "Jump Absolute" },
1151 const struct type_name *ty;
1153 for (ty = type_names; ty->mask; ty++)
1155 fprintf (stdout, "%s, ", ty->tname);
1159 #endif /* DEBUG386 */
1161 static bfd_reloc_code_real_type reloc
1162 PARAMS ((int, int, int, bfd_reloc_code_real_type));
1164 static bfd_reloc_code_real_type
1165 reloc (size, pcrel, sign, other)
1169 bfd_reloc_code_real_type other;
1171 if (other != NO_RELOC)
1177 as_bad (_("There are no unsigned pc-relative relocations"));
1180 case 1: return BFD_RELOC_8_PCREL;
1181 case 2: return BFD_RELOC_16_PCREL;
1182 case 4: return BFD_RELOC_32_PCREL;
1184 as_bad (_("can not do %d byte pc-relative relocation"), size);
1191 case 4: return BFD_RELOC_X86_64_32S;
1196 case 1: return BFD_RELOC_8;
1197 case 2: return BFD_RELOC_16;
1198 case 4: return BFD_RELOC_32;
1199 case 8: return BFD_RELOC_64;
1201 as_bad (_("can not do %s %d byte relocation"),
1202 sign ? "signed" : "unsigned", size);
1206 return BFD_RELOC_NONE;
1209 /* Here we decide which fixups can be adjusted to make them relative to
1210 the beginning of the section instead of the symbol. Basically we need
1211 to make sure that the dynamic relocations are done correctly, so in
1212 some cases we force the original symbol to be used. */
1215 tc_i386_fix_adjustable (fixP)
1216 fixS *fixP ATTRIBUTE_UNUSED;
1218 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
1219 if (OUTPUT_FLAVOR != bfd_target_elf_flavour)
1222 /* Don't adjust pc-relative references to merge sections in 64-bit
1224 if (use_rela_relocations
1225 && (S_GET_SEGMENT (fixP->fx_addsy)->flags & SEC_MERGE) != 0
1229 /* The x86_64 GOTPCREL are represented as 32bit PCrel relocations
1230 and changed later by validate_fix. */
1231 if (GOT_symbol && fixP->fx_subsy == GOT_symbol
1232 && fixP->fx_r_type == BFD_RELOC_32_PCREL)
1235 /* adjust_reloc_syms doesn't know about the GOT. */
1236 if (fixP->fx_r_type == BFD_RELOC_386_GOTOFF
1237 || fixP->fx_r_type == BFD_RELOC_386_PLT32
1238 || fixP->fx_r_type == BFD_RELOC_386_GOT32
1239 || fixP->fx_r_type == BFD_RELOC_386_TLS_GD
1240 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDM
1241 || fixP->fx_r_type == BFD_RELOC_386_TLS_LDO_32
1242 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE_32
1243 || fixP->fx_r_type == BFD_RELOC_386_TLS_IE
1244 || fixP->fx_r_type == BFD_RELOC_386_TLS_GOTIE
1245 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE_32
1246 || fixP->fx_r_type == BFD_RELOC_386_TLS_LE
1247 || fixP->fx_r_type == BFD_RELOC_X86_64_PLT32
1248 || fixP->fx_r_type == BFD_RELOC_X86_64_GOT32
1249 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTPCREL
1250 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSGD
1251 || fixP->fx_r_type == BFD_RELOC_X86_64_TLSLD
1252 || fixP->fx_r_type == BFD_RELOC_X86_64_DTPOFF32
1253 || fixP->fx_r_type == BFD_RELOC_X86_64_GOTTPOFF
1254 || fixP->fx_r_type == BFD_RELOC_X86_64_TPOFF32
1255 || fixP->fx_r_type == BFD_RELOC_VTABLE_INHERIT
1256 || fixP->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
1262 static int intel_float_operand PARAMS ((const char *mnemonic));
1265 intel_float_operand (mnemonic)
1266 const char *mnemonic;
1268 if (mnemonic[0] == 'f' && mnemonic[1] == 'i')
1271 if (mnemonic[0] == 'f')
1277 /* This is the guts of the machine-dependent assembler. LINE points to a
1278 machine dependent instruction. This function is supposed to emit
1279 the frags/bytes it assembles to. */
1286 char mnemonic[MAX_MNEM_SIZE];
1288 /* Initialize globals. */
1289 memset (&i, '\0', sizeof (i));
1290 for (j = 0; j < MAX_OPERANDS; j++)
1291 i.reloc[j] = NO_RELOC;
1292 memset (disp_expressions, '\0', sizeof (disp_expressions));
1293 memset (im_expressions, '\0', sizeof (im_expressions));
1294 save_stack_p = save_stack;
1296 /* First parse an instruction mnemonic & call i386_operand for the operands.
1297 We assume that the scrubber has arranged it so that line[0] is the valid
1298 start of a (possibly prefixed) mnemonic. */
1300 line = parse_insn (line, mnemonic);
1304 line = parse_operands (line, mnemonic);
1308 /* Now we've parsed the mnemonic into a set of templates, and have the
1309 operands at hand. */
1311 /* All intel opcodes have reversed operands except for "bound" and
1312 "enter". We also don't reverse intersegment "jmp" and "call"
1313 instructions with 2 immediate operands so that the immediate segment
1314 precedes the offset, as it does when in AT&T mode. "enter" and the
1315 intersegment "jmp" and "call" instructions are the only ones that
1316 have two immediate operands. */
1317 if (intel_syntax && i.operands > 1
1318 && (strcmp (mnemonic, "bound") != 0)
1319 && !((i.types[0] & Imm) && (i.types[1] & Imm)))
1325 if (i.disp_operands)
1328 /* Next, we find a template that matches the given insn,
1329 making sure the overlap of the given operands types is consistent
1330 with the template operand types. */
1332 if (!match_template ())
1337 /* Undo SYSV386_COMPAT brokenness when in Intel mode. See i386.h */
1339 && (i.tm.base_opcode & 0xfffffde0) == 0xdce0)
1340 i.tm.base_opcode ^= FloatR;
1342 /* Zap movzx and movsx suffix. The suffix may have been set from
1343 "word ptr" or "byte ptr" on the source operand, but we'll use
1344 the suffix later to choose the destination register. */
1345 if ((i.tm.base_opcode & ~9) == 0x0fb6)
1349 if (i.tm.opcode_modifier & FWait)
1350 if (!add_prefix (FWAIT_OPCODE))
1353 /* Check string instruction segment overrides. */
1354 if ((i.tm.opcode_modifier & IsString) != 0 && i.mem_operands != 0)
1356 if (!check_string ())
1360 if (!process_suffix ())
1363 /* Make still unresolved immediate matches conform to size of immediate
1364 given in i.suffix. */
1365 if (!finalize_imm ())
1368 if (i.types[0] & Imm1)
1369 i.imm_operands = 0; /* kludge for shift insns. */
1370 if (i.types[0] & ImplicitRegister)
1372 if (i.types[1] & ImplicitRegister)
1374 if (i.types[2] & ImplicitRegister)
1377 if (i.tm.opcode_modifier & ImmExt)
1381 if ((i.tm.cpu_flags & CpuPNI) && i.operands > 0)
1383 /* These Intel Prescott New Instructions have the fixed
1384 operands with an opcode suffix which is coded in the same
1385 place as an 8-bit immediate field would be. Here we check
1386 those operands and remove them afterwards. */
1389 for (x = 0; x < i.operands; x++)
1390 if (i.op[x].regs->reg_num != x)
1391 as_bad (_("can't use register '%%%s' as operand %d in '%s'."),
1392 i.op[x].regs->reg_name, x + 1, i.tm.name);
1396 /* These AMD 3DNow! and Intel Katmai New Instructions have an
1397 opcode suffix which is coded in the same place as an 8-bit
1398 immediate field would be. Here we fake an 8-bit immediate
1399 operand from the opcode suffix stored in tm.extension_opcode. */
1401 assert (i.imm_operands == 0 && i.operands <= 2 && 2 < MAX_OPERANDS);
1403 exp = &im_expressions[i.imm_operands++];
1404 i.op[i.operands].imms = exp;
1405 i.types[i.operands++] = Imm8;
1406 exp->X_op = O_constant;
1407 exp->X_add_number = i.tm.extension_opcode;
1408 i.tm.extension_opcode = None;
1411 /* For insns with operands there are more diddles to do to the opcode. */
1414 if (!process_operands ())
1417 else if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
1419 /* UnixWare fsub no args is alias for fsubp, fadd -> faddp, etc. */
1420 as_warn (_("translating to `%sp'"), i.tm.name);
1423 /* Handle conversion of 'int $3' --> special int3 insn. */
1424 if (i.tm.base_opcode == INT_OPCODE && i.op[0].imms->X_add_number == 3)
1426 i.tm.base_opcode = INT3_OPCODE;
1430 if ((i.tm.opcode_modifier & (Jump | JumpByte | JumpDword))
1431 && i.op[0].disps->X_op == O_constant)
1433 /* Convert "jmp constant" (and "call constant") to a jump (call) to
1434 the absolute address given by the constant. Since ix86 jumps and
1435 calls are pc relative, we need to generate a reloc. */
1436 i.op[0].disps->X_add_symbol = &abs_symbol;
1437 i.op[0].disps->X_op = O_symbol;
1440 if ((i.tm.opcode_modifier & Rex64) != 0)
1441 i.rex |= REX_MODE64;
1443 /* For 8 bit registers we need an empty rex prefix. Also if the
1444 instruction already has a prefix, we need to convert old
1445 registers to new ones. */
1447 if (((i.types[0] & Reg8) != 0
1448 && (i.op[0].regs->reg_flags & RegRex64) != 0)
1449 || ((i.types[1] & Reg8) != 0
1450 && (i.op[1].regs->reg_flags & RegRex64) != 0)
1451 || (((i.types[0] & Reg8) != 0 || (i.types[1] & Reg8) != 0)
1456 i.rex |= REX_OPCODE;
1457 for (x = 0; x < 2; x++)
1459 /* Look for 8 bit operand that uses old registers. */
1460 if ((i.types[x] & Reg8) != 0
1461 && (i.op[x].regs->reg_flags & RegRex64) == 0)
1463 /* In case it is "hi" register, give up. */
1464 if (i.op[x].regs->reg_num > 3)
1465 as_bad (_("can't encode register '%%%s' in an instruction requiring REX prefix.\n"),
1466 i.op[x].regs->reg_name);
1468 /* Otherwise it is equivalent to the extended register.
1469 Since the encoding doesn't change this is merely
1470 cosmetic cleanup for debug output. */
1472 i.op[x].regs = i.op[x].regs + 8;
1478 add_prefix (REX_OPCODE | i.rex);
1480 /* We are ready to output the insn. */
1485 parse_insn (line, mnemonic)
1490 char *token_start = l;
1493 /* Non-zero if we found a prefix only acceptable with string insns. */
1494 const char *expecting_string_instruction = NULL;
1499 while ((*mnem_p = mnemonic_chars[(unsigned char) *l]) != 0)
1502 if (mnem_p >= mnemonic + MAX_MNEM_SIZE)
1504 as_bad (_("no such instruction: `%s'"), token_start);
1509 if (!is_space_char (*l)
1510 && *l != END_OF_INSN
1511 && *l != PREFIX_SEPARATOR
1514 as_bad (_("invalid character %s in mnemonic"),
1515 output_invalid (*l));
1518 if (token_start == l)
1520 if (*l == PREFIX_SEPARATOR)
1521 as_bad (_("expecting prefix; got nothing"));
1523 as_bad (_("expecting mnemonic; got nothing"));
1527 /* Look up instruction (or prefix) via hash table. */
1528 current_templates = hash_find (op_hash, mnemonic);
1530 if (*l != END_OF_INSN
1531 && (!is_space_char (*l) || l[1] != END_OF_INSN)
1532 && current_templates
1533 && (current_templates->start->opcode_modifier & IsPrefix))
1535 /* If we are in 16-bit mode, do not allow addr16 or data16.
1536 Similarly, in 32-bit mode, do not allow addr32 or data32. */
1537 if ((current_templates->start->opcode_modifier & (Size16 | Size32))
1538 && flag_code != CODE_64BIT
1539 && (((current_templates->start->opcode_modifier & Size32) != 0)
1540 ^ (flag_code == CODE_16BIT)))
1542 as_bad (_("redundant %s prefix"),
1543 current_templates->start->name);
1546 /* Add prefix, checking for repeated prefixes. */
1547 switch (add_prefix (current_templates->start->base_opcode))
1552 expecting_string_instruction = current_templates->start->name;
1555 /* Skip past PREFIX_SEPARATOR and reset token_start. */
1562 if (!current_templates)
1564 /* See if we can get a match by trimming off a suffix. */
1567 case WORD_MNEM_SUFFIX:
1568 case BYTE_MNEM_SUFFIX:
1569 case QWORD_MNEM_SUFFIX:
1570 i.suffix = mnem_p[-1];
1572 current_templates = hash_find (op_hash, mnemonic);
1574 case SHORT_MNEM_SUFFIX:
1575 case LONG_MNEM_SUFFIX:
1578 i.suffix = mnem_p[-1];
1580 current_templates = hash_find (op_hash, mnemonic);
1588 if (intel_float_operand (mnemonic))
1589 i.suffix = SHORT_MNEM_SUFFIX;
1591 i.suffix = LONG_MNEM_SUFFIX;
1593 current_templates = hash_find (op_hash, mnemonic);
1597 if (!current_templates)
1599 as_bad (_("no such instruction: `%s'"), token_start);
1604 if (current_templates->start->opcode_modifier & (Jump | JumpByte))
1606 /* Check for a branch hint. We allow ",pt" and ",pn" for
1607 predict taken and predict not taken respectively.
1608 I'm not sure that branch hints actually do anything on loop
1609 and jcxz insns (JumpByte) for current Pentium4 chips. They
1610 may work in the future and it doesn't hurt to accept them
1612 if (l[0] == ',' && l[1] == 'p')
1616 if (!add_prefix (DS_PREFIX_OPCODE))
1620 else if (l[2] == 'n')
1622 if (!add_prefix (CS_PREFIX_OPCODE))
1628 /* Any other comma loses. */
1631 as_bad (_("invalid character %s in mnemonic"),
1632 output_invalid (*l));
1636 /* Check if instruction is supported on specified architecture. */
1637 if ((current_templates->start->cpu_flags & ~(Cpu64 | CpuNo64))
1638 & ~(cpu_arch_flags & ~(Cpu64 | CpuNo64)))
1640 as_warn (_("`%s' is not supported on `%s'"),
1641 current_templates->start->name, cpu_arch_name);
1643 else if ((Cpu386 & ~cpu_arch_flags) && (flag_code != CODE_16BIT))
1645 as_warn (_("use .code16 to ensure correct addressing mode"));
1648 /* Check for rep/repne without a string instruction. */
1649 if (expecting_string_instruction
1650 && !(current_templates->start->opcode_modifier & IsString))
1652 as_bad (_("expecting string instruction after `%s'"),
1653 expecting_string_instruction);
1661 parse_operands (l, mnemonic)
1663 const char *mnemonic;
1667 /* 1 if operand is pending after ','. */
1668 unsigned int expecting_operand = 0;
1670 /* Non-zero if operand parens not balanced. */
1671 unsigned int paren_not_balanced;
1673 while (*l != END_OF_INSN)
1675 /* Skip optional white space before operand. */
1676 if (is_space_char (*l))
1678 if (!is_operand_char (*l) && *l != END_OF_INSN)
1680 as_bad (_("invalid character %s before operand %d"),
1681 output_invalid (*l),
1685 token_start = l; /* after white space */
1686 paren_not_balanced = 0;
1687 while (paren_not_balanced || *l != ',')
1689 if (*l == END_OF_INSN)
1691 if (paren_not_balanced)
1694 as_bad (_("unbalanced parenthesis in operand %d."),
1697 as_bad (_("unbalanced brackets in operand %d."),
1702 break; /* we are done */
1704 else if (!is_operand_char (*l) && !is_space_char (*l))
1706 as_bad (_("invalid character %s in operand %d"),
1707 output_invalid (*l),
1714 ++paren_not_balanced;
1716 --paren_not_balanced;
1721 ++paren_not_balanced;
1723 --paren_not_balanced;
1727 if (l != token_start)
1728 { /* Yes, we've read in another operand. */
1729 unsigned int operand_ok;
1730 this_operand = i.operands++;
1731 if (i.operands > MAX_OPERANDS)
1733 as_bad (_("spurious operands; (%d operands/instruction max)"),
1737 /* Now parse operand adding info to 'i' as we go along. */
1738 END_STRING_AND_SAVE (l);
1742 i386_intel_operand (token_start,
1743 intel_float_operand (mnemonic));
1745 operand_ok = i386_operand (token_start);
1747 RESTORE_END_STRING (l);
1753 if (expecting_operand)
1755 expecting_operand_after_comma:
1756 as_bad (_("expecting operand after ','; got nothing"));
1761 as_bad (_("expecting operand before ','; got nothing"));
1766 /* Now *l must be either ',' or END_OF_INSN. */
1769 if (*++l == END_OF_INSN)
1771 /* Just skip it, if it's \n complain. */
1772 goto expecting_operand_after_comma;
1774 expecting_operand = 1;
1783 union i386_op temp_op;
1784 unsigned int temp_type;
1785 enum bfd_reloc_code_real temp_reloc;
1789 if (i.operands == 2)
1794 else if (i.operands == 3)
1799 temp_type = i.types[xchg2];
1800 i.types[xchg2] = i.types[xchg1];
1801 i.types[xchg1] = temp_type;
1802 temp_op = i.op[xchg2];
1803 i.op[xchg2] = i.op[xchg1];
1804 i.op[xchg1] = temp_op;
1805 temp_reloc = i.reloc[xchg2];
1806 i.reloc[xchg2] = i.reloc[xchg1];
1807 i.reloc[xchg1] = temp_reloc;
1809 if (i.mem_operands == 2)
1811 const seg_entry *temp_seg;
1812 temp_seg = i.seg[0];
1813 i.seg[0] = i.seg[1];
1814 i.seg[1] = temp_seg;
1818 /* Try to ensure constant immediates are represented in the smallest
1823 char guess_suffix = 0;
1827 guess_suffix = i.suffix;
1828 else if (i.reg_operands)
1830 /* Figure out a suffix from the last register operand specified.
1831 We can't do this properly yet, ie. excluding InOutPortReg,
1832 but the following works for instructions with immediates.
1833 In any case, we can't set i.suffix yet. */
1834 for (op = i.operands; --op >= 0;)
1835 if (i.types[op] & Reg)
1837 if (i.types[op] & Reg8)
1838 guess_suffix = BYTE_MNEM_SUFFIX;
1839 else if (i.types[op] & Reg16)
1840 guess_suffix = WORD_MNEM_SUFFIX;
1841 else if (i.types[op] & Reg32)
1842 guess_suffix = LONG_MNEM_SUFFIX;
1843 else if (i.types[op] & Reg64)
1844 guess_suffix = QWORD_MNEM_SUFFIX;
1848 else if ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0))
1849 guess_suffix = WORD_MNEM_SUFFIX;
1851 for (op = i.operands; --op >= 0;)
1852 if (i.types[op] & Imm)
1854 switch (i.op[op].imms->X_op)
1857 /* If a suffix is given, this operand may be shortened. */
1858 switch (guess_suffix)
1860 case LONG_MNEM_SUFFIX:
1861 i.types[op] |= Imm32 | Imm64;
1863 case WORD_MNEM_SUFFIX:
1864 i.types[op] |= Imm16 | Imm32S | Imm32 | Imm64;
1866 case BYTE_MNEM_SUFFIX:
1867 i.types[op] |= Imm16 | Imm8 | Imm8S | Imm32S | Imm32 | Imm64;
1871 /* If this operand is at most 16 bits, convert it
1872 to a signed 16 bit number before trying to see
1873 whether it will fit in an even smaller size.
1874 This allows a 16-bit operand such as $0xffe0 to
1875 be recognised as within Imm8S range. */
1876 if ((i.types[op] & Imm16)
1877 && (i.op[op].imms->X_add_number & ~(offsetT) 0xffff) == 0)
1879 i.op[op].imms->X_add_number =
1880 (((i.op[op].imms->X_add_number & 0xffff) ^ 0x8000) - 0x8000);
1882 if ((i.types[op] & Imm32)
1883 && ((i.op[op].imms->X_add_number & ~(((offsetT) 2 << 31) - 1))
1886 i.op[op].imms->X_add_number = ((i.op[op].imms->X_add_number
1887 ^ ((offsetT) 1 << 31))
1888 - ((offsetT) 1 << 31));
1890 i.types[op] |= smallest_imm_type (i.op[op].imms->X_add_number);
1892 /* We must avoid matching of Imm32 templates when 64bit
1893 only immediate is available. */
1894 if (guess_suffix == QWORD_MNEM_SUFFIX)
1895 i.types[op] &= ~Imm32;
1902 /* Symbols and expressions. */
1904 /* Convert symbolic operand to proper sizes for matching. */
1905 switch (guess_suffix)
1907 case QWORD_MNEM_SUFFIX:
1908 i.types[op] = Imm64 | Imm32S;
1910 case LONG_MNEM_SUFFIX:
1911 i.types[op] = Imm32 | Imm64;
1913 case WORD_MNEM_SUFFIX:
1914 i.types[op] = Imm16 | Imm32 | Imm64;
1917 case BYTE_MNEM_SUFFIX:
1918 i.types[op] = Imm8 | Imm8S | Imm16 | Imm32S | Imm32;
1927 /* Try to use the smallest displacement type too. */
1933 for (op = i.operands; --op >= 0;)
1934 if ((i.types[op] & Disp) && i.op[op].disps->X_op == O_constant)
1936 offsetT disp = i.op[op].disps->X_add_number;
1938 if (i.types[op] & Disp16)
1940 /* We know this operand is at most 16 bits, so
1941 convert to a signed 16 bit number before trying
1942 to see whether it will fit in an even smaller
1945 disp = (((disp & 0xffff) ^ 0x8000) - 0x8000);
1947 else if (i.types[op] & Disp32)
1949 /* We know this operand is at most 32 bits, so convert to a
1950 signed 32 bit number before trying to see whether it will
1951 fit in an even smaller size. */
1952 disp &= (((offsetT) 2 << 31) - 1);
1953 disp = (disp ^ ((offsetT) 1 << 31)) - ((addressT) 1 << 31);
1955 if (flag_code == CODE_64BIT)
1957 if (fits_in_signed_long (disp))
1958 i.types[op] |= Disp32S;
1959 if (fits_in_unsigned_long (disp))
1960 i.types[op] |= Disp32;
1962 if ((i.types[op] & (Disp32 | Disp32S | Disp16))
1963 && fits_in_signed_byte (disp))
1964 i.types[op] |= Disp8;
1971 /* Points to template once we've found it. */
1973 unsigned int overlap0, overlap1, overlap2;
1974 unsigned int found_reverse_match;
1977 #define MATCH(overlap, given, template) \
1978 ((overlap & ~JumpAbsolute) \
1979 && (((given) & (BaseIndex | JumpAbsolute)) \
1980 == ((overlap) & (BaseIndex | JumpAbsolute))))
1982 /* If given types r0 and r1 are registers they must be of the same type
1983 unless the expected operand type register overlap is null.
1984 Note that Acc in a template matches every size of reg. */
1985 #define CONSISTENT_REGISTER_MATCH(m0, g0, t0, m1, g1, t1) \
1986 (((g0) & Reg) == 0 || ((g1) & Reg) == 0 \
1987 || ((g0) & Reg) == ((g1) & Reg) \
1988 || ((((m0) & Acc) ? Reg : (t0)) & (((m1) & Acc) ? Reg : (t1)) & Reg) == 0 )
1993 found_reverse_match = 0;
1994 suffix_check = (i.suffix == BYTE_MNEM_SUFFIX
1996 : (i.suffix == WORD_MNEM_SUFFIX
1998 : (i.suffix == SHORT_MNEM_SUFFIX
2000 : (i.suffix == LONG_MNEM_SUFFIX
2002 : (i.suffix == QWORD_MNEM_SUFFIX
2004 : (i.suffix == LONG_DOUBLE_MNEM_SUFFIX
2005 ? No_xSuf : 0))))));
2007 for (t = current_templates->start;
2008 t < current_templates->end;
2011 /* Must have right number of operands. */
2012 if (i.operands != t->operands)
2015 /* Check the suffix, except for some instructions in intel mode. */
2016 if ((t->opcode_modifier & suffix_check)
2018 && (t->opcode_modifier & IgnoreSize))
2020 && t->base_opcode == 0xd9
2021 && (t->extension_opcode == 5 /* 0xd9,5 "fldcw" */
2022 || t->extension_opcode == 7))) /* 0xd9,7 "f{n}stcw" */
2025 /* Do not verify operands when there are none. */
2026 else if (!t->operands)
2028 if (t->cpu_flags & ~cpu_arch_flags)
2030 /* We've found a match; break out of loop. */
2034 overlap0 = i.types[0] & t->operand_types[0];
2035 switch (t->operands)
2038 if (!MATCH (overlap0, i.types[0], t->operand_types[0]))
2043 overlap1 = i.types[1] & t->operand_types[1];
2044 if (!MATCH (overlap0, i.types[0], t->operand_types[0])
2045 || !MATCH (overlap1, i.types[1], t->operand_types[1])
2046 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2047 t->operand_types[0],
2048 overlap1, i.types[1],
2049 t->operand_types[1]))
2051 /* Check if other direction is valid ... */
2052 if ((t->opcode_modifier & (D | FloatD)) == 0)
2055 /* Try reversing direction of operands. */
2056 overlap0 = i.types[0] & t->operand_types[1];
2057 overlap1 = i.types[1] & t->operand_types[0];
2058 if (!MATCH (overlap0, i.types[0], t->operand_types[1])
2059 || !MATCH (overlap1, i.types[1], t->operand_types[0])
2060 || !CONSISTENT_REGISTER_MATCH (overlap0, i.types[0],
2061 t->operand_types[1],
2062 overlap1, i.types[1],
2063 t->operand_types[0]))
2065 /* Does not match either direction. */
2068 /* found_reverse_match holds which of D or FloatDR
2070 found_reverse_match = t->opcode_modifier & (D | FloatDR);
2072 /* Found a forward 2 operand match here. */
2073 else if (t->operands == 3)
2075 /* Here we make use of the fact that there are no
2076 reverse match 3 operand instructions, and all 3
2077 operand instructions only need to be checked for
2078 register consistency between operands 2 and 3. */
2079 overlap2 = i.types[2] & t->operand_types[2];
2080 if (!MATCH (overlap2, i.types[2], t->operand_types[2])
2081 || !CONSISTENT_REGISTER_MATCH (overlap1, i.types[1],
2082 t->operand_types[1],
2083 overlap2, i.types[2],
2084 t->operand_types[2]))
2088 /* Found either forward/reverse 2 or 3 operand match here:
2089 slip through to break. */
2091 if (t->cpu_flags & ~cpu_arch_flags)
2093 found_reverse_match = 0;
2096 /* We've found a match; break out of loop. */
2100 if (t == current_templates->end)
2102 /* We found no match. */
2103 as_bad (_("suffix or operands invalid for `%s'"),
2104 current_templates->start->name);
2108 if (!quiet_warnings)
2111 && ((i.types[0] & JumpAbsolute)
2112 != (t->operand_types[0] & JumpAbsolute)))
2114 as_warn (_("indirect %s without `*'"), t->name);
2117 if ((t->opcode_modifier & (IsPrefix | IgnoreSize))
2118 == (IsPrefix | IgnoreSize))
2120 /* Warn them that a data or address size prefix doesn't
2121 affect assembly of the next line of code. */
2122 as_warn (_("stand-alone `%s' prefix"), t->name);
2126 /* Copy the template we found. */
2128 if (found_reverse_match)
2130 /* If we found a reverse match we must alter the opcode
2131 direction bit. found_reverse_match holds bits to change
2132 (different for int & float insns). */
2134 i.tm.base_opcode ^= found_reverse_match;
2136 i.tm.operand_types[0] = t->operand_types[1];
2137 i.tm.operand_types[1] = t->operand_types[0];
2146 int mem_op = (i.types[0] & AnyMem) ? 0 : 1;
2147 if ((i.tm.operand_types[mem_op] & EsSeg) != 0)
2149 if (i.seg[0] != NULL && i.seg[0] != &es)
2151 as_bad (_("`%s' operand %d must use `%%es' segment"),
2156 /* There's only ever one segment override allowed per instruction.
2157 This instruction possibly has a legal segment override on the
2158 second operand, so copy the segment to where non-string
2159 instructions store it, allowing common code. */
2160 i.seg[0] = i.seg[1];
2162 else if ((i.tm.operand_types[mem_op + 1] & EsSeg) != 0)
2164 if (i.seg[1] != NULL && i.seg[1] != &es)
2166 as_bad (_("`%s' operand %d must use `%%es' segment"),
2178 /* If matched instruction specifies an explicit instruction mnemonic
2180 if (i.tm.opcode_modifier & (Size16 | Size32 | Size64))
2182 if (i.tm.opcode_modifier & Size16)
2183 i.suffix = WORD_MNEM_SUFFIX;
2184 else if (i.tm.opcode_modifier & Size64)
2185 i.suffix = QWORD_MNEM_SUFFIX;
2187 i.suffix = LONG_MNEM_SUFFIX;
2189 else if (i.reg_operands)
2191 /* If there's no instruction mnemonic suffix we try to invent one
2192 based on register operands. */
2195 /* We take i.suffix from the last register operand specified,
2196 Destination register type is more significant than source
2199 for (op = i.operands; --op >= 0;)
2200 if ((i.types[op] & Reg)
2201 && !(i.tm.operand_types[op] & InOutPortReg))
2203 i.suffix = ((i.types[op] & Reg8) ? BYTE_MNEM_SUFFIX :
2204 (i.types[op] & Reg16) ? WORD_MNEM_SUFFIX :
2205 (i.types[op] & Reg64) ? QWORD_MNEM_SUFFIX :
2210 else if (i.suffix == BYTE_MNEM_SUFFIX)
2212 if (!check_byte_reg ())
2215 else if (i.suffix == LONG_MNEM_SUFFIX)
2217 if (!check_long_reg ())
2220 else if (i.suffix == QWORD_MNEM_SUFFIX)
2222 if (!check_qword_reg ())
2225 else if (i.suffix == WORD_MNEM_SUFFIX)
2227 if (!check_word_reg ())
2230 else if (intel_syntax && (i.tm.opcode_modifier & IgnoreSize))
2231 /* Do nothing if the instruction is going to ignore the prefix. */
2236 else if ((i.tm.opcode_modifier & DefaultSize) && !i.suffix)
2238 i.suffix = stackop_size;
2241 /* Change the opcode based on the operand size given by i.suffix;
2242 We need not change things for byte insns. */
2244 if (!i.suffix && (i.tm.opcode_modifier & W))
2246 as_bad (_("no instruction mnemonic suffix given and no register operands; can't size instruction"));
2250 if (i.suffix && i.suffix != BYTE_MNEM_SUFFIX)
2252 /* It's not a byte, select word/dword operation. */
2253 if (i.tm.opcode_modifier & W)
2255 if (i.tm.opcode_modifier & ShortForm)
2256 i.tm.base_opcode |= 8;
2258 i.tm.base_opcode |= 1;
2261 /* Now select between word & dword operations via the operand
2262 size prefix, except for instructions that will ignore this
2264 if (i.suffix != QWORD_MNEM_SUFFIX
2265 && !(i.tm.opcode_modifier & IgnoreSize)
2266 && ((i.suffix == LONG_MNEM_SUFFIX) == (flag_code == CODE_16BIT)
2267 || (flag_code == CODE_64BIT
2268 && (i.tm.opcode_modifier & JumpByte))))
2270 unsigned int prefix = DATA_PREFIX_OPCODE;
2271 if (i.tm.opcode_modifier & JumpByte) /* jcxz, loop */
2272 prefix = ADDR_PREFIX_OPCODE;
2274 if (!add_prefix (prefix))
2278 /* Set mode64 for an operand. */
2279 if (i.suffix == QWORD_MNEM_SUFFIX
2280 && flag_code == CODE_64BIT
2281 && (i.tm.opcode_modifier & NoRex64) == 0)
2282 i.rex |= REX_MODE64;
2284 /* Size floating point instruction. */
2285 if (i.suffix == LONG_MNEM_SUFFIX)
2287 if (i.tm.opcode_modifier & FloatMF)
2288 i.tm.base_opcode ^= 4;
2299 for (op = i.operands; --op >= 0;)
2301 /* If this is an eight bit register, it's OK. If it's the 16 or
2302 32 bit version of an eight bit register, we will just use the
2303 low portion, and that's OK too. */
2304 if (i.types[op] & Reg8)
2307 /* movzx and movsx should not generate this warning. */
2309 && (i.tm.base_opcode == 0xfb7
2310 || i.tm.base_opcode == 0xfb6
2311 || i.tm.base_opcode == 0x63
2312 || i.tm.base_opcode == 0xfbe
2313 || i.tm.base_opcode == 0xfbf))
2316 if ((i.types[op] & WordReg) && i.op[op].regs->reg_num < 4
2318 /* Check that the template allows eight bit regs. This
2319 kills insns such as `orb $1,%edx', which maybe should be
2321 && (i.tm.operand_types[op] & (Reg8 | InOutPortReg))
2325 /* Prohibit these changes in the 64bit mode, since the
2326 lowering is more complicated. */
2327 if (flag_code == CODE_64BIT
2328 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2330 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2331 i.op[op].regs->reg_name,
2335 #if REGISTER_WARNINGS
2337 && (i.tm.operand_types[op] & InOutPortReg) == 0)
2338 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2339 (i.op[op].regs + (i.types[op] & Reg16
2340 ? REGNAM_AL - REGNAM_AX
2341 : REGNAM_AL - REGNAM_EAX))->reg_name,
2342 i.op[op].regs->reg_name,
2347 /* Any other register is bad. */
2348 if (i.types[op] & (Reg | RegMMX | RegXMM
2350 | Control | Debug | Test
2351 | FloatReg | FloatAcc))
2353 as_bad (_("`%%%s' not allowed with `%s%c'"),
2354 i.op[op].regs->reg_name,
2368 for (op = i.operands; --op >= 0;)
2369 /* Reject eight bit registers, except where the template requires
2370 them. (eg. movzb) */
2371 if ((i.types[op] & Reg8) != 0
2372 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2374 as_bad (_("`%%%s' not allowed with `%s%c'"),
2375 i.op[op].regs->reg_name,
2380 /* Warn if the e prefix on a general reg is missing. */
2381 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2382 && (i.types[op] & Reg16) != 0
2383 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2385 /* Prohibit these changes in the 64bit mode, since the
2386 lowering is more complicated. */
2387 if (flag_code == CODE_64BIT)
2389 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2390 i.op[op].regs->reg_name,
2394 #if REGISTER_WARNINGS
2396 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2397 (i.op[op].regs + REGNAM_EAX - REGNAM_AX)->reg_name,
2398 i.op[op].regs->reg_name,
2402 /* Warn if the r prefix on a general reg is missing. */
2403 else if ((i.types[op] & Reg64) != 0
2404 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2406 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2407 i.op[op].regs->reg_name,
2419 for (op = i.operands; --op >= 0; )
2420 /* Reject eight bit registers, except where the template requires
2421 them. (eg. movzb) */
2422 if ((i.types[op] & Reg8) != 0
2423 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2425 as_bad (_("`%%%s' not allowed with `%s%c'"),
2426 i.op[op].regs->reg_name,
2431 /* Warn if the e prefix on a general reg is missing. */
2432 else if (((i.types[op] & Reg16) != 0
2433 || (i.types[op] & Reg32) != 0)
2434 && (i.tm.operand_types[op] & (Reg32 | Acc)) != 0)
2436 /* Prohibit these changes in the 64bit mode, since the
2437 lowering is more complicated. */
2438 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2439 i.op[op].regs->reg_name,
2450 for (op = i.operands; --op >= 0;)
2451 /* Reject eight bit registers, except where the template requires
2452 them. (eg. movzb) */
2453 if ((i.types[op] & Reg8) != 0
2454 && (i.tm.operand_types[op] & (Reg16 | Reg32 | Acc)) != 0)
2456 as_bad (_("`%%%s' not allowed with `%s%c'"),
2457 i.op[op].regs->reg_name,
2462 /* Warn if the e prefix on a general reg is present. */
2463 else if ((!quiet_warnings || flag_code == CODE_64BIT)
2464 && (i.types[op] & Reg32) != 0
2465 && (i.tm.operand_types[op] & (Reg16 | Acc)) != 0)
2467 /* Prohibit these changes in the 64bit mode, since the
2468 lowering is more complicated. */
2469 if (flag_code == CODE_64BIT)
2471 as_bad (_("Incorrect register `%%%s' used with `%c' suffix"),
2472 i.op[op].regs->reg_name,
2477 #if REGISTER_WARNINGS
2478 as_warn (_("using `%%%s' instead of `%%%s' due to `%c' suffix"),
2479 (i.op[op].regs + REGNAM_AX - REGNAM_EAX)->reg_name,
2480 i.op[op].regs->reg_name,
2490 unsigned int overlap0, overlap1, overlap2;
2492 overlap0 = i.types[0] & i.tm.operand_types[0];
2493 if ((overlap0 & (Imm8 | Imm8S | Imm16 | Imm32 | Imm32S))
2494 && overlap0 != Imm8 && overlap0 != Imm8S
2495 && overlap0 != Imm16 && overlap0 != Imm32S
2496 && overlap0 != Imm32 && overlap0 != Imm64)
2500 overlap0 &= (i.suffix == BYTE_MNEM_SUFFIX
2502 : (i.suffix == WORD_MNEM_SUFFIX
2504 : (i.suffix == QWORD_MNEM_SUFFIX
2508 else if (overlap0 == (Imm16 | Imm32S | Imm32)
2509 || overlap0 == (Imm16 | Imm32)
2510 || overlap0 == (Imm16 | Imm32S))
2512 overlap0 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2515 if (overlap0 != Imm8 && overlap0 != Imm8S
2516 && overlap0 != Imm16 && overlap0 != Imm32S
2517 && overlap0 != Imm32 && overlap0 != Imm64)
2519 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size"));
2523 i.types[0] = overlap0;
2525 overlap1 = i.types[1] & i.tm.operand_types[1];
2526 if ((overlap1 & (Imm8 | Imm8S | Imm16 | Imm32S | Imm32))
2527 && overlap1 != Imm8 && overlap1 != Imm8S
2528 && overlap1 != Imm16 && overlap1 != Imm32S
2529 && overlap1 != Imm32 && overlap1 != Imm64)
2533 overlap1 &= (i.suffix == BYTE_MNEM_SUFFIX
2535 : (i.suffix == WORD_MNEM_SUFFIX
2537 : (i.suffix == QWORD_MNEM_SUFFIX
2541 else if (overlap1 == (Imm16 | Imm32 | Imm32S)
2542 || overlap1 == (Imm16 | Imm32)
2543 || overlap1 == (Imm16 | Imm32S))
2545 overlap1 = ((flag_code == CODE_16BIT) ^ (i.prefix[DATA_PREFIX] != 0)
2548 if (overlap1 != Imm8 && overlap1 != Imm8S
2549 && overlap1 != Imm16 && overlap1 != Imm32S
2550 && overlap1 != Imm32 && overlap1 != Imm64)
2552 as_bad (_("no instruction mnemonic suffix given; can't determine immediate size %x %c"),overlap1, i.suffix);
2556 i.types[1] = overlap1;
2558 overlap2 = i.types[2] & i.tm.operand_types[2];
2559 assert ((overlap2 & Imm) == 0);
2560 i.types[2] = overlap2;
2568 /* Default segment register this instruction will use for memory
2569 accesses. 0 means unknown. This is only for optimizing out
2570 unnecessary segment overrides. */
2571 const seg_entry *default_seg = 0;
2573 /* The imul $imm, %reg instruction is converted into
2574 imul $imm, %reg, %reg, and the clr %reg instruction
2575 is converted into xor %reg, %reg. */
2576 if (i.tm.opcode_modifier & regKludge)
2578 unsigned int first_reg_op = (i.types[0] & Reg) ? 0 : 1;
2579 /* Pretend we saw the extra register operand. */
2580 assert (i.op[first_reg_op + 1].regs == 0);
2581 i.op[first_reg_op + 1].regs = i.op[first_reg_op].regs;
2582 i.types[first_reg_op + 1] = i.types[first_reg_op];
2586 if (i.tm.opcode_modifier & ShortForm)
2588 /* The register or float register operand is in operand 0 or 1. */
2589 unsigned int op = (i.types[0] & (Reg | FloatReg)) ? 0 : 1;
2590 /* Register goes in low 3 bits of opcode. */
2591 i.tm.base_opcode |= i.op[op].regs->reg_num;
2592 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2594 if (!quiet_warnings && (i.tm.opcode_modifier & Ugh) != 0)
2596 /* Warn about some common errors, but press on regardless.
2597 The first case can be generated by gcc (<= 2.8.1). */
2598 if (i.operands == 2)
2600 /* Reversed arguments on faddp, fsubp, etc. */
2601 as_warn (_("translating to `%s %%%s,%%%s'"), i.tm.name,
2602 i.op[1].regs->reg_name,
2603 i.op[0].regs->reg_name);
2607 /* Extraneous `l' suffix on fp insn. */
2608 as_warn (_("translating to `%s %%%s'"), i.tm.name,
2609 i.op[0].regs->reg_name);
2613 else if (i.tm.opcode_modifier & Modrm)
2615 /* The opcode is completed (modulo i.tm.extension_opcode which
2616 must be put into the modrm byte). Now, we make the modrm and
2617 index base bytes based on all the info we've collected. */
2619 default_seg = build_modrm_byte ();
2621 else if (i.tm.opcode_modifier & (Seg2ShortForm | Seg3ShortForm))
2623 if (i.tm.base_opcode == POP_SEG_SHORT
2624 && i.op[0].regs->reg_num == 1)
2626 as_bad (_("you can't `pop %%cs'"));
2629 i.tm.base_opcode |= (i.op[0].regs->reg_num << 3);
2630 if ((i.op[0].regs->reg_flags & RegRex) != 0)
2633 else if ((i.tm.base_opcode & ~(D | W)) == MOV_AX_DISP32)
2637 else if ((i.tm.opcode_modifier & IsString) != 0)
2639 /* For the string instructions that allow a segment override
2640 on one of their operands, the default segment is ds. */
2644 if (i.tm.base_opcode == 0x8d /* lea */ && i.seg[0] && !quiet_warnings)
2645 as_warn (_("segment override on `lea' is ineffectual"));
2647 /* If a segment was explicitly specified, and the specified segment
2648 is not the default, use an opcode prefix to select it. If we
2649 never figured out what the default segment is, then default_seg
2650 will be zero at this point, and the specified segment prefix will
2652 if ((i.seg[0]) && (i.seg[0] != default_seg))
2654 if (!add_prefix (i.seg[0]->seg_prefix))
2660 static const seg_entry *
2663 const seg_entry *default_seg = 0;
2665 /* i.reg_operands MUST be the number of real register operands;
2666 implicit registers do not count. */
2667 if (i.reg_operands == 2)
2669 unsigned int source, dest;
2670 source = ((i.types[0]
2671 & (Reg | RegMMX | RegXMM
2673 | Control | Debug | Test))
2678 /* One of the register operands will be encoded in the i.tm.reg
2679 field, the other in the combined i.tm.mode and i.tm.regmem
2680 fields. If no form of this instruction supports a memory
2681 destination operand, then we assume the source operand may
2682 sometimes be a memory operand and so we need to store the
2683 destination in the i.rm.reg field. */
2684 if ((i.tm.operand_types[dest] & AnyMem) == 0)
2686 i.rm.reg = i.op[dest].regs->reg_num;
2687 i.rm.regmem = i.op[source].regs->reg_num;
2688 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2690 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2695 i.rm.reg = i.op[source].regs->reg_num;
2696 i.rm.regmem = i.op[dest].regs->reg_num;
2697 if ((i.op[dest].regs->reg_flags & RegRex) != 0)
2699 if ((i.op[source].regs->reg_flags & RegRex) != 0)
2704 { /* If it's not 2 reg operands... */
2707 unsigned int fake_zero_displacement = 0;
2708 unsigned int op = ((i.types[0] & AnyMem)
2710 : (i.types[1] & AnyMem) ? 1 : 2);
2714 if (i.base_reg == 0)
2717 if (!i.disp_operands)
2718 fake_zero_displacement = 1;
2719 if (i.index_reg == 0)
2721 /* Operand is just <disp> */
2722 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0)
2723 && (flag_code != CODE_64BIT))
2725 i.rm.regmem = NO_BASE_REGISTER_16;
2726 i.types[op] &= ~Disp;
2727 i.types[op] |= Disp16;
2729 else if (flag_code != CODE_64BIT
2730 || (i.prefix[ADDR_PREFIX] != 0))
2732 i.rm.regmem = NO_BASE_REGISTER;
2733 i.types[op] &= ~Disp;
2734 i.types[op] |= Disp32;
2738 /* 64bit mode overwrites the 32bit absolute
2739 addressing by RIP relative addressing and
2740 absolute addressing is encoded by one of the
2741 redundant SIB forms. */
2742 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2743 i.sib.base = NO_BASE_REGISTER;
2744 i.sib.index = NO_INDEX_REGISTER;
2745 i.types[op] &= ~Disp;
2746 i.types[op] |= Disp32S;
2749 else /* !i.base_reg && i.index_reg */
2751 i.sib.index = i.index_reg->reg_num;
2752 i.sib.base = NO_BASE_REGISTER;
2753 i.sib.scale = i.log2_scale_factor;
2754 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2755 i.types[op] &= ~Disp;
2756 if (flag_code != CODE_64BIT)
2757 i.types[op] |= Disp32; /* Must be 32 bit */
2759 i.types[op] |= Disp32S;
2760 if ((i.index_reg->reg_flags & RegRex) != 0)
2764 /* RIP addressing for 64bit mode. */
2765 else if (i.base_reg->reg_type == BaseIndex)
2767 i.rm.regmem = NO_BASE_REGISTER;
2768 i.types[op] &= ~Disp;
2769 i.types[op] |= Disp32S;
2770 i.flags[op] = Operand_PCrel;
2772 else if (i.base_reg->reg_type & Reg16)
2774 switch (i.base_reg->reg_num)
2777 if (i.index_reg == 0)
2779 else /* (%bx,%si) -> 0, or (%bx,%di) -> 1 */
2780 i.rm.regmem = i.index_reg->reg_num - 6;
2784 if (i.index_reg == 0)
2787 if ((i.types[op] & Disp) == 0)
2789 /* fake (%bp) into 0(%bp) */
2790 i.types[op] |= Disp8;
2791 fake_zero_displacement = 1;
2794 else /* (%bp,%si) -> 2, or (%bp,%di) -> 3 */
2795 i.rm.regmem = i.index_reg->reg_num - 6 + 2;
2797 default: /* (%si) -> 4 or (%di) -> 5 */
2798 i.rm.regmem = i.base_reg->reg_num - 6 + 4;
2800 i.rm.mode = mode_from_disp_size (i.types[op]);
2802 else /* i.base_reg and 32/64 bit mode */
2804 if (flag_code == CODE_64BIT
2805 && (i.types[op] & Disp))
2807 if (i.types[op] & Disp8)
2808 i.types[op] = Disp8 | Disp32S;
2810 i.types[op] = Disp32S;
2812 i.rm.regmem = i.base_reg->reg_num;
2813 if ((i.base_reg->reg_flags & RegRex) != 0)
2815 i.sib.base = i.base_reg->reg_num;
2816 /* x86-64 ignores REX prefix bit here to avoid decoder
2818 if ((i.base_reg->reg_num & 7) == EBP_REG_NUM)
2821 if (i.disp_operands == 0)
2823 fake_zero_displacement = 1;
2824 i.types[op] |= Disp8;
2827 else if (i.base_reg->reg_num == ESP_REG_NUM)
2831 i.sib.scale = i.log2_scale_factor;
2832 if (i.index_reg == 0)
2834 /* <disp>(%esp) becomes two byte modrm with no index
2835 register. We've already stored the code for esp
2836 in i.rm.regmem ie. ESCAPE_TO_TWO_BYTE_ADDRESSING.
2837 Any base register besides %esp will not use the
2838 extra modrm byte. */
2839 i.sib.index = NO_INDEX_REGISTER;
2840 #if !SCALE1_WHEN_NO_INDEX
2841 /* Another case where we force the second modrm byte. */
2842 if (i.log2_scale_factor)
2843 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2848 i.sib.index = i.index_reg->reg_num;
2849 i.rm.regmem = ESCAPE_TO_TWO_BYTE_ADDRESSING;
2850 if ((i.index_reg->reg_flags & RegRex) != 0)
2853 i.rm.mode = mode_from_disp_size (i.types[op]);
2856 if (fake_zero_displacement)
2858 /* Fakes a zero displacement assuming that i.types[op]
2859 holds the correct displacement size. */
2862 assert (i.op[op].disps == 0);
2863 exp = &disp_expressions[i.disp_operands++];
2864 i.op[op].disps = exp;
2865 exp->X_op = O_constant;
2866 exp->X_add_number = 0;
2867 exp->X_add_symbol = (symbolS *) 0;
2868 exp->X_op_symbol = (symbolS *) 0;
2872 /* Fill in i.rm.reg or i.rm.regmem field with register operand
2873 (if any) based on i.tm.extension_opcode. Again, we must be
2874 careful to make sure that segment/control/debug/test/MMX
2875 registers are coded into the i.rm.reg field. */
2880 & (Reg | RegMMX | RegXMM
2882 | Control | Debug | Test))
2885 & (Reg | RegMMX | RegXMM
2887 | Control | Debug | Test))
2890 /* If there is an extension opcode to put here, the register
2891 number must be put into the regmem field. */
2892 if (i.tm.extension_opcode != None)
2894 i.rm.regmem = i.op[op].regs->reg_num;
2895 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2900 i.rm.reg = i.op[op].regs->reg_num;
2901 if ((i.op[op].regs->reg_flags & RegRex) != 0)
2905 /* Now, if no memory operand has set i.rm.mode = 0, 1, 2 we
2906 must set it to 3 to indicate this is a register operand
2907 in the regmem field. */
2908 if (!i.mem_operands)
2912 /* Fill in i.rm.reg field with extension opcode (if any). */
2913 if (i.tm.extension_opcode != None)
2914 i.rm.reg = i.tm.extension_opcode;
2925 relax_substateT subtype;
2930 if (flag_code == CODE_16BIT)
2934 if (i.prefix[DATA_PREFIX] != 0)
2940 /* Pentium4 branch hints. */
2941 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
2942 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
2947 if (i.prefix[REX_PREFIX] != 0)
2953 if (i.prefixes != 0 && !intel_syntax)
2954 as_warn (_("skipping prefixes on this instruction"));
2956 /* It's always a symbol; End frag & setup for relax.
2957 Make sure there is enough room in this frag for the largest
2958 instruction we may generate in md_convert_frag. This is 2
2959 bytes for the opcode and room for the prefix and largest
2961 frag_grow (prefix + 2 + 4);
2962 /* Prefix and 1 opcode byte go in fr_fix. */
2963 p = frag_more (prefix + 1);
2964 if (i.prefix[DATA_PREFIX] != 0)
2965 *p++ = DATA_PREFIX_OPCODE;
2966 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE
2967 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE)
2968 *p++ = i.prefix[SEG_PREFIX];
2969 if (i.prefix[REX_PREFIX] != 0)
2970 *p++ = i.prefix[REX_PREFIX];
2971 *p = i.tm.base_opcode;
2973 if ((unsigned char) *p == JUMP_PC_RELATIVE)
2974 subtype = ENCODE_RELAX_STATE (UNCOND_JUMP, SMALL);
2975 else if ((cpu_arch_flags & Cpu386) != 0)
2976 subtype = ENCODE_RELAX_STATE (COND_JUMP, SMALL);
2978 subtype = ENCODE_RELAX_STATE (COND_JUMP86, SMALL);
2981 sym = i.op[0].disps->X_add_symbol;
2982 off = i.op[0].disps->X_add_number;
2984 if (i.op[0].disps->X_op != O_constant
2985 && i.op[0].disps->X_op != O_symbol)
2987 /* Handle complex expressions. */
2988 sym = make_expr_symbol (i.op[0].disps);
2992 /* 1 possible extra opcode + 4 byte displacement go in var part.
2993 Pass reloc in fr_var. */
2994 frag_var (rs_machine_dependent, 5, i.reloc[0], subtype, sym, off, p);
3004 if (i.tm.opcode_modifier & JumpByte)
3006 /* This is a loop or jecxz type instruction. */
3008 if (i.prefix[ADDR_PREFIX] != 0)
3010 FRAG_APPEND_1_CHAR (ADDR_PREFIX_OPCODE);
3013 /* Pentium4 branch hints. */
3014 if (i.prefix[SEG_PREFIX] == CS_PREFIX_OPCODE /* not taken */
3015 || i.prefix[SEG_PREFIX] == DS_PREFIX_OPCODE /* taken */)
3017 FRAG_APPEND_1_CHAR (i.prefix[SEG_PREFIX]);
3026 if (flag_code == CODE_16BIT)
3029 if (i.prefix[DATA_PREFIX] != 0)
3031 FRAG_APPEND_1_CHAR (DATA_PREFIX_OPCODE);
3041 if (i.prefix[REX_PREFIX] != 0)
3043 FRAG_APPEND_1_CHAR (i.prefix[REX_PREFIX]);
3047 if (i.prefixes != 0 && !intel_syntax)
3048 as_warn (_("skipping prefixes on this instruction"));
3050 p = frag_more (1 + size);
3051 *p++ = i.tm.base_opcode;
3053 fixP = fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3054 i.op[0].disps, 1, reloc (size, 1, 1, i.reloc[0]));
3056 /* All jumps handled here are signed, but don't use a signed limit
3057 check for 32 and 16 bit jumps as we want to allow wrap around at
3058 4G and 64k respectively. */
3060 fixP->fx_signed = 1;
3064 output_interseg_jump ()
3072 if (flag_code == CODE_16BIT)
3076 if (i.prefix[DATA_PREFIX] != 0)
3082 if (i.prefix[REX_PREFIX] != 0)
3092 if (i.prefixes != 0 && !intel_syntax)
3093 as_warn (_("skipping prefixes on this instruction"));
3095 /* 1 opcode; 2 segment; offset */
3096 p = frag_more (prefix + 1 + 2 + size);
3098 if (i.prefix[DATA_PREFIX] != 0)
3099 *p++ = DATA_PREFIX_OPCODE;
3101 if (i.prefix[REX_PREFIX] != 0)
3102 *p++ = i.prefix[REX_PREFIX];
3104 *p++ = i.tm.base_opcode;
3105 if (i.op[1].imms->X_op == O_constant)
3107 offsetT n = i.op[1].imms->X_add_number;
3110 && !fits_in_unsigned_word (n)
3111 && !fits_in_signed_word (n))
3113 as_bad (_("16-bit jump out of range"));
3116 md_number_to_chars (p, n, size);
3119 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3120 i.op[1].imms, 0, reloc (size, 0, 0, i.reloc[1]));
3121 if (i.op[0].imms->X_op != O_constant)
3122 as_bad (_("can't handle non absolute segment in `%s'"),
3124 md_number_to_chars (p + size, (valueT) i.op[0].imms->X_add_number, 2);
3130 fragS *insn_start_frag;
3131 offsetT insn_start_off;
3133 /* Tie dwarf2 debug info to the address at the start of the insn.
3134 We can't do this after the insn has been output as the current
3135 frag may have been closed off. eg. by frag_var. */
3136 dwarf2_emit_insn (0);
3138 insn_start_frag = frag_now;
3139 insn_start_off = frag_now_fix ();
3142 if (i.tm.opcode_modifier & Jump)
3144 else if (i.tm.opcode_modifier & (JumpByte | JumpDword))
3146 else if (i.tm.opcode_modifier & JumpInterSegment)
3147 output_interseg_jump ();
3150 /* Output normal instructions here. */
3153 unsigned int prefix;
3155 /* All opcodes on i386 have either 1 or 2 bytes. Supplemental
3156 Streaming SIMD extensions 3 Instructions have 3 bytes. We may
3157 use one more higher byte to specify a prefix the instruction
3159 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3161 if (i.tm.base_opcode & 0xff000000)
3163 prefix = (i.tm.base_opcode >> 24) & 0xff;
3167 else if ((i.tm.base_opcode & 0xff0000) != 0)
3169 prefix = (i.tm.base_opcode >> 16) & 0xff;
3170 if ((i.tm.cpu_flags & CpuPadLock) != 0)
3173 if (prefix != REPE_PREFIX_OPCODE
3174 || i.prefix[LOCKREP_PREFIX] != REPE_PREFIX_OPCODE)
3175 add_prefix (prefix);
3178 add_prefix (prefix);
3181 /* The prefix bytes. */
3183 q < i.prefix + sizeof (i.prefix) / sizeof (i.prefix[0]);
3189 md_number_to_chars (p, (valueT) *q, 1);
3193 /* Now the opcode; be careful about word order here! */
3194 if (fits_in_unsigned_byte (i.tm.base_opcode))
3196 FRAG_APPEND_1_CHAR (i.tm.base_opcode);
3200 if ((i.tm.cpu_flags & CpuSSSE3) != 0)
3203 *p++ = (i.tm.base_opcode >> 16) & 0xff;
3208 /* Put out high byte first: can't use md_number_to_chars! */
3209 *p++ = (i.tm.base_opcode >> 8) & 0xff;
3210 *p = i.tm.base_opcode & 0xff;
3213 /* Now the modrm byte and sib byte (if present). */
3214 if (i.tm.opcode_modifier & Modrm)
3217 md_number_to_chars (p,
3218 (valueT) (i.rm.regmem << 0
3222 /* If i.rm.regmem == ESP (4)
3223 && i.rm.mode != (Register mode)
3225 ==> need second modrm byte. */
3226 if (i.rm.regmem == ESCAPE_TO_TWO_BYTE_ADDRESSING
3228 && !(i.base_reg && (i.base_reg->reg_type & Reg16) != 0))
3231 md_number_to_chars (p,
3232 (valueT) (i.sib.base << 0
3234 | i.sib.scale << 6),
3239 if (i.disp_operands)
3240 output_disp (insn_start_frag, insn_start_off);
3243 output_imm (insn_start_frag, insn_start_off);
3251 #endif /* DEBUG386 */
3255 output_disp (insn_start_frag, insn_start_off)
3256 fragS *insn_start_frag;
3257 offsetT insn_start_off;
3262 for (n = 0; n < i.operands; n++)
3264 if (i.types[n] & Disp)
3266 if (i.op[n].disps->X_op == O_constant)
3272 if (i.types[n] & (Disp8 | Disp16 | Disp64))
3275 if (i.types[n] & Disp8)
3277 if (i.types[n] & Disp64)
3280 val = offset_in_range (i.op[n].disps->X_add_number,
3282 p = frag_more (size);
3283 md_number_to_chars (p, val, size);
3287 enum bfd_reloc_code_real reloc_type;
3290 int pcrel = (i.flags[n] & Operand_PCrel) != 0;
3292 /* The PC relative address is computed relative
3293 to the instruction boundary, so in case immediate
3294 fields follows, we need to adjust the value. */
3295 if (pcrel && i.imm_operands)
3300 for (n1 = 0; n1 < i.operands; n1++)
3301 if (i.types[n1] & Imm)
3303 if (i.types[n1] & (Imm8 | Imm8S | Imm16 | Imm64))
3306 if (i.types[n1] & (Imm8 | Imm8S))
3308 if (i.types[n1] & Imm64)
3313 /* We should find the immediate. */
3314 if (n1 == i.operands)
3316 i.op[n].disps->X_add_number -= imm_size;
3319 if (i.types[n] & Disp32S)
3322 if (i.types[n] & (Disp16 | Disp64))
3325 if (i.types[n] & Disp64)
3329 p = frag_more (size);
3330 reloc_type = reloc (size, pcrel, sign, i.reloc[n]);
3331 if (reloc_type == BFD_RELOC_32
3333 && GOT_symbol == i.op[n].disps->X_add_symbol
3334 && (i.op[n].disps->X_op == O_symbol
3335 || (i.op[n].disps->X_op == O_add
3336 && ((symbol_get_value_expression
3337 (i.op[n].disps->X_op_symbol)->X_op)
3342 if (insn_start_frag == frag_now)
3343 add = (p - frag_now->fr_literal) - insn_start_off;
3348 add = insn_start_frag->fr_fix - insn_start_off;
3349 for (fr = insn_start_frag->fr_next;
3350 fr && fr != frag_now; fr = fr->fr_next)
3352 add += p - frag_now->fr_literal;
3355 /* We don't support dynamic linking on x86-64 yet. */
3356 if (flag_code == CODE_64BIT)
3358 reloc_type = BFD_RELOC_386_GOTPC;
3359 i.op[n].disps->X_add_number += add;
3361 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3362 i.op[n].disps, pcrel, reloc_type);
3369 output_imm (insn_start_frag, insn_start_off)
3370 fragS *insn_start_frag;
3371 offsetT insn_start_off;
3376 for (n = 0; n < i.operands; n++)
3378 if (i.types[n] & Imm)
3380 if (i.op[n].imms->X_op == O_constant)
3386 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3389 if (i.types[n] & (Imm8 | Imm8S))
3391 else if (i.types[n] & Imm64)
3394 val = offset_in_range (i.op[n].imms->X_add_number,
3396 p = frag_more (size);
3397 md_number_to_chars (p, val, size);
3401 /* Not absolute_section.
3402 Need a 32-bit fixup (don't support 8bit
3403 non-absolute imms). Try to support other
3405 enum bfd_reloc_code_real reloc_type;
3409 if ((i.types[n] & (Imm32S))
3410 && i.suffix == QWORD_MNEM_SUFFIX)
3412 if (i.types[n] & (Imm8 | Imm8S | Imm16 | Imm64))
3415 if (i.types[n] & (Imm8 | Imm8S))
3417 if (i.types[n] & Imm64)
3421 p = frag_more (size);
3422 reloc_type = reloc (size, 0, sign, i.reloc[n]);
3424 /* This is tough to explain. We end up with this one if we
3425 * have operands that look like
3426 * "_GLOBAL_OFFSET_TABLE_+[.-.L284]". The goal here is to
3427 * obtain the absolute address of the GOT, and it is strongly
3428 * preferable from a performance point of view to avoid using
3429 * a runtime relocation for this. The actual sequence of
3430 * instructions often look something like:
3435 * addl $_GLOBAL_OFFSET_TABLE_+[.-.L66],%ebx
3437 * The call and pop essentially return the absolute address
3438 * of the label .L66 and store it in %ebx. The linker itself
3439 * will ultimately change the first operand of the addl so
3440 * that %ebx points to the GOT, but to keep things simple, the
3441 * .o file must have this operand set so that it generates not
3442 * the absolute address of .L66, but the absolute address of
3443 * itself. This allows the linker itself simply treat a GOTPC
3444 * relocation as asking for a pcrel offset to the GOT to be
3445 * added in, and the addend of the relocation is stored in the
3446 * operand field for the instruction itself.
3448 * Our job here is to fix the operand so that it would add
3449 * the correct offset so that %ebx would point to itself. The
3450 * thing that is tricky is that .-.L66 will point to the
3451 * beginning of the instruction, so we need to further modify
3452 * the operand so that it will point to itself. There are
3453 * other cases where you have something like:
3455 * .long $_GLOBAL_OFFSET_TABLE_+[.-.L66]
3457 * and here no correction would be required. Internally in
3458 * the assembler we treat operands of this form as not being
3459 * pcrel since the '.' is explicitly mentioned, and I wonder
3460 * whether it would simplify matters to do it this way. Who
3461 * knows. In earlier versions of the PIC patches, the
3462 * pcrel_adjust field was used to store the correction, but
3463 * since the expression is not pcrel, I felt it would be
3464 * confusing to do it this way. */
3466 if (reloc_type == BFD_RELOC_32
3468 && GOT_symbol == i.op[n].imms->X_add_symbol
3469 && (i.op[n].imms->X_op == O_symbol
3470 || (i.op[n].imms->X_op == O_add
3471 && ((symbol_get_value_expression
3472 (i.op[n].imms->X_op_symbol)->X_op)
3477 if (insn_start_frag == frag_now)
3478 add = (p - frag_now->fr_literal) - insn_start_off;
3483 add = insn_start_frag->fr_fix - insn_start_off;
3484 for (fr = insn_start_frag->fr_next;
3485 fr && fr != frag_now; fr = fr->fr_next)
3487 add += p - frag_now->fr_literal;
3490 /* We don't support dynamic linking on x86-64 yet. */
3491 if (flag_code == CODE_64BIT)
3493 reloc_type = BFD_RELOC_386_GOTPC;
3494 i.op[n].imms->X_add_number += add;
3496 fix_new_exp (frag_now, p - frag_now->fr_literal, size,
3497 i.op[n].imms, 0, reloc_type);
3504 static char *lex_got PARAMS ((enum bfd_reloc_code_real *, int *));
3506 /* Parse operands of the form
3507 <symbol>@GOTOFF+<nnn>
3508 and similar .plt or .got references.
3510 If we find one, set up the correct relocation in RELOC and copy the
3511 input string, minus the `@GOTOFF' into a malloc'd buffer for
3512 parsing by the calling routine. Return this buffer, and if ADJUST
3513 is non-null set it to the length of the string we removed from the
3514 input line. Otherwise return NULL. */
3516 lex_got (reloc, adjust)
3517 enum bfd_reloc_code_real *reloc;
3520 static const char * const mode_name[NUM_FLAG_CODE] = { "32", "16", "64" };
3521 static const struct {
3523 const enum bfd_reloc_code_real rel[NUM_FLAG_CODE];
3525 { "PLT", { BFD_RELOC_386_PLT32, 0, BFD_RELOC_X86_64_PLT32 } },
3526 { "GOTOFF", { BFD_RELOC_386_GOTOFF, 0, 0 } },
3527 { "GOTPCREL", { 0, 0, BFD_RELOC_X86_64_GOTPCREL } },
3528 { "TLSGD", { BFD_RELOC_386_TLS_GD, 0, BFD_RELOC_X86_64_TLSGD } },
3529 { "TLSLDM", { BFD_RELOC_386_TLS_LDM, 0, 0 } },
3530 { "TLSLD", { 0, 0, BFD_RELOC_X86_64_TLSLD } },
3531 { "GOTTPOFF", { BFD_RELOC_386_TLS_IE_32, 0, BFD_RELOC_X86_64_GOTTPOFF } },
3532 { "TPOFF", { BFD_RELOC_386_TLS_LE_32, 0, BFD_RELOC_X86_64_TPOFF32 } },
3533 { "NTPOFF", { BFD_RELOC_386_TLS_LE, 0, 0 } },
3534 { "DTPOFF", { BFD_RELOC_386_TLS_LDO_32, 0, BFD_RELOC_X86_64_DTPOFF32 } },
3535 { "GOTNTPOFF",{ BFD_RELOC_386_TLS_GOTIE, 0, 0 } },
3536 { "INDNTPOFF",{ BFD_RELOC_386_TLS_IE, 0, 0 } },
3537 { "GOT", { BFD_RELOC_386_GOT32, 0, BFD_RELOC_X86_64_GOT32 } }
3542 for (cp = input_line_pointer; *cp != '@'; cp++)
3543 if (is_end_of_line[(unsigned char) *cp])
3546 for (j = 0; j < sizeof (gotrel) / sizeof (gotrel[0]); j++)
3550 len = strlen (gotrel[j].str);
3551 if (strncasecmp (cp + 1, gotrel[j].str, len) == 0)
3553 if (gotrel[j].rel[(unsigned int) flag_code] != 0)
3556 char *tmpbuf, *past_reloc;
3558 *reloc = gotrel[j].rel[(unsigned int) flag_code];
3562 if (GOT_symbol == NULL)
3563 GOT_symbol = symbol_find_or_make (GLOBAL_OFFSET_TABLE_NAME);
3565 /* Replace the relocation token with ' ', so that
3566 errors like foo@GOTOFF1 will be detected. */
3568 /* The length of the first part of our input line. */
3569 first = cp - input_line_pointer;
3571 /* The second part goes from after the reloc token until
3572 (and including) an end_of_line char. Don't use strlen
3573 here as the end_of_line char may not be a NUL. */
3574 past_reloc = cp + 1 + len;
3575 for (cp = past_reloc; !is_end_of_line[(unsigned char) *cp++]; )
3577 second = cp - past_reloc;
3579 /* Allocate and copy string. The trailing NUL shouldn't
3580 be necessary, but be safe. */
3581 tmpbuf = xmalloc (first + second + 2);
3582 memcpy (tmpbuf, input_line_pointer, first);
3583 tmpbuf[first] = ' ';
3584 memcpy (tmpbuf + first + 1, past_reloc, second);
3585 tmpbuf[first + second + 1] = '\0';
3589 as_bad (_("@%s reloc is not supported in %s bit mode"),
3590 gotrel[j].str, mode_name[(unsigned int) flag_code]);
3595 /* Might be a symbol version string. Don't as_bad here. */
3599 /* x86_cons_fix_new is called via the expression parsing code when a
3600 reloc is needed. We use this hook to get the correct .got reloc. */
3601 static enum bfd_reloc_code_real got_reloc = NO_RELOC;
3604 x86_cons_fix_new (frag, off, len, exp)
3610 enum bfd_reloc_code_real r = reloc (len, 0, 0, got_reloc);
3611 got_reloc = NO_RELOC;
3612 fix_new_exp (frag, off, len, exp, 0, r);
3616 x86_cons (exp, size)
3622 /* Handle @GOTOFF and the like in an expression. */
3624 char *gotfree_input_line;
3627 save = input_line_pointer;
3628 gotfree_input_line = lex_got (&got_reloc, &adjust);
3629 if (gotfree_input_line)
3630 input_line_pointer = gotfree_input_line;
3634 if (gotfree_input_line)
3636 /* expression () has merrily parsed up to the end of line,
3637 or a comma - in the wrong buffer. Transfer how far
3638 input_line_pointer has moved to the right buffer. */
3639 input_line_pointer = (save
3640 + (input_line_pointer - gotfree_input_line)
3642 free (gotfree_input_line);
3650 static int i386_immediate PARAMS ((char *));
3653 i386_immediate (imm_start)
3656 char *save_input_line_pointer;
3658 char *gotfree_input_line;
3663 if (i.imm_operands == MAX_IMMEDIATE_OPERANDS)
3665 as_bad (_("only 1 or 2 immediate operands are allowed"));
3669 exp = &im_expressions[i.imm_operands++];
3670 i.op[this_operand].imms = exp;
3672 if (is_space_char (*imm_start))
3675 save_input_line_pointer = input_line_pointer;
3676 input_line_pointer = imm_start;
3679 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3680 if (gotfree_input_line)
3681 input_line_pointer = gotfree_input_line;
3684 exp_seg = expression (exp);
3687 if (*input_line_pointer)
3688 as_bad (_("junk `%s' after expression"), input_line_pointer);
3690 input_line_pointer = save_input_line_pointer;
3692 if (gotfree_input_line)
3693 free (gotfree_input_line);
3696 if (exp->X_op == O_absent || exp->X_op == O_big)
3698 /* Missing or bad expr becomes absolute 0. */
3699 as_bad (_("missing or invalid immediate expression `%s' taken as 0"),
3701 exp->X_op = O_constant;
3702 exp->X_add_number = 0;
3703 exp->X_add_symbol = (symbolS *) 0;
3704 exp->X_op_symbol = (symbolS *) 0;
3706 else if (exp->X_op == O_constant)
3708 /* Size it properly later. */
3709 i.types[this_operand] |= Imm64;
3710 /* If BFD64, sign extend val. */
3711 if (!use_rela_relocations)
3712 if ((exp->X_add_number & ~(((addressT) 2 << 31) - 1)) == 0)
3713 exp->X_add_number = (exp->X_add_number ^ ((addressT) 1 << 31)) - ((addressT) 1 << 31);
3715 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3716 else if (OUTPUT_FLAVOR == bfd_target_aout_flavour
3717 && exp_seg != absolute_section
3718 && exp_seg != text_section
3719 && exp_seg != data_section
3720 && exp_seg != bss_section
3721 && exp_seg != undefined_section
3722 && !bfd_is_com_section (exp_seg))
3724 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3730 /* This is an address. The size of the address will be
3731 determined later, depending on destination register,
3732 suffix, or the default for the section. */
3733 i.types[this_operand] |= Imm8 | Imm16 | Imm32 | Imm32S | Imm64;
3739 static char *i386_scale PARAMS ((char *));
3746 char *save = input_line_pointer;
3748 input_line_pointer = scale;
3749 val = get_absolute_expression ();
3755 i.log2_scale_factor = 0;
3758 i.log2_scale_factor = 1;
3761 i.log2_scale_factor = 2;
3764 i.log2_scale_factor = 3;
3767 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
3769 input_line_pointer = save;
3772 if (i.log2_scale_factor != 0 && i.index_reg == 0)
3774 as_warn (_("scale factor of %d without an index register"),
3775 1 << i.log2_scale_factor);
3776 #if SCALE1_WHEN_NO_INDEX
3777 i.log2_scale_factor = 0;
3780 scale = input_line_pointer;
3781 input_line_pointer = save;
3785 static int i386_displacement PARAMS ((char *, char *));
3788 i386_displacement (disp_start, disp_end)
3794 char *save_input_line_pointer;
3796 char *gotfree_input_line;
3798 int bigdisp = Disp32;
3800 if (flag_code == CODE_64BIT)
3802 if (i.prefix[ADDR_PREFIX] == 0)
3805 else if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3807 i.types[this_operand] |= bigdisp;
3809 exp = &disp_expressions[i.disp_operands];
3810 i.op[this_operand].disps = exp;
3812 save_input_line_pointer = input_line_pointer;
3813 input_line_pointer = disp_start;
3814 END_STRING_AND_SAVE (disp_end);
3816 #ifndef GCC_ASM_O_HACK
3817 #define GCC_ASM_O_HACK 0
3820 END_STRING_AND_SAVE (disp_end + 1);
3821 if ((i.types[this_operand] & BaseIndex) != 0
3822 && displacement_string_end[-1] == '+')
3824 /* This hack is to avoid a warning when using the "o"
3825 constraint within gcc asm statements.
3828 #define _set_tssldt_desc(n,addr,limit,type) \
3829 __asm__ __volatile__ ( \
3831 "movw %w1,2+%0\n\t" \
3833 "movb %b1,4+%0\n\t" \
3834 "movb %4,5+%0\n\t" \
3835 "movb $0,6+%0\n\t" \
3836 "movb %h1,7+%0\n\t" \
3838 : "=o"(*(n)) : "q" (addr), "ri"(limit), "i"(type))
3840 This works great except that the output assembler ends
3841 up looking a bit weird if it turns out that there is
3842 no offset. You end up producing code that looks like:
3855 So here we provide the missing zero. */
3857 *displacement_string_end = '0';
3861 gotfree_input_line = lex_got (&i.reloc[this_operand], NULL);
3862 if (gotfree_input_line)
3863 input_line_pointer = gotfree_input_line;
3866 exp_seg = expression (exp);
3869 if (*input_line_pointer)
3870 as_bad (_("junk `%s' after expression"), input_line_pointer);
3872 RESTORE_END_STRING (disp_end + 1);
3874 RESTORE_END_STRING (disp_end);
3875 input_line_pointer = save_input_line_pointer;
3877 if (gotfree_input_line)
3878 free (gotfree_input_line);
3881 /* We do this to make sure that the section symbol is in
3882 the symbol table. We will ultimately change the relocation
3883 to be relative to the beginning of the section. */
3884 if (i.reloc[this_operand] == BFD_RELOC_386_GOTOFF
3885 || i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3887 if (exp->X_op != O_symbol)
3889 as_bad (_("bad expression used with @%s"),
3890 (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL
3896 if (S_IS_LOCAL (exp->X_add_symbol)
3897 && S_GET_SEGMENT (exp->X_add_symbol) != undefined_section)
3898 section_symbol (S_GET_SEGMENT (exp->X_add_symbol));
3899 exp->X_op = O_subtract;
3900 exp->X_op_symbol = GOT_symbol;
3901 if (i.reloc[this_operand] == BFD_RELOC_X86_64_GOTPCREL)
3902 i.reloc[this_operand] = BFD_RELOC_32_PCREL;
3904 i.reloc[this_operand] = BFD_RELOC_32;
3907 if (exp->X_op == O_absent || exp->X_op == O_big)
3909 /* Missing or bad expr becomes absolute 0. */
3910 as_bad (_("missing or invalid displacement expression `%s' taken as 0"),
3912 exp->X_op = O_constant;
3913 exp->X_add_number = 0;
3914 exp->X_add_symbol = (symbolS *) 0;
3915 exp->X_op_symbol = (symbolS *) 0;
3918 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
3919 if (exp->X_op != O_constant
3920 && OUTPUT_FLAVOR == bfd_target_aout_flavour
3921 && exp_seg != absolute_section
3922 && exp_seg != text_section
3923 && exp_seg != data_section
3924 && exp_seg != bss_section
3925 && exp_seg != undefined_section
3926 && !bfd_is_com_section (exp_seg))
3928 as_bad (_("unimplemented segment %s in operand"), exp_seg->name);
3932 else if (flag_code == CODE_64BIT)
3933 i.types[this_operand] |= Disp32S | Disp32;
3937 static int i386_index_check PARAMS ((const char *));
3939 /* Make sure the memory operand we've been dealt is valid.
3940 Return 1 on success, 0 on a failure. */
3943 i386_index_check (operand_string)
3944 const char *operand_string;
3947 #if INFER_ADDR_PREFIX
3953 if (flag_code == CODE_64BIT)
3955 if (i.prefix[ADDR_PREFIX] == 0)
3959 && ((i.base_reg->reg_type & Reg64) == 0)
3960 && (i.base_reg->reg_type != BaseIndex
3963 && ((i.index_reg->reg_type & (Reg64 | BaseIndex))
3964 != (Reg64 | BaseIndex))))
3971 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
3973 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
3974 != (Reg32 | BaseIndex))))
3980 if ((flag_code == CODE_16BIT) ^ (i.prefix[ADDR_PREFIX] != 0))
3984 && ((i.base_reg->reg_type & (Reg16 | BaseIndex | RegRex))
3985 != (Reg16 | BaseIndex)))
3987 && (((i.index_reg->reg_type & (Reg16 | BaseIndex))
3988 != (Reg16 | BaseIndex))
3990 && i.base_reg->reg_num < 6
3991 && i.index_reg->reg_num >= 6
3992 && i.log2_scale_factor == 0))))
3999 && (i.base_reg->reg_type & (Reg32 | RegRex)) != Reg32)
4001 && ((i.index_reg->reg_type & (Reg32 | BaseIndex | RegRex))
4002 != (Reg32 | BaseIndex))))
4008 #if INFER_ADDR_PREFIX
4009 if (flag_code != CODE_64BIT
4010 && i.prefix[ADDR_PREFIX] == 0 && stackop_size != '\0')
4012 i.prefix[ADDR_PREFIX] = ADDR_PREFIX_OPCODE;
4014 /* Change the size of any displacement too. At most one of
4015 Disp16 or Disp32 is set.
4016 FIXME. There doesn't seem to be any real need for separate
4017 Disp16 and Disp32 flags. The same goes for Imm16 and Imm32.
4018 Removing them would probably clean up the code quite a lot. */
4019 if (i.types[this_operand] & (Disp16 | Disp32))
4020 i.types[this_operand] ^= (Disp16 | Disp32);
4025 as_bad (_("`%s' is not a valid base/index expression"),
4029 as_bad (_("`%s' is not a valid %s bit base/index expression"),
4031 flag_code_names[flag_code]);
4037 /* Parse OPERAND_STRING into the i386_insn structure I. Returns non-zero
4041 i386_operand (operand_string)
4042 char *operand_string;
4046 char *op_string = operand_string;
4048 if (is_space_char (*op_string))
4051 /* We check for an absolute prefix (differentiating,
4052 for example, 'jmp pc_relative_label' from 'jmp *absolute_label'. */
4053 if (*op_string == ABSOLUTE_PREFIX)
4056 if (is_space_char (*op_string))
4058 i.types[this_operand] |= JumpAbsolute;
4061 /* Check if operand is a register. */
4062 if ((*op_string == REGISTER_PREFIX || allow_naked_reg)
4063 && (r = parse_register (op_string, &end_op)) != NULL)
4065 /* Check for a segment override by searching for ':' after a
4066 segment register. */
4068 if (is_space_char (*op_string))
4070 if (*op_string == ':' && (r->reg_type & (SReg2 | SReg3)))
4075 i.seg[i.mem_operands] = &es;
4078 i.seg[i.mem_operands] = &cs;
4081 i.seg[i.mem_operands] = &ss;
4084 i.seg[i.mem_operands] = &ds;
4087 i.seg[i.mem_operands] = &fs;
4090 i.seg[i.mem_operands] = &gs;
4094 /* Skip the ':' and whitespace. */
4096 if (is_space_char (*op_string))
4099 if (!is_digit_char (*op_string)
4100 && !is_identifier_char (*op_string)
4101 && *op_string != '('
4102 && *op_string != ABSOLUTE_PREFIX)
4104 as_bad (_("bad memory operand `%s'"), op_string);
4107 /* Handle case of %es:*foo. */
4108 if (*op_string == ABSOLUTE_PREFIX)
4111 if (is_space_char (*op_string))
4113 i.types[this_operand] |= JumpAbsolute;
4115 goto do_memory_reference;
4119 as_bad (_("junk `%s' after register"), op_string);
4122 i.types[this_operand] |= r->reg_type & ~BaseIndex;
4123 i.op[this_operand].regs = r;
4126 else if (*op_string == REGISTER_PREFIX)
4128 as_bad (_("bad register name `%s'"), op_string);
4131 else if (*op_string == IMMEDIATE_PREFIX)
4134 if (i.types[this_operand] & JumpAbsolute)
4136 as_bad (_("immediate operand illegal with absolute jump"));
4139 if (!i386_immediate (op_string))
4142 else if (is_digit_char (*op_string)
4143 || is_identifier_char (*op_string)
4144 || *op_string == '(')
4146 /* This is a memory reference of some sort. */
4149 /* Start and end of displacement string expression (if found). */
4150 char *displacement_string_start;
4151 char *displacement_string_end;
4153 do_memory_reference:
4154 if ((i.mem_operands == 1
4155 && (current_templates->start->opcode_modifier & IsString) == 0)
4156 || i.mem_operands == 2)
4158 as_bad (_("too many memory references for `%s'"),
4159 current_templates->start->name);
4163 /* Check for base index form. We detect the base index form by
4164 looking for an ')' at the end of the operand, searching
4165 for the '(' matching it, and finding a REGISTER_PREFIX or ','
4167 base_string = op_string + strlen (op_string);
4170 if (is_space_char (*base_string))
4173 /* If we only have a displacement, set-up for it to be parsed later. */
4174 displacement_string_start = op_string;
4175 displacement_string_end = base_string + 1;
4177 if (*base_string == ')')
4180 unsigned int parens_balanced = 1;
4181 /* We've already checked that the number of left & right ()'s are
4182 equal, so this loop will not be infinite. */
4186 if (*base_string == ')')
4188 if (*base_string == '(')
4191 while (parens_balanced);
4193 temp_string = base_string;
4195 /* Skip past '(' and whitespace. */
4197 if (is_space_char (*base_string))
4200 if (*base_string == ','
4201 || ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4202 && (i.base_reg = parse_register (base_string, &end_op)) != NULL))
4204 displacement_string_end = temp_string;
4206 i.types[this_operand] |= BaseIndex;
4210 base_string = end_op;
4211 if (is_space_char (*base_string))
4215 /* There may be an index reg or scale factor here. */
4216 if (*base_string == ',')
4219 if (is_space_char (*base_string))
4222 if ((*base_string == REGISTER_PREFIX || allow_naked_reg)
4223 && (i.index_reg = parse_register (base_string, &end_op)) != NULL)
4225 base_string = end_op;
4226 if (is_space_char (*base_string))
4228 if (*base_string == ',')
4231 if (is_space_char (*base_string))
4234 else if (*base_string != ')')
4236 as_bad (_("expecting `,' or `)' after index register in `%s'"),
4241 else if (*base_string == REGISTER_PREFIX)
4243 as_bad (_("bad register name `%s'"), base_string);
4247 /* Check for scale factor. */
4248 if (*base_string != ')')
4250 char *end_scale = i386_scale (base_string);
4255 base_string = end_scale;
4256 if (is_space_char (*base_string))
4258 if (*base_string != ')')
4260 as_bad (_("expecting `)' after scale factor in `%s'"),
4265 else if (!i.index_reg)
4267 as_bad (_("expecting index register or scale factor after `,'; got '%c'"),
4272 else if (*base_string != ')')
4274 as_bad (_("expecting `,' or `)' after base register in `%s'"),
4279 else if (*base_string == REGISTER_PREFIX)
4281 as_bad (_("bad register name `%s'"), base_string);
4286 /* If there's an expression beginning the operand, parse it,
4287 assuming displacement_string_start and
4288 displacement_string_end are meaningful. */
4289 if (displacement_string_start != displacement_string_end)
4291 if (!i386_displacement (displacement_string_start,
4292 displacement_string_end))
4296 /* Special case for (%dx) while doing input/output op. */
4298 && i.base_reg->reg_type == (Reg16 | InOutPortReg)
4300 && i.log2_scale_factor == 0
4301 && i.seg[i.mem_operands] == 0
4302 && (i.types[this_operand] & Disp) == 0)
4304 i.types[this_operand] = InOutPortReg;
4308 if (i386_index_check (operand_string) == 0)
4314 /* It's not a memory operand; argh! */
4315 as_bad (_("invalid char %s beginning operand %d `%s'"),
4316 output_invalid (*op_string),
4321 return 1; /* Normal return. */
4324 /* md_estimate_size_before_relax()
4326 Called just before relax() for rs_machine_dependent frags. The x86
4327 assembler uses these frags to handle variable size jump
4330 Any symbol that is now undefined will not become defined.
4331 Return the correct fr_subtype in the frag.
4332 Return the initial "guess for variable size of frag" to caller.
4333 The guess is actually the growth beyond the fixed part. Whatever
4334 we do to grow the fixed or variable part contributes to our
4338 md_estimate_size_before_relax (fragP, segment)
4342 /* We've already got fragP->fr_subtype right; all we have to do is
4343 check for un-relaxable symbols. On an ELF system, we can't relax
4344 an externally visible symbol, because it may be overridden by a
4346 if (S_GET_SEGMENT (fragP->fr_symbol) != segment
4347 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4348 || (OUTPUT_FLAVOR == bfd_target_elf_flavour
4349 && (S_IS_EXTERNAL (fragP->fr_symbol)
4350 || S_IS_WEAK (fragP->fr_symbol)))
4354 /* Symbol is undefined in this segment, or we need to keep a
4355 reloc so that weak symbols can be overridden. */
4356 int size = (fragP->fr_subtype & CODE16) ? 2 : 4;
4357 enum bfd_reloc_code_real reloc_type;
4358 unsigned char *opcode;
4361 if (fragP->fr_var != NO_RELOC)
4362 reloc_type = fragP->fr_var;
4364 reloc_type = BFD_RELOC_16_PCREL;
4366 reloc_type = BFD_RELOC_32_PCREL;
4368 old_fr_fix = fragP->fr_fix;
4369 opcode = (unsigned char *) fragP->fr_opcode;
4371 switch (TYPE_FROM_RELAX_STATE (fragP->fr_subtype))
4374 /* Make jmp (0xeb) a (d)word displacement jump. */
4376 fragP->fr_fix += size;
4377 fix_new (fragP, old_fr_fix, size,
4379 fragP->fr_offset, 1,
4385 && (!no_cond_jump_promotion || fragP->fr_var != NO_RELOC))
4387 /* Negate the condition, and branch past an
4388 unconditional jump. */
4391 /* Insert an unconditional jump. */
4393 /* We added two extra opcode bytes, and have a two byte
4395 fragP->fr_fix += 2 + 2;
4396 fix_new (fragP, old_fr_fix + 2, 2,
4398 fragP->fr_offset, 1,
4405 if (no_cond_jump_promotion && fragP->fr_var == NO_RELOC)
4410 fixP = fix_new (fragP, old_fr_fix, 1,
4412 fragP->fr_offset, 1,
4414 fixP->fx_signed = 1;
4418 /* This changes the byte-displacement jump 0x7N
4419 to the (d)word-displacement jump 0x0f,0x8N. */
4420 opcode[1] = opcode[0] + 0x10;
4421 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4422 /* We've added an opcode byte. */
4423 fragP->fr_fix += 1 + size;
4424 fix_new (fragP, old_fr_fix + 1, size,
4426 fragP->fr_offset, 1,
4431 BAD_CASE (fragP->fr_subtype);
4435 return fragP->fr_fix - old_fr_fix;
4438 /* Guess size depending on current relax state. Initially the relax
4439 state will correspond to a short jump and we return 1, because
4440 the variable part of the frag (the branch offset) is one byte
4441 long. However, we can relax a section more than once and in that
4442 case we must either set fr_subtype back to the unrelaxed state,
4443 or return the value for the appropriate branch. */
4444 return md_relax_table[fragP->fr_subtype].rlx_length;
4447 /* Called after relax() is finished.
4449 In: Address of frag.
4450 fr_type == rs_machine_dependent.
4451 fr_subtype is what the address relaxed to.
4453 Out: Any fixSs and constants are set up.
4454 Caller will turn frag into a ".space 0". */
4457 md_convert_frag (abfd, sec, fragP)
4458 bfd *abfd ATTRIBUTE_UNUSED;
4459 segT sec ATTRIBUTE_UNUSED;
4462 unsigned char *opcode;
4463 unsigned char *where_to_put_displacement = NULL;
4464 offsetT target_address;
4465 offsetT opcode_address;
4466 unsigned int extension = 0;
4467 offsetT displacement_from_opcode_start;
4469 opcode = (unsigned char *) fragP->fr_opcode;
4471 /* Address we want to reach in file space. */
4472 target_address = S_GET_VALUE (fragP->fr_symbol) + fragP->fr_offset;
4474 /* Address opcode resides at in file space. */
4475 opcode_address = fragP->fr_address + fragP->fr_fix;
4477 /* Displacement from opcode start to fill into instruction. */
4478 displacement_from_opcode_start = target_address - opcode_address;
4480 if ((fragP->fr_subtype & BIG) == 0)
4482 /* Don't have to change opcode. */
4483 extension = 1; /* 1 opcode + 1 displacement */
4484 where_to_put_displacement = &opcode[1];
4488 if (no_cond_jump_promotion
4489 && TYPE_FROM_RELAX_STATE (fragP->fr_subtype) != UNCOND_JUMP)
4490 as_warn_where (fragP->fr_file, fragP->fr_line, _("long jump required"));
4492 switch (fragP->fr_subtype)
4494 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG):
4495 extension = 4; /* 1 opcode + 4 displacement */
4497 where_to_put_displacement = &opcode[1];
4500 case ENCODE_RELAX_STATE (UNCOND_JUMP, BIG16):
4501 extension = 2; /* 1 opcode + 2 displacement */
4503 where_to_put_displacement = &opcode[1];
4506 case ENCODE_RELAX_STATE (COND_JUMP, BIG):
4507 case ENCODE_RELAX_STATE (COND_JUMP86, BIG):
4508 extension = 5; /* 2 opcode + 4 displacement */
4509 opcode[1] = opcode[0] + 0x10;
4510 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4511 where_to_put_displacement = &opcode[2];
4514 case ENCODE_RELAX_STATE (COND_JUMP, BIG16):
4515 extension = 3; /* 2 opcode + 2 displacement */
4516 opcode[1] = opcode[0] + 0x10;
4517 opcode[0] = TWO_BYTE_OPCODE_ESCAPE;
4518 where_to_put_displacement = &opcode[2];
4521 case ENCODE_RELAX_STATE (COND_JUMP86, BIG16):
4526 where_to_put_displacement = &opcode[3];
4530 BAD_CASE (fragP->fr_subtype);
4535 /* Now put displacement after opcode. */
4536 md_number_to_chars ((char *) where_to_put_displacement,
4537 (valueT) (displacement_from_opcode_start - extension),
4538 DISP_SIZE_FROM_RELAX_STATE (fragP->fr_subtype));
4539 fragP->fr_fix += extension;
4542 /* Size of byte displacement jmp. */
4543 int md_short_jump_size = 2;
4545 /* Size of dword displacement jmp. */
4546 int md_long_jump_size = 5;
4548 /* Size of relocation record. */
4549 const int md_reloc_size = 8;
4552 md_create_short_jump (ptr, from_addr, to_addr, frag, to_symbol)
4554 addressT from_addr, to_addr;
4555 fragS *frag ATTRIBUTE_UNUSED;
4556 symbolS *to_symbol ATTRIBUTE_UNUSED;
4560 offset = to_addr - (from_addr + 2);
4561 /* Opcode for byte-disp jump. */
4562 md_number_to_chars (ptr, (valueT) 0xeb, 1);
4563 md_number_to_chars (ptr + 1, (valueT) offset, 1);
4567 md_create_long_jump (ptr, from_addr, to_addr, frag, to_symbol)
4569 addressT from_addr, to_addr;
4570 fragS *frag ATTRIBUTE_UNUSED;
4571 symbolS *to_symbol ATTRIBUTE_UNUSED;
4575 offset = to_addr - (from_addr + 5);
4576 md_number_to_chars (ptr, (valueT) 0xe9, 1);
4577 md_number_to_chars (ptr + 1, (valueT) offset, 4);
4580 /* Apply a fixup (fixS) to segment data, once it has been determined
4581 by our caller that we have all the info we need to fix it up.
4583 On the 386, immediates, displacements, and data pointers are all in
4584 the same (little-endian) format, so we don't need to care about which
4588 md_apply_fix3 (fixP, valP, seg)
4589 /* The fix we're to put in. */
4591 /* Pointer to the value of the bits. */
4593 /* Segment fix is from. */
4594 segT seg ATTRIBUTE_UNUSED;
4596 char *p = fixP->fx_where + fixP->fx_frag->fr_literal;
4597 valueT value = *valP;
4599 #if !defined (TE_Mach)
4602 switch (fixP->fx_r_type)
4608 fixP->fx_r_type = BFD_RELOC_32_PCREL;
4611 fixP->fx_r_type = BFD_RELOC_16_PCREL;
4614 fixP->fx_r_type = BFD_RELOC_8_PCREL;
4619 if (fixP->fx_addsy != NULL
4620 && (fixP->fx_r_type == BFD_RELOC_32_PCREL
4621 || fixP->fx_r_type == BFD_RELOC_16_PCREL
4622 || fixP->fx_r_type == BFD_RELOC_8_PCREL)
4623 && !use_rela_relocations)
4625 /* This is a hack. There should be a better way to handle this.
4626 This covers for the fact that bfd_install_relocation will
4627 subtract the current location (for partial_inplace, PC relative
4628 relocations); see more below. */
4630 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4632 || OUTPUT_FLAVOR == bfd_target_coff_flavour
4635 value += fixP->fx_where + fixP->fx_frag->fr_address;
4637 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4638 if (OUTPUT_FLAVOR == bfd_target_elf_flavour)
4640 segT sym_seg = S_GET_SEGMENT (fixP->fx_addsy);
4643 || (symbol_section_p (fixP->fx_addsy)
4644 && sym_seg != absolute_section))
4645 && !generic_force_reloc (fixP))
4647 /* Yes, we add the values in twice. This is because
4648 bfd_install_relocation subtracts them out again. I think
4649 bfd_install_relocation is broken, but I don't dare change
4651 value += fixP->fx_where + fixP->fx_frag->fr_address;
4655 #if defined (OBJ_COFF) && defined (TE_PE)
4656 /* For some reason, the PE format does not store a section
4657 address offset for a PC relative symbol. */
4658 if (S_GET_SEGMENT (fixP->fx_addsy) != seg)
4659 value += md_pcrel_from (fixP);
4663 /* Fix a few things - the dynamic linker expects certain values here,
4664 and we must not disappoint it. */
4665 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4666 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
4668 switch (fixP->fx_r_type)
4670 case BFD_RELOC_386_PLT32:
4671 case BFD_RELOC_X86_64_PLT32:
4672 /* Make the jump instruction point to the address of the operand. At
4673 runtime we merely add the offset to the actual PLT entry. */
4677 case BFD_RELOC_386_TLS_GD:
4678 case BFD_RELOC_386_TLS_LDM:
4679 case BFD_RELOC_386_TLS_IE_32:
4680 case BFD_RELOC_386_TLS_IE:
4681 case BFD_RELOC_386_TLS_GOTIE:
4682 case BFD_RELOC_X86_64_TLSGD:
4683 case BFD_RELOC_X86_64_TLSLD:
4684 case BFD_RELOC_X86_64_GOTTPOFF:
4685 value = 0; /* Fully resolved at runtime. No addend. */
4687 case BFD_RELOC_386_TLS_LE:
4688 case BFD_RELOC_386_TLS_LDO_32:
4689 case BFD_RELOC_386_TLS_LE_32:
4690 case BFD_RELOC_X86_64_DTPOFF32:
4691 case BFD_RELOC_X86_64_TPOFF32:
4692 S_SET_THREAD_LOCAL (fixP->fx_addsy);
4695 case BFD_RELOC_386_GOT32:
4696 case BFD_RELOC_X86_64_GOT32:
4697 value = 0; /* Fully resolved at runtime. No addend. */
4700 case BFD_RELOC_VTABLE_INHERIT:
4701 case BFD_RELOC_VTABLE_ENTRY:
4708 #endif /* defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF) */
4710 #endif /* !defined (TE_Mach) */
4712 /* Are we finished with this relocation now? */
4713 if (fixP->fx_addsy == NULL)
4715 else if (use_rela_relocations)
4717 fixP->fx_no_overflow = 1;
4718 /* Remember value for tc_gen_reloc. */
4719 fixP->fx_addnumber = value;
4723 md_number_to_chars (p, value, fixP->fx_size);
4726 #define MAX_LITTLENUMS 6
4728 /* Turn the string pointed to by litP into a floating point constant
4729 of type TYPE, and emit the appropriate bytes. The number of
4730 LITTLENUMS emitted is stored in *SIZEP. An error message is
4731 returned, or NULL on OK. */
4734 md_atof (type, litP, sizeP)
4740 LITTLENUM_TYPE words[MAX_LITTLENUMS];
4741 LITTLENUM_TYPE *wordP;
4763 return _("Bad call to md_atof ()");
4765 t = atof_ieee (input_line_pointer, type, words);
4767 input_line_pointer = t;
4769 *sizeP = prec * sizeof (LITTLENUM_TYPE);
4770 /* This loops outputs the LITTLENUMs in REVERSE order; in accord with
4771 the bigendian 386. */
4772 for (wordP = words + prec - 1; prec--;)
4774 md_number_to_chars (litP, (valueT) (*wordP--), sizeof (LITTLENUM_TYPE));
4775 litP += sizeof (LITTLENUM_TYPE);
4780 char output_invalid_buf[8];
4787 sprintf (output_invalid_buf, "'%c'", c);
4789 sprintf (output_invalid_buf, "(0x%x)", (unsigned) c);
4790 return output_invalid_buf;
4793 /* REG_STRING starts *before* REGISTER_PREFIX. */
4795 static const reg_entry *
4796 parse_register (reg_string, end_op)
4800 char *s = reg_string;
4802 char reg_name_given[MAX_REG_NAME_SIZE + 1];
4805 /* Skip possible REGISTER_PREFIX and possible whitespace. */
4806 if (*s == REGISTER_PREFIX)
4809 if (is_space_char (*s))
4813 while ((*p++ = register_chars[(unsigned char) *s]) != '\0')
4815 if (p >= reg_name_given + MAX_REG_NAME_SIZE)
4816 return (const reg_entry *) NULL;
4820 /* For naked regs, make sure that we are not dealing with an identifier.
4821 This prevents confusing an identifier like `eax_var' with register
4823 if (allow_naked_reg && identifier_chars[(unsigned char) *s])
4824 return (const reg_entry *) NULL;
4828 r = (const reg_entry *) hash_find (reg_hash, reg_name_given);
4830 /* Handle floating point regs, allowing spaces in the (i) part. */
4831 if (r == i386_regtab /* %st is first entry of table */)
4833 if (is_space_char (*s))
4838 if (is_space_char (*s))
4840 if (*s >= '0' && *s <= '7')
4842 r = &i386_float_regtab[*s - '0'];
4844 if (is_space_char (*s))
4852 /* We have "%st(" then garbage. */
4853 return (const reg_entry *) NULL;
4858 && (r->reg_flags & (RegRex64 | RegRex)) != 0
4859 && flag_code != CODE_64BIT)
4861 return (const reg_entry *) NULL;
4867 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4868 const char *md_shortopts = "kVQ:sqn";
4870 const char *md_shortopts = "qn";
4873 struct option md_longopts[] = {
4874 #define OPTION_32 (OPTION_MD_BASE + 0)
4875 {"32", no_argument, NULL, OPTION_32},
4876 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4877 #define OPTION_64 (OPTION_MD_BASE + 1)
4878 {"64", no_argument, NULL, OPTION_64},
4880 {NULL, no_argument, NULL, 0}
4882 size_t md_longopts_size = sizeof (md_longopts);
4885 md_parse_option (c, arg)
4887 char *arg ATTRIBUTE_UNUSED;
4892 optimize_align_code = 0;
4899 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4900 /* -Qy, -Qn: SVR4 arguments controlling whether a .comment section
4901 should be emitted or not. FIXME: Not implemented. */
4905 /* -V: SVR4 argument to print version ID. */
4907 print_version_id ();
4910 /* -k: Ignore for FreeBSD compatibility. */
4915 /* -s: On i386 Solaris, this tells the native assembler to use
4916 .stab instead of .stab.excl. We always use .stab anyhow. */
4921 const char **list, **l;
4923 list = bfd_target_list ();
4924 for (l = list; *l != NULL; l++)
4925 if (strcmp (*l, "elf64-x86-64") == 0)
4927 default_arch = "x86_64";
4931 as_fatal (_("No compiled in support for x86_64"));
4938 default_arch = "i386";
4948 md_show_usage (stream)
4951 #if defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF)
4952 fprintf (stream, _("\
4954 -V print assembler version number\n\
4956 -n Do not optimize code alignment\n\
4957 -q quieten some warnings\n\
4960 fprintf (stream, _("\
4961 -n Do not optimize code alignment\n\
4962 -q quieten some warnings\n"));
4966 #if ((defined (OBJ_MAYBE_COFF) && defined (OBJ_MAYBE_AOUT)) \
4967 || defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
4969 /* Pick the target format to use. */
4972 i386_target_format ()
4974 if (!strcmp (default_arch, "x86_64"))
4975 set_code_flag (CODE_64BIT);
4976 else if (!strcmp (default_arch, "i386"))
4977 set_code_flag (CODE_32BIT);
4979 as_fatal (_("Unknown architecture"));
4980 switch (OUTPUT_FLAVOR)
4982 #ifdef OBJ_MAYBE_AOUT
4983 case bfd_target_aout_flavour:
4984 return AOUT_TARGET_FORMAT;
4986 #ifdef OBJ_MAYBE_COFF
4987 case bfd_target_coff_flavour:
4990 #if defined (OBJ_MAYBE_ELF) || defined (OBJ_ELF)
4991 case bfd_target_elf_flavour:
4993 if (flag_code == CODE_64BIT)
4994 use_rela_relocations = 1;
4995 return flag_code == CODE_64BIT ? "elf64-x86-64" : ELF_TARGET_FORMAT;
5004 #endif /* OBJ_MAYBE_ more than one */
5006 #if (defined (OBJ_ELF) || defined (OBJ_MAYBE_ELF))
5007 void i386_elf_emit_arch_note ()
5009 if (OUTPUT_FLAVOR == bfd_target_elf_flavour
5010 && cpu_arch_name != NULL)
5013 asection *seg = now_seg;
5014 subsegT subseg = now_subseg;
5015 Elf_Internal_Note i_note;
5016 Elf_External_Note e_note;
5017 asection *note_secp;
5020 /* Create the .note section. */
5021 note_secp = subseg_new (".note", 0);
5022 bfd_set_section_flags (stdoutput,
5024 SEC_HAS_CONTENTS | SEC_READONLY);
5026 /* Process the arch string. */
5027 len = strlen (cpu_arch_name);
5029 i_note.namesz = len + 1;
5031 i_note.type = NT_ARCH;
5032 p = frag_more (sizeof (e_note.namesz));
5033 md_number_to_chars (p, (valueT) i_note.namesz, sizeof (e_note.namesz));
5034 p = frag_more (sizeof (e_note.descsz));
5035 md_number_to_chars (p, (valueT) i_note.descsz, sizeof (e_note.descsz));
5036 p = frag_more (sizeof (e_note.type));
5037 md_number_to_chars (p, (valueT) i_note.type, sizeof (e_note.type));
5038 p = frag_more (len + 1);
5039 strcpy (p, cpu_arch_name);
5041 frag_align (2, 0, 0);
5043 subseg_set (seg, subseg);
5049 md_undefined_symbol (name)
5052 if (name[0] == GLOBAL_OFFSET_TABLE_NAME[0]
5053 && name[1] == GLOBAL_OFFSET_TABLE_NAME[1]
5054 && name[2] == GLOBAL_OFFSET_TABLE_NAME[2]
5055 && strcmp (name, GLOBAL_OFFSET_TABLE_NAME) == 0)
5059 if (symbol_find (name))
5060 as_bad (_("GOT already in symbol table"));
5061 GOT_symbol = symbol_new (name, undefined_section,
5062 (valueT) 0, &zero_address_frag);
5069 /* Round up a section size to the appropriate boundary. */
5072 md_section_align (segment, size)
5073 segT segment ATTRIBUTE_UNUSED;
5076 #if (defined (OBJ_AOUT) || defined (OBJ_MAYBE_AOUT))
5077 if (OUTPUT_FLAVOR == bfd_target_aout_flavour)
5079 /* For a.out, force the section size to be aligned. If we don't do
5080 this, BFD will align it for us, but it will not write out the
5081 final bytes of the section. This may be a bug in BFD, but it is
5082 easier to fix it here since that is how the other a.out targets
5086 align = bfd_get_section_alignment (stdoutput, segment);
5087 size = ((size + (1 << align) - 1) & ((valueT) -1 << align));
5094 /* On the i386, PC-relative offsets are relative to the start of the
5095 next instruction. That is, the address of the offset, plus its
5096 size, since the offset is always the last part of the insn. */
5099 md_pcrel_from (fixP)
5102 return fixP->fx_size + fixP->fx_where + fixP->fx_frag->fr_address;
5109 int ignore ATTRIBUTE_UNUSED;
5113 temp = get_absolute_expression ();
5114 subseg_set (bss_section, (subsegT) temp);
5115 demand_empty_rest_of_line ();
5121 i386_validate_fix (fixp)
5124 if (fixp->fx_subsy && fixp->fx_subsy == GOT_symbol)
5126 /* GOTOFF relocation are nonsense in 64bit mode. */
5127 if (fixp->fx_r_type == BFD_RELOC_32_PCREL)
5129 if (flag_code != CODE_64BIT)
5131 fixp->fx_r_type = BFD_RELOC_X86_64_GOTPCREL;
5135 if (flag_code == CODE_64BIT)
5137 fixp->fx_r_type = BFD_RELOC_386_GOTOFF;
5144 tc_gen_reloc (section, fixp)
5145 asection *section ATTRIBUTE_UNUSED;
5149 bfd_reloc_code_real_type code;
5151 switch (fixp->fx_r_type)
5153 case BFD_RELOC_X86_64_PLT32:
5154 case BFD_RELOC_X86_64_GOT32:
5155 case BFD_RELOC_X86_64_GOTPCREL:
5156 case BFD_RELOC_386_PLT32:
5157 case BFD_RELOC_386_GOT32:
5158 case BFD_RELOC_386_GOTOFF:
5159 case BFD_RELOC_386_GOTPC:
5160 case BFD_RELOC_386_TLS_GD:
5161 case BFD_RELOC_386_TLS_LDM:
5162 case BFD_RELOC_386_TLS_LDO_32:
5163 case BFD_RELOC_386_TLS_IE_32:
5164 case BFD_RELOC_386_TLS_IE:
5165 case BFD_RELOC_386_TLS_GOTIE:
5166 case BFD_RELOC_386_TLS_LE_32:
5167 case BFD_RELOC_386_TLS_LE:
5168 case BFD_RELOC_X86_64_32S:
5169 case BFD_RELOC_X86_64_TLSGD:
5170 case BFD_RELOC_X86_64_TLSLD:
5171 case BFD_RELOC_X86_64_DTPOFF32:
5172 case BFD_RELOC_X86_64_GOTTPOFF:
5173 case BFD_RELOC_X86_64_TPOFF32:
5175 case BFD_RELOC_VTABLE_ENTRY:
5176 case BFD_RELOC_VTABLE_INHERIT:
5177 code = fixp->fx_r_type;
5182 switch (fixp->fx_size)
5185 as_bad_where (fixp->fx_file, fixp->fx_line,
5186 _("can not do %d byte pc-relative relocation"),
5188 code = BFD_RELOC_32_PCREL;
5190 case 1: code = BFD_RELOC_8_PCREL; break;
5191 case 2: code = BFD_RELOC_16_PCREL; break;
5192 case 4: code = BFD_RELOC_32_PCREL; break;
5197 switch (fixp->fx_size)
5200 as_bad_where (fixp->fx_file, fixp->fx_line,
5201 _("can not do %d byte relocation"),
5203 code = BFD_RELOC_32;
5205 case 1: code = BFD_RELOC_8; break;
5206 case 2: code = BFD_RELOC_16; break;
5207 case 4: code = BFD_RELOC_32; break;
5209 case 8: code = BFD_RELOC_64; break;
5216 if (code == BFD_RELOC_32
5218 && fixp->fx_addsy == GOT_symbol)
5220 /* We don't support GOTPC on 64bit targets. */
5221 if (flag_code == CODE_64BIT)
5223 code = BFD_RELOC_386_GOTPC;
5226 rel = (arelent *) xmalloc (sizeof (arelent));
5227 rel->sym_ptr_ptr = (asymbol **) xmalloc (sizeof (asymbol *));
5228 *rel->sym_ptr_ptr = symbol_get_bfdsym (fixp->fx_addsy);
5230 rel->address = fixp->fx_frag->fr_address + fixp->fx_where;
5231 if (!use_rela_relocations)
5233 /* HACK: Since i386 ELF uses Rel instead of Rela, encode the
5234 vtable entry to be used in the relocation's section offset. */
5235 if (fixp->fx_r_type == BFD_RELOC_VTABLE_ENTRY)
5236 rel->address = fixp->fx_offset;
5240 /* Use the rela in 64bit mode. */
5243 if (!fixp->fx_pcrel)
5244 rel->addend = fixp->fx_offset;
5248 case BFD_RELOC_X86_64_PLT32:
5249 case BFD_RELOC_X86_64_GOT32:
5250 case BFD_RELOC_X86_64_GOTPCREL:
5251 case BFD_RELOC_X86_64_TLSGD:
5252 case BFD_RELOC_X86_64_TLSLD:
5253 case BFD_RELOC_X86_64_GOTTPOFF:
5254 rel->addend = fixp->fx_offset - fixp->fx_size;
5257 rel->addend = (section->vma
5259 + fixp->fx_addnumber
5260 + md_pcrel_from (fixp));
5265 rel->howto = bfd_reloc_type_lookup (stdoutput, code);
5266 if (rel->howto == NULL)
5268 as_bad_where (fixp->fx_file, fixp->fx_line,
5269 _("cannot represent relocation type %s"),
5270 bfd_get_reloc_code_name (code));
5271 /* Set howto to a garbage value so that we can keep going. */
5272 rel->howto = bfd_reloc_type_lookup (stdoutput, BFD_RELOC_32);
5273 assert (rel->howto != NULL);
5280 /* Parse operands using Intel syntax. This implements a recursive descent
5281 parser based on the BNF grammar published in Appendix B of the MASM 6.1
5284 FIXME: We do not recognize the full operand grammar defined in the MASM
5285 documentation. In particular, all the structure/union and
5286 high-level macro operands are missing.
5288 Uppercase words are terminals, lower case words are non-terminals.
5289 Objects surrounded by double brackets '[[' ']]' are optional. Vertical
5290 bars '|' denote choices. Most grammar productions are implemented in
5291 functions called 'intel_<production>'.
5293 Initial production is 'expr'.
5299 byteRegister AL | AH | BL | BH | CL | CH | DL | DH
5301 constant digits [[ radixOverride ]]
5303 dataType BYTE | WORD | DWORD | QWORD | XWORD
5336 gpRegister AX | EAX | BX | EBX | CX | ECX | DX | EDX
5337 | BP | EBP | SP | ESP | DI | EDI | SI | ESI
5339 hexdigit a | b | c | d | e | f
5340 | A | B | C | D | E | F
5350 register specialRegister
5354 segmentRegister CS | DS | ES | FS | GS | SS
5356 specialRegister CR0 | CR2 | CR3
5357 | DR0 | DR1 | DR2 | DR3 | DR6 | DR7
5358 | TR3 | TR4 | TR5 | TR6 | TR7
5360 We simplify the grammar in obvious places (e.g., register parsing is
5361 done by calling parse_register) and eliminate immediate left recursion
5362 to implement a recursive-descent parser.
5402 /* Parsing structure for the intel syntax parser. Used to implement the
5403 semantic actions for the operand grammar. */
5404 struct intel_parser_s
5406 char *op_string; /* The string being parsed. */
5407 int got_a_float; /* Whether the operand is a float. */
5408 int op_modifier; /* Operand modifier. */
5409 int is_mem; /* 1 if operand is memory reference. */
5410 const reg_entry *reg; /* Last register reference found. */
5411 char *disp; /* Displacement string being built. */
5414 static struct intel_parser_s intel_parser;
5416 /* Token structure for parsing intel syntax. */
5419 int code; /* Token code. */
5420 const reg_entry *reg; /* Register entry for register tokens. */
5421 char *str; /* String representation. */
5424 static struct intel_token cur_token, prev_token;
5426 /* Token codes for the intel parser. Since T_SHORT is already used
5427 by COFF, undefine it first to prevent a warning. */
5442 /* Prototypes for intel parser functions. */
5443 static int intel_match_token PARAMS ((int code));
5444 static void intel_get_token PARAMS ((void));
5445 static void intel_putback_token PARAMS ((void));
5446 static int intel_expr PARAMS ((void));
5447 static int intel_e05 PARAMS ((void));
5448 static int intel_e05_1 PARAMS ((void));
5449 static int intel_e06 PARAMS ((void));
5450 static int intel_e06_1 PARAMS ((void));
5451 static int intel_e09 PARAMS ((void));
5452 static int intel_e09_1 PARAMS ((void));
5453 static int intel_e10 PARAMS ((void));
5454 static int intel_e10_1 PARAMS ((void));
5455 static int intel_e11 PARAMS ((void));
5458 i386_intel_operand (operand_string, got_a_float)
5459 char *operand_string;
5465 /* Initialize token holders. */
5466 cur_token.code = prev_token.code = T_NIL;
5467 cur_token.reg = prev_token.reg = NULL;
5468 cur_token.str = prev_token.str = NULL;
5470 /* Initialize parser structure. */
5471 p = intel_parser.op_string = (char *) malloc (strlen (operand_string) + 1);
5474 strcpy (intel_parser.op_string, operand_string);
5475 intel_parser.got_a_float = got_a_float;
5476 intel_parser.op_modifier = -1;
5477 intel_parser.is_mem = 0;
5478 intel_parser.reg = NULL;
5479 intel_parser.disp = (char *) malloc (strlen (operand_string) + 1);
5480 if (intel_parser.disp == NULL)
5482 intel_parser.disp[0] = '\0';
5484 /* Read the first token and start the parser. */
5486 ret = intel_expr ();
5490 /* If we found a memory reference, hand it over to i386_displacement
5491 to fill in the rest of the operand fields. */
5492 if (intel_parser.is_mem)
5494 if ((i.mem_operands == 1
5495 && (current_templates->start->opcode_modifier & IsString) == 0)
5496 || i.mem_operands == 2)
5498 as_bad (_("too many memory references for '%s'"),
5499 current_templates->start->name);
5504 char *s = intel_parser.disp;
5507 /* Add the displacement expression. */
5509 ret = i386_displacement (s, s + strlen (s));
5511 ret = i386_index_check (operand_string);
5515 /* Constant and OFFSET expressions are handled by i386_immediate. */
5516 else if (intel_parser.op_modifier == OFFSET_FLAT
5517 || intel_parser.reg == NULL)
5518 ret = i386_immediate (intel_parser.disp);
5522 free (intel_parser.disp);
5532 /* expr SHORT e05 */
5533 if (cur_token.code == T_SHORT)
5535 intel_parser.op_modifier = SHORT;
5536 intel_match_token (T_SHORT);
5538 return (intel_e05 ());
5543 return intel_e05 ();
5553 return (intel_e06 () && intel_e05_1 ());
5559 /* e05' addOp e06 e05' */
5560 if (cur_token.code == '+' || cur_token.code == '-')
5562 strcat (intel_parser.disp, cur_token.str);
5563 intel_match_token (cur_token.code);
5565 return (intel_e06 () && intel_e05_1 ());
5580 return (intel_e09 () && intel_e06_1 ());
5586 /* e06' mulOp e09 e06' */
5587 if (cur_token.code == '*' || cur_token.code == '/')
5589 strcat (intel_parser.disp, cur_token.str);
5590 intel_match_token (cur_token.code);
5592 return (intel_e09 () && intel_e06_1 ());
5600 /* e09 OFFSET e10 e09'
5609 /* e09 OFFSET e10 e09' */
5610 if (cur_token.code == T_OFFSET)
5612 intel_parser.is_mem = 0;
5613 intel_parser.op_modifier = OFFSET_FLAT;
5614 intel_match_token (T_OFFSET);
5616 return (intel_e10 () && intel_e09_1 ());
5621 return (intel_e10 () && intel_e09_1 ());
5627 /* e09' PTR e10 e09' */
5628 if (cur_token.code == T_PTR)
5630 if (prev_token.code == T_BYTE)
5631 i.suffix = BYTE_MNEM_SUFFIX;
5633 else if (prev_token.code == T_WORD)
5635 if (intel_parser.got_a_float == 2) /* "fi..." */
5636 i.suffix = SHORT_MNEM_SUFFIX;
5638 i.suffix = WORD_MNEM_SUFFIX;
5641 else if (prev_token.code == T_DWORD)
5643 if (intel_parser.got_a_float == 1) /* "f..." */
5644 i.suffix = SHORT_MNEM_SUFFIX;
5646 i.suffix = LONG_MNEM_SUFFIX;
5649 else if (prev_token.code == T_QWORD)
5651 if (intel_parser.got_a_float == 1) /* "f..." */
5652 i.suffix = LONG_MNEM_SUFFIX;
5654 i.suffix = QWORD_MNEM_SUFFIX;
5657 else if (prev_token.code == T_XWORD)
5658 i.suffix = LONG_DOUBLE_MNEM_SUFFIX;
5662 as_bad (_("Unknown operand modifier `%s'\n"), prev_token.str);
5666 intel_match_token (T_PTR);
5668 return (intel_e10 () && intel_e09_1 ());
5671 /* e09 : e10 e09' */
5672 else if (cur_token.code == ':')
5674 /* Mark as a memory operand only if it's not already known to be an
5675 offset expression. */
5676 if (intel_parser.op_modifier != OFFSET_FLAT)
5677 intel_parser.is_mem = 1;
5679 return (intel_match_token (':') && intel_e10 () && intel_e09_1 ());
5694 return (intel_e11 () && intel_e10_1 ());
5700 /* e10' [ expr ] e10' */
5701 if (cur_token.code == '[')
5703 intel_match_token ('[');
5705 /* Mark as a memory operand only if it's not already known to be an
5706 offset expression. If it's an offset expression, we need to keep
5708 if (intel_parser.op_modifier != OFFSET_FLAT)
5709 intel_parser.is_mem = 1;
5711 strcat (intel_parser.disp, "[");
5713 /* Add a '+' to the displacement string if necessary. */
5714 if (*intel_parser.disp != '\0'
5715 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5716 strcat (intel_parser.disp, "+");
5718 if (intel_expr () && intel_match_token (']'))
5720 /* Preserve brackets when the operand is an offset expression. */
5721 if (intel_parser.op_modifier == OFFSET_FLAT)
5722 strcat (intel_parser.disp, "]");
5724 return intel_e10_1 ();
5751 if (cur_token.code == '(')
5753 intel_match_token ('(');
5754 strcat (intel_parser.disp, "(");
5756 if (intel_expr () && intel_match_token (')'))
5758 strcat (intel_parser.disp, ")");
5766 else if (cur_token.code == '[')
5768 intel_match_token ('[');
5770 /* Mark as a memory operand only if it's not already known to be an
5771 offset expression. If it's an offset expression, we need to keep
5773 if (intel_parser.op_modifier != OFFSET_FLAT)
5774 intel_parser.is_mem = 1;
5776 strcat (intel_parser.disp, "[");
5778 /* Operands for jump/call inside brackets denote absolute addresses. */
5779 if (current_templates->start->opcode_modifier & Jump
5780 || current_templates->start->opcode_modifier & JumpDword
5781 || current_templates->start->opcode_modifier & JumpByte
5782 || current_templates->start->opcode_modifier & JumpInterSegment)
5783 i.types[this_operand] |= JumpAbsolute;
5785 /* Add a '+' to the displacement string if necessary. */
5786 if (*intel_parser.disp != '\0'
5787 && *(intel_parser.disp + strlen (intel_parser.disp) - 1) != '+')
5788 strcat (intel_parser.disp, "+");
5790 if (intel_expr () && intel_match_token (']'))
5792 /* Preserve brackets when the operand is an offset expression. */
5793 if (intel_parser.op_modifier == OFFSET_FLAT)
5794 strcat (intel_parser.disp, "]");
5807 else if (cur_token.code == T_BYTE
5808 || cur_token.code == T_WORD
5809 || cur_token.code == T_DWORD
5810 || cur_token.code == T_QWORD
5811 || cur_token.code == T_XWORD)
5813 intel_match_token (cur_token.code);
5820 else if (cur_token.code == '$' || cur_token.code == '.')
5822 strcat (intel_parser.disp, cur_token.str);
5823 intel_match_token (cur_token.code);
5825 /* Mark as a memory operand only if it's not already known to be an
5826 offset expression. */
5827 if (intel_parser.op_modifier != OFFSET_FLAT)
5828 intel_parser.is_mem = 1;
5834 else if (cur_token.code == T_REG)
5836 const reg_entry *reg = intel_parser.reg = cur_token.reg;
5838 intel_match_token (T_REG);
5840 /* Check for segment change. */
5841 if (cur_token.code == ':')
5843 if (reg->reg_type & (SReg2 | SReg3))
5845 switch (reg->reg_num)
5848 i.seg[i.mem_operands] = &es;
5851 i.seg[i.mem_operands] = &cs;
5854 i.seg[i.mem_operands] = &ss;
5857 i.seg[i.mem_operands] = &ds;
5860 i.seg[i.mem_operands] = &fs;
5863 i.seg[i.mem_operands] = &gs;
5869 as_bad (_("`%s' is not a valid segment register"), reg->reg_name);
5874 /* Not a segment register. Check for register scaling. */
5875 else if (cur_token.code == '*')
5877 if (!intel_parser.is_mem)
5879 as_bad (_("Register scaling only allowed in memory operands."));
5883 /* What follows must be a valid scale. */
5884 if (intel_match_token ('*')
5885 && strchr ("01248", *cur_token.str))
5888 i.types[this_operand] |= BaseIndex;
5890 /* Set the scale after setting the register (otherwise,
5891 i386_scale will complain) */
5892 i386_scale (cur_token.str);
5893 intel_match_token (T_CONST);
5897 as_bad (_("expecting scale factor of 1, 2, 4, or 8: got `%s'"),
5903 /* No scaling. If this is a memory operand, the register is either a
5904 base register (first occurrence) or an index register (second
5906 else if (intel_parser.is_mem && !(reg->reg_type & (SReg2 | SReg3)))
5908 if (i.base_reg && i.index_reg)
5910 as_bad (_("Too many register references in memory operand.\n"));
5914 if (i.base_reg == NULL)
5919 i.types[this_operand] |= BaseIndex;
5922 /* Offset modifier. Add the register to the displacement string to be
5923 parsed as an immediate expression after we're done. */
5924 else if (intel_parser.op_modifier == OFFSET_FLAT)
5925 strcat (intel_parser.disp, reg->reg_name);
5927 /* It's neither base nor index nor offset. */
5930 i.types[this_operand] |= reg->reg_type & ~BaseIndex;
5931 i.op[this_operand].regs = reg;
5935 /* Since registers are not part of the displacement string (except
5936 when we're parsing offset operands), we may need to remove any
5937 preceding '+' from the displacement string. */
5938 if (*intel_parser.disp != '\0'
5939 && intel_parser.op_modifier != OFFSET_FLAT)
5941 char *s = intel_parser.disp;
5942 s += strlen (s) - 1;
5951 else if (cur_token.code == T_ID)
5953 /* Add the identifier to the displacement string. */
5954 strcat (intel_parser.disp, cur_token.str);
5955 intel_match_token (T_ID);
5957 /* The identifier represents a memory reference only if it's not
5958 preceded by an offset modifier. */
5959 if (intel_parser.op_modifier != OFFSET_FLAT)
5960 intel_parser.is_mem = 1;
5966 else if (cur_token.code == T_CONST
5967 || cur_token.code == '-'
5968 || cur_token.code == '+')
5972 /* Allow constants that start with `+' or `-'. */
5973 if (cur_token.code == '-' || cur_token.code == '+')
5975 strcat (intel_parser.disp, cur_token.str);
5976 intel_match_token (cur_token.code);
5977 if (cur_token.code != T_CONST)
5979 as_bad (_("Syntax error. Expecting a constant. Got `%s'.\n"),
5985 save_str = (char *) malloc (strlen (cur_token.str) + 1);
5986 if (save_str == NULL)
5988 strcpy (save_str, cur_token.str);
5990 /* Get the next token to check for register scaling. */
5991 intel_match_token (cur_token.code);
5993 /* Check if this constant is a scaling factor for an index register. */
5994 if (cur_token.code == '*')
5996 if (intel_match_token ('*') && cur_token.code == T_REG)
5998 if (!intel_parser.is_mem)
6000 as_bad (_("Register scaling only allowed in memory operands."));
6004 /* The constant is followed by `* reg', so it must be
6006 if (strchr ("01248", *save_str))
6008 i.index_reg = cur_token.reg;
6009 i.types[this_operand] |= BaseIndex;
6011 /* Set the scale after setting the register (otherwise,
6012 i386_scale will complain) */
6013 i386_scale (save_str);
6014 intel_match_token (T_REG);
6016 /* Since registers are not part of the displacement
6017 string, we may need to remove any preceding '+' from
6018 the displacement string. */
6019 if (*intel_parser.disp != '\0')
6021 char *s = intel_parser.disp;
6022 s += strlen (s) - 1;
6035 /* The constant was not used for register scaling. Since we have
6036 already consumed the token following `*' we now need to put it
6037 back in the stream. */
6039 intel_putback_token ();
6042 /* Add the constant to the displacement string. */
6043 strcat (intel_parser.disp, save_str);
6049 as_bad (_("Unrecognized token '%s'"), cur_token.str);
6053 /* Match the given token against cur_token. If they match, read the next
6054 token from the operand string. */
6056 intel_match_token (code)
6059 if (cur_token.code == code)
6066 as_bad (_("Unexpected token `%s'\n"), cur_token.str);
6071 /* Read a new token from intel_parser.op_string and store it in cur_token. */
6076 const reg_entry *reg;
6077 struct intel_token new_token;
6079 new_token.code = T_NIL;
6080 new_token.reg = NULL;
6081 new_token.str = NULL;
6083 /* Free the memory allocated to the previous token and move
6084 cur_token to prev_token. */
6086 free (prev_token.str);
6088 prev_token = cur_token;
6090 /* Skip whitespace. */
6091 while (is_space_char (*intel_parser.op_string))
6092 intel_parser.op_string++;
6094 /* Return an empty token if we find nothing else on the line. */
6095 if (*intel_parser.op_string == '\0')
6097 cur_token = new_token;
6101 /* The new token cannot be larger than the remainder of the operand
6103 new_token.str = (char *) malloc (strlen (intel_parser.op_string) + 1);
6104 if (new_token.str == NULL)
6106 new_token.str[0] = '\0';
6108 if (strchr ("0123456789", *intel_parser.op_string))
6110 char *p = new_token.str;
6111 char *q = intel_parser.op_string;
6112 new_token.code = T_CONST;
6114 /* Allow any kind of identifier char to encompass floating point and
6115 hexadecimal numbers. */
6116 while (is_identifier_char (*q))
6120 /* Recognize special symbol names [0-9][bf]. */
6121 if (strlen (intel_parser.op_string) == 2
6122 && (intel_parser.op_string[1] == 'b'
6123 || intel_parser.op_string[1] == 'f'))
6124 new_token.code = T_ID;
6127 else if (strchr ("+-/*:[]()", *intel_parser.op_string))
6129 new_token.code = *intel_parser.op_string;
6130 new_token.str[0] = *intel_parser.op_string;
6131 new_token.str[1] = '\0';
6134 else if ((*intel_parser.op_string == REGISTER_PREFIX || allow_naked_reg)
6135 && ((reg = parse_register (intel_parser.op_string, &end_op)) != NULL))
6137 new_token.code = T_REG;
6138 new_token.reg = reg;
6140 if (*intel_parser.op_string == REGISTER_PREFIX)
6142 new_token.str[0] = REGISTER_PREFIX;
6143 new_token.str[1] = '\0';
6146 strcat (new_token.str, reg->reg_name);
6149 else if (is_identifier_char (*intel_parser.op_string))
6151 char *p = new_token.str;
6152 char *q = intel_parser.op_string;
6154 /* A '.' or '$' followed by an identifier char is an identifier.
6155 Otherwise, it's operator '.' followed by an expression. */
6156 if ((*q == '.' || *q == '$') && !is_identifier_char (*(q + 1)))
6158 new_token.code = *q;
6159 new_token.str[0] = *q;
6160 new_token.str[1] = '\0';
6164 while (is_identifier_char (*q) || *q == '@')
6168 if (strcasecmp (new_token.str, "BYTE") == 0)
6169 new_token.code = T_BYTE;
6171 else if (strcasecmp (new_token.str, "WORD") == 0)
6172 new_token.code = T_WORD;
6174 else if (strcasecmp (new_token.str, "DWORD") == 0)
6175 new_token.code = T_DWORD;
6177 else if (strcasecmp (new_token.str, "QWORD") == 0)
6178 new_token.code = T_QWORD;
6180 else if (strcasecmp (new_token.str, "XWORD") == 0)
6181 new_token.code = T_XWORD;
6183 else if (strcasecmp (new_token.str, "PTR") == 0)
6184 new_token.code = T_PTR;
6186 else if (strcasecmp (new_token.str, "SHORT") == 0)
6187 new_token.code = T_SHORT;
6189 else if (strcasecmp (new_token.str, "OFFSET") == 0)
6191 new_token.code = T_OFFSET;
6193 /* ??? This is not mentioned in the MASM grammar but gcc
6194 makes use of it with -mintel-syntax. OFFSET may be
6195 followed by FLAT: */
6196 if (strncasecmp (q, " FLAT:", 6) == 0)
6197 strcat (new_token.str, " FLAT:");
6200 /* ??? This is not mentioned in the MASM grammar. */
6201 else if (strcasecmp (new_token.str, "FLAT") == 0)
6202 new_token.code = T_OFFSET;
6205 new_token.code = T_ID;
6210 as_bad (_("Unrecognized token `%s'\n"), intel_parser.op_string);
6212 intel_parser.op_string += strlen (new_token.str);
6213 cur_token = new_token;
6216 /* Put cur_token back into the token stream and make cur_token point to
6219 intel_putback_token ()
6221 intel_parser.op_string -= strlen (cur_token.str);
6222 free (cur_token.str);
6223 cur_token = prev_token;
6225 /* Forget prev_token. */
6226 prev_token.code = T_NIL;
6227 prev_token.reg = NULL;
6228 prev_token.str = NULL;
6232 tc_x86_regname_to_dw2regnum (const char *regname)
6234 unsigned int regnum;
6235 unsigned int regnames_count;
6236 char *regnames_32[] =
6238 "eax", "ecx", "edx", "ebx",
6239 "esp", "ebp", "esi", "edi",
6242 char *regnames_64[] =
6244 "rax", "rbx", "rcx", "rdx",
6245 "rdi", "rsi", "rbp", "rsp",
6246 "r8", "r9", "r10", "r11",
6247 "r12", "r13", "r14", "r15",
6252 if (flag_code == CODE_64BIT)
6254 regnames = regnames_64;
6255 regnames_count = ARRAY_SIZE (regnames_64);
6259 regnames = regnames_32;
6260 regnames_count = ARRAY_SIZE (regnames_32);
6263 for (regnum = 0; regnum < regnames_count; regnum++)
6264 if (strcmp (regname, regnames[regnum]) == 0)
6271 tc_x86_frame_initial_instructions (void)
6273 static unsigned int sp_regno;
6276 sp_regno = tc_x86_regname_to_dw2regnum (flag_code == CODE_64BIT
6279 cfi_add_CFA_def_cfa (sp_regno, -x86_cie_data_alignment);
6280 cfi_add_CFA_offset (x86_dwarf2_return_column, x86_cie_data_alignment);