2 * Copyright (c) 1992, 1993
3 * The Regents of the University of California. All rights reserved.
5 * This software was developed by the Computer Systems Engineering group
6 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and
7 * contributed to Berkeley.
9 * All advertising materials mentioning features or use of this software
10 * must display the following acknowledgement:
11 * This product includes software developed by the University of
12 * California, Lawrence Berkeley Laboratory.
14 * Redistribution and use in source and binary forms, with or without
15 * modification, are permitted provided that the following conditions
17 * 1. Redistributions of source code must retain the above copyright
18 * notice, this list of conditions and the following disclaimer.
19 * 2. Redistributions in binary form must reproduce the above copyright
20 * notice, this list of conditions and the following disclaimer in the
21 * documentation and/or other materials provided with the distribution.
22 * 4. Neither the name of the University nor the names of its contributors
23 * may be used to endorse or promote products derived from this software
24 * without specific prior written permission.
26 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
27 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
28 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
29 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
30 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
31 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
32 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
33 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
34 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
35 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
38 * @(#)fpu_explode.c 8.1 (Berkeley) 6/11/93
39 * $NetBSD: fpu_explode.c,v 1.5 2000/08/03 18:32:08 eeh Exp $
42 #include <sys/cdefs.h>
43 __FBSDID("$FreeBSD$");
46 * FPU subroutines: `explode' the machine's `packed binary' format numbers
47 * into our internal format.
50 #include <sys/param.h>
52 #include <machine/frame.h>
53 #include <machine/fp.h>
54 #include <machine/fsr.h>
55 #include <machine/ieee.h>
56 #include <machine/instr.h>
58 #include "fpu_arith.h"
60 #include "fpu_extern.h"
61 #include "__sparc_utrap_private.h"
64 * N.B.: in all of the following, we assume the FP format is
66 * ---------------------------
67 * | s | exponent | fraction |
68 * ---------------------------
70 * (which represents -1**s * 1.fraction * 2**exponent), so that the
71 * sign bit is way at the top (bit 31), the exponent is next, and
72 * then the remaining bits mark the fraction. A zero exponent means
73 * zero or denormalized (0.fraction rather than 1.fraction), and the
74 * maximum possible exponent, 2bias+1, signals inf (fraction==0) or NaN.
76 * Since the sign bit is always the topmost bit---this holds even for
77 * integers---we set that outside all the *tof functions. Each function
78 * returns the class code for the new number (but note that we use
79 * FPC_QNAN for all NaNs; fpu_explode will fix this if appropriate).
94 * The value FP_1 represents 2^FP_LG, so set the exponent
95 * there and let normalization fix it up. Convert negative
96 * numbers to sign-and-magnitude. Note that this relies on
97 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
101 * The sign bit decides whether i should be interpreted as
102 * a signed or unsigned entity.
104 if (fp->fp_sign && (int)i < 0)
127 * The value FP_1 represents 2^FP_LG, so set the exponent
128 * there and let normalization fix it up. Convert negative
129 * numbers to sign-and-magnitude. Note that this relies on
130 * fpu_norm()'s handling of `supernormals'; see fpu_subr.c.
134 * The sign bit decides whether i should be interpreted as
135 * a signed or unsigned entity.
137 if (fp->fp_sign && (int64_t)i < 0)
138 *((int64_t*)fp->fp_mant) = -i;
140 *((int64_t*)fp->fp_mant) = i;
147 #define mask(nbits) ((1L << (nbits)) - 1)
150 * All external floating formats convert to internal in the same manner,
151 * as defined here. Note that only normals get an implied 1.0 inserted.
153 #define FP_TOF(exp, expbias, allfrac, f0, f1, f2, f3) \
157 fp->fp_exp = 1 - expbias; \
158 fp->fp_mant[0] = f0; \
159 fp->fp_mant[1] = f1; \
160 fp->fp_mant[2] = f2; \
161 fp->fp_mant[3] = f3; \
165 if (exp == (2 * expbias + 1)) { \
168 fp->fp_mant[0] = f0; \
169 fp->fp_mant[1] = f1; \
170 fp->fp_mant[2] = f2; \
171 fp->fp_mant[3] = f3; \
174 fp->fp_exp = exp - expbias; \
175 fp->fp_mant[0] = FP_1 | f0; \
176 fp->fp_mant[1] = f1; \
177 fp->fp_mant[2] = f2; \
178 fp->fp_mant[3] = f3; \
182 * 32-bit single precision -> fpn.
183 * We assume a single occupies at most (64-FP_LG) bits in the internal
184 * format: i.e., needs at most fp_mant[0] and fp_mant[1].
193 #define SNG_SHIFT (SNG_FRACBITS - FP_LG)
195 exp = (i >> (32 - 1 - SNG_EXPBITS)) & mask(SNG_EXPBITS);
196 frac = i & mask(SNG_FRACBITS);
197 f0 = frac >> SNG_SHIFT;
198 f1 = frac << (32 - SNG_SHIFT);
199 FP_TOF(exp, SNG_EXP_BIAS, frac, f0, f1, 0, 0);
203 * 64-bit double -> fpn.
204 * We assume this uses at most (96-FP_LG) bits.
212 u_int frac, f0, f1, f2;
213 #define DBL_SHIFT (DBL_FRACBITS - 32 - FP_LG)
215 exp = (i >> (32 - 1 - DBL_EXPBITS)) & mask(DBL_EXPBITS);
216 frac = i & mask(DBL_FRACBITS - 32);
217 f0 = frac >> DBL_SHIFT;
218 f1 = (frac << (32 - DBL_SHIFT)) | (j >> DBL_SHIFT);
219 f2 = j << (32 - DBL_SHIFT);
221 FP_TOF(exp, DBL_EXP_BIAS, frac, f0, f1, f2, 0);
225 * 128-bit extended -> fpn.
228 __fpu_qtof(fp, i, j, k, l)
233 u_int frac, f0, f1, f2, f3;
234 #define EXT_SHIFT (-(EXT_FRACBITS - 3 * 32 - FP_LG)) /* left shift! */
237 * Note that ext and fpn `line up', hence no shifting needed.
239 exp = (i >> (32 - 1 - EXT_EXPBITS)) & mask(EXT_EXPBITS);
240 frac = i & mask(EXT_FRACBITS - 3 * 32);
241 f0 = (frac << EXT_SHIFT) | (j >> (32 - EXT_SHIFT));
242 f1 = (j << EXT_SHIFT) | (k >> (32 - EXT_SHIFT));
243 f2 = (k << EXT_SHIFT) | (l >> (32 - EXT_SHIFT));
246 FP_TOF(exp, EXT_EXP_BIAS, frac, f0, f1, f2, f3);
250 * Explode the contents of a / regpair / regquad.
251 * If the input is a signalling NaN, an NV (invalid) exception
252 * will be set. (Note that nothing but NV can occur until ALU
253 * operations are performed.)
256 __fpu_explode(fe, fp, type, reg)
265 if (type == FTYPE_LNG || type == FTYPE_DBL || type == FTYPE_EXT) {
266 l[0] = __fpu_getreg64(reg & ~1);
268 fp->fp_sign = sp[0] >> 31;
270 s = __fpu_getreg(reg);
271 fp->fp_sign = s >> 31;
276 s = __fpu_xtof(fp, l[0]);
280 s = __fpu_itof(fp, s);
284 s = __fpu_stof(fp, s);
288 s = __fpu_dtof(fp, sp[0], sp[1]);
292 l[1] = __fpu_getreg64((reg & ~1) + 2);
293 s = __fpu_qtof(fp, sp[0], sp[1], sp[2], sp[3]);
297 __utrap_panic("fpu_explode");
300 if (s == FPC_QNAN && (fp->fp_mant[0] & FP_QUIETBIT) == 0) {
302 * Input is a signalling NaN. All operations that return
303 * an input NaN operand put it through a ``NaN conversion'',
304 * which basically just means ``turn on the quiet bit''.
305 * We do this here so that all NaNs internally look quiet
306 * (we can tell signalling ones by their class).
308 fp->fp_mant[0] |= FP_QUIETBIT;
309 fe->fe_cx = FSR_NV; /* assert invalid operand */
313 DPRINTF(FPE_REG, ("fpu_explode: %%%c%d => ", (type == FTYPE_LNG) ? 'x' :
314 ((type == FTYPE_INT) ? 'i' :
315 ((type == FTYPE_SNG) ? 's' :
316 ((type == FTYPE_DBL) ? 'd' :
317 ((type == FTYPE_EXT) ? 'q' : '?')))),
319 DUMPFPN(FPE_REG, fp);
320 DPRINTF(FPE_REG, ("\n"));