2 * Copyright (c) 2003 Peter Wemm.
3 * Copyright (c) 1990 The Regents of the University of California.
6 * This code is derived from software contributed to Berkeley by
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
12 * 1. Redistributions of source code must retain the above copyright
13 * notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 * notice, this list of conditions and the following disclaimer in the
16 * documentation and/or other materials provided with the distribution.
17 * 4. Neither the name of the University nor the names of its contributors
18 * may be used to endorse or promote products derived from this software
19 * without specific prior written permission.
21 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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36 #include <machine/asmacros.h>
37 #include <machine/specialreg.h>
40 #include "opt_sched.h"
42 /*****************************************************************************/
44 /*****************************************************************************/
54 #if defined(SCHED_ULE) && defined(SMP)
63 * This is the second half of cpu_switch(). It is used when the current
64 * thread is either a dummy or slated to die, and we no longer care
65 * about its state. This is only a slight optimization and is probably
66 * not worth it anymore. Note that we need to clear the pm_active bits so
67 * we do need the old proc if it still exists.
74 movq PCPU(IDLETHREAD),%rdi
76 movq TD_PCB(%rdi),%r8 /* Old pcb */
77 movl PCPU(CPUID), %eax
78 /* release bit from old pm_active */
79 movq TD_PROC(%rdi), %rdx /* oldtd->td_proc */
80 movq P_VMSPACE(%rdx), %rdx /* proc->p_vmspace */
81 LK btrl %eax, VM_PMAP+PM_ACTIVE(%rdx) /* clear old */
82 movq TD_PCB(%rsi),%r8 /* newtd->td_proc */
83 movq PCB_CR3(%r8),%rdx
84 movq %rdx,%cr3 /* new address space */
89 * cpu_switch(old, new, mtx)
91 * Save the current thread state, then select the next thread to run
98 /* Switch to new thread. First, save context. */
100 movb $1,PCB_FULL_IRET(%r8)
102 movq (%rsp),%rax /* Hardware registers */
103 movq %r15,PCB_R15(%r8)
104 movq %r14,PCB_R14(%r8)
105 movq %r13,PCB_R13(%r8)
106 movq %r12,PCB_R12(%r8)
107 movq %rbp,PCB_RBP(%r8)
108 movq %rsp,PCB_RSP(%r8)
109 movq %rbx,PCB_RBX(%r8)
110 movq %rax,PCB_RIP(%r8)
112 testl $PCB_DBREGS,PCB_FLAGS(%r8)
113 jnz store_dr /* static predict not taken */
116 /* have we used fp, and need a save? */
117 cmpq %rdi,PCPU(FPCURTHREAD)
119 addq $PCB_SAVEFPU,%r8
126 movq %rax,PCPU(FPCURTHREAD)
129 /* Save is done. Now fire up new thread. Leave old vmspace. */
130 movq TD_PCB(%rsi),%r8
132 /* switch address space */
133 movq PCB_CR3(%r8),%rcx
135 cmpq %rcx,%rax /* Same address space? */
137 SETLK %rdx, TD_LOCK(%rdi) /* Release the old thread */
140 movq %rcx,%cr3 /* new address space */
141 movl PCPU(CPUID), %eax
142 /* Release bit from old pmap->pm_active */
143 movq TD_PROC(%rdi), %rcx /* oldproc */
144 movq P_VMSPACE(%rcx), %rcx
145 LK btrl %eax, VM_PMAP+PM_ACTIVE(%rcx) /* clear old */
146 SETLK %rdx, TD_LOCK(%rdi) /* Release the old thread */
148 /* Set bit in new pmap->pm_active */
149 movq TD_PROC(%rsi),%rdx /* newproc */
150 movq P_VMSPACE(%rdx), %rdx
151 LK btsl %eax, VM_PMAP+PM_ACTIVE(%rdx) /* set new */
154 #if defined(SCHED_ULE) && defined(SMP)
155 /* Wait for the new thread to become unblocked */
156 movq $blocked_lock, %rdx
158 movq TD_LOCK(%rsi),%rcx
164 * At this point, we've switched address spaces and are ready
165 * to load up the rest of the next context.
168 /* Skip loading user fsbase/gsbase for kthreads */
169 testl $TDP_KTHREAD,TD_PFLAGS(%rsi)
175 movq TD_PROC(%rsi),%rcx
176 cmpq $0, P_MD+MD_LDT(%rcx)
181 /* Restore fs base in GDT */
182 movl PCB_FSBASE(%r8),%eax
183 movq PCPU(FS32P),%rdx
190 /* Restore gs base in GDT */
191 movl PCB_GSBASE(%r8),%eax
192 movq PCPU(GS32P),%rdx
200 /* Do we need to reload tss ? */
202 movq PCB_TSSP(%r8),%rdx
204 cmovzq PCPU(COMMONTSSP),%rdx
209 movq %r8,PCPU(CURPCB)
210 /* Update the TSS_RSP0 pointer for the next interrupt */
211 movq %r8,COMMON_TSS_RSP0(%rdx)
212 movq %rsi,PCPU(CURTHREAD) /* into next thread */
214 /* Test if debug registers should be restored. */
215 testl $PCB_DBREGS,PCB_FLAGS(%r8)
216 jnz load_dr /* static predict not taken */
219 /* Restore context. */
220 movq PCB_R15(%r8),%r15
221 movq PCB_R14(%r8),%r14
222 movq PCB_R13(%r8),%r13
223 movq PCB_R12(%r8),%r12
224 movq PCB_RBP(%r8),%rbp
225 movq PCB_RSP(%r8),%rsp
226 movq PCB_RBX(%r8),%rbx
227 movq PCB_RIP(%r8),%rax
232 * We order these strangely for several reasons.
233 * 1: I wanted to use static branch prediction hints
234 * 2: Most athlon64/opteron cpus don't have them. They define
235 * a forward branch as 'predict not taken'. Intel cores have
236 * the 'rep' prefix to invert this.
237 * So, to make it work on both forms of cpu we do the detour.
238 * We use jumps rather than call in order to avoid the stack.
242 movq %dr7,%rax /* yes, do the save */
248 andq $0x0000fc00, %rax /* disable all watchpoints */
249 movq %r15,PCB_DR0(%r8)
250 movq %r14,PCB_DR1(%r8)
251 movq %r13,PCB_DR2(%r8)
252 movq %r12,PCB_DR3(%r8)
253 movq %r11,PCB_DR6(%r8)
254 movq %rax,PCB_DR7(%r8)
260 movq PCB_DR0(%r8),%r15
261 movq PCB_DR1(%r8),%r14
262 movq PCB_DR2(%r8),%r13
263 movq PCB_DR3(%r8),%r12
264 movq PCB_DR6(%r8),%r11
265 movq PCB_DR7(%r8),%rcx
268 /* Preserve reserved bits in %dr7 */
269 andq $0x0000fc00,%rax
270 andq $~0x0000fc00,%rcx
278 do_tss: movq %rdx,PCPU(TSSP)
288 movb $0x89,5(%rax) /* unset busy */
293 do_ldt: movq PCPU(LDT),%rax
294 movq P_MD+MD_LDT_SD(%rcx),%rdx
296 movq P_MD+MD_LDT_SD+8(%rcx),%rdx
304 * Update pcb, saving current processor state.
310 /* Save caller's return address. */
312 movq %rax,PCB_RIP(%rcx)
315 movq %rax,PCB_CR3(%rcx)
317 movq %rbx,PCB_RBX(%rcx)
318 movq %rsp,PCB_RSP(%rcx)
319 movq %rbp,PCB_RBP(%rcx)
320 movq %r12,PCB_R12(%rcx)
321 movq %r13,PCB_R13(%rcx)
322 movq %r14,PCB_R14(%rcx)
323 movq %r15,PCB_R15(%rcx)
326 * If fpcurthread == NULL, then the fpu h/w state is irrelevant and the
327 * state had better already be in the pcb. This is true for forks
328 * but not for dumps (the old book-keeping with FP flags in the pcb
329 * always lost for dumps because the dump pcb has 0 flags).
331 * If fpcurthread != NULL, then we have to save the fpu h/w state to
332 * fpcurthread's pcb and copy it to the requested pcb, or save to the
333 * requested pcb and reload. Copying is easier because we would
334 * have to handle h/w bugs for reloading. We used to lose the
335 * parent's fpu state for forks by forgetting to reload.
339 movq PCPU(FPCURTHREAD),%rax
343 movq TD_PCB(%rax),%rdi
344 leaq PCB_SAVEFPU(%rdi),%rdi
351 movq $PCB_SAVEFPU_SIZE,%rdx /* arg 3 */
352 leaq PCB_SAVEFPU(%rcx),%rsi /* arg 2 */
353 /* arg 1 (%rdi) already loaded */
363 * Update xpcb, saving current processor state.
369 /* Save caller's return address. */
371 movq %rax,PCB_RIP(%r8)
373 movq %rbx,PCB_RBX(%r8)
374 movq %rsp,PCB_RSP(%r8)
375 movq %rbp,PCB_RBP(%r8)
376 movq %r12,PCB_R12(%r8)
377 movq %r13,PCB_R13(%r8)
378 movq %r14,PCB_R14(%r8)
379 movq %r15,PCB_R15(%r8)
382 movq %rax,XPCB_CR0(%r8)
384 movq %rax,XPCB_CR2(%r8)
386 movq %rax,XPCB_CR4(%r8)
389 movq %rax,PCB_DR0(%r8)
391 movq %rax,PCB_DR1(%r8)
393 movq %rax,PCB_DR2(%r8)
395 movq %rax,PCB_DR3(%r8)
397 movq %rax,PCB_DR6(%r8)
399 movq %rax,PCB_DR7(%r8)
406 movl $MSR_FSBASE,%ecx
409 leaq (%rax,%rdx),%rax
410 movq %rax,PCB_FSBASE(%r8)
411 movl $MSR_GSBASE,%ecx
414 leaq (%rax,%rdx),%rax
415 movq %rax,PCB_GSBASE(%r8)
416 movl $MSR_KGSBASE,%ecx
419 leaq (%rax,%rdx),%rax
420 movq %rax,XPCB_KGSBASE(%r8)