2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 * notice, this list of conditions and the following disclaimer in the
12 * documentation and/or other materials provided with the distribution.
13 * 3. Neither the name of the author nor the names of any co-contributors
14 * may be used to endorse or promote products derived from this software
15 * without specific prior written permission.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * PIC driver for the 8259A Master and Slave PICs in PC/AT machines.
34 #include <sys/cdefs.h>
35 __FBSDID("$FreeBSD$");
37 #include "opt_auto_eoi.h"
40 #include <sys/param.h>
41 #include <sys/systm.h>
43 #include <sys/interrupt.h>
44 #include <sys/kernel.h>
46 #include <sys/module.h>
48 #include <machine/cpufunc.h>
49 #include <machine/frame.h>
50 #include <machine/intr_machdep.h>
51 #include <machine/md_var.h>
52 #include <machine/resource.h>
53 #include <machine/segments.h>
55 #include <dev/ic/i8259.h>
56 #include <amd64/isa/icu.h>
57 #include <amd64/isa/isa.h>
59 #include <isa/isavar.h>
65 * PC-AT machines wire the slave PIC to pin 2 on the master PIC.
70 * Determine the base master and slave modes not including auto EOI support.
71 * All machines that FreeBSD supports use 8086 mode.
73 #define BASE_MASTER_MODE ICW4_8086
74 #define BASE_SLAVE_MODE ICW4_8086
76 /* Enable automatic EOI if requested. */
78 #define MASTER_MODE (BASE_MASTER_MODE | ICW4_AEOI)
80 #define MASTER_MODE BASE_MASTER_MODE
83 #define SLAVE_MODE (BASE_SLAVE_MODE | ICW4_AEOI)
85 #define SLAVE_MODE BASE_SLAVE_MODE
88 #define IRQ_MASK(irq) (1 << (irq))
89 #define IMEN_MASK(ai) (IRQ_MASK((ai)->at_irq))
91 #define NUM_ISA_IRQS 16
93 static void atpic_init(void *dummy);
95 unsigned int imen; /* XXX */
98 IDTVEC(atpic_intr0), IDTVEC(atpic_intr1), IDTVEC(atpic_intr2),
99 IDTVEC(atpic_intr3), IDTVEC(atpic_intr4), IDTVEC(atpic_intr5),
100 IDTVEC(atpic_intr6), IDTVEC(atpic_intr7), IDTVEC(atpic_intr8),
101 IDTVEC(atpic_intr9), IDTVEC(atpic_intr10), IDTVEC(atpic_intr11),
102 IDTVEC(atpic_intr12), IDTVEC(atpic_intr13), IDTVEC(atpic_intr14),
103 IDTVEC(atpic_intr15);
105 #define IRQ(ap, ai) ((ap)->at_irqbase + (ai)->at_irq)
107 #define ATPIC(io, base, eoi, imenptr) \
108 { { atpic_enable_source, atpic_disable_source, (eoi), \
109 atpic_enable_intr, atpic_disable_intr, atpic_vector, \
110 atpic_source_pending, NULL, atpic_resume, atpic_config_intr,\
111 atpic_assign_cpu }, (io), (base), IDT_IO_INTS + (base), \
114 #define INTSRC(irq) \
115 { { &atpics[(irq) / 8].at_pic }, IDTVEC(atpic_intr ## irq ), \
126 struct atpic_intsrc {
127 struct intsrc at_intsrc;
129 int at_irq; /* Relative to PIC base. */
130 enum intr_trigger at_trigger;
132 u_long at_straycount;
135 static void atpic_enable_source(struct intsrc *isrc);
136 static void atpic_disable_source(struct intsrc *isrc, int eoi);
137 static void atpic_eoi_master(struct intsrc *isrc);
138 static void atpic_eoi_slave(struct intsrc *isrc);
139 static void atpic_enable_intr(struct intsrc *isrc);
140 static void atpic_disable_intr(struct intsrc *isrc);
141 static int atpic_vector(struct intsrc *isrc);
142 static void atpic_resume(struct pic *pic);
143 static int atpic_source_pending(struct intsrc *isrc);
144 static int atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
145 enum intr_polarity pol);
146 static int atpic_assign_cpu(struct intsrc *isrc, u_int apic_id);
147 static void i8259_init(struct atpic *pic, int slave);
149 static struct atpic atpics[] = {
150 ATPIC(IO_ICU1, 0, atpic_eoi_master, (uint8_t *)&imen),
151 ATPIC(IO_ICU2, 8, atpic_eoi_slave, ((uint8_t *)&imen) + 1)
154 static struct atpic_intsrc atintrs[] = {
173 CTASSERT(sizeof(atintrs) / sizeof(atintrs[0]) == NUM_ISA_IRQS);
176 _atpic_eoi_master(struct intsrc *isrc)
179 KASSERT(isrc->is_pic == &atpics[MASTER].at_pic,
180 ("%s: mismatched pic", __func__));
182 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
187 * The data sheet says no auto-EOI on slave, but it sometimes works.
188 * So, if AUTO_EOI_2 is enabled, we use it.
191 _atpic_eoi_slave(struct intsrc *isrc)
194 KASSERT(isrc->is_pic == &atpics[SLAVE].at_pic,
195 ("%s: mismatched pic", __func__));
197 outb(atpics[SLAVE].at_ioaddr, OCW2_EOI);
199 outb(atpics[MASTER].at_ioaddr, OCW2_EOI);
205 atpic_enable_source(struct intsrc *isrc)
207 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
208 struct atpic *ap = (struct atpic *)isrc->is_pic;
211 if (*ap->at_imen & IMEN_MASK(ai)) {
212 *ap->at_imen &= ~IMEN_MASK(ai);
213 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
219 atpic_disable_source(struct intsrc *isrc, int eoi)
221 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
222 struct atpic *ap = (struct atpic *)isrc->is_pic;
225 if (ai->at_trigger != INTR_TRIGGER_EDGE) {
226 *ap->at_imen |= IMEN_MASK(ai);
227 outb(ap->at_ioaddr + ICU_IMR_OFFSET, *ap->at_imen);
231 * Take care to call these functions directly instead of through
232 * a function pointer. All of the referenced variables should
233 * still be hot in the cache.
235 if (eoi == PIC_EOI) {
236 if (isrc->is_pic == &atpics[MASTER].at_pic)
237 _atpic_eoi_master(isrc);
239 _atpic_eoi_slave(isrc);
246 atpic_eoi_master(struct intsrc *isrc)
250 _atpic_eoi_master(isrc);
256 atpic_eoi_slave(struct intsrc *isrc)
260 _atpic_eoi_slave(isrc);
266 atpic_enable_intr(struct intsrc *isrc)
271 atpic_disable_intr(struct intsrc *isrc)
277 atpic_vector(struct intsrc *isrc)
279 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
280 struct atpic *ap = (struct atpic *)isrc->is_pic;
282 return (IRQ(ap, ai));
286 atpic_source_pending(struct intsrc *isrc)
288 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
289 struct atpic *ap = (struct atpic *)isrc->is_pic;
291 return (inb(ap->at_ioaddr) & IMEN_MASK(ai));
295 atpic_resume(struct pic *pic)
297 struct atpic *ap = (struct atpic *)pic;
299 i8259_init(ap, ap == &atpics[SLAVE]);
300 if (ap == &atpics[SLAVE] && elcr_found)
305 atpic_config_intr(struct intsrc *isrc, enum intr_trigger trig,
306 enum intr_polarity pol)
308 struct atpic_intsrc *ai = (struct atpic_intsrc *)isrc;
311 /* Map conforming values to edge/hi and sanity check the values. */
312 if (trig == INTR_TRIGGER_CONFORM)
313 trig = INTR_TRIGGER_EDGE;
314 if (pol == INTR_POLARITY_CONFORM)
315 pol = INTR_POLARITY_HIGH;
316 vector = atpic_vector(isrc);
317 if ((trig == INTR_TRIGGER_EDGE && pol == INTR_POLARITY_LOW) ||
318 (trig == INTR_TRIGGER_LEVEL && pol == INTR_POLARITY_HIGH)) {
320 "atpic: Mismatched config for IRQ%u: trigger %s, polarity %s\n",
321 vector, trig == INTR_TRIGGER_EDGE ? "edge" : "level",
322 pol == INTR_POLARITY_HIGH ? "high" : "low");
326 /* If there is no change, just return. */
327 if (ai->at_trigger == trig)
331 * Certain IRQs can never be level/lo, so don't try to set them
332 * that way if asked. At least some ELCR registers ignore setting
333 * these bits as well.
335 if ((vector == 0 || vector == 1 || vector == 2 || vector == 13) &&
336 trig == INTR_TRIGGER_LEVEL) {
339 "atpic: Ignoring invalid level/low configuration for IRQ%u\n",
345 printf("atpic: No ELCR to configure IRQ%u as %s\n",
346 vector, trig == INTR_TRIGGER_EDGE ? "edge/high" :
351 printf("atpic: Programming IRQ%u as %s\n", vector,
352 trig == INTR_TRIGGER_EDGE ? "edge/high" : "level/low");
354 elcr_write_trigger(atpic_vector(isrc), trig);
355 ai->at_trigger = trig;
361 atpic_assign_cpu(struct intsrc *isrc, u_int apic_id)
365 * 8259A's are only used in UP in which case all interrupts always
366 * go to the sole CPU and this function shouldn't even be called.
368 panic("%s: bad cookie", __func__);
372 i8259_init(struct atpic *pic, int slave)
376 /* Reset the PIC and program with next four bytes. */
378 outb(pic->at_ioaddr, ICW1_RESET | ICW1_IC4);
379 imr_addr = pic->at_ioaddr + ICU_IMR_OFFSET;
382 outb(imr_addr, pic->at_intbase);
385 * Setup slave links. For the master pic, indicate what line
386 * the slave is configured on. For the slave indicate
387 * which line on the master we are connected to.
390 outb(imr_addr, ICU_SLAVEID);
392 outb(imr_addr, IRQ_MASK(ICU_SLAVEID));
396 outb(imr_addr, SLAVE_MODE);
398 outb(imr_addr, MASTER_MODE);
400 /* Set interrupt enable mask. */
401 outb(imr_addr, *pic->at_imen);
403 /* Reset is finished, default to IRR on read. */
404 outb(pic->at_ioaddr, OCW3_SEL | OCW3_RR);
406 /* OCW2_L1 sets priority order to 3-7, 0-2 (com2 first). */
408 outb(pic->at_ioaddr, OCW2_R | OCW2_SL | OCW2_L1);
415 struct atpic_intsrc *ai;
418 /* Start off with all interrupts disabled. */
420 i8259_init(&atpics[MASTER], 0);
421 i8259_init(&atpics[SLAVE], 1);
422 atpic_enable_source((struct intsrc *)&atintrs[ICU_SLAVEID]);
424 /* Install low-level interrupt handlers for all of our IRQs. */
425 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
426 if (i == ICU_SLAVEID)
428 ai->at_intsrc.is_count = &ai->at_count;
429 ai->at_intsrc.is_straycount = &ai->at_straycount;
430 setidt(((struct atpic *)ai->at_intsrc.is_pic)->at_intbase +
431 ai->at_irq, ai->at_intr, SDT_SYSIGT, SEL_KPL, 0);
435 * Look for an ELCR. If we find one, update the trigger modes.
436 * If we don't find one, assume that IRQs 0, 1, 2, and 13 are
437 * edge triggered and that everything else is level triggered.
438 * We only use the trigger information to reprogram the ELCR if
439 * we have one and as an optimization to avoid masking edge
440 * triggered interrupts. For the case that we don't have an ELCR,
441 * it doesn't hurt to mask an edge triggered interrupt, so we
442 * assume level trigger for any interrupt that we aren't sure is
446 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
447 ai->at_trigger = elcr_read_trigger(i);
449 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++)
456 ai->at_trigger = INTR_TRIGGER_EDGE;
459 ai->at_trigger = INTR_TRIGGER_LEVEL;
466 atpic_init(void *dummy __unused)
468 struct atpic_intsrc *ai;
472 * Register our PICs, even if we aren't going to use any of their
473 * pins so that they are suspended and resumed.
475 if (intr_register_pic(&atpics[0].at_pic) != 0 ||
476 intr_register_pic(&atpics[1].at_pic) != 0)
477 panic("Unable to register ATPICs");
480 * If any of the ISA IRQs have an interrupt source already, then
481 * assume that the APICs are being used and don't register any
482 * of our interrupt sources. This makes sure we don't accidentally
483 * use mixed mode. The "accidental" use could otherwise occur on
484 * machines that route the ACPI SCI interrupt to a different ISA
485 * IRQ (at least one machines routes it to IRQ 13) thus disabling
486 * that APIC ISA routing and allowing the ATPIC source for that IRQ
487 * to leak through. We used to depend on this feature for routing
488 * IRQ0 via mixed mode, but now we don't use mixed mode at all.
490 for (i = 0; i < NUM_ISA_IRQS; i++)
491 if (intr_lookup_source(i) != NULL)
494 /* Loop through all interrupt sources and add them. */
495 for (i = 0, ai = atintrs; i < NUM_ISA_IRQS; i++, ai++) {
496 if (i == ICU_SLAVEID)
498 intr_register_source(&ai->at_intsrc);
501 SYSINIT(atpic_init, SI_SUB_INTR, SI_ORDER_SECOND + 1, atpic_init, NULL);
504 atpic_handle_intr(u_int vector, struct trapframe *frame)
508 KASSERT(vector < NUM_ISA_IRQS, ("unknown int %u\n", vector));
509 isrc = &atintrs[vector].at_intsrc;
512 * If we don't have an event, see if this is a spurious
515 if (isrc->is_event == NULL && (vector == 7 || vector == 15)) {
519 * Read the ISR register to see if IRQ 7/15 is really
520 * pending. Reset read register back to IRR when done.
522 port = ((struct atpic *)isrc->is_pic)->at_ioaddr;
524 outb(port, OCW3_SEL | OCW3_RR | OCW3_RIS);
526 outb(port, OCW3_SEL | OCW3_RR);
528 if ((isr & IRQ_MASK(7)) == 0)
531 intr_execute_handlers(isrc, frame);
536 * Bus attachment for the ISA PIC.
538 static struct isa_pnp_id atpic_ids[] = {
539 { 0x0000d041 /* PNP0000 */, "AT interrupt controller" },
544 atpic_probe(device_t dev)
548 result = ISA_PNP_PROBE(device_get_parent(dev), dev, atpic_ids);
555 * We might be granted IRQ 2, as this is typically consumed by chaining
556 * between the two PIC components. If we're using the APIC, however,
557 * this may not be the case, and as such we should free the resource.
560 * The generic ISA attachment code will handle allocating any other resources
561 * that we don't explicitly claim here.
564 atpic_attach(device_t dev)
566 struct resource *res;
569 /* Try to allocate our IRQ and then free it. */
571 res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 0);
573 bus_release_resource(dev, SYS_RES_IRQ, rid, res);
577 static device_method_t atpic_methods[] = {
578 /* Device interface */
579 DEVMETHOD(device_probe, atpic_probe),
580 DEVMETHOD(device_attach, atpic_attach),
581 DEVMETHOD(device_detach, bus_generic_detach),
582 DEVMETHOD(device_shutdown, bus_generic_shutdown),
583 DEVMETHOD(device_suspend, bus_generic_suspend),
584 DEVMETHOD(device_resume, bus_generic_resume),
588 static driver_t atpic_driver = {
594 static devclass_t atpic_devclass;
596 DRIVER_MODULE(atpic, isa, atpic_driver, atpic_devclass, 0, 0);
597 DRIVER_MODULE(atpic, acpi, atpic_driver, atpic_devclass, 0, 0);
600 * Return a bitmap of the current interrupt requests. This is 8259-specific
601 * and is only suitable for use at probe time.
604 isa_irq_pending(void)
611 return ((irr2 << 8) | irr1);