2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice unmodified, this list of conditions, and the following
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
32 #include <sys/param.h>
33 #include <sys/systm.h>
35 #include <sys/kernel.h>
36 #include <sys/malloc.h>
37 #include <sys/module.h>
38 #include <sys/sysctl.h>
40 #include <dev/pci/pcivar.h>
41 #include <dev/pci/pcireg.h>
42 #include <dev/pci/pcib_private.h>
43 #include <isa/isavar.h>
44 #include <machine/legacyvar.h>
45 #include <machine/pci_cfgreg.h>
46 #include <machine/resource.h>
51 legacy_pcib_maxslots(device_t dev)
56 /* read configuration space register */
59 legacy_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func,
62 return(pci_cfgregread(bus, slot, func, reg, bytes));
65 /* write configuration space register */
68 legacy_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func,
69 u_int reg, uint32_t data, int bytes)
71 pci_cfgregwrite(bus, slot, func, reg, data, bytes);
77 legacy_pcib_route_interrupt(device_t pcib, device_t dev, int pin)
80 /* No routing possible */
81 return (PCI_INVALID_IRQ);
84 /* Pass MSI requests up to the nexus. */
87 legacy_pcib_alloc_msi(device_t pcib, device_t dev, int count, int maxcount,
92 bus = device_get_parent(pcib);
93 return (PCIB_ALLOC_MSI(device_get_parent(bus), dev, count, maxcount,
98 legacy_pcib_alloc_msix(device_t pcib, device_t dev, int *irq)
102 bus = device_get_parent(pcib);
103 return (PCIB_ALLOC_MSIX(device_get_parent(bus), dev, irq));
107 legacy_pcib_map_msi(device_t pcib, device_t dev, int irq, uint64_t *addr,
112 bus = device_get_parent(pcib);
113 return (PCIB_MAP_MSI(device_get_parent(bus), dev, irq, addr, data));
117 legacy_pcib_is_host_bridge(int bus, int slot, int func,
118 uint32_t id, uint8_t class, uint8_t subclass,
121 const char *s = NULL;
124 if (class == PCIC_BRIDGE && subclass == PCIS_BRIDGE_HOST)
125 s = "Host to PCI bridge";
130 * Scan the first pci bus for host-pci bridges and add pcib instances
131 * to the nexus for each bridge.
134 legacy_pcib_identify(driver_t *driver, device_t parent)
143 devclass_t pci_devclass;
145 if (pci_cfgregopen() == 0)
148 * Check to see if we haven't already had a PCI bus added
149 * via some other means. If we have, bail since otherwise
150 * we're going to end up duplicating it.
152 if ((pci_devclass = devclass_find("pci")) &&
153 devclass_get_device(pci_devclass, 0))
159 for (slot = 0; slot <= PCI_SLOTMAX; slot++) {
161 hdrtype = legacy_pcib_read_config(0, bus, slot, func,
164 * When enumerating bus devices, the standard says that
165 * one should check the header type and ignore the slots whose
166 * header types that the software doesn't know about. We use
167 * this to filter out devices.
169 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE)
171 if ((hdrtype & PCIM_MFDEV) &&
172 (!found_orion || hdrtype != 0xff))
173 pcifunchigh = PCI_FUNCMAX;
176 for (func = 0; func <= pcifunchigh; func++) {
178 * Read the IDs and class from the device.
181 u_int8_t class, subclass, busnum;
186 id = legacy_pcib_read_config(0, bus, slot, func,
190 class = legacy_pcib_read_config(0, bus, slot, func,
192 subclass = legacy_pcib_read_config(0, bus, slot, func,
195 s = legacy_pcib_is_host_bridge(bus, slot, func,
202 * Check to see if the physical bus has already
203 * been seen. Eg: hybrid 32 and 64 bit host
204 * bridges to the same logical bus.
206 if (device_get_children(parent, &devs, &ndevs) == 0) {
207 for (i = 0; s != NULL && i < ndevs; i++) {
208 if (strcmp(device_get_name(devs[i]),
211 if (legacy_get_pcibus(devs[i]) == busnum)
220 * Add at priority 100 to make sure we
221 * go after any motherboard resources
223 child = BUS_ADD_CHILD(parent, 100,
225 device_set_desc(child, s);
226 legacy_set_pcibus(child, busnum);
229 if (id == 0x12258086)
231 if (id == 0x84c48086)
235 if (found824xx && bus == 0) {
241 * Make sure we add at least one bridge since some old
242 * hardware doesn't actually have a host-pci bridge device.
243 * Note that pci_cfgregopen() thinks we have PCI devices..
248 "legacy_pcib_identify: no bridge found, adding pcib0 anyway\n");
249 child = BUS_ADD_CHILD(parent, 100, "pcib", 0);
250 legacy_set_pcibus(child, 0);
255 legacy_pcib_probe(device_t dev)
258 if (pci_cfgregopen() == 0)
264 legacy_pcib_attach(device_t dev)
268 bus = pcib_get_bus(dev);
269 device_add_child(dev, "pci", bus);
270 return bus_generic_attach(dev);
274 legacy_pcib_read_ivar(device_t dev, device_t child, int which,
279 case PCIB_IVAR_DOMAIN:
283 *result = legacy_get_pcibus(dev);
290 legacy_pcib_write_ivar(device_t dev, device_t child, int which,
295 case PCIB_IVAR_DOMAIN:
298 legacy_set_pcibus(dev, value);
304 SYSCTL_DECL(_hw_pci);
306 static unsigned long legacy_host_mem_start = 0x80000000;
307 TUNABLE_ULONG("hw.pci.host_mem_start", &legacy_host_mem_start);
308 SYSCTL_ULONG(_hw_pci, OID_AUTO, host_mem_start, CTLFLAG_RDTUN,
309 &legacy_host_mem_start, 0x80000000,
310 "Limit the host bridge memory to being above this address. Must be\n\
311 set at boot via a tunable.");
314 legacy_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid,
315 u_long start, u_long end, u_long count, u_int flags)
318 * If no memory preference is given, use upper 32MB slot most
319 * bioses use for their memory window. Typically other bridges
320 * before us get in the way to assert their preferences on memory.
321 * Hardcoding like this sucks, so a more MD/MI way needs to be
322 * found to do it. This is typically only used on older laptops
323 * that don't have pci busses behind pci bridge, so assuming > 32MB
326 * However, this can cause problems for other chipsets, so we make
327 * this tunable by hw.pci.host_mem_start.
329 if (type == SYS_RES_MEMORY && start == 0UL && end == ~0UL)
330 start = legacy_host_mem_start;
331 if (type == SYS_RES_IOPORT && start == 0UL && end == ~0UL)
333 return (bus_generic_alloc_resource(dev, child, type, rid, start, end,
337 static device_method_t legacy_pcib_methods[] = {
338 /* Device interface */
339 DEVMETHOD(device_identify, legacy_pcib_identify),
340 DEVMETHOD(device_probe, legacy_pcib_probe),
341 DEVMETHOD(device_attach, legacy_pcib_attach),
342 DEVMETHOD(device_shutdown, bus_generic_shutdown),
343 DEVMETHOD(device_suspend, bus_generic_suspend),
344 DEVMETHOD(device_resume, bus_generic_resume),
347 DEVMETHOD(bus_print_child, bus_generic_print_child),
348 DEVMETHOD(bus_read_ivar, legacy_pcib_read_ivar),
349 DEVMETHOD(bus_write_ivar, legacy_pcib_write_ivar),
350 DEVMETHOD(bus_alloc_resource, legacy_pcib_alloc_resource),
351 DEVMETHOD(bus_release_resource, bus_generic_release_resource),
352 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource),
353 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource),
354 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr),
355 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr),
358 DEVMETHOD(pcib_maxslots, legacy_pcib_maxslots),
359 DEVMETHOD(pcib_read_config, legacy_pcib_read_config),
360 DEVMETHOD(pcib_write_config, legacy_pcib_write_config),
361 DEVMETHOD(pcib_route_interrupt, legacy_pcib_route_interrupt),
362 DEVMETHOD(pcib_alloc_msi, legacy_pcib_alloc_msi),
363 DEVMETHOD(pcib_release_msi, pcib_release_msi),
364 DEVMETHOD(pcib_alloc_msix, legacy_pcib_alloc_msix),
365 DEVMETHOD(pcib_release_msix, pcib_release_msix),
366 DEVMETHOD(pcib_map_msi, legacy_pcib_map_msi),
371 static devclass_t hostb_devclass;
373 DEFINE_CLASS_0(pcib, legacy_pcib_driver, legacy_pcib_methods, 1);
374 DRIVER_MODULE(pcib, legacy, legacy_pcib_driver, hostb_devclass, 0, 0);
378 * Install placeholder to claim the resources owned by the
379 * PCI bus interface. This could be used to extract the
380 * config space registers in the extreme case where the PnP
381 * ID is available and the PCI BIOS isn't, but for now we just
382 * eat the PnP ID and do nothing else.
384 * XXX we should silence this probe, as it will generally confuse
387 static struct isa_pnp_id pcibus_pnp_ids[] = {
388 { 0x030ad041 /* PNP0A03 */, "PCI Bus" },
389 { 0x080ad041 /* PNP0A08 */, "PCIe Bus" },
394 pcibus_pnp_probe(device_t dev)
398 if ((result = ISA_PNP_PROBE(device_get_parent(dev), dev, pcibus_pnp_ids)) <= 0)
404 pcibus_pnp_attach(device_t dev)
409 static device_method_t pcibus_pnp_methods[] = {
410 /* Device interface */
411 DEVMETHOD(device_probe, pcibus_pnp_probe),
412 DEVMETHOD(device_attach, pcibus_pnp_attach),
413 DEVMETHOD(device_detach, bus_generic_detach),
414 DEVMETHOD(device_shutdown, bus_generic_shutdown),
415 DEVMETHOD(device_suspend, bus_generic_suspend),
416 DEVMETHOD(device_resume, bus_generic_resume),
420 static devclass_t pcibus_pnp_devclass;
422 DEFINE_CLASS_0(pcibus_pnp, pcibus_pnp_driver, pcibus_pnp_methods, 1);
423 DRIVER_MODULE(pcibus_pnp, isa, pcibus_pnp_driver, pcibus_pnp_devclass, 0, 0);