1 /* $NetBSD: locore.S,v 1.14 2003/04/20 16:21:40 thorpej Exp $ */
4 * Copyright (C) 1994-1997 Mark Brinicombe
5 * Copyright (C) 1994 Brini
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
16 * 3. All advertising materials mentioning features or use of this software
17 * must display the following acknowledgement:
18 * This product includes software developed by Brini.
19 * 4. The name of Brini may not be used to endorse or promote products
20 * derived from this software without specific prior written permission.
22 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR
23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
25 * IN NO EVENT SHALL BRINI BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
26 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
27 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
28 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
29 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
30 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF
31 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
36 #include <sys/syscall.h>
37 #include <machine/asm.h>
38 #include <machine/armreg.h>
39 #include <machine/pte.h>
40 __FBSDID("$FreeBSD$");
42 /* What size should this really be ? It is only used by initarm() */
43 #define INIT_ARM_STACK_SIZE 2048
46 * This is for kvm_mkdb, and should be the address of the beginning
47 * of the kernel text segment (not necessarily the same as kernbase).
51 #define CPWAIT_BRANCH \
55 mrc p15, 0, tmp, c2, c0, 0 /* arbitrary read of CP15 */ ;\
56 mov tmp, tmp /* wait for it to complete */ ;\
57 CPWAIT_BRANCH /* branch to next insn */
62 .set kernbase,KERNBASE
64 .set physaddr,PHYSADDR
71 * Move metadata ptr to r12 (ip)
76 /* Make sure interrupts are disabled. */
78 orr r7, r7, #(I32_bit|F32_bit)
81 #if defined (FLASHADDR) && defined(LOADERRAMADDR)
82 /* Check if we're running from flash. */
85 * If we're running with MMU disabled, test against the
86 * physical address instead.
88 mrc p15, 0, r2, c1, c0, 0
89 ands r2, r2, #CPU_CONTROL_MMU_ENABLE
91 ldrne r8, =LOADERRAMADDR
113 Lram_offset: .word from_ram-_C_LABEL(_start)
118 bic r7, r7, #0xf0000000
119 orr r7, r7, #PHYSADDR
123 /* Disable MMU for a while */
124 mrc p15, 0, r2, c1, c0, 0
125 bic r2, r2, #(CPU_CONTROL_MMU_ENABLE | CPU_CONTROL_DC_ENABLE |\
126 CPU_CONTROL_WBUF_ENABLE)
127 bic r2, r2, #(CPU_CONTROL_IC_ENABLE)
128 bic r2, r2, #(CPU_CONTROL_BPRD_ENABLE)
129 mcr p15, 0, r2, c1, c0, 0
136 #ifdef STARTUP_PAGETABLE_ADDR
137 /* build page table from scratch */
138 ldr r0, Lstartup_pagetable
139 adr r4, mmu_init_table
145 add r3, r3, #(L1_S_SIZE)
149 ldmia r4!, {r1,r2,r3} /* # of sections, VA, PA|attr */
152 bicne r5, r5, #0xf0000000
153 orrne r5, r5, #PHYSADDR
156 mcr p15, 0, r0, c2, c0, 0 /* Set TTB */
157 mcr p15, 0, r0, c8, c7, 0 /* Flush TLB */
159 /* Set the Domain Access register. Very important! */
160 mov r0, #((DOMAIN_CLIENT << (PMAP_DOMAIN_KERNEL*2)) | DOMAIN_CLIENT)
161 mcr p15, 0, r0, c3, c0, 0
163 mrc p15, 0, r0, c1, c0, 0
164 orr r0, r0, #CPU_CONTROL_MMU_ENABLE
165 mcr p15, 0, r0, c1, c0, 0
175 ldmia r1, {r1, r2, sp} /* Set initial stack and */
176 sub r2, r2, r1 /* get zero init data */
179 str r3, [r1], #0x0004 /* get zero init data */
185 mov r0, ip /* Load argument: metadata ptr */
187 mov fp, #0 /* trace back starts here */
188 bl _C_LABEL(initarm) /* Off we go */
190 /* init arm will return the new stack pointer. */
193 bl _C_LABEL(mi_startup) /* call mi_startup()! */
195 adr r0, .Lmainreturned
198 #ifdef STARTUP_PAGETABLE_ADDR
199 #define MMU_INIT(va,pa,n_sec,attr) \
201 .word 4*((va)>>L1_S_SHIFT) ; \
213 .word STARTUP_PAGETABLE_ADDR
215 /* fill all table VA==PA */
216 /* map SDRAM VA==PA, WT cacheable */
217 MMU_INIT(PHYSADDR, PHYSADDR , 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
218 /* map VA 0xc0000000..0xc3ffffff to PA */
219 MMU_INIT(KERNBASE, PHYSADDR, 64, L1_TYPE_S|L1_S_C|L1_S_AP(AP_KRW))
221 .word 0 /* end of table */
226 .word svcstk + INIT_ARM_STACK_SIZE
228 #if defined(FLASHADDR) && defined(LOADERRAMADDR)
230 .word _C_LABEL(_arm_memcpy)
236 .asciz "main() returned"
241 .space INIT_ARM_STACK_SIZE
247 .word _C_LABEL(cpufuncs)
251 bic r2, r2, #(PSR_MODE)
252 orr r2, r2, #(PSR_SVC32_MODE)
253 orr r2, r2, #(I32_bit | F32_bit)
256 ldr r4, .Lcpu_reset_address
261 ldr pc, [r0, #CF_IDCACHE_WBINV_ALL]
263 ldr pc, [r0, #CF_L2CACHE_WBINV_ALL]
266 * Load the cpu_reset_needs_v4_MMU_disable flag to determine if it's
270 ldr r1, .Lcpu_reset_needs_v4_MMU_disable
276 * MMU & IDC off, 32 bit program & data space
277 * Hurl ourselves into the ROM
279 mov r0, #(CPU_CONTROL_32BP_ENABLE | CPU_CONTROL_32BD_ENABLE)
280 mcr 15, 0, r0, c1, c0, 0
281 mcrne 15, 0, r2, c8, c7, 0 /* nail I+D TLB on ARMv4 and greater */
285 * _cpu_reset_address contains the address to branch to, to complete
286 * the cpu reset after turning the MMU off
287 * This variable is provided by the hardware specific code
290 .word _C_LABEL(cpu_reset_address)
293 * cpu_reset_needs_v4_MMU_disable contains a flag that signals if the
294 * v4 MMU disable instruction needs executing... it is an illegal instruction
295 * on f.e. ARM6/7 that locks up the computer in an endless illegal
296 * instruction / data-abort / reset loop.
298 .Lcpu_reset_needs_v4_MMU_disable:
299 .word _C_LABEL(cpu_reset_needs_v4_MMU_disable)
316 .global _C_LABEL(esym)
317 _C_LABEL(esym): .word _C_LABEL(end)
326 /* Well if that failed we better exit quick ! */
332 .global _C_LABEL(esigcode)
338 .long esigcode-sigcode
339 /* End of locore.S */