sys/arm/mv/common.c

   1 /*-
   2  * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
   3  * All rights reserved.
   4  *
   5  * Developed by Semihalf.
   6  *
   7  * Redistribution and use in source and binary forms, with or without
   8  * modification, are permitted provided that the following conditions
   9  * are met:
  10  * 1. Redistributions of source code must retain the above copyright
  11  *    notice, this list of conditions and the following disclaimer.
  12  * 2. Redistributions in binary form must reproduce the above copyright
  13  *    notice, this list of conditions and the following disclaimer in the
  14  *    documentation and/or other materials provided with the distribution.
  15  * 3. Neither the name of MARVELL nor the names of contributors
  16  *    may be used to endorse or promote products derived from this software
  17  *    without specific prior written permission.
  18  *
  19  * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
  20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  22  * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
  23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
  25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
  27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  29  * SUCH DAMAGE.
  30  */
  31
  32 #include <sys/cdefs.h>
  33 __FBSDID("$FreeBSD$");
  34
  35 #include <sys/systm.h>
  36 #include <sys/bus.h>
  37
  38 #include <machine/bus.h>
  39
  40 #include <arm/mv/mvreg.h>
  41 #include <arm/mv/mvvar.h>
  42 #include <arm/mv/mvwin.h>
  43
  44 static int win_eth_can_remap(int i);
  45
  46 static int decode_win_cpu_valid(void);
  47 static int decode_win_usb_valid(void);
  48 static int decode_win_eth_valid(void);
  49 static int decode_win_pcie_valid(void);
  50 static int decode_win_sata_valid(void);
  51 static int decode_win_cesa_valid(void);
  52
  53 static void decode_win_cpu_setup(void);
  54 static void decode_win_usb_setup(void);
  55 static void decode_win_eth_setup(uint32_t base);
  56 static void decode_win_pcie_setup(uint32_t base);
  57 static void decode_win_sata_setup(void);
  58 static void decode_win_cesa_setup(void);
  59
  60 static void decode_win_cesa_dump(void);
  61 static void decode_win_usb_dump(void);
  62
  63 static uint32_t used_cpu_wins;
  64
  65 uint32_t
  66 read_cpu_ctrl(uint32_t reg)
  67 {
  68
  69         return (bus_space_read_4(obio_tag, MV_CPU_CONTROL_BASE, reg));
  70 }
  71
  72 void
  73 write_cpu_ctrl(uint32_t reg, uint32_t val)
  74 {
  75
  76         bus_space_write_4(obio_tag, MV_CPU_CONTROL_BASE, reg, val);
  77 }
  78
  79 void
  80 cpu_reset(void)
  81 {
  82
  83         write_cpu_ctrl(RSTOUTn_MASK, SOFT_RST_OUT_EN);
  84         write_cpu_ctrl(SYSTEM_SOFT_RESET, SYS_SOFT_RST);
  85         while (1);
  86 }
  87
  88 uint32_t
  89 cpu_extra_feat(void)
  90 {
  91         uint32_t dev, rev;
  92         uint32_t ef = 0;
  93
  94         soc_id(&dev, &rev);
  95         if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100_Z0 ||
  96             dev == MV_DEV_MV78100)
  97                 __asm __volatile("mrc p15, 1, %0, c15, c1, 0" : "=r" (ef));
  98         else if (dev == MV_DEV_88F5182 || dev == MV_DEV_88F5281)
  99                 __asm __volatile("mrc p15, 0, %0, c14, c0, 0" : "=r" (ef));
 100         else if (bootverbose)
 101                 printf("This ARM Core does not support any extra features\n");
 102
 103         return (ef);
 104 }
 105
 106 uint32_t
 107 soc_power_ctrl_get(uint32_t mask)
 108 {
 109
 110         if (mask != CPU_PM_CTRL_NONE)
 111                 mask &= read_cpu_ctrl(CPU_PM_CTRL);
 112
 113         return (mask);
 114 }
 115
 116 void
 117 soc_id(uint32_t *dev, uint32_t *rev)
 118 {
 119
 120         /*
 121          * Notice: system identifiers are available in the registers range of
 122          * PCIE controller, so using this function is only allowed (and
 123          * possible) after the internal registers range has been mapped in via
 124          * pmap_devmap_bootstrap().
 125          */
 126         *dev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 0) >> 16;
 127         *rev = bus_space_read_4(obio_tag, MV_PCIE_BASE, 8) & 0xff;
 128 }
 129
 130 void
 131 soc_identify(void)
 132 {
 133         uint32_t d, r;
 134         const char *dev;
 135         const char *rev;
 136
 137         soc_id(&d, &r);
 138
 139         printf("SOC: ");
 140         if (bootverbose)
 141                 printf("(0x%4x:0x%02x) ", d, r);
 142
 143         rev = "";
 144         switch (d) {
 145         case MV_DEV_88F5181:
 146                 dev = "Marvell 88F5181";
 147                 if (r == 3)
 148                         rev = "B1";
 149                 break;
 150         case MV_DEV_88F5182:
 151                 dev = "Marvell 88F5182";
 152                 if (r == 2)
 153                         rev = "A2";
 154                 break;
 155         case MV_DEV_88F5281:
 156                 dev = "Marvell 88F5281";
 157                 if (r == 4)
 158                         rev = "D0";
 159                 else if (r == 5)
 160                         rev = "D1";
 161                 else if (r == 6)
 162                         rev = "D2";
 163                 break;
 164         case MV_DEV_88F6281:
 165                 dev = "Marvell 88F6281";
 166                 if (r == 0)
 167                         rev = "Z0";
 168                 else if (r == 2)
 169                         rev = "A0";
 170                 break;
 171         case MV_DEV_MV78100_Z0:
 172                 dev = "Marvell MV78100 Z0";
 173                 break;
 174         case MV_DEV_MV78100:
 175                 dev = "Marvell MV78100";
 176                 break;
 177         default:
 178                 dev = "UNKNOWN";
 179                 break;
 180         }
 181
 182         printf("%s", dev);
 183         if (*rev != '\0')
 184                 printf(" rev %s", rev);
 185         printf(", TClock %dMHz\n", get_tclk() / 1000 / 1000);
 186
 187         /* TODO add info on currently set endianess */
 188 }
 189
 190 int
 191 soc_decode_win(void)
 192 {
 193         uint32_t dev, rev;
 194
 195         /* Retrieve our ID: some windows facilities vary between SoC models */
 196         soc_id(&dev, &rev);
 197
 198         if (decode_win_cpu_valid() != 1 || decode_win_usb_valid() != 1 ||
 199             decode_win_eth_valid() != 1 || decode_win_idma_valid() != 1 ||
 200             decode_win_pcie_valid() != 1 || decode_win_sata_valid() != 1 ||
 201             decode_win_cesa_valid() != 1)
 202                 return(-1);
 203
 204         decode_win_cpu_setup();
 205         decode_win_usb_setup();
 206         decode_win_eth_setup(MV_ETH0_BASE);
 207         if (dev == MV_DEV_MV78100 || dev == MV_DEV_MV78100_Z0)
 208                 decode_win_eth_setup(MV_ETH1_BASE);
 209         if (dev == MV_DEV_88F6281 || dev == MV_DEV_MV78100 ||
 210             dev == MV_DEV_MV78100_Z0)
 211                 decode_win_cesa_setup();
 212
 213         decode_win_idma_setup();
 214         decode_win_xor_setup();
 215
 216         if (dev == MV_DEV_MV78100 || dev == MV_DEV_MV78100_Z0) {
 217                 decode_win_pcie_setup(MV_PCIE00_BASE);
 218                 decode_win_pcie_setup(MV_PCIE01_BASE);
 219                 decode_win_pcie_setup(MV_PCIE02_BASE);
 220                 decode_win_pcie_setup(MV_PCIE03_BASE);
 221                 decode_win_pcie_setup(MV_PCIE10_BASE);
 222                 decode_win_pcie_setup(MV_PCIE11_BASE);
 223                 decode_win_pcie_setup(MV_PCIE12_BASE);
 224                 decode_win_pcie_setup(MV_PCIE13_BASE);
 225         } else
 226                 decode_win_pcie_setup(MV_PCIE_BASE);
 227
 228         if (dev != MV_DEV_88F5281)
 229                 decode_win_sata_setup();
 230
 231         return (0);
 232 }
 233
 234 /**************************************************************************
 235  * Decode windows registers accessors
 236  **************************************************************************/
 237 WIN_REG_IDX_RD(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
 238 WIN_REG_IDX_RD(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
 239 WIN_REG_IDX_RD(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
 240 WIN_REG_IDX_RD(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
 241 WIN_REG_IDX_WR(win_cpu, cr, MV_WIN_CPU_CTRL, MV_MBUS_BRIDGE_BASE)
 242 WIN_REG_IDX_WR(win_cpu, br, MV_WIN_CPU_BASE, MV_MBUS_BRIDGE_BASE)
 243 WIN_REG_IDX_WR(win_cpu, remap_l, MV_WIN_CPU_REMAP_LO, MV_MBUS_BRIDGE_BASE)
 244 WIN_REG_IDX_WR(win_cpu, remap_h, MV_WIN_CPU_REMAP_HI, MV_MBUS_BRIDGE_BASE)
 245
 246 WIN_REG_IDX_RD(ddr, br, MV_WIN_DDR_BASE, MV_DDR_CADR_BASE)
 247 WIN_REG_IDX_RD(ddr, sz, MV_WIN_DDR_SIZE, MV_DDR_CADR_BASE)
 248
 249 WIN_REG_IDX_RD2(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
 250 WIN_REG_IDX_RD2(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
 251 WIN_REG_IDX_WR2(win_usb, cr, MV_WIN_USB_CTRL, MV_USB_AWR_BASE)
 252 WIN_REG_IDX_WR2(win_usb, br, MV_WIN_USB_BASE, MV_USB_AWR_BASE)
 253
 254 WIN_REG_IDX_RD(win_cesa, cr, MV_WIN_CESA_CTRL, MV_CESA_BASE)
 255 WIN_REG_IDX_RD(win_cesa, br, MV_WIN_CESA_BASE, MV_CESA_BASE)
 256 WIN_REG_IDX_WR(win_cesa, cr, MV_WIN_CESA_CTRL, MV_CESA_BASE)
 257 WIN_REG_IDX_WR(win_cesa, br, MV_WIN_CESA_BASE, MV_CESA_BASE)
 258
 259 WIN_REG_BASE_IDX_RD(win_eth, br, MV_WIN_ETH_BASE)
 260 WIN_REG_BASE_IDX_RD(win_eth, sz, MV_WIN_ETH_SIZE)
 261 WIN_REG_BASE_IDX_RD(win_eth, har, MV_WIN_ETH_REMAP)
 262 WIN_REG_BASE_IDX_WR(win_eth, br, MV_WIN_ETH_BASE)
 263 WIN_REG_BASE_IDX_WR(win_eth, sz, MV_WIN_ETH_SIZE)
 264 WIN_REG_BASE_IDX_WR(win_eth, har, MV_WIN_ETH_REMAP)
 265
 266 WIN_REG_IDX_RD2(win_xor, br, MV_WIN_XOR_BASE, MV_XOR_BASE)
 267 WIN_REG_IDX_RD2(win_xor, sz, MV_WIN_XOR_SIZE, MV_XOR_BASE)
 268 WIN_REG_IDX_RD2(win_xor, har, MV_WIN_XOR_REMAP, MV_XOR_BASE)
 269 WIN_REG_IDX_RD2(win_xor, ctrl, MV_WIN_XOR_CTRL, MV_XOR_BASE)
 270 WIN_REG_IDX_WR2(win_xor, br, MV_WIN_XOR_BASE, MV_XOR_BASE)
 271 WIN_REG_IDX_WR2(win_xor, sz, MV_WIN_XOR_SIZE, MV_XOR_BASE)
 272 WIN_REG_IDX_WR2(win_xor, har, MV_WIN_XOR_REMAP, MV_XOR_BASE)
 273 WIN_REG_IDX_WR2(win_xor, ctrl, MV_WIN_XOR_CTRL, MV_XOR_BASE)
 274
 275 WIN_REG_BASE_RD(win_eth, bare, 0x290)
 276 WIN_REG_BASE_RD(win_eth, epap, 0x294)
 277 WIN_REG_BASE_WR(win_eth, bare, 0x290)
 278 WIN_REG_BASE_WR(win_eth, epap, 0x294)
 279
 280 WIN_REG_BASE_IDX_RD(win_pcie, cr, MV_WIN_PCIE_CTRL);
 281 WIN_REG_BASE_IDX_RD(win_pcie, br, MV_WIN_PCIE_BASE);
 282 WIN_REG_BASE_IDX_RD(win_pcie, remap, MV_WIN_PCIE_REMAP);
 283 WIN_REG_BASE_IDX_WR(win_pcie, cr, MV_WIN_PCIE_CTRL);
 284 WIN_REG_BASE_IDX_WR(win_pcie, br, MV_WIN_PCIE_BASE);
 285 WIN_REG_BASE_IDX_WR(win_pcie, remap, MV_WIN_PCIE_REMAP);
 286 WIN_REG_BASE_IDX_WR(pcie, bar, MV_PCIE_BAR);
 287
 288 WIN_REG_IDX_RD(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
 289 WIN_REG_IDX_RD(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
 290 WIN_REG_IDX_RD(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
 291 WIN_REG_IDX_RD(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
 292 WIN_REG_IDX_WR(win_idma, br, MV_WIN_IDMA_BASE, MV_IDMA_BASE)
 293 WIN_REG_IDX_WR(win_idma, sz, MV_WIN_IDMA_SIZE, MV_IDMA_BASE)
 294 WIN_REG_IDX_WR(win_idma, har, MV_WIN_IDMA_REMAP, MV_IDMA_BASE)
 295 WIN_REG_IDX_WR(win_idma, cap, MV_WIN_IDMA_CAP, MV_IDMA_BASE)
 296 WIN_REG_RD(win_idma, bare, 0xa80, MV_IDMA_BASE)
 297 WIN_REG_WR(win_idma, bare, 0xa80, MV_IDMA_BASE)
 298
 299 WIN_REG_IDX_RD(win_sata, cr, MV_WIN_SATA_CTRL, MV_SATAHC_BASE);
 300 WIN_REG_IDX_RD(win_sata, br, MV_WIN_SATA_BASE, MV_SATAHC_BASE);
 301 WIN_REG_IDX_WR(win_sata, cr, MV_WIN_SATA_CTRL, MV_SATAHC_BASE);
 302 WIN_REG_IDX_WR(win_sata, br, MV_WIN_SATA_BASE, MV_SATAHC_BASE);
 303
 304 /**************************************************************************
 305  * Decode windows helper routines
 306  **************************************************************************/
 307 void
 308 soc_dump_decode_win(void)
 309 {
 310         uint32_t dev, rev;
 311         int i;
 312
 313         soc_id(&dev, &rev);
 314
 315         for (i = 0; i < MV_WIN_CPU_MAX; i++) {
 316                 printf("CPU window#%d: c 0x%08x, b 0x%08x", i,
 317                     win_cpu_cr_read(i),
 318                     win_cpu_br_read(i));
 319
 320                 if (win_cpu_can_remap(i))
 321                         printf(", rl 0x%08x, rh 0x%08x",
 322                             win_cpu_remap_l_read(i),
 323                             win_cpu_remap_h_read(i));
 324
 325                 printf("\n");
 326         }
 327         printf("Internal regs base: 0x%08x\n",
 328             bus_space_read_4(obio_tag, MV_INTREGS_BASE, 0));
 329
 330         for (i = 0; i < MV_WIN_DDR_MAX; i++)
 331                 printf("DDR CS#%d: b 0x%08x, s 0x%08x\n", i,
 332                     ddr_br_read(i), ddr_sz_read(i));
 333
 334         for (i = 0; i < MV_WIN_ETH_MAX; i++) {
 335                 printf("ETH window#%d: b 0x%08x, s 0x%08x", i,
 336                     win_eth_br_read(MV_ETH0_BASE, i),
 337                     win_eth_sz_read(MV_ETH0_BASE, i));
 338
 339                 if (win_eth_can_remap(i))
 340                         printf(", ha 0x%08x",
 341                             win_eth_har_read(MV_ETH0_BASE, i));
 342
 343                 printf("\n");
 344         }
 345         printf("ETH windows: bare 0x%08x, epap 0x%08x\n",
 346             win_eth_bare_read(MV_ETH0_BASE),
 347             win_eth_epap_read(MV_ETH0_BASE));
 348
 349         decode_win_idma_dump();
 350         decode_win_cesa_dump();
 351         decode_win_usb_dump();
 352         printf("\n");
 353 }
 354
 355 /**************************************************************************
 356  * CPU windows routines
 357  **************************************************************************/
 358 int
 359 win_cpu_can_remap(int i)
 360 {
 361         uint32_t dev, rev;
 362
 363         soc_id(&dev, &rev);
 364
 365         /* Depending on the SoC certain windows have remap capability */
 366         if ((dev == MV_DEV_88F5182 && i < 2) ||
 367             (dev == MV_DEV_88F5281 && i < 4) ||
 368             (dev == MV_DEV_88F6281 && i < 4) ||
 369             (dev == MV_DEV_MV78100 && i < 8) ||
 370             (dev == MV_DEV_MV78100_Z0 && i < 8))
 371                 return (1);
 372
 373         return (0);
 374 }
 375
 376 /* XXX This should check for overlapping remap fields too.. */
 377 int
 378 decode_win_overlap(int win, int win_no, const struct decode_win *wintab)
 379 {
 380         const struct decode_win *tab;
 381         int i;
 382
 383         tab = wintab;
 384
 385         for (i = 0; i < win_no; i++, tab++) {
 386                 if (i == win)
 387                         /* Skip self */
 388                         continue;
 389
 390                 if ((tab->base + tab->size - 1) < (wintab + win)->base)
 391                         continue;
 392
 393                 else if (((wintab + win)->base + (wintab + win)->size - 1) <
 394                     tab->base)
 395                         continue;
 396                 else
 397                         return (i);
 398         }
 399
 400         return (-1);
 401 }
 402
 403 static int
 404 decode_win_cpu_valid(void)
 405 {
 406         int i, j, rv;
 407         uint32_t b, e, s;
 408
 409         if (cpu_wins_no > MV_WIN_CPU_MAX) {
 410                 printf("CPU windows: too many entries: %d\n", cpu_wins_no);
 411                 return (-1);
 412         }
 413
 414         rv = 1;
 415         for (i = 0; i < cpu_wins_no; i++) {
 416
 417                 if (cpu_wins[i].target == 0) {
 418                         printf("CPU window#%d: DDR target window is not "
 419                             "supposed to be reprogrammed!\n", i);
 420                         rv = 0;
 421                 }
 422
 423                 if (cpu_wins[i].remap >= 0 && win_cpu_can_remap(i) != 1) {
 424                         printf("CPU window#%d: not capable of remapping, but "
 425                             "val 0x%08x defined\n", i, cpu_wins[i].remap);
 426                         rv = 0;
 427                 }
 428
 429                 s = cpu_wins[i].size;
 430                 b = cpu_wins[i].base;
 431                 e = b + s - 1;
 432                 if (s > (0xFFFFFFFF - b + 1)) {
 433                         /*
 434                          * XXX this boundary check should account for 64bit
 435                          * and remapping..
 436                          */
 437                         printf("CPU window#%d: no space for size 0x%08x at "
 438                             "0x%08x\n", i, s, b);
 439                         rv = 0;
 440                         continue;
 441                 }
 442
 443                 j = decode_win_overlap(i, cpu_wins_no, &cpu_wins[0]);
 444                 if (j >= 0) {
 445                         printf("CPU window#%d: (0x%08x - 0x%08x) overlaps "
 446                             "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
 447                             cpu_wins[j].base,
 448                             cpu_wins[j].base + cpu_wins[j].size - 1);
 449                         rv = 0;
 450                 }
 451         }
 452
 453         return (rv);
 454 }
 455
 456 int
 457 decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
 458     int remap)
 459 {
 460         uint32_t br, cr;
 461         int win;
 462
 463         if (used_cpu_wins >= MV_WIN_CPU_MAX)
 464                 return (-1);
 465
 466         win = used_cpu_wins++;
 467
 468         br = base & 0xffff0000;
 469         win_cpu_br_write(win, br);
 470
 471         if (win_cpu_can_remap(win)) {
 472                 if (remap >= 0) {
 473                         win_cpu_remap_l_write(win, remap & 0xffff0000);
 474                         win_cpu_remap_h_write(win, 0);
 475                 } else {
 476                         /*
 477                          * Remap function is not used for a given window
 478                          * (capable of remapping) - set remap field with the
 479                          * same value as base.
 480                          */
 481                         win_cpu_remap_l_write(win, base & 0xffff0000);
 482                         win_cpu_remap_h_write(win, 0);
 483                 }
 484         }
 485
 486         cr = ((size - 1) & 0xffff0000) | (attr << 8) | (target << 4) | 1;
 487         win_cpu_cr_write(win, cr);
 488
 489         return (0);
 490 }
 491
 492 static void
 493 decode_win_cpu_setup(void)
 494 {
 495         int i;
 496
 497         used_cpu_wins = 0;
 498
 499         /* Disable all CPU windows */
 500         for (i = 0; i < MV_WIN_CPU_MAX; i++) {
 501                 win_cpu_cr_write(i, 0);
 502                 win_cpu_br_write(i, 0);
 503                 if (win_cpu_can_remap(i)) {
 504                         win_cpu_remap_l_write(i, 0);
 505                         win_cpu_remap_h_write(i, 0);
 506                 }
 507         }
 508
 509         for (i = 0; i < cpu_wins_no; i++)
 510                 if (cpu_wins[i].target > 0)
 511                         decode_win_cpu_set(cpu_wins[i].target,
 512                             cpu_wins[i].attr, cpu_wins[i].base,
 513                             cpu_wins[i].size, cpu_wins[i].remap);
 514
 515 }
 516
 517 /*
 518  * Check if we're able to cover all active DDR banks.
 519  */
 520 static int
 521 decode_win_can_cover_ddr(int max)
 522 {
 523         int i, c;
 524
 525         c = 0;
 526         for (i = 0; i < MV_WIN_DDR_MAX; i++)
 527                 if (ddr_is_active(i))
 528                         c++;
 529
 530         if (c > max) {
 531                 printf("Unable to cover all active DDR banks: "
 532                     "%d, available windows: %d\n", c, max);
 533                 return (0);
 534         }
 535
 536         return (1);
 537 }
 538
 539 /**************************************************************************
 540  * DDR windows routines
 541  **************************************************************************/
 542 int
 543 ddr_is_active(int i)
 544 {
 545
 546         if (ddr_sz_read(i) & 0x1)
 547                 return (1);
 548
 549         return (0);
 550 }
 551
 552 uint32_t
 553 ddr_base(int i)
 554 {
 555
 556         return (ddr_br_read(i) & 0xff000000);
 557 }
 558
 559 uint32_t
 560 ddr_size(int i)
 561 {
 562
 563         return ((ddr_sz_read(i) | 0x00ffffff) + 1);
 564 }
 565
 566 uint32_t
 567 ddr_attr(int i)
 568 {
 569
 570         return (i == 0 ? 0xe :
 571             (i == 1 ? 0xd :
 572             (i == 2 ? 0xb :
 573             (i == 3 ? 0x7 : 0xff))));
 574 }
 575
 576 uint32_t
 577 ddr_target(int i)
 578 {
 579
 580         /* Mbus unit ID is 0x0 for DDR SDRAM controller */
 581         return (0);
 582 }
 583
 584 /**************************************************************************
 585  * USB windows routines
 586  **************************************************************************/
 587 static int
 588 decode_win_usb_valid(void)
 589 {
 590
 591         return (decode_win_can_cover_ddr(MV_WIN_USB_MAX));
 592 }
 593
 594 static __inline int
 595 usb_max_ports(void)
 596 {
 597         uint32_t dev, rev;
 598
 599         soc_id(&dev, &rev);
 600         return ((dev == MV_DEV_MV78100 || dev == MV_DEV_MV78100_Z0) ? 3 : 1);
 601 }
 602
 603 static void
 604 decode_win_usb_dump(void)
 605 {
 606         int i, p, m;
 607
 608         m = usb_max_ports();
 609         for (p = 0; p < m; p++)
 610                 for (i = 0; i < MV_WIN_USB_MAX; i++)
 611                         printf("USB window#%d: c 0x%08x, b 0x%08x\n", i,
 612                             win_usb_cr_read(i, p), win_usb_br_read(i, p));
 613 }
 614
 615 /*
 616  * Set USB decode windows.
 617  */
 618 static void
 619 decode_win_usb_setup(void)
 620 {
 621         uint32_t br, cr;
 622         int i, j, p, m;
 623
 624         /* Disable and clear all USB windows for all ports */
 625         m = usb_max_ports();
 626         for (p = 0; p < m; p++) {
 627
 628                 for (i = 0; i < MV_WIN_USB_MAX; i++) {
 629                         win_usb_cr_write(i, p, 0);
 630                         win_usb_br_write(i, p, 0);
 631                 }
 632
 633                 /* Only access to active DRAM banks is required */
 634                 for (i = 0; i < MV_WIN_DDR_MAX; i++) {
 635                         if (ddr_is_active(i)) {
 636                                 br = ddr_base(i);
 637                                 /*
 638                                  * XXX for 6281 we should handle Mbus write
 639                                  * burst limit field in the ctrl reg
 640                                  */
 641                                 cr = (((ddr_size(i) - 1) & 0xffff0000) |
 642                                     (ddr_attr(i) << 8) |
 643                                     (ddr_target(i) << 4) | 1);
 644
 645                                 /* Set the first free USB window */
 646                                 for (j = 0; j < MV_WIN_USB_MAX; j++) {
 647                                         if (win_usb_cr_read(j, p) & 0x1)
 648                                                 continue;
 649
 650                                         win_usb_br_write(j, p, br);
 651                                         win_usb_cr_write(j, p, cr);
 652                                         break;
 653                                 }
 654                         }
 655                 }
 656         }
 657 }
 658
 659 /**************************************************************************
 660  * ETH windows routines
 661  **************************************************************************/
 662
 663 static int
 664 win_eth_can_remap(int i)
 665 {
 666
 667         /* ETH encode windows 0-3 have remap capability */
 668         if (i < 4)
 669                 return (1);
 670
 671         return (0);
 672 }
 673
 674 static int
 675 eth_bare_read(uint32_t base, int i)
 676 {
 677         uint32_t v;
 678
 679         v = win_eth_bare_read(base);
 680         v &= (1 << i);
 681
 682         return (v >> i);
 683 }
 684
 685 static void
 686 eth_bare_write(uint32_t base, int i, int val)
 687 {
 688         uint32_t v;
 689
 690         v = win_eth_bare_read(base);
 691         v &= ~(1 << i);
 692         v |= (val << i);
 693         win_eth_bare_write(base, v);
 694 }
 695
 696 static void
 697 eth_epap_write(uint32_t base, int i, int val)
 698 {
 699         uint32_t v;
 700
 701         v = win_eth_epap_read(base);
 702         v &= ~(0x3 << (i * 2));
 703         v |= (val << (i * 2));
 704         win_eth_epap_write(base, v);
 705 }
 706
 707 static void
 708 decode_win_eth_setup(uint32_t base)
 709 {
 710         uint32_t br, sz;
 711         int i, j;
 712
 713         /* Disable, clear and revoke protection for all ETH windows */
 714         for (i = 0; i < MV_WIN_ETH_MAX; i++) {
 715
 716                 eth_bare_write(base, i, 1);
 717                 eth_epap_write(base, i, 0);
 718                 win_eth_br_write(base, i, 0);
 719                 win_eth_sz_write(base, i, 0);
 720                 if (win_eth_can_remap(i))
 721                         win_eth_har_write(base, i, 0);
 722         }
 723
 724         /* Only access to active DRAM banks is required */
 725         for (i = 0; i < MV_WIN_DDR_MAX; i++)
 726                 if (ddr_is_active(i)) {
 727
 728                         br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
 729                         sz = ((ddr_size(i) - 1) & 0xffff0000);
 730
 731                         /* Set the first free ETH window */
 732                         for (j = 0; j < MV_WIN_ETH_MAX; j++) {
 733                                 if (eth_bare_read(base, j) == 0)
 734                                         continue;
 735
 736                                 win_eth_br_write(base, j, br);
 737                                 win_eth_sz_write(base, j, sz);
 738
 739                                 /* XXX remapping ETH windows not supported */
 740
 741                                 /* Set protection RW */
 742                                 eth_epap_write(base, j, 0x3);
 743
 744                                 /* Enable window */
 745                                 eth_bare_write(base, j, 0);
 746                                 break;
 747                         }
 748                 }
 749 }
 750
 751 static int
 752 decode_win_eth_valid(void)
 753 {
 754
 755         return (decode_win_can_cover_ddr(MV_WIN_ETH_MAX));
 756 }
 757
 758 /**************************************************************************
 759  * PCIE windows routines
 760  **************************************************************************/
 761
 762 static void
 763 decode_win_pcie_setup(uint32_t base)
 764 {
 765         uint32_t size = 0;
 766         uint32_t cr, br;
 767         int i, j;
 768
 769         for (i = 0; i < MV_PCIE_BAR_MAX; i++)
 770                 pcie_bar_write(base, i, 0);
 771
 772         for (i = 0; i < MV_WIN_PCIE_MAX; i++) {
 773                 win_pcie_cr_write(base, i, 0);
 774                 win_pcie_br_write(base, i, 0);
 775                 win_pcie_remap_write(base, i, 0);
 776         }
 777
 778         for (i = 0; i < MV_WIN_DDR_MAX; i++) {
 779                 if (ddr_is_active(i)) {
 780                         /* Map DDR to BAR 1 */
 781                         cr = (ddr_size(i) - 1) & 0xffff0000;
 782                         size += ddr_size(i) & 0xffff0000;
 783                         cr |= (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
 784                         br = ddr_base(i);
 785
 786                         /* Use the first available PCIE window */
 787                         for (j = 0; j < MV_WIN_PCIE_MAX; j++) {
 788                                 if (win_pcie_cr_read(base, j) != 0)
 789                                         continue;
 790
 791                                 win_pcie_br_write(base, j, br);
 792                                 win_pcie_cr_write(base, j, cr);
 793                                 break;
 794                         }
 795                 }
 796         }
 797
 798         /*
 799          * Upper 16 bits in BAR register is interpreted as BAR size
 800          * (in 64 kB units) plus 64kB, so substract 0x10000
 801          * form value passed to register to get correct value.
 802          */
 803         size -= 0x10000;
 804         pcie_bar_write(base, 0, size | 1);
 805 }
 806
 807 static int
 808 decode_win_pcie_valid(void)
 809 {
 810
 811         return (decode_win_can_cover_ddr(MV_WIN_PCIE_MAX));
 812 }
 813
 814 /**************************************************************************
 815  * IDMA windows routines
 816  **************************************************************************/
 817 #if defined(SOC_MV_ORION) || defined(SOC_MV_DISCOVERY)
 818 static int
 819 idma_bare_read(int i)
 820 {
 821         uint32_t v;
 822
 823         v = win_idma_bare_read();
 824         v &= (1 << i);
 825
 826         return (v >> i);
 827 }
 828
 829 static void
 830 idma_bare_write(int i, int val)
 831 {
 832         uint32_t v;
 833
 834         v = win_idma_bare_read();
 835         v &= ~(1 << i);
 836         v |= (val << i);
 837         win_idma_bare_write(v);
 838 }
 839
 840 /*
 841  * Sets channel protection 'val' for window 'w' on channel 'c'
 842  */
 843 static void
 844 idma_cap_write(int c, int w, int val)
 845 {
 846         uint32_t v;
 847
 848         v = win_idma_cap_read(c);
 849         v &= ~(0x3 << (w * 2));
 850         v |= (val << (w * 2));
 851         win_idma_cap_write(c, v);
 852 }
 853
 854 /*
 855  * Set protection 'val' on all channels for window 'w'
 856  */
 857 static void
 858 idma_set_prot(int w, int val)
 859 {
 860         int c;
 861
 862         for (c = 0; c < MV_IDMA_CHAN_MAX; c++)
 863                 idma_cap_write(c, w, val);
 864 }
 865
 866 static int
 867 win_idma_can_remap(int i)
 868 {
 869
 870         /* IDMA decode windows 0-3 have remap capability */
 871         if (i < 4)
 872                 return (1);
 873
 874         return (0);
 875 }
 876
 877 void
 878 decode_win_idma_setup(void)
 879 {
 880         uint32_t br, sz;
 881         int i, j;
 882
 883         /*
 884          * Disable and clear all IDMA windows, revoke protection for all channels
 885          */
 886         for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
 887
 888                 idma_bare_write(i, 1);
 889                 win_idma_br_write(i, 0);
 890                 win_idma_sz_write(i, 0);
 891                 if (win_idma_can_remap(i) == 1)
 892                         win_idma_har_write(i, 0);
 893         }
 894         for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
 895                 win_idma_cap_write(i, 0);
 896
 897         /*
 898          * Set up access to all active DRAM banks
 899          */
 900         for (i = 0; i < MV_WIN_DDR_MAX; i++)
 901                 if (ddr_is_active(i)) {
 902                         br = ddr_base(i) | (ddr_attr(i) << 8) | ddr_target(i);
 903                         sz = ((ddr_size(i) - 1) & 0xffff0000);
 904
 905                         /* Place DDR entries in non-remapped windows */
 906                         for (j = 0; j < MV_WIN_IDMA_MAX; j++)
 907                                 if (win_idma_can_remap(j) != 1 &&
 908                                     idma_bare_read(j) == 1) {
 909
 910                                         /* Configure window */
 911                                         win_idma_br_write(j, br);
 912                                         win_idma_sz_write(j, sz);
 913
 914                                         /* Set protection RW on all channels */
 915                                         idma_set_prot(j, 0x3);
 916
 917                                         /* Enable window */
 918                                         idma_bare_write(j, 0);
 919                                         break;
 920                                 }
 921                 }
 922
 923         /*
 924          * Remaining targets -- from statically defined table
 925          */
 926         for (i = 0; i < idma_wins_no; i++)
 927                 if (idma_wins[i].target > 0) {
 928                         br = (idma_wins[i].base & 0xffff0000) |
 929                             (idma_wins[i].attr << 8) | idma_wins[i].target;
 930                         sz = ((idma_wins[i].size - 1) & 0xffff0000);
 931
 932                         /* Set the first free IDMA window */
 933                         for (j = 0; j < MV_WIN_IDMA_MAX; j++) {
 934                                 if (idma_bare_read(j) == 0)
 935                                         continue;
 936
 937                                 /* Configure window */
 938                                 win_idma_br_write(j, br);
 939                                 win_idma_sz_write(j, sz);
 940                                 if (win_idma_can_remap(j) &&
 941                                     idma_wins[j].remap >= 0)
 942                                         win_idma_har_write(j, idma_wins[j].remap);
 943
 944                                 /* Set protection RW on all channels */
 945                                 idma_set_prot(j, 0x3);
 946
 947                                 /* Enable window */
 948                                 idma_bare_write(j, 0);
 949                                 break;
 950                         }
 951                 }
 952 }
 953
 954 int
 955 decode_win_idma_valid(void)
 956 {
 957         const struct decode_win *wintab;
 958         int c, i, j, rv;
 959         uint32_t b, e, s;
 960
 961         if (idma_wins_no > MV_WIN_IDMA_MAX) {
 962                 printf("IDMA windows: too many entries: %d\n", idma_wins_no);
 963                 return (-1);
 964         }
 965         for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
 966                 if (ddr_is_active(i))
 967                         c++;
 968
 969         if (idma_wins_no > (MV_WIN_IDMA_MAX - c)) {
 970                 printf("IDMA windows: too many entries: %d, available: %d\n",
 971                     idma_wins_no, MV_WIN_IDMA_MAX - c);
 972                 return (-1);
 973         }
 974
 975         wintab = idma_wins;
 976         rv = 1;
 977         for (i = 0; i < idma_wins_no; i++, wintab++) {
 978
 979                 if (wintab->target == 0) {
 980                         printf("IDMA window#%d: DDR target window is not "
 981                             "supposed to be reprogrammed!\n", i);
 982                         rv = 0;
 983                 }
 984
 985                 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
 986                         printf("IDMA window#%d: not capable of remapping, but "
 987                             "val 0x%08x defined\n", i, wintab->remap);
 988                         rv = 0;
 989                 }
 990
 991                 s = wintab->size;
 992                 b = wintab->base;
 993                 e = b + s - 1;
 994                 if (s > (0xFFFFFFFF - b + 1)) {
 995                         /* XXX this boundary check should account for 64bit and
 996                          * remapping.. */
 997                         printf("IDMA window#%d: no space for size 0x%08x at "
 998                             "0x%08x\n", i, s, b);
 999                         rv = 0;
1000                         continue;
1001                 }
1002
1003                 j = decode_win_overlap(i, idma_wins_no, &idma_wins[0]);
1004                 if (j >= 0) {
1005                         printf("IDMA window#%d: (0x%08x - 0x%08x) overlaps "
1006                             "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1007                             idma_wins[j].base,
1008                             idma_wins[j].base + idma_wins[j].size - 1);
1009                         rv = 0;
1010                 }
1011         }
1012
1013         return (rv);
1014 }
1015
1016 void
1017 decode_win_idma_dump(void)
1018 {
1019         int i;
1020
1021         for (i = 0; i < MV_WIN_IDMA_MAX; i++) {
1022                 printf("IDMA window#%d: b 0x%08x, s 0x%08x", i,
1023                     win_idma_br_read(i), win_idma_sz_read(i));
1024
1025                 if (win_idma_can_remap(i))
1026                         printf(", ha 0x%08x", win_idma_har_read(i));
1027
1028                 printf("\n");
1029         }
1030         for (i = 0; i < MV_IDMA_CHAN_MAX; i++)
1031                 printf("IDMA channel#%d: ap 0x%08x\n", i,
1032                     win_idma_cap_read(i));
1033         printf("IDMA windows: bare 0x%08x\n", win_idma_bare_read());
1034 }
1035 #else
1036
1037 /* Provide dummy functions to satisfy the build for SoCs not equipped with IDMA */
1038 int
1039 decode_win_idma_valid(void)
1040 {
1041
1042         return (1);
1043 }
1044
1045 void
1046 decode_win_idma_setup(void)
1047 {
1048 }
1049
1050 void
1051 decode_win_idma_dump(void)
1052 {
1053 }
1054 #endif
1055
1056 /**************************************************************************
1057  * XOR windows routines
1058  **************************************************************************/
1059 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
1060 static int
1061 xor_ctrl_read(int i, int c, int e)
1062 {
1063         uint32_t v;
1064         v = win_xor_ctrl_read(c, e);
1065         v &= (1 << i);
1066
1067         return (v >> i);
1068 }
1069
1070 static void
1071 xor_ctrl_write(int i, int c, int e, int val)
1072 {
1073         uint32_t v;
1074
1075         v = win_xor_ctrl_read(c, e);
1076         v &= ~(1 << i);
1077         v |= (val << i);
1078         win_xor_ctrl_write(c, e, v);
1079 }
1080
1081 /*
1082  * Set channel protection 'val' for window 'w' on channel 'c'
1083  */
1084
1085 static void
1086 xor_chan_write(int c, int e, int w, int val)
1087 {
1088         uint32_t v;
1089
1090         v = win_xor_ctrl_read(c, e);
1091         v &= ~(0x3 << (w * 2 + 16));
1092         v |= (val << (w * 2 + 16));
1093         win_xor_ctrl_write(c, e, v);
1094 }
1095
1096 /*
1097  * Set protection 'val' on all channels for window 'w' on engine 'e'
1098  */
1099 static void
1100 xor_set_prot(int w, int e, int val)
1101 {
1102         int c;
1103
1104         for (c = 0; c < MV_XOR_CHAN_MAX; c++)
1105                 xor_chan_write(c, e, w, val);
1106 }
1107
1108 static int
1109 win_xor_can_remap(int i)
1110 {
1111
1112         /* XOR decode windows 0-3 have remap capability */
1113         if (i < 4)
1114                 return (1);
1115
1116         return (0);
1117 }
1118
1119 static int
1120 xor_max_eng(void)
1121 {
1122         uint32_t dev, rev;
1123
1124         soc_id(&dev, &rev);
1125         if (dev == MV_DEV_88F6281)
1126                 return (2);
1127         else if ((dev == MV_DEV_MV78100) || (dev == MV_DEV_MV78100_Z0))
1128                 return (1);
1129         else
1130                 return (0);
1131 }
1132
1133 static void
1134 xor_active_dram(int c, int e, int *window)
1135 {
1136         uint32_t br, sz;
1137         int i, m, w;
1138
1139         /*
1140          * Set up access to all active DRAM banks
1141          */
1142         m = xor_max_eng();
1143         for (i = 0; i < m; i++)
1144                 if (ddr_is_active(i)) {
1145                         br = ddr_base(i) | (ddr_attr(i) << 8) |
1146                             ddr_target(i);
1147                         sz = ((ddr_size(i) - 1) & 0xffff0000);
1148
1149                         /* Place DDR entries in non-remapped windows */
1150                         for (w = 0; w < MV_WIN_XOR_MAX; w++)
1151                                 if (win_xor_can_remap(w) != 1 &&
1152                                     (xor_ctrl_read(w, c, e) == 0) &&
1153                                     w > *window) {
1154                                         /* Configure window */
1155                                         win_xor_br_write(w, e, br);
1156                                         win_xor_sz_write(w, e, sz);
1157
1158                                         /* Set protection RW on all channels */
1159                                         xor_set_prot(w, e, 0x3);
1160
1161                                         /* Enable window */
1162                                         xor_ctrl_write(w, c, e, 1);
1163                                         (*window)++;
1164                                         break;
1165                                 }
1166                 }
1167 }
1168
1169 void
1170 decode_win_xor_setup(void)
1171 {
1172         uint32_t br, sz;
1173         int i, j, z, e = 1, m, window;
1174
1175         /*
1176          * Disable and clear all XOR windows, revoke protection for all
1177          * channels
1178          */
1179         m = xor_max_eng();
1180         for (j = 0; j < m; j++, e--) {
1181
1182                 /* Number of non-remaped windows */
1183                 window = MV_XOR_NON_REMAP - 1;
1184
1185                 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1186                         win_xor_br_write(i, e, 0);
1187                         win_xor_sz_write(i, e, 0);
1188                 }
1189
1190                 if (win_xor_can_remap(i) == 1)
1191                         win_xor_har_write(i, e, 0);
1192
1193                 for (i = 0; i < MV_XOR_CHAN_MAX; i++) {
1194                         win_xor_ctrl_write(i, e, 0);
1195                         xor_active_dram(i, e, &window);
1196                 }
1197
1198                 /*
1199                  * Remaining targets -- from a statically defined table
1200                  */
1201                 for (i = 0; i < xor_wins_no; i++)
1202                         if (xor_wins[i].target > 0) {
1203                                 br = (xor_wins[i].base & 0xffff0000) |
1204                                     (xor_wins[i].attr << 8) |
1205                                     xor_wins[i].target;
1206                                 sz = ((xor_wins[i].size - 1) & 0xffff0000);
1207
1208                                 /* Set the first free XOR window */
1209                                 for (z = 0; z < MV_WIN_XOR_MAX; z++) {
1210                                         if (xor_ctrl_read(z, 0, e) &&
1211                                             xor_ctrl_read(z, 1, e))
1212                                                 continue;
1213
1214                                         /* Configure window */
1215                                         win_xor_br_write(z, e, br);
1216                                         win_xor_sz_write(z, e, sz);
1217                                         if (win_xor_can_remap(z) &&
1218                                             xor_wins[z].remap >= 0)
1219                                                 win_xor_har_write(z, e,
1220                                                     xor_wins[z].remap);
1221
1222                                         /* Set protection RW on all channels */
1223                                         xor_set_prot(z, e, 0x3);
1224
1225                                         /* Enable window */
1226                                         xor_ctrl_write(z, 0, e, 1);
1227                                         xor_ctrl_write(z, 1, e, 1);
1228                                         break;
1229                                 }
1230                         }
1231         }
1232 }
1233
1234 int
1235 decode_win_xor_valid(void)
1236 {
1237         const struct decode_win *wintab;
1238         int c, i, j, rv;
1239         uint32_t b, e, s;
1240
1241         if (xor_wins_no > MV_WIN_XOR_MAX) {
1242                 printf("XOR windows: too many entries: %d\n", xor_wins_no);
1243                 return (-1);
1244         }
1245         for (i = 0, c = 0; i < MV_WIN_DDR_MAX; i++)
1246                 if (ddr_is_active(i))
1247                         c++;
1248
1249         if (xor_wins_no > (MV_WIN_XOR_MAX - c)) {
1250                 printf("XOR windows: too many entries: %d, available: %d\n",
1251                     xor_wins_no, MV_WIN_IDMA_MAX - c);
1252                 return (-1);
1253         }
1254
1255         wintab = xor_wins;
1256         rv = 1;
1257         for (i = 0; i < xor_wins_no; i++, wintab++) {
1258
1259                 if (wintab->target == 0) {
1260                         printf("XOR window#%d: DDR target window is not "
1261                             "supposed to be reprogrammed!\n", i);
1262                         rv = 0;
1263                 }
1264
1265                 if (wintab->remap >= 0 && win_cpu_can_remap(i) != 1) {
1266                         printf("XOR window#%d: not capable of remapping, but "
1267                             "val 0x%08x defined\n", i, wintab->remap);
1268                         rv = 0;
1269                 }
1270
1271                 s = wintab->size;
1272                 b = wintab->base;
1273                 e = b + s - 1;
1274                 if (s > (0xFFFFFFFF - b + 1)) {
1275                         /*
1276                          * XXX this boundary check should account for 64bit
1277                          * and remapping..
1278                          */
1279                         printf("XOR window#%d: no space for size 0x%08x at "
1280                             "0x%08x\n", i, s, b);
1281                         rv = 0;
1282                         continue;
1283                 }
1284
1285                 j = decode_win_overlap(i, xor_wins_no, &xor_wins[0]);
1286                 if (j >= 0) {
1287                         printf("XOR window#%d: (0x%08x - 0x%08x) overlaps "
1288                             "with #%d (0x%08x - 0x%08x)\n", i, b, e, j,
1289                             xor_wins[j].base,
1290                             xor_wins[j].base + xor_wins[j].size - 1);
1291                         rv = 0;
1292                 }
1293         }
1294
1295         return (rv);
1296 }
1297
1298 void
1299 decode_win_xor_dump(void)
1300 {
1301         int i, j;
1302         int e = 1;
1303
1304         for (j = 0; j < xor_max_eng(); j++, e--) {
1305                 for (i = 0; i < MV_WIN_XOR_MAX; i++) {
1306                         printf("XOR window#%d: b 0x%08x, s 0x%08x", i,
1307                             win_xor_br_read(i, e), win_xor_sz_read(i, e));
1308
1309                         if (win_xor_can_remap(i))
1310                                 printf(", ha 0x%08x", win_xor_har_read(i, e));
1311
1312                         printf("\n");
1313                 }
1314                 for (i = 0; i < MV_XOR_CHAN_MAX; i++)
1315                         printf("XOR control#%d: 0x%08x\n", i,
1316                             win_xor_ctrl_read(i, e));
1317         }
1318 }
1319
1320 #else
1321 /* Provide dummy functions to satisfy the build for SoCs not equipped with XOR */
1322 int
1323 decode_win_xor_valid(void)
1324 {
1325
1326         return (1);
1327 }
1328
1329 void
1330 decode_win_xor_setup(void)
1331 {
1332 }
1333
1334 void
1335 decode_win_xor_dump(void)
1336 {
1337 }
1338 #endif
1339
1340 /**************************************************************************
1341  * CESA TDMA windows routines
1342  **************************************************************************/
1343 #if defined(SOC_MV_KIRKWOOD) || defined(SOC_MV_DISCOVERY)
1344 /*
1345  * Dump CESA TDMA decode windows.
1346  */
1347 static void
1348 decode_win_cesa_dump(void)
1349 {
1350         int i;
1351
1352         for (i = 0; i < MV_WIN_CESA_MAX; i++)
1353                 printf("CESA window#%d: c 0x%08x, b 0x%08x\n", i,
1354                     win_cesa_cr_read(i), win_cesa_br_read(i));
1355 }
1356
1357
1358 /*
1359  * Set CESA TDMA decode windows.
1360  */
1361 static void
1362 decode_win_cesa_setup(void)
1363 {
1364         uint32_t br, cr;
1365         int i, j;
1366
1367         /* Disable and clear all CESA windows */
1368         for (i = 0; i < MV_WIN_CESA_MAX; i++) {
1369                 win_cesa_cr_write(i, 0);
1370                 win_cesa_br_write(i, 0);
1371         }
1372
1373         /* Only access to active DRAM banks is required. */
1374         for (i = 0; i < MV_WIN_DDR_MAX; i++)
1375                 if (ddr_is_active(i)) {
1376                         br = ddr_base(i);
1377                         cr = (((ddr_size(i) - 1) & 0xffff0000) |
1378                            (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1);
1379
1380                         /* Set the first available CESA window */
1381                         for (j = 0; j < MV_WIN_CESA_MAX; j++) {
1382                                 if (win_cesa_cr_read(j) & 0x1)
1383                                         continue;
1384
1385                                 win_cesa_br_write(j, br);
1386                                 win_cesa_cr_write(j, cr);
1387                                 break;
1388                         }
1389                 }
1390 }
1391
1392 /*
1393  * Check CESA TDMA decode windows.
1394  */
1395 static int
1396 decode_win_cesa_valid(void)
1397 {
1398
1399         return (decode_win_can_cover_ddr(MV_WIN_CESA_MAX));
1400 }
1401 #else
1402
1403 /*
1404  * Provide dummy functions to satisfy the build for SoCs not equipped with
1405  * CESA
1406  */
1407
1408 int
1409 decode_win_cesa_valid(void)
1410 {
1411
1412         return (1);
1413 }
1414
1415 void
1416 decode_win_cesa_setup(void)
1417 {
1418 }
1419
1420 void
1421 decode_win_cesa_dump(void)
1422 {
1423 }
1424 #endif
1425
1426 /**************************************************************************
1427  * SATA windows routines
1428  **************************************************************************/
1429 static void
1430 decode_win_sata_setup(void)
1431 {
1432         uint32_t cr, br;
1433         int i, j;
1434
1435         for (i = 0; i < MV_WIN_SATA_MAX; i++) {
1436                 win_sata_cr_write(i, 0);
1437                 win_sata_br_write(i, 0);
1438         }
1439
1440         for (i = 0; i < MV_WIN_DDR_MAX; i++)
1441                 if (ddr_is_active(i)) {
1442                         cr = ((ddr_size(i) - 1) & 0xffff0000) |
1443                             (ddr_attr(i) << 8) | (ddr_target(i) << 4) | 1;
1444                         br = ddr_base(i);
1445
1446                         /* Use the first available SATA window */
1447                         for (j = 0; j < MV_WIN_SATA_MAX; j++) {
1448                                 if ((win_sata_cr_read(j) & 1) != 0)
1449                                         continue;
1450
1451                                 win_sata_br_write(j, br);
1452                                 win_sata_cr_write(j, cr);
1453                                 break;
1454                         }
1455                 }
1456 }
1457
1458 static int
1459 decode_win_sata_valid(void)
1460 {
1461         uint32_t dev, rev;
1462
1463         soc_id(&dev, &rev);
1464         if (dev == MV_DEV_88F5281)
1465                 return (1);
1466
1467         return (decode_win_can_cover_ddr(MV_WIN_SATA_MAX));
1468 }