2 * Copyright (c) 2006 Benno Rice.
3 * Copyright (C) 2008 MARVELL INTERNATIONAL LTD.
6 * Adapted and extended for Marvell SoCs by Semihalf.
8 * Redistribution and use in source and binary forms, with or without
9 * modification, are permitted provided that the following conditions
11 * 1. Redistributions of source code must retain the above copyright
12 * notice, this list of conditions and the following disclaimer.
13 * 2. Redistributions in binary form must reproduce the above copyright
14 * notice, this list of conditions and the following disclaimer in the
15 * documentation and/or other materials provided with the distribution.
17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
28 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0_gpio.c, rev 1
31 #include <sys/cdefs.h>
32 __FBSDID("$FreeBSD$");
34 #include <sys/param.h>
35 #include <sys/systm.h>
37 #include <sys/kernel.h>
39 #include <sys/interrupt.h>
40 #include <sys/module.h>
41 #include <sys/malloc.h>
42 #include <sys/mutex.h>
44 #include <sys/queue.h>
45 #include <sys/timetc.h>
46 #include <machine/bus.h>
47 #include <machine/intr.h>
49 #include <arm/mv/mvvar.h>
50 #include <arm/mv/mvreg.h>
52 #define GPIO_MAX_INTR_COUNT 8
53 #define GPIO_PINS_PER_REG 32
55 struct mv_gpio_softc {
56 struct resource * res[GPIO_MAX_INTR_COUNT + 1];
57 void *ih_cookie[GPIO_MAX_INTR_COUNT];
59 bus_space_handle_t bsh;
60 uint8_t pin_num; /* number of GPIO pins */
61 uint8_t irq_num; /* number of real IRQs occupied by GPIO controller */
65 extern struct resource_spec mv_gpio_res[];
67 static struct mv_gpio_softc *mv_gpio_softc = NULL;
68 static uint32_t gpio_setup[MV_GPIO_MAX_NPINS];
70 static int mv_gpio_probe(device_t);
71 static int mv_gpio_attach(device_t);
72 static void mv_gpio_intr(void *);
74 static void mv_gpio_intr_handler(int pin);
75 static uint32_t mv_gpio_reg_read(uint32_t reg);
76 static void mv_gpio_reg_write(uint32_t reg, uint32_t val);
77 static void mv_gpio_reg_set(uint32_t reg, uint32_t val);
78 static void mv_gpio_reg_clear(uint32_t reg, uint32_t val);
80 static void mv_gpio_blink(uint32_t pin, uint8_t enable);
81 static void mv_gpio_polarity(uint32_t pin, uint8_t enable);
82 static void mv_gpio_level(uint32_t pin, uint8_t enable);
83 static void mv_gpio_edge(uint32_t pin, uint8_t enable);
84 static void mv_gpio_out_en(uint32_t pin, uint8_t enable);
85 static void mv_gpio_int_ack(uint32_t pin);
86 static void mv_gpio_value_set(uint32_t pin, uint8_t val);
87 static uint32_t mv_gpio_value_get(uint32_t pin);
89 static device_method_t mv_gpio_methods[] = {
90 DEVMETHOD(device_probe, mv_gpio_probe),
91 DEVMETHOD(device_attach, mv_gpio_attach),
95 static driver_t mv_gpio_driver = {
98 sizeof(struct mv_gpio_softc),
101 static devclass_t mv_gpio_devclass;
103 DRIVER_MODULE(gpio, mbus, mv_gpio_driver, mv_gpio_devclass, 0, 0);
106 mv_gpio_probe(device_t dev)
109 device_set_desc(dev, "Marvell Integrated GPIO Controller");
114 mv_gpio_attach(device_t dev)
117 struct mv_gpio_softc *sc;
118 uint32_t dev_id, rev_id;
120 sc = (struct mv_gpio_softc *)device_get_softc(dev);
122 if (mv_gpio_softc != NULL)
126 /* Get chip id and revision */
127 soc_id(&dev_id, &rev_id);
129 if (dev_id == MV_DEV_88F5182 ||
130 dev_id == MV_DEV_88F5281 ||
131 dev_id == MV_DEV_MV78100 ||
132 dev_id == MV_DEV_MV78100_Z0 ) {
137 } else if (dev_id == MV_DEV_88F6281) {
143 device_printf(dev, "unknown chip id=0x%x\n", dev_id);
147 error = bus_alloc_resources(dev, mv_gpio_res, sc->res);
149 device_printf(dev, "could not allocate resources\n");
153 sc->bst = rman_get_bustag(sc->res[0]);
154 sc->bsh = rman_get_bushandle(sc->res[0]);
156 /* Disable and clear all interrupts */
157 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_EDGE_MASK, 0);
158 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_LEV_MASK, 0);
159 bus_space_write_4(sc->bst, sc->bsh, GPIO_INT_CAUSE, 0);
162 bus_space_write_4(sc->bst, sc->bsh,
163 GPIO_HI_INT_EDGE_MASK, 0);
164 bus_space_write_4(sc->bst, sc->bsh,
165 GPIO_HI_INT_LEV_MASK, 0);
166 bus_space_write_4(sc->bst, sc->bsh,
167 GPIO_HI_INT_CAUSE, 0);
170 for (i = 0; i < sc->irq_num; i++) {
171 if (bus_setup_intr(dev, sc->res[1 + i],
172 INTR_TYPE_MISC | INTR_FAST,
173 (driver_filter_t *)mv_gpio_intr, NULL,
174 sc, &sc->ih_cookie[i]) != 0) {
175 bus_release_resources(dev, mv_gpio_res, sc->res);
176 device_printf(dev, "could not set up intr %d\n", i);
181 /* Setup GPIO lines */
182 for (i = 0; mv_gpio_config[i].gc_gpio >= 0; i++) {
183 mv_gpio_configure(mv_gpio_config[i].gc_gpio,
184 mv_gpio_config[i].gc_flags, ~0u);
186 if (mv_gpio_config[i].gc_output < 0)
187 mv_gpio_out_en(mv_gpio_config[i].gc_gpio, 0);
189 mv_gpio_out(mv_gpio_config[i].gc_gpio,
190 mv_gpio_config[i].gc_output, 1);
197 mv_gpio_intr(void *arg)
199 uint32_t int_cause, gpio_val;
200 uint32_t int_cause_hi, gpio_val_hi = 0;
203 int_cause = mv_gpio_reg_read(GPIO_INT_CAUSE);
204 gpio_val = mv_gpio_reg_read(GPIO_DATA_IN);
205 gpio_val &= int_cause;
206 if (mv_gpio_softc->use_high) {
207 int_cause_hi = mv_gpio_reg_read(GPIO_HI_INT_CAUSE);
208 gpio_val_hi = mv_gpio_reg_read(GPIO_HI_DATA_IN);
209 gpio_val_hi &= int_cause_hi;
213 while (gpio_val != 0) {
215 mv_gpio_intr_handler(i);
220 if (mv_gpio_softc->use_high) {
222 while (gpio_val_hi != 0) {
224 mv_gpio_intr_handler(i + GPIO_PINS_PER_REG);
232 * GPIO interrupt handling
235 static struct intr_event *gpio_events[MV_GPIO_MAX_NPINS];
238 mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
239 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep)
241 struct intr_event *event;
244 if (pin < 0 || pin >= mv_gpio_softc->pin_num)
246 event = gpio_events[pin];
248 error = intr_event_create(&event, (void *)pin, 0, pin,
249 (void (*)(void *))mv_gpio_intr_mask,
250 (void (*)(void *))mv_gpio_intr_unmask,
251 (void (*)(void *))mv_gpio_int_ack,
256 gpio_events[pin] = event;
259 intr_event_add_handler(event, name, filt, hand, arg,
260 intr_priority(flags), flags, cookiep);
265 mv_gpio_intr_mask(int pin)
268 if (pin >= mv_gpio_softc->pin_num)
271 if (gpio_setup[pin] & MV_GPIO_EDGE)
272 mv_gpio_edge(pin, 0);
274 mv_gpio_level(pin, 0);
278 mv_gpio_intr_unmask(int pin)
281 if (pin >= mv_gpio_softc->pin_num)
284 if (gpio_setup[pin] & MV_GPIO_EDGE)
285 mv_gpio_edge(pin, 1);
287 mv_gpio_level(pin, 1);
291 mv_gpio_intr_handler(int pin)
293 struct intr_event *event;
295 event = gpio_events[pin];
296 if (event == NULL || TAILQ_EMPTY(&event->ie_handlers))
299 intr_event_handle(event, NULL);
303 mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask)
306 if (pin >= mv_gpio_softc->pin_num)
309 if (mask & MV_GPIO_BLINK)
310 mv_gpio_blink(pin, flags & MV_GPIO_BLINK);
311 if (mask & MV_GPIO_POLAR_LOW)
312 mv_gpio_polarity(pin, flags & MV_GPIO_POLAR_LOW);
313 if (mask & MV_GPIO_EDGE)
314 mv_gpio_edge(pin, flags & MV_GPIO_EDGE);
315 if (mask & MV_GPIO_LEVEL)
316 mv_gpio_level(pin, flags & MV_GPIO_LEVEL);
318 gpio_setup[pin] &= ~(mask);
319 gpio_setup[pin] |= (flags & mask);
325 mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable)
328 mv_gpio_value_set(pin, val);
329 mv_gpio_out_en(pin, enable);
333 mv_gpio_in(uint32_t pin)
336 return (mv_gpio_value_get(pin));
340 mv_gpio_reg_read(uint32_t reg)
343 return (bus_space_read_4(mv_gpio_softc->bst,
344 mv_gpio_softc->bsh, reg));
348 mv_gpio_reg_write(uint32_t reg, uint32_t val)
351 bus_space_write_4(mv_gpio_softc->bst,
352 mv_gpio_softc->bsh, reg, val);
356 mv_gpio_reg_set(uint32_t reg, uint32_t pin)
360 reg_val = mv_gpio_reg_read(reg);
361 reg_val |= GPIO(pin);
362 mv_gpio_reg_write(reg, reg_val);
366 mv_gpio_reg_clear(uint32_t reg, uint32_t pin)
370 reg_val = mv_gpio_reg_read(reg);
371 reg_val &= ~(GPIO(pin));
372 mv_gpio_reg_write(reg, reg_val);
376 mv_gpio_out_en(uint32_t pin, uint8_t enable)
380 if (pin >= mv_gpio_softc->pin_num)
383 if (pin >= GPIO_PINS_PER_REG) {
384 reg = GPIO_HI_DATA_OUT_EN_CTRL;
385 pin -= GPIO_PINS_PER_REG;
387 reg = GPIO_DATA_OUT_EN_CTRL;
390 mv_gpio_reg_clear(reg, pin);
392 mv_gpio_reg_set(reg, pin);
396 mv_gpio_blink(uint32_t pin, uint8_t enable)
400 if (pin >= mv_gpio_softc->pin_num)
403 if (pin >= GPIO_PINS_PER_REG) {
404 reg = GPIO_HI_BLINK_EN;
405 pin -= GPIO_PINS_PER_REG;
410 mv_gpio_reg_set(reg, pin);
412 mv_gpio_reg_clear(reg, pin);
416 mv_gpio_polarity(uint32_t pin, uint8_t enable)
420 if (pin >= mv_gpio_softc->pin_num)
423 if (pin >= GPIO_PINS_PER_REG) {
424 reg = GPIO_HI_DATA_IN_POLAR;
425 pin -= GPIO_PINS_PER_REG;
427 reg = GPIO_DATA_IN_POLAR;
430 mv_gpio_reg_set(reg, pin);
432 mv_gpio_reg_clear(reg, pin);
436 mv_gpio_level(uint32_t pin, uint8_t enable)
440 if (pin >= mv_gpio_softc->pin_num)
443 if (pin >= GPIO_PINS_PER_REG) {
444 reg = GPIO_HI_INT_LEV_MASK;
445 pin -= GPIO_PINS_PER_REG;
447 reg = GPIO_INT_LEV_MASK;
450 mv_gpio_reg_set(reg, pin);
452 mv_gpio_reg_clear(reg, pin);
456 mv_gpio_edge(uint32_t pin, uint8_t enable)
460 if (pin >= mv_gpio_softc->pin_num)
463 if (pin >= GPIO_PINS_PER_REG) {
464 reg = GPIO_HI_INT_EDGE_MASK;
465 pin -= GPIO_PINS_PER_REG;
467 reg = GPIO_INT_EDGE_MASK;
470 mv_gpio_reg_set(reg, pin);
472 mv_gpio_reg_clear(reg, pin);
476 mv_gpio_int_ack(uint32_t pin)
480 if (pin >= mv_gpio_softc->pin_num)
483 if (pin >= GPIO_PINS_PER_REG) {
484 reg = GPIO_HI_INT_CAUSE;
485 pin -= GPIO_PINS_PER_REG;
487 reg = GPIO_INT_CAUSE;
489 mv_gpio_reg_clear(reg, pin);
493 mv_gpio_value_get(uint32_t pin)
495 uint32_t reg, reg_val;
497 if (pin >= mv_gpio_softc->pin_num)
500 if (pin >= GPIO_PINS_PER_REG) {
501 reg = GPIO_HI_DATA_IN;
502 pin -= GPIO_PINS_PER_REG;
506 reg_val = mv_gpio_reg_read(reg);
508 return (reg_val & GPIO(pin));
512 mv_gpio_value_set(uint32_t pin, uint8_t val)
516 if (pin >= mv_gpio_softc->pin_num)
519 if (pin >= GPIO_PINS_PER_REG) {
520 reg = GPIO_HI_DATA_OUT;
521 pin -= GPIO_PINS_PER_REG;
526 mv_gpio_reg_set(reg, pin);
528 mv_gpio_reg_clear(reg, pin);