2 * Copyright (c) 2002, 2003 Wasabi Systems, Inc.
5 * Written by Jason R. Thorpe for Wasabi Systems, Inc.
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
10 * 1. Redistributions of source code must retain the above copyright
11 * notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 * notice, this list of conditions and the following disclaimer in the
14 * documentation and/or other materials provided with the distribution.
15 * 3. All advertising materials mentioning features or use of this software
16 * must display the following acknowledgement:
17 * This product includes software developed for the NetBSD Project by
18 * Wasabi Systems, Inc.
19 * 4. The name of Wasabi Systems, Inc. may not be used to endorse
20 * or promote products derived from this software without specific prior
23 * THIS SOFTWARE IS PROVIDED BY WASABI SYSTEMS, INC. ``AS IS'' AND
24 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL WASABI SYSTEMS, INC
27 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33 * POSSIBILITY OF SUCH DAMAGE.
35 * from: FreeBSD: //depot/projects/arm/src/sys/arm/xscale/pxa2x0/pxa2x0var.h, rev 1
46 #define MV_TYPE_PCIE 1
47 #define MV_TYPE_PCIE_AGGR_LANE 2 /* Additional PCIE lane to aggregate */
50 bus_space_tag_t obio_bst; /* bus space tag */
53 struct rman obio_gpio;
60 u_int od_irqs[7 + 1]; /* keep additional entry for -1 sentinel */
61 u_int od_gpio[2 + 1]; /* as above for IRQ */
63 struct resource_list od_resources;
66 struct obio_pci_irq_map {
78 /* Note IO/MEM regions are assumed VA == PA */
79 bus_addr_t op_io_base;
84 bus_addr_t op_mem_base;
86 int op_mem_win_target;
89 const struct obio_pci_irq_map *op_pci_irq_map;
90 int op_irq; /* used if IRQ map table is NULL */
94 int gc_gpio; /* GPIO number */
95 uint32_t gc_flags; /* GPIO flags */
96 int gc_output; /* GPIO output value */
100 int target; /* Mbus unit ID */
101 int attr; /* Attributes of the target interface */
102 vm_paddr_t base; /* Physical base addr */
107 extern const struct obio_pci mv_pci_info[];
108 extern const struct gpio_config mv_gpio_config[];
109 extern bus_space_tag_t obio_tag;
110 extern struct obio_device obio_devices[];
111 extern const struct decode_win *cpu_wins;
112 extern const struct decode_win *idma_wins;
113 extern const struct decode_win *xor_wins;
114 extern int cpu_wins_no;
115 extern int idma_wins_no;
116 extern int xor_wins_no;
118 /* Function prototypes */
119 int mv_gpio_setup_intrhandler(const char *name, driver_filter_t *filt,
120 void (*hand)(void *), void *arg, int pin, int flags, void **cookiep);
121 void mv_gpio_intr_mask(int pin);
122 void mv_gpio_intr_unmask(int pin);
123 int mv_gpio_configure(uint32_t pin, uint32_t flags, uint32_t mask);
124 void mv_gpio_out(uint32_t pin, uint8_t val, uint8_t enable);
125 uint8_t mv_gpio_in(uint32_t pin);
127 int platform_pmap_init(void);
128 void platform_mpp_init(void);
129 int soc_decode_win(void);
130 void soc_id(uint32_t *dev, uint32_t *rev);
131 void soc_identify(void);
132 void soc_dump_decode_win(void);
133 uint32_t soc_power_ctrl_get(uint32_t mask);
135 int decode_win_cpu_set(int target, int attr, vm_paddr_t base, uint32_t size,
137 int decode_win_overlap(int, int, const struct decode_win *);
138 int win_cpu_can_remap(int);
140 void decode_win_idma_dump(void);
141 void decode_win_idma_setup(void);
142 int decode_win_idma_valid(void);
144 void decode_win_xor_dump(void);
145 void decode_win_xor_setup(void);
146 int decode_win_xor_valid(void);
148 int ddr_is_active(int i);
149 uint32_t ddr_base(int i);
150 uint32_t ddr_size(int i);
151 uint32_t ddr_attr(int i);
152 uint32_t ddr_target(int i);
154 uint32_t cpu_extra_feat(void);
155 uint32_t get_tclk(void);
156 uint32_t read_cpu_ctrl(uint32_t);
157 void write_cpu_ctrl(uint32_t, uint32_t);
159 enum mbus_device_ivars {
163 #define MBUS_ACCESSOR(var, ivar, type) \
164 __BUS_ACCESSOR(mbus, var, MBUS, ivar, type)
166 MBUS_ACCESSOR(base, BASE, u_long)
170 #endif /* _MVVAR_H_ */