2 /*******************************************************************************
4 * Module Name: hwregs - Read/write access functions for the various ACPI
5 * control and status registers.
7 ******************************************************************************/
9 /******************************************************************************
13 * Some or all of this work - Copyright (c) 1999 - 2009, Intel Corp.
14 * All rights reserved.
18 * 2.1. This is your license from Intel Corp. under its intellectual property
19 * rights. You may have additional license terms from the party that provided
20 * you this software, covering your right to use that party's intellectual
23 * 2.2. Intel grants, free of charge, to any person ("Licensee") obtaining a
24 * copy of the source code appearing in this file ("Covered Code") an
25 * irrevocable, perpetual, worldwide license under Intel's copyrights in the
26 * base code distributed originally by Intel ("Original Intel Code") to copy,
27 * make derivatives, distribute, use and display any portion of the Covered
28 * Code in any form, with the right to sublicense such rights; and
30 * 2.3. Intel grants Licensee a non-exclusive and non-transferable patent
31 * license (with the right to sublicense), under only those claims of Intel
32 * patents that are infringed by the Original Intel Code, to make, use, sell,
33 * offer to sell, and import the Covered Code and derivative works thereof
34 * solely to the minimum extent necessary to exercise the above copyright
35 * license, and in no event shall the patent license extend to any additions
36 * to or modifications of the Original Intel Code. No other license or right
37 * is granted directly or by implication, estoppel or otherwise;
39 * The above copyright and patent license is granted only if the following
44 * 3.1. Redistribution of Source with Rights to Further Distribute Source.
45 * Redistribution of source code of any substantial portion of the Covered
46 * Code or modification with rights to further distribute source must include
47 * the above Copyright Notice, the above License, this list of Conditions,
48 * and the following Disclaimer and Export Compliance provision. In addition,
49 * Licensee must cause all Covered Code to which Licensee contributes to
50 * contain a file documenting the changes Licensee made to create that Covered
51 * Code and the date of any change. Licensee must include in that file the
52 * documentation of any changes made by any predecessor Licensee. Licensee
53 * must include a prominent statement that the modification is derived,
54 * directly or indirectly, from Original Intel Code.
56 * 3.2. Redistribution of Source with no Rights to Further Distribute Source.
57 * Redistribution of source code of any substantial portion of the Covered
58 * Code or modification without rights to further distribute source must
59 * include the following Disclaimer and Export Compliance provision in the
60 * documentation and/or other materials provided with distribution. In
61 * addition, Licensee may not authorize further sublicense of source of any
62 * portion of the Covered Code, and must include terms to the effect that the
63 * license from Licensee to its licensee is limited to the intellectual
64 * property embodied in the software Licensee provides to its licensee, and
65 * not to intellectual property embodied in modifications its licensee may
68 * 3.3. Redistribution of Executable. Redistribution in executable form of any
69 * substantial portion of the Covered Code or modification must reproduce the
70 * above Copyright Notice, and the following Disclaimer and Export Compliance
71 * provision in the documentation and/or other materials provided with the
74 * 3.4. Intel retains all right, title, and interest in and to the Original
77 * 3.5. Neither the name Intel nor any other trademark owned or controlled by
78 * Intel shall be used in advertising or otherwise to promote the sale, use or
79 * other dealings in products derived from or relating to the Covered Code
80 * without prior written authorization from Intel.
82 * 4. Disclaimer and Export Compliance
84 * 4.1. INTEL MAKES NO WARRANTY OF ANY KIND REGARDING ANY SOFTWARE PROVIDED
85 * HERE. ANY SOFTWARE ORIGINATING FROM INTEL OR DERIVED FROM INTEL SOFTWARE
86 * IS PROVIDED "AS IS," AND INTEL WILL NOT PROVIDE ANY SUPPORT, ASSISTANCE,
87 * INSTALLATION, TRAINING OR OTHER SERVICES. INTEL WILL NOT PROVIDE ANY
88 * UPDATES, ENHANCEMENTS OR EXTENSIONS. INTEL SPECIFICALLY DISCLAIMS ANY
89 * IMPLIED WARRANTIES OF MERCHANTABILITY, NONINFRINGEMENT AND FITNESS FOR A
92 * 4.2. IN NO EVENT SHALL INTEL HAVE ANY LIABILITY TO LICENSEE, ITS LICENSEES
93 * OR ANY OTHER THIRD PARTY, FOR ANY LOST PROFITS, LOST DATA, LOSS OF USE OR
94 * COSTS OF PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES, OR FOR ANY INDIRECT,
95 * SPECIAL OR CONSEQUENTIAL DAMAGES ARISING OUT OF THIS AGREEMENT, UNDER ANY
96 * CAUSE OF ACTION OR THEORY OF LIABILITY, AND IRRESPECTIVE OF WHETHER INTEL
97 * HAS ADVANCE NOTICE OF THE POSSIBILITY OF SUCH DAMAGES. THESE LIMITATIONS
98 * SHALL APPLY NOTWITHSTANDING THE FAILURE OF THE ESSENTIAL PURPOSE OF ANY
101 * 4.3. Licensee shall not export, either directly or indirectly, any of this
102 * software or system incorporating such software without first obtaining any
103 * required license or other approval from the U. S. Department of Commerce or
104 * any other agency or department of the United States Government. In the
105 * event Licensee exports any such software from the United States or
106 * re-exports any such software from a foreign destination, Licensee shall
107 * ensure that the distribution and export/re-export of the software is in
108 * compliance with all laws, regulations, orders, or other restrictions of the
109 * U.S. Export Administration Regulations. Licensee agrees that neither it nor
110 * any of its subsidiaries will export/re-export any technical data, process,
111 * software, or service, directly or indirectly, to any country for which the
112 * United States government or any agency thereof requires an export license,
113 * other governmental approval, or letter of assurance, without first obtaining
114 * such license, approval or letter.
116 *****************************************************************************/
120 #include <contrib/dev/acpica/include/acpi.h>
121 #include <contrib/dev/acpica/include/accommon.h>
122 #include <contrib/dev/acpica/include/acevents.h>
124 #define _COMPONENT ACPI_HARDWARE
125 ACPI_MODULE_NAME ("hwregs")
128 /* Local Prototypes */
133 ACPI_GENERIC_ADDRESS *RegisterA,
134 ACPI_GENERIC_ADDRESS *RegisterB);
137 AcpiHwWriteMultiple (
139 ACPI_GENERIC_ADDRESS *RegisterA,
140 ACPI_GENERIC_ADDRESS *RegisterB);
143 /*******************************************************************************
145 * FUNCTION: AcpiHwClearAcpiStatus
151 * DESCRIPTION: Clears all fixed and general purpose status bits
153 ******************************************************************************/
156 AcpiHwClearAcpiStatus (
160 ACPI_CPU_FLAGS LockFlags = 0;
163 ACPI_FUNCTION_TRACE (HwClearAcpiStatus);
166 ACPI_DEBUG_PRINT ((ACPI_DB_IO, "About to write %04X to %8.8X%8.8X\n",
167 ACPI_BITMASK_ALL_FIXED_STATUS,
168 ACPI_FORMAT_UINT64 (AcpiGbl_XPm1aStatus.Address)));
170 LockFlags = AcpiOsAcquireLock (AcpiGbl_HardwareLock);
172 /* Clear the fixed events in PM1 A/B */
174 Status = AcpiHwRegisterWrite (ACPI_REGISTER_PM1_STATUS,
175 ACPI_BITMASK_ALL_FIXED_STATUS);
176 if (ACPI_FAILURE (Status))
181 /* Clear the GPE Bits in all GPE registers in all GPE blocks */
183 Status = AcpiEvWalkGpeList (AcpiHwClearGpeBlock, NULL);
186 AcpiOsReleaseLock (AcpiGbl_HardwareLock, LockFlags);
187 return_ACPI_STATUS (Status);
191 /*******************************************************************************
193 * FUNCTION: AcpiHwGetRegisterBitMask
195 * PARAMETERS: RegisterId - Index of ACPI Register to access
197 * RETURN: The bitmask to be used when accessing the register
199 * DESCRIPTION: Map RegisterId into a register bitmask.
201 ******************************************************************************/
203 ACPI_BIT_REGISTER_INFO *
204 AcpiHwGetBitRegisterInfo (
207 ACPI_FUNCTION_ENTRY ();
210 if (RegisterId > ACPI_BITREG_MAX)
212 ACPI_ERROR ((AE_INFO, "Invalid BitRegister ID: %X", RegisterId));
216 return (&AcpiGbl_BitRegisterInfo[RegisterId]);
220 /******************************************************************************
222 * FUNCTION: AcpiHwWritePm1Control
224 * PARAMETERS: Pm1aControl - Value to be written to PM1A control
225 * Pm1bControl - Value to be written to PM1B control
229 * DESCRIPTION: Write the PM1 A/B control registers. These registers are
230 * different than than the PM1 A/B status and enable registers
231 * in that different values can be written to the A/B registers.
232 * Most notably, the SLP_TYP bits can be different, as per the
233 * values returned from the _Sx predefined methods.
235 ******************************************************************************/
238 AcpiHwWritePm1Control (
245 ACPI_FUNCTION_TRACE (HwWritePm1Control);
248 Status = AcpiWrite (Pm1aControl, &AcpiGbl_FADT.XPm1aControlBlock);
249 if (ACPI_FAILURE (Status))
251 return_ACPI_STATUS (Status);
254 if (AcpiGbl_FADT.XPm1bControlBlock.Address)
256 Status = AcpiWrite (Pm1bControl, &AcpiGbl_FADT.XPm1bControlBlock);
258 return_ACPI_STATUS (Status);
262 /******************************************************************************
264 * FUNCTION: AcpiHwRegisterRead
266 * PARAMETERS: RegisterId - ACPI Register ID
267 * ReturnValue - Where the register value is returned
269 * RETURN: Status and the value read.
271 * DESCRIPTION: Read from the specified ACPI register
273 ******************************************************************************/
284 ACPI_FUNCTION_TRACE (HwRegisterRead);
289 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
291 Status = AcpiHwReadMultiple (&Value,
292 &AcpiGbl_XPm1aStatus,
293 &AcpiGbl_XPm1bStatus);
297 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
299 Status = AcpiHwReadMultiple (&Value,
300 &AcpiGbl_XPm1aEnable,
301 &AcpiGbl_XPm1bEnable);
305 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
307 Status = AcpiHwReadMultiple (&Value,
308 &AcpiGbl_FADT.XPm1aControlBlock,
309 &AcpiGbl_FADT.XPm1bControlBlock);
312 * Zero the write-only bits. From the ACPI specification, "Hardware
313 * Write-Only Bits": "Upon reads to registers with write-only bits,
314 * software masks out all write-only bits."
316 Value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
320 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
322 Status = AcpiRead (&Value, &AcpiGbl_FADT.XPm2ControlBlock);
326 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
328 Status = AcpiRead (&Value, &AcpiGbl_FADT.XPmTimerBlock);
332 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
334 Status = AcpiHwReadPort (AcpiGbl_FADT.SmiCommand, &Value, 8);
339 ACPI_ERROR ((AE_INFO, "Unknown Register ID: %X",
341 Status = AE_BAD_PARAMETER;
345 if (ACPI_SUCCESS (Status))
347 *ReturnValue = Value;
350 return_ACPI_STATUS (Status);
354 /******************************************************************************
356 * FUNCTION: AcpiHwRegisterWrite
358 * PARAMETERS: RegisterId - ACPI Register ID
359 * Value - The value to write
363 * DESCRIPTION: Write to the specified ACPI register
365 * NOTE: In accordance with the ACPI specification, this function automatically
366 * preserves the value of the following bits, meaning that these bits cannot be
367 * changed via this interface:
369 * PM1_CONTROL[0] = SCI_EN
374 * 1) Hardware Ignored Bits: When software writes to a register with ignored
375 * bit fields, it preserves the ignored bit fields
376 * 2) SCI_EN: OSPM always preserves this bit position
378 ******************************************************************************/
381 AcpiHwRegisterWrite (
389 ACPI_FUNCTION_TRACE (HwRegisterWrite);
394 case ACPI_REGISTER_PM1_STATUS: /* PM1 A/B: 16-bit access each */
396 * Handle the "ignored" bit in PM1 Status. According to the ACPI
397 * specification, ignored bits are to be preserved when writing.
398 * Normally, this would mean a read/modify/write sequence. However,
399 * preserving a bit in the status register is different. Writing a
400 * one clears the status, and writing a zero preserves the status.
401 * Therefore, we must always write zero to the ignored bit.
403 * This behavior is clarified in the ACPI 4.0 specification.
405 Value &= ~ACPI_PM1_STATUS_PRESERVED_BITS;
407 Status = AcpiHwWriteMultiple (Value,
408 &AcpiGbl_XPm1aStatus,
409 &AcpiGbl_XPm1bStatus);
413 case ACPI_REGISTER_PM1_ENABLE: /* PM1 A/B: 16-bit access each */
415 Status = AcpiHwWriteMultiple (Value,
416 &AcpiGbl_XPm1aEnable,
417 &AcpiGbl_XPm1bEnable);
421 case ACPI_REGISTER_PM1_CONTROL: /* PM1 A/B: 16-bit access each */
424 * Perform a read first to preserve certain bits (per ACPI spec)
425 * Note: This includes SCI_EN, we never want to change this bit
427 Status = AcpiHwReadMultiple (&ReadValue,
428 &AcpiGbl_FADT.XPm1aControlBlock,
429 &AcpiGbl_FADT.XPm1bControlBlock);
430 if (ACPI_FAILURE (Status))
435 /* Insert the bits to be preserved */
437 ACPI_INSERT_BITS (Value, ACPI_PM1_CONTROL_PRESERVED_BITS, ReadValue);
439 /* Now we can write the data */
441 Status = AcpiHwWriteMultiple (Value,
442 &AcpiGbl_FADT.XPm1aControlBlock,
443 &AcpiGbl_FADT.XPm1bControlBlock);
447 case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */
450 * For control registers, all reserved bits must be preserved,
451 * as per the ACPI spec.
453 Status = AcpiRead (&ReadValue, &AcpiGbl_FADT.XPm2ControlBlock);
454 if (ACPI_FAILURE (Status))
459 /* Insert the bits to be preserved */
461 ACPI_INSERT_BITS (Value, ACPI_PM2_CONTROL_PRESERVED_BITS, ReadValue);
463 Status = AcpiWrite (Value, &AcpiGbl_FADT.XPm2ControlBlock);
467 case ACPI_REGISTER_PM_TIMER: /* 32-bit access */
469 Status = AcpiWrite (Value, &AcpiGbl_FADT.XPmTimerBlock);
473 case ACPI_REGISTER_SMI_COMMAND_BLOCK: /* 8-bit access */
475 /* SMI_CMD is currently always in IO space */
477 Status = AcpiHwWritePort (AcpiGbl_FADT.SmiCommand, Value, 8);
482 ACPI_ERROR ((AE_INFO, "Unknown Register ID: %X",
484 Status = AE_BAD_PARAMETER;
489 return_ACPI_STATUS (Status);
493 /******************************************************************************
495 * FUNCTION: AcpiHwReadMultiple
497 * PARAMETERS: Value - Where the register value is returned
498 * RegisterA - First ACPI register (required)
499 * RegisterB - Second ACPI register (optional)
503 * DESCRIPTION: Read from the specified two-part ACPI register (such as PM1 A/B)
505 ******************************************************************************/
510 ACPI_GENERIC_ADDRESS *RegisterA,
511 ACPI_GENERIC_ADDRESS *RegisterB)
518 /* The first register is always required */
520 Status = AcpiRead (&ValueA, RegisterA);
521 if (ACPI_FAILURE (Status))
526 /* Second register is optional */
528 if (RegisterB->Address)
530 Status = AcpiRead (&ValueB, RegisterB);
531 if (ACPI_FAILURE (Status))
538 * OR the two return values together. No shifting or masking is necessary,
539 * because of how the PM1 registers are defined in the ACPI specification:
541 * "Although the bits can be split between the two register blocks (each
542 * register block has a unique pointer within the FADT), the bit positions
543 * are maintained. The register block with unimplemented bits (that is,
544 * those implemented in the other register block) always returns zeros,
545 * and writes have no side effects"
547 *Value = (ValueA | ValueB);
552 /******************************************************************************
554 * FUNCTION: AcpiHwWriteMultiple
556 * PARAMETERS: Value - The value to write
557 * RegisterA - First ACPI register (required)
558 * RegisterB - Second ACPI register (optional)
562 * DESCRIPTION: Write to the specified two-part ACPI register (such as PM1 A/B)
564 ******************************************************************************/
567 AcpiHwWriteMultiple (
569 ACPI_GENERIC_ADDRESS *RegisterA,
570 ACPI_GENERIC_ADDRESS *RegisterB)
575 /* The first register is always required */
577 Status = AcpiWrite (Value, RegisterA);
578 if (ACPI_FAILURE (Status))
584 * Second register is optional
586 * No bit shifting or clearing is necessary, because of how the PM1
587 * registers are defined in the ACPI specification:
589 * "Although the bits can be split between the two register blocks (each
590 * register block has a unique pointer within the FADT), the bit positions
591 * are maintained. The register block with unimplemented bits (that is,
592 * those implemented in the other register block) always returns zeros,
593 * and writes have no side effects"
595 if (RegisterB->Address)
597 Status = AcpiWrite (Value, RegisterB);