2 * Copyright (c) 2009 Alexander Motin <mav@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
30 #include <sys/param.h>
31 #include <sys/module.h>
32 #include <sys/systm.h>
33 #include <sys/kernel.h>
36 #include <sys/endian.h>
37 #include <sys/malloc.h>
39 #include <sys/mutex.h>
41 #include <sys/taskqueue.h>
43 #include <machine/stdarg.h>
44 #include <machine/resource.h>
45 #include <machine/bus.h>
47 #include <dev/pci/pcivar.h>
48 #include <dev/pci/pcireg.h>
52 #include <cam/cam_ccb.h>
53 #include <cam/cam_sim.h>
54 #include <cam/cam_xpt_sim.h>
55 #include <cam/cam_xpt_periph.h>
56 #include <cam/cam_debug.h>
58 /* local prototypes */
59 static int ahci_setup_interrupt(device_t dev);
60 static void ahci_intr(void *data);
61 static void ahci_intr_one(void *data);
62 static int ahci_suspend(device_t dev);
63 static int ahci_resume(device_t dev);
64 static int ahci_ch_suspend(device_t dev);
65 static int ahci_ch_resume(device_t dev);
66 static void ahci_ch_intr_locked(void *data);
67 static void ahci_ch_intr(void *data);
68 static int ahci_ctlr_reset(device_t dev);
69 static void ahci_begin_transaction(device_t dev, union ccb *ccb);
70 static void ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error);
71 static void ahci_execute_transaction(struct ahci_slot *slot);
72 static void ahci_timeout(struct ahci_slot *slot);
73 static void ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et);
74 static int ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag);
75 static void ahci_dmainit(device_t dev);
76 static void ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
77 static void ahci_dmafini(device_t dev);
78 static void ahci_slotsalloc(device_t dev);
79 static void ahci_slotsfree(device_t dev);
80 static void ahci_reset(device_t dev);
81 static void ahci_start(device_t dev);
82 static void ahci_stop(device_t dev);
83 static void ahci_clo(device_t dev);
84 static void ahci_start_fr(device_t dev);
85 static void ahci_stop_fr(device_t dev);
87 static int ahci_sata_connect(struct ahci_channel *ch);
88 static int ahci_sata_phy_reset(device_t dev, int quick);
90 static void ahci_issue_read_log(device_t dev);
91 static void ahci_process_read_log(device_t dev, union ccb *ccb);
93 static void ahciaction(struct cam_sim *sim, union ccb *ccb);
94 static void ahcipoll(struct cam_sim *sim);
96 MALLOC_DEFINE(M_AHCI, "AHCI driver", "AHCI driver data buffers");
99 * AHCI v1.x compliant SATA chipset support functions
102 ahci_probe(device_t dev)
105 /* is this a possible AHCI candidate ? */
106 if (pci_get_class(dev) != PCIC_STORAGE ||
107 pci_get_subclass(dev) != PCIS_STORAGE_SATA)
110 /* is this PCI device flagged as an AHCI compliant chip ? */
111 if (pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0)
114 device_set_desc_copy(dev, "AHCI controller");
115 return (BUS_PROBE_VENDOR);
119 ahci_attach(device_t dev)
121 struct ahci_controller *ctlr = device_get_softc(dev);
123 int error, unit, speed;
124 u_int32_t version, caps;
127 /* if we have a memory BAR(5) we are likely on an AHCI part */
128 ctlr->r_rid = PCIR_BAR(5);
129 if (!(ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
130 &ctlr->r_rid, RF_ACTIVE)))
132 /* Setup our own memory management for channels. */
133 ctlr->sc_iomem.rm_type = RMAN_ARRAY;
134 ctlr->sc_iomem.rm_descr = "I/O memory addresses";
135 if ((error = rman_init(&ctlr->sc_iomem)) != 0) {
136 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
139 if ((error = rman_manage_region(&ctlr->sc_iomem,
140 rman_get_start(ctlr->r_mem), rman_get_end(ctlr->r_mem))) != 0) {
141 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
142 rman_fini(&ctlr->sc_iomem);
145 /* Reset controller */
146 if ((error = ahci_ctlr_reset(dev)) != 0) {
147 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
148 rman_fini(&ctlr->sc_iomem);
151 /* Get the number of HW channels */
152 ctlr->ichannels = ATA_INL(ctlr->r_mem, AHCI_PI);
153 ctlr->channels = MAX(flsl(ctlr->ichannels),
154 (ATA_INL(ctlr->r_mem, AHCI_CAP) & AHCI_CAP_NPMASK) + 1);
155 /* Setup interrupts. */
156 if (ahci_setup_interrupt(dev)) {
157 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
158 rman_fini(&ctlr->sc_iomem);
161 /* Announce HW capabilities. */
162 version = ATA_INL(ctlr->r_mem, AHCI_VS);
163 caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
164 speed = (caps & AHCI_CAP_ISS) >> AHCI_CAP_ISS_SHIFT;
166 "AHCI v%x.%02x with %d %sGbps ports, Port Multiplier %s\n",
167 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
168 ((version >> 4) & 0xf0) + (version & 0x0f),
169 (caps & AHCI_CAP_NPMASK) + 1,
170 ((speed == 1) ? "1.5":((speed == 2) ? "3":
171 ((speed == 3) ? "6":"?"))),
172 (caps & AHCI_CAP_SPM) ?
173 "supported" : "not supported");
175 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
176 (caps & AHCI_CAP_64BIT) ? " 64bit":"",
177 (caps & AHCI_CAP_SNCQ) ? " NCQ":"",
178 (caps & AHCI_CAP_SSNTF) ? " SNTF":"",
179 (caps & AHCI_CAP_SMPS) ? " MPS":"",
180 (caps & AHCI_CAP_SSS) ? " SS":"",
181 (caps & AHCI_CAP_SALP) ? " ALP":"",
182 (caps & AHCI_CAP_SAL) ? " AL":"",
183 (caps & AHCI_CAP_SCLO) ? " CLO":"",
184 ((speed == 1) ? "1.5":((speed == 2) ? "3":
185 ((speed == 3) ? "6":"?"))));
186 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
187 (caps & AHCI_CAP_SAM) ? " AM":"",
188 (caps & AHCI_CAP_SPM) ? " PM":"",
189 (caps & AHCI_CAP_FBSS) ? " FBS":"",
190 (caps & AHCI_CAP_PMD) ? " PMD":"",
191 (caps & AHCI_CAP_SSC) ? " SSC":"",
192 (caps & AHCI_CAP_PSC) ? " PSC":"",
193 ((caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
194 (caps & AHCI_CAP_CCCS) ? " CCC":"",
195 (caps & AHCI_CAP_EMS) ? " EM":"",
196 (caps & AHCI_CAP_SXS) ? " eSATA":"",
197 (caps & AHCI_CAP_NPMASK) + 1);
199 /* Attach all channels on this controller */
200 for (unit = 0; unit < ctlr->channels; unit++) {
201 if ((ctlr->ichannels & (1 << unit)) == 0)
203 child = device_add_child(dev, "ahcich", -1);
205 device_printf(dev, "failed to add channel device\n");
207 device_set_ivars(child, (void *)(intptr_t)unit);
209 bus_generic_attach(dev);
214 ahci_detach(device_t dev)
216 struct ahci_controller *ctlr = device_get_softc(dev);
220 /* Detach & delete all children */
221 if (!device_get_children(dev, &children, &nchildren)) {
222 for (i = 0; i < nchildren; i++)
223 device_delete_child(dev, children[i]);
224 free(children, M_TEMP);
226 /* Free interrupts. */
227 for (i = 0; i < ctlr->numirqs; i++) {
228 if (ctlr->irqs[i].r_irq) {
229 bus_teardown_intr(dev, ctlr->irqs[i].r_irq,
230 ctlr->irqs[i].handle);
231 bus_release_resource(dev, SYS_RES_IRQ,
232 ctlr->irqs[i].r_irq_rid, ctlr->irqs[i].r_irq);
235 pci_release_msi(dev);
237 rman_fini(&ctlr->sc_iomem);
239 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, ctlr->r_mem);
244 ahci_ctlr_reset(device_t dev)
246 struct ahci_controller *ctlr = device_get_softc(dev);
249 if (pci_read_config(dev, 0x00, 4) == 0x28298086 &&
250 (pci_read_config(dev, 0x92, 1) & 0xfe) == 0x04)
251 pci_write_config(dev, 0x92, 0x01, 1);
252 /* Enable AHCI mode */
253 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
254 /* Reset AHCI controller */
255 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE|AHCI_GHC_HR);
256 for (timeout = 1000; timeout > 0; timeout--) {
258 if ((ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_HR) == 0)
262 device_printf(dev, "AHCI controller reset failure\n");
265 /* Reenable AHCI mode */
266 ATA_OUTL(ctlr->r_mem, AHCI_GHC, AHCI_GHC_AE);
267 /* Clear interrupts */
268 ATA_OUTL(ctlr->r_mem, AHCI_IS, ATA_INL(ctlr->r_mem, AHCI_IS));
269 /* Enable AHCI interrupts */
270 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
271 ATA_INL(ctlr->r_mem, AHCI_GHC) | AHCI_GHC_IE);
276 ahci_suspend(device_t dev)
278 struct ahci_controller *ctlr = device_get_softc(dev);
280 bus_generic_suspend(dev);
281 /* Disable interupts, so the state change(s) doesn't trigger */
282 ATA_OUTL(ctlr->r_mem, AHCI_GHC,
283 ATA_INL(ctlr->r_mem, AHCI_GHC) & (~AHCI_GHC_IE));
288 ahci_resume(device_t dev)
292 if ((res = ahci_ctlr_reset(dev)) != 0)
294 return (bus_generic_resume(dev));
298 ahci_setup_interrupt(device_t dev)
300 struct ahci_controller *ctlr = device_get_softc(dev);
304 resource_int_value(device_get_name(dev),
305 device_get_unit(dev), "msi", &msi);
309 msi = min(1, pci_msi_count(dev));
311 msi = pci_msi_count(dev);
312 /* Allocate MSI if needed/present. */
313 if (msi && pci_alloc_msi(dev, &msi) == 0) {
319 /* Check for single MSI vector fallback. */
320 if (ctlr->numirqs > 1 &&
321 (ATA_INL(ctlr->r_mem, AHCI_GHC) & AHCI_GHC_MRSM) != 0) {
322 device_printf(dev, "Falling back to one MSI\n");
325 /* Allocate all IRQs. */
326 for (i = 0; i < ctlr->numirqs; i++) {
327 ctlr->irqs[i].ctlr = ctlr;
328 ctlr->irqs[i].r_irq_rid = i + (msi ? 1 : 0);
329 if (ctlr->numirqs == 1 || i >= ctlr->channels)
330 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ALL;
331 else if (i == ctlr->numirqs - 1)
332 ctlr->irqs[i].mode = AHCI_IRQ_MODE_AFTER;
334 ctlr->irqs[i].mode = AHCI_IRQ_MODE_ONE;
335 if (!(ctlr->irqs[i].r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
336 &ctlr->irqs[i].r_irq_rid, RF_SHAREABLE | RF_ACTIVE))) {
337 device_printf(dev, "unable to map interrupt\n");
340 if ((bus_setup_intr(dev, ctlr->irqs[i].r_irq, ATA_INTR_FLAGS, NULL,
341 (ctlr->irqs[i].mode == AHCI_IRQ_MODE_ONE) ? ahci_intr_one : ahci_intr,
342 &ctlr->irqs[i], &ctlr->irqs[i].handle))) {
343 /* SOS XXX release r_irq */
344 device_printf(dev, "unable to setup interrupt\n");
352 * Common case interrupt handler.
355 ahci_intr(void *data)
357 struct ahci_controller_irq *irq = data;
358 struct ahci_controller *ctlr = irq->ctlr;
363 is = ATA_INL(ctlr->r_mem, AHCI_IS);
364 if (irq->mode == AHCI_IRQ_MODE_ALL)
366 else /* AHCI_IRQ_MODE_AFTER */
367 unit = irq->r_irq_rid - 1;
368 for (; unit < ctlr->channels; unit++) {
369 if ((is & (1 << unit)) != 0 &&
370 (arg = ctlr->interrupt[unit].argument)) {
371 ctlr->interrupt[unit].function(arg);
372 ATA_OUTL(ctlr->r_mem, AHCI_IS, 1 << unit);
378 * Simplified interrupt handler for multivector MSI mode.
381 ahci_intr_one(void *data)
383 struct ahci_controller_irq *irq = data;
384 struct ahci_controller *ctlr = irq->ctlr;
388 unit = irq->r_irq_rid - 1;
389 if ((arg = ctlr->interrupt[unit].argument))
390 ctlr->interrupt[unit].function(arg);
393 static struct resource *
394 ahci_alloc_resource(device_t dev, device_t child, int type, int *rid,
395 u_long start, u_long end, u_long count, u_int flags)
397 struct ahci_controller *ctlr = device_get_softc(dev);
398 int unit = ((struct ahci_channel *)device_get_softc(child))->unit;
399 struct resource *res = NULL;
400 int offset = AHCI_OFFSET + (unit << 7);
405 st = rman_get_start(ctlr->r_mem);
406 res = rman_reserve_resource(&ctlr->sc_iomem, st + offset,
407 st + offset + 127, 128, RF_ACTIVE, child);
409 bus_space_handle_t bsh;
411 bsh = rman_get_bushandle(ctlr->r_mem);
412 bst = rman_get_bustag(ctlr->r_mem);
413 bus_space_subregion(bst, bsh, offset, 128, &bsh);
414 rman_set_bushandle(res, bsh);
415 rman_set_bustag(res, bst);
419 if (*rid == ATA_IRQ_RID)
420 res = ctlr->irqs[0].r_irq;
427 ahci_release_resource(device_t dev, device_t child, int type, int rid,
433 rman_release_resource(r);
436 if (rid != ATA_IRQ_RID)
444 ahci_setup_intr(device_t dev, device_t child, struct resource *irq,
445 int flags, driver_filter_t *filter, driver_intr_t *function,
446 void *argument, void **cookiep)
448 struct ahci_controller *ctlr = device_get_softc(dev);
449 int unit = (intptr_t)device_get_ivars(child);
451 if (filter != NULL) {
452 printf("ahci.c: we cannot use a filter here\n");
455 ctlr->interrupt[unit].function = function;
456 ctlr->interrupt[unit].argument = argument;
461 ahci_teardown_intr(device_t dev, device_t child, struct resource *irq,
464 struct ahci_controller *ctlr = device_get_softc(dev);
465 int unit = (intptr_t)device_get_ivars(child);
467 ctlr->interrupt[unit].function = NULL;
468 ctlr->interrupt[unit].argument = NULL;
473 ahci_print_child(device_t dev, device_t child)
477 retval = bus_print_child_header(dev, child);
478 retval += printf(" at channel %d",
479 (int)(intptr_t)device_get_ivars(child));
480 retval += bus_print_child_footer(dev, child);
485 devclass_t ahci_devclass;
486 static device_method_t ahci_methods[] = {
487 DEVMETHOD(device_probe, ahci_probe),
488 DEVMETHOD(device_attach, ahci_attach),
489 DEVMETHOD(device_detach, ahci_detach),
490 DEVMETHOD(device_suspend, ahci_suspend),
491 DEVMETHOD(device_resume, ahci_resume),
492 DEVMETHOD(bus_print_child, ahci_print_child),
493 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource),
494 DEVMETHOD(bus_release_resource, ahci_release_resource),
495 DEVMETHOD(bus_setup_intr, ahci_setup_intr),
496 DEVMETHOD(bus_teardown_intr,ahci_teardown_intr),
499 static driver_t ahci_driver = {
502 sizeof(struct ahci_controller)
504 DRIVER_MODULE(ahci, pci, ahci_driver, ahci_devclass, 0, 0);
505 MODULE_VERSION(ahci, 1);
506 MODULE_DEPEND(ahci, cam, 1, 1, 1);
509 ahci_ch_probe(device_t dev)
512 device_set_desc_copy(dev, "AHCI channel");
517 ahci_ch_attach(device_t dev)
519 struct ahci_controller *ctlr = device_get_softc(device_get_parent(dev));
520 struct ahci_channel *ch = device_get_softc(dev);
521 struct cam_devq *devq;
525 ch->unit = (intptr_t)device_get_ivars(dev);
526 ch->caps = ATA_INL(ctlr->r_mem, AHCI_CAP);
527 ch->numslots = ((ch->caps & AHCI_CAP_NCS) >> AHCI_CAP_NCS_SHIFT) + 1,
528 resource_int_value(device_get_name(dev),
529 device_get_unit(dev), "pm_level", &ch->pm_level);
530 /* Limit speed for my onboard JMicron external port.
531 * It is not eSATA really. */
532 if (pci_get_devid(ctlr->dev) == 0x2363197b &&
533 pci_get_subvendor(ctlr->dev) == 0x1043 &&
534 pci_get_subdevice(ctlr->dev) == 0x81e4 &&
537 resource_int_value(device_get_name(dev),
538 device_get_unit(dev), "sata_rev", &ch->sata_rev);
539 mtx_init(&ch->mtx, "AHCI channel lock", NULL, MTX_DEF);
541 if (!(ch->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY,
545 ahci_slotsalloc(dev);
549 if (!(ch->r_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ,
550 &rid, RF_SHAREABLE | RF_ACTIVE))) {
551 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
552 device_printf(dev, "Unable to map interrupt\n");
555 if ((bus_setup_intr(dev, ch->r_irq, ATA_INTR_FLAGS, NULL,
556 ahci_ch_intr_locked, dev, &ch->ih))) {
557 device_printf(dev, "Unable to setup interrupt\n");
561 /* Create the device queue for our SIM. */
562 devq = cam_simq_alloc(ch->numslots);
564 device_printf(dev, "Unable to allocate simq\n");
568 /* Construct SIM entry */
569 ch->sim = cam_sim_alloc(ahciaction, ahcipoll, "ahcich", ch,
570 device_get_unit(dev), &ch->mtx, ch->numslots, 0, devq);
571 if (ch->sim == NULL) {
572 device_printf(dev, "unable to allocate sim\n");
576 if (xpt_bus_register(ch->sim, dev, 0) != CAM_SUCCESS) {
577 device_printf(dev, "unable to register xpt bus\n");
581 if (xpt_create_path(&ch->path, /*periph*/NULL, cam_sim_path(ch->sim),
582 CAM_TARGET_WILDCARD, CAM_LUN_WILDCARD) != CAM_REQ_CMP) {
583 device_printf(dev, "unable to create path\n");
587 mtx_unlock(&ch->mtx);
591 xpt_bus_deregister(cam_sim_path(ch->sim));
593 cam_sim_free(ch->sim, /*free_devq*/TRUE);
595 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
596 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
597 mtx_unlock(&ch->mtx);
602 ahci_ch_detach(device_t dev)
604 struct ahci_channel *ch = device_get_softc(dev);
607 xpt_async(AC_LOST_DEVICE, ch->path, NULL);
608 xpt_free_path(ch->path);
609 xpt_bus_deregister(cam_sim_path(ch->sim));
610 cam_sim_free(ch->sim, /*free_devq*/TRUE);
611 mtx_unlock(&ch->mtx);
613 bus_teardown_intr(dev, ch->r_irq, ch->ih);
614 bus_release_resource(dev, SYS_RES_IRQ, ATA_IRQ_RID, ch->r_irq);
616 ahci_ch_suspend(dev);
620 bus_release_resource(dev, SYS_RES_MEMORY, ch->unit, ch->r_mem);
621 mtx_destroy(&ch->mtx);
626 ahci_ch_suspend(device_t dev)
628 struct ahci_channel *ch = device_get_softc(dev);
630 /* Disable port interrupts. */
631 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
632 /* Reset command register. */
635 ATA_OUTL(ch->r_mem, AHCI_P_CMD, 0);
636 /* Allow everything, including partial and slumber modes. */
637 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, 0);
638 /* Request slumber mode transition and give some time to get there. */
639 ATA_OUTL(ch->r_mem, AHCI_P_CMD, AHCI_P_CMD_SLUMBER);
642 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_DET_DISABLE);
647 ahci_ch_resume(device_t dev)
649 struct ahci_channel *ch = device_get_softc(dev);
652 /* Disable port interrupts */
653 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
654 /* Setup work areas */
655 work = ch->dma.work_bus + AHCI_CL_OFFSET;
656 ATA_OUTL(ch->r_mem, AHCI_P_CLB, work & 0xffffffff);
657 ATA_OUTL(ch->r_mem, AHCI_P_CLBU, work >> 32);
658 work = ch->dma.rfis_bus;
659 ATA_OUTL(ch->r_mem, AHCI_P_FB, work & 0xffffffff);
660 ATA_OUTL(ch->r_mem, AHCI_P_FBU, work >> 32);
661 /* Activate the channel and power/spin up device */
662 ATA_OUTL(ch->r_mem, AHCI_P_CMD,
663 (AHCI_P_CMD_ACTIVE | AHCI_P_CMD_POD | AHCI_P_CMD_SUD |
664 ((ch->pm_level > 1) ? AHCI_P_CMD_ALPE : 0) |
665 ((ch->pm_level > 2) ? AHCI_P_CMD_ASP : 0 )));
671 devclass_t ahcich_devclass;
672 static device_method_t ahcich_methods[] = {
673 DEVMETHOD(device_probe, ahci_ch_probe),
674 DEVMETHOD(device_attach, ahci_ch_attach),
675 DEVMETHOD(device_detach, ahci_ch_detach),
676 DEVMETHOD(device_suspend, ahci_ch_suspend),
677 DEVMETHOD(device_resume, ahci_ch_resume),
680 static driver_t ahcich_driver = {
683 sizeof(struct ahci_channel)
685 DRIVER_MODULE(ahcich, ahci, ahcich_driver, ahci_devclass, 0, 0);
687 struct ahci_dc_cb_args {
693 ahci_dmainit(device_t dev)
695 struct ahci_channel *ch = device_get_softc(dev);
696 struct ahci_dc_cb_args dcba;
698 if (ch->caps & AHCI_CAP_64BIT)
699 ch->dma.max_address = BUS_SPACE_MAXADDR;
701 ch->dma.max_address = BUS_SPACE_MAXADDR_32BIT;
703 if (bus_dma_tag_create(bus_get_dma_tag(dev), 1024, 0,
704 ch->dma.max_address, BUS_SPACE_MAXADDR,
705 NULL, NULL, AHCI_WORK_SIZE, 1, AHCI_WORK_SIZE,
706 0, NULL, NULL, &ch->dma.work_tag))
708 if (bus_dmamem_alloc(ch->dma.work_tag, (void **)&ch->dma.work, 0,
711 if (bus_dmamap_load(ch->dma.work_tag, ch->dma.work_map, ch->dma.work,
712 AHCI_WORK_SIZE, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
713 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
716 ch->dma.work_bus = dcba.maddr;
717 /* FIS receive area. */
718 if (bus_dma_tag_create(bus_get_dma_tag(dev), 4096, 0,
719 ch->dma.max_address, BUS_SPACE_MAXADDR,
720 NULL, NULL, 4096, 1, 4096,
721 0, NULL, NULL, &ch->dma.rfis_tag))
723 if (bus_dmamem_alloc(ch->dma.rfis_tag, (void **)&ch->dma.rfis, 0,
726 if (bus_dmamap_load(ch->dma.rfis_tag, ch->dma.rfis_map, ch->dma.rfis,
727 4096, ahci_dmasetupc_cb, &dcba, 0) || dcba.error) {
728 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
731 ch->dma.rfis_bus = dcba.maddr;
733 if (bus_dma_tag_create(bus_get_dma_tag(dev), 2, 0,
734 ch->dma.max_address, BUS_SPACE_MAXADDR,
736 AHCI_SG_ENTRIES * PAGE_SIZE * ch->numslots,
737 AHCI_SG_ENTRIES, AHCI_PRD_MAX,
738 0, busdma_lock_mutex, &ch->mtx, &ch->dma.data_tag)) {
744 device_printf(dev, "WARNING - DMA initialization failed\n");
749 ahci_dmasetupc_cb(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
751 struct ahci_dc_cb_args *dcba = (struct ahci_dc_cb_args *)xsc;
753 if (!(dcba->error = error))
754 dcba->maddr = segs[0].ds_addr;
758 ahci_dmafini(device_t dev)
760 struct ahci_channel *ch = device_get_softc(dev);
762 if (ch->dma.data_tag) {
763 bus_dma_tag_destroy(ch->dma.data_tag);
764 ch->dma.data_tag = NULL;
766 if (ch->dma.rfis_bus) {
767 bus_dmamap_unload(ch->dma.rfis_tag, ch->dma.rfis_map);
768 bus_dmamem_free(ch->dma.rfis_tag, ch->dma.rfis, ch->dma.rfis_map);
769 ch->dma.rfis_bus = 0;
770 ch->dma.rfis_map = NULL;
773 if (ch->dma.work_bus) {
774 bus_dmamap_unload(ch->dma.work_tag, ch->dma.work_map);
775 bus_dmamem_free(ch->dma.work_tag, ch->dma.work, ch->dma.work_map);
776 ch->dma.work_bus = 0;
777 ch->dma.work_map = NULL;
780 if (ch->dma.work_tag) {
781 bus_dma_tag_destroy(ch->dma.work_tag);
782 ch->dma.work_tag = NULL;
787 ahci_slotsalloc(device_t dev)
789 struct ahci_channel *ch = device_get_softc(dev);
792 /* Alloc and setup command/dma slots */
793 bzero(ch->slot, sizeof(ch->slot));
794 for (i = 0; i < ch->numslots; i++) {
795 struct ahci_slot *slot = &ch->slot[i];
799 slot->state = AHCI_SLOT_EMPTY;
801 callout_init_mtx(&slot->timeout, &ch->mtx, 0);
803 if (bus_dmamap_create(ch->dma.data_tag, 0, &slot->dma.data_map))
804 device_printf(ch->dev, "FAILURE - create data_map\n");
809 ahci_slotsfree(device_t dev)
811 struct ahci_channel *ch = device_get_softc(dev);
814 /* Free all dma slots */
815 for (i = 0; i < ch->numslots; i++) {
816 struct ahci_slot *slot = &ch->slot[i];
818 if (slot->dma.data_map) {
819 bus_dmamap_destroy(ch->dma.data_tag, slot->dma.data_map);
820 slot->dma.data_map = NULL;
826 ahci_phy_check_events(device_t dev)
828 struct ahci_channel *ch = device_get_softc(dev);
829 u_int32_t error = ATA_INL(ch->r_mem, AHCI_P_SERR);
831 /* Clear error bits/interrupt */
832 ATA_OUTL(ch->r_mem, AHCI_P_SERR, error);
833 /* If we have a connection event, deal with it */
834 if ((error & ATA_SE_PHY_CHANGED) && (ch->pm_level == 0)) {
835 u_int32_t status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
836 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
837 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
838 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE)) {
840 device_printf(dev, "CONNECT requested\n");
844 device_printf(dev, "DISCONNECT requested\n");
851 ahci_ch_intr_locked(void *data)
853 device_t dev = (device_t)data;
854 struct ahci_channel *ch = device_get_softc(dev);
858 mtx_unlock(&ch->mtx);
862 ahci_ch_intr(void *data)
864 device_t dev = (device_t)data;
865 struct ahci_channel *ch = device_get_softc(dev);
866 uint32_t istatus, cstatus, sstatus, ok, err;
867 enum ahci_err_type et;
868 int i, ccs, ncq_err = 0;
870 /* Read and clear interrupt statuses. */
871 istatus = ATA_INL(ch->r_mem, AHCI_P_IS);
872 ATA_OUTL(ch->r_mem, AHCI_P_IS, istatus);
873 /* Read command statuses. */
874 cstatus = ATA_INL(ch->r_mem, AHCI_P_CI);
875 sstatus = ATA_INL(ch->r_mem, AHCI_P_SACT);
876 /* Process PHY events */
877 if (istatus & (AHCI_P_IX_PRC | AHCI_P_IX_PC))
878 ahci_phy_check_events(dev);
879 /* Process command errors */
880 if (istatus & (AHCI_P_IX_IF | AHCI_P_IX_HBD | AHCI_P_IX_HBF |
881 AHCI_P_IX_TFE | AHCI_P_IX_OF)) {
882 //device_printf(dev, "%s ERROR is %08x cs %08x ss %08x rs %08x tfd %02x serr %08x\n",
883 // __func__, istatus, cstatus, sstatus, ch->rslots, ATA_INL(ch->r_mem, AHCI_P_TFD),
884 // ATA_INL(ch->r_mem, AHCI_P_SERR));
885 ccs = (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CCS_MASK)
886 >> AHCI_P_CMD_CCS_SHIFT;
887 /* Kick controller into sane state */
890 ok = ch->rslots & ~(cstatus | sstatus);
891 err = ch->rslots & (cstatus | sstatus);
894 ok = ch->rslots & ~(cstatus | sstatus);
897 /* Complete all successfull commands. */
898 for (i = 0; i < ch->numslots; i++) {
900 ahci_end_transaction(&ch->slot[i], AHCI_ERR_NONE);
902 /* On error, complete the rest of commands with error statuses. */
905 xpt_freeze_simq(ch->sim, ch->numrslots);
907 union ccb *fccb = ch->frozen;
909 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
912 for (i = 0; i < ch->numslots; i++) {
913 /* XXX: reqests in loading state. */
914 if (((err >> i) & 1) == 0)
916 if (istatus & AHCI_P_IX_TFE) {
917 /* Task File Error */
918 if (ch->numtslots == 0) {
919 /* Untagged operation. */
923 et = AHCI_ERR_INNOCENT;
925 /* Tagged operation. */
929 } else if (istatus & AHCI_P_IX_IF) {
933 et = AHCI_ERR_INVALID;
934 ahci_end_transaction(&ch->slot[i], et);
937 ahci_issue_read_log(dev);
941 /* Must be called with channel locked. */
943 ahci_check_collision(device_t dev, union ccb *ccb)
945 struct ahci_channel *ch = device_get_softc(dev);
947 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
948 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
949 /* Tagged command while untagged are active. */
950 if (ch->numrslots != 0 && ch->numtslots == 0)
952 /* Tagged command while tagged to other target is active. */
953 if (ch->numtslots != 0 &&
954 ch->taggedtarget != ccb->ccb_h.target_id)
957 /* Untagged command while tagged are active. */
958 if (ch->numrslots != 0 && ch->numtslots != 0)
961 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
962 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT))) {
963 /* Atomic command while anything active. */
964 if (ch->numrslots != 0)
967 /* We have some atomic command running. */
973 /* Must be called with channel locked. */
975 ahci_begin_transaction(device_t dev, union ccb *ccb)
977 struct ahci_channel *ch = device_get_softc(dev);
978 struct ahci_slot *slot;
981 /* Choose empty slot. */
985 if (tag >= ch->numslots)
987 if (ch->slot[tag].state == AHCI_SLOT_EMPTY)
989 } while (tag != ch->lastslot);
990 if (ch->slot[tag].state != AHCI_SLOT_EMPTY)
991 device_printf(ch->dev, "ALL SLOTS BUSY!\n");
993 /* Occupy chosen slot. */
994 slot = &ch->slot[tag];
996 /* Update channel stats. */
998 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
999 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1001 ch->taggedtarget = ccb->ccb_h.target_id;
1003 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1004 (ccb->ataio.cmd.flags & (CAM_ATAIO_CONTROL | CAM_ATAIO_NEEDRESULT)))
1005 ch->aslots |= (1 << slot->slot);
1006 slot->dma.nsegs = 0;
1007 /* If request moves data, setup and load SG list */
1008 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1012 slot->state = AHCI_SLOT_LOADING;
1013 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1014 buf = ccb->ataio.data_ptr;
1015 size = ccb->ataio.dxfer_len;
1017 buf = ccb->csio.data_ptr;
1018 size = ccb->csio.dxfer_len;
1020 bus_dmamap_load(ch->dma.data_tag, slot->dma.data_map,
1021 buf, size, ahci_dmasetprd, slot, 0);
1023 ahci_execute_transaction(slot);
1026 /* Locked by busdma engine. */
1028 ahci_dmasetprd(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
1030 struct ahci_slot *slot = arg;
1031 struct ahci_channel *ch = device_get_softc(slot->dev);
1032 struct ahci_cmd_tab *ctp;
1033 struct ahci_dma_prd *prd;
1037 device_printf(slot->dev, "DMA load error\n");
1039 xpt_freeze_simq(ch->sim, 1);
1040 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1043 KASSERT(nsegs <= AHCI_SG_ENTRIES, ("too many DMA segment entries\n"));
1044 /* Get a piece of the workspace for this request */
1045 ctp = (struct ahci_cmd_tab *)
1046 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1047 /* Fill S/G table */
1048 prd = &ctp->prd_tab[0];
1049 for (i = 0; i < nsegs; i++) {
1050 prd[i].dba = htole64(segs[i].ds_addr);
1051 prd[i].dbc = htole32((segs[i].ds_len - 1) & AHCI_PRD_MASK);
1053 slot->dma.nsegs = nsegs;
1054 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1055 ((slot->ccb->ccb_h.flags & CAM_DIR_IN) ?
1056 BUS_DMASYNC_PREREAD : BUS_DMASYNC_PREWRITE));
1057 ahci_execute_transaction(slot);
1060 /* Must be called with channel locked. */
1062 ahci_execute_transaction(struct ahci_slot *slot)
1064 device_t dev = slot->dev;
1065 struct ahci_channel *ch = device_get_softc(dev);
1066 struct ahci_cmd_tab *ctp;
1067 struct ahci_cmd_list *clp;
1068 union ccb *ccb = slot->ccb;
1069 int port = ccb->ccb_h.target_id & 0x0f;
1072 /* Get a piece of the workspace for this request */
1073 ctp = (struct ahci_cmd_tab *)
1074 (ch->dma.work + AHCI_CT_OFFSET + (AHCI_CT_SIZE * slot->slot));
1075 /* Setup the FIS for this request */
1076 if (!(fis_size = ahci_setup_fis(ctp, ccb, slot->slot))) {
1077 device_printf(ch->dev, "Setting up SATA FIS failed\n");
1079 xpt_freeze_simq(ch->sim, 1);
1080 ahci_end_transaction(slot, AHCI_ERR_INVALID);
1083 /* Setup the command list entry */
1084 clp = (struct ahci_cmd_list *)
1085 (ch->dma.work + AHCI_CL_OFFSET + (AHCI_CL_SIZE * slot->slot));
1086 clp->prd_length = slot->dma.nsegs;
1087 clp->cmd_flags = (ccb->ccb_h.flags & CAM_DIR_OUT ? AHCI_CMD_WRITE : 0) |
1088 (ccb->ccb_h.func_code == XPT_SCSI_IO ?
1089 (AHCI_CMD_ATAPI | AHCI_CMD_PREFETCH) : 0) |
1090 (fis_size / sizeof(u_int32_t)) |
1092 /* Special handling for Soft Reset command. */
1093 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1094 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1095 (ccb->ataio.cmd.control & ATA_A_RESET)) {
1096 /* Kick controller into sane state */
1100 clp->cmd_flags |= AHCI_CMD_RESET | AHCI_CMD_CLR_BUSY;
1103 clp->cmd_table_phys = htole64(ch->dma.work_bus + AHCI_CT_OFFSET +
1104 (AHCI_CT_SIZE * slot->slot));
1105 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1106 BUS_DMASYNC_PREWRITE);
1107 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1108 BUS_DMASYNC_PREREAD);
1109 /* Set ACTIVE bit for NCQ commands. */
1110 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1111 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1112 ATA_OUTL(ch->r_mem, AHCI_P_SACT, 1 << slot->slot);
1114 /* Issue command to the controller. */
1115 slot->state = AHCI_SLOT_RUNNING;
1116 ch->rslots |= (1 << slot->slot);
1117 ATA_OUTL(ch->r_mem, AHCI_P_CI, (1 << slot->slot));
1118 /* Device reset commands doesn't interrupt. Poll them. */
1119 if (ccb->ccb_h.func_code == XPT_ATA_IO &&
1120 (ccb->ataio.cmd.command == ATA_DEVICE_RESET ||
1121 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL))) {
1122 int count, timeout = ccb->ccb_h.timeout;
1123 enum ahci_err_type et = AHCI_ERR_NONE;
1125 for (count = 0; count < timeout; count++) {
1127 if (!(ATA_INL(ch->r_mem, AHCI_P_CI) & (1 << slot->slot)))
1129 if (ATA_INL(ch->r_mem, AHCI_P_TFD) & ATA_S_ERROR) {
1130 device_printf(ch->dev,
1131 "Poll error on slot %d, TFD: %04x\n",
1132 slot->slot, ATA_INL(ch->r_mem, AHCI_P_TFD));
1137 if (timeout && (count >= timeout)) {
1138 device_printf(ch->dev,
1139 "Poll timeout on slot %d\n", slot->slot);
1140 et = AHCI_ERR_TIMEOUT;
1142 if (et != AHCI_ERR_NONE) {
1143 /* Kick controller into sane state */
1145 ahci_start(ch->dev);
1146 xpt_freeze_simq(ch->sim, 1);
1148 ahci_end_transaction(slot, et);
1151 /* Start command execution timeout */
1152 callout_reset(&slot->timeout, (int)ccb->ccb_h.timeout * hz / 1000,
1153 (timeout_t*)ahci_timeout, slot);
1157 /* Locked by callout mechanism. */
1159 ahci_timeout(struct ahci_slot *slot)
1161 device_t dev = slot->dev;
1162 struct ahci_channel *ch = device_get_softc(dev);
1165 device_printf(dev, "Timeout on slot %d\n", slot->slot);
1166 /* Kick controller into sane state. */
1168 ahci_start(ch->dev);
1171 xpt_freeze_simq(ch->sim, ch->numrslots);
1172 /* Handle command with timeout. */
1173 ahci_end_transaction(&ch->slot[slot->slot], AHCI_ERR_TIMEOUT);
1174 /* Handle the rest of commands. */
1176 union ccb *fccb = ch->frozen;
1178 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1181 for (i = 0; i < ch->numslots; i++) {
1182 /* Do we have a running request on slot? */
1183 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1185 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1189 /* Must be called with channel locked. */
1191 ahci_end_transaction(struct ahci_slot *slot, enum ahci_err_type et)
1193 device_t dev = slot->dev;
1194 struct ahci_channel *ch = device_get_softc(dev);
1195 union ccb *ccb = slot->ccb;
1197 /* Cancel command execution timeout */
1198 callout_stop(&slot->timeout);
1199 bus_dmamap_sync(ch->dma.work_tag, ch->dma.work_map,
1200 BUS_DMASYNC_POSTWRITE);
1201 /* Read result registers to the result struct
1202 * May be incorrect if several commands finished same time,
1203 * so read only when sure or have to.
1205 if (ccb->ccb_h.func_code == XPT_ATA_IO) {
1206 struct ata_res *res = &ccb->ataio.res;
1208 if ((et == AHCI_ERR_TFE) ||
1209 (ccb->ataio.cmd.flags & CAM_ATAIO_NEEDRESULT)) {
1210 u_int8_t *fis = ch->dma.rfis + 0x40;
1211 uint16_t tfd = ATA_INL(ch->r_mem, AHCI_P_TFD);
1213 bus_dmamap_sync(ch->dma.rfis_tag, ch->dma.rfis_map,
1214 BUS_DMASYNC_POSTREAD);
1216 res->error = tfd >> 8;
1217 res->lba_low = fis[4];
1218 res->lba_mid = fis[5];
1219 res->lba_high = fis[6];
1220 res->device = fis[7];
1221 res->lba_low_exp = fis[8];
1222 res->lba_mid_exp = fis[9];
1223 res->lba_high_exp = fis[10];
1224 res->sector_count = fis[12];
1225 res->sector_count_exp = fis[13];
1227 bzero(res, sizeof(*res));
1229 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE) {
1230 bus_dmamap_sync(ch->dma.data_tag, slot->dma.data_map,
1231 (ccb->ccb_h.flags & CAM_DIR_IN) ?
1232 BUS_DMASYNC_POSTREAD : BUS_DMASYNC_POSTWRITE);
1233 bus_dmamap_unload(ch->dma.data_tag, slot->dma.data_map);
1235 /* Set proper result status. */
1236 ccb->ccb_h.status &= ~CAM_STATUS_MASK;
1237 if (et != AHCI_ERR_NONE)
1238 ccb->ccb_h.status |= CAM_RELEASE_SIMQ;
1241 ccb->ccb_h.status |= CAM_REQ_CMP;
1242 if (ccb->ccb_h.func_code == XPT_SCSI_IO)
1243 ccb->csio.scsi_status = SCSI_STATUS_OK;
1245 case AHCI_ERR_INVALID:
1246 ccb->ccb_h.status |= CAM_REQ_INVALID;
1248 case AHCI_ERR_INNOCENT:
1249 ccb->ccb_h.status |= CAM_REQUEUE_REQ;
1252 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1253 ccb->ccb_h.status |= CAM_SCSI_STATUS_ERROR;
1254 ccb->csio.scsi_status = SCSI_STATUS_CHECK_COND;
1256 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1260 ccb->ccb_h.status |= CAM_UNCOR_PARITY;
1262 case AHCI_ERR_TIMEOUT:
1263 ccb->ccb_h.status |= CAM_CMD_TIMEOUT;
1266 ccb->ccb_h.status |= CAM_ATA_STATUS_ERROR;
1268 ccb->ccb_h.status |= CAM_REQ_CMP_ERR;
1271 ch->rslots &= ~(1 << slot->slot);
1272 ch->aslots &= ~(1 << slot->slot);
1273 slot->state = AHCI_SLOT_EMPTY;
1275 /* Update channel stats. */
1277 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1278 (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA)) {
1281 /* If it was first request of reset sequence and there is no error,
1282 * proceed to second request. */
1283 if ((ccb->ccb_h.func_code == XPT_ATA_IO) &&
1284 (ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) &&
1285 (ccb->ataio.cmd.control & ATA_A_RESET) &&
1286 et == AHCI_ERR_NONE) {
1287 ccb->ataio.cmd.control &= ~ATA_A_RESET;
1288 ahci_begin_transaction(dev, ccb);
1291 /* If it was NCQ command error, put result on hold. */
1292 if (et == AHCI_ERR_NCQ) {
1293 ch->hold[slot->slot] = ccb;
1294 } else if (ch->readlog) /* If it was our READ LOG command - process it. */
1295 ahci_process_read_log(dev, ccb);
1298 /* Unfreeze frozen command. */
1299 if (ch->frozen && ch->numrslots == 0) {
1300 union ccb *fccb = ch->frozen;
1302 ahci_begin_transaction(dev, fccb);
1303 xpt_release_simq(ch->sim, TRUE);
1308 ahci_issue_read_log(device_t dev)
1310 struct ahci_channel *ch = device_get_softc(dev);
1312 struct ccb_ataio *ataio;
1316 /* Find some holden command. */
1317 for (i = 0; i < ch->numslots; i++) {
1321 ccb = xpt_alloc_ccb_nowait();
1323 device_printf(dev, "Unable allocate READ LOG command");
1326 ccb->ccb_h = ch->hold[i]->ccb_h; /* Reuse old header. */
1327 ccb->ccb_h.func_code = XPT_ATA_IO;
1328 ccb->ccb_h.flags = CAM_DIR_IN;
1329 ccb->ccb_h.timeout = 1000; /* 1s should be enough. */
1330 ataio = &ccb->ataio;
1331 ataio->data_ptr = malloc(512, M_AHCI, M_NOWAIT);
1332 if (ataio->data_ptr == NULL) {
1333 device_printf(dev, "Unable allocate memory for READ LOG command");
1336 ataio->dxfer_len = 512;
1337 bzero(&ataio->cmd, sizeof(ataio->cmd));
1338 ataio->cmd.flags = CAM_ATAIO_48BIT;
1339 ataio->cmd.command = 0x2F; /* READ LOG EXT */
1340 ataio->cmd.sector_count = 1;
1341 ataio->cmd.sector_count_exp = 0;
1342 ataio->cmd.lba_low = 0x10;
1343 ataio->cmd.lba_mid = 0;
1344 ataio->cmd.lba_mid_exp = 0;
1346 ahci_begin_transaction(dev, ccb);
1350 ahci_process_read_log(device_t dev, union ccb *ccb)
1352 struct ahci_channel *ch = device_get_softc(dev);
1354 struct ata_res *res;
1359 data = ccb->ataio.data_ptr;
1360 if ((ccb->ccb_h.status & CAM_STATUS_MASK) == CAM_REQ_CMP &&
1361 (data[0] & 0x80) == 0) {
1362 for (i = 0; i < ch->numslots; i++) {
1365 if ((data[0] & 0x1F) == i) {
1366 res = &ch->hold[i]->ataio.res;
1367 res->status = data[2];
1368 res->error = data[3];
1369 res->lba_low = data[4];
1370 res->lba_mid = data[5];
1371 res->lba_high = data[6];
1372 res->device = data[7];
1373 res->lba_low_exp = data[8];
1374 res->lba_mid_exp = data[9];
1375 res->lba_high_exp = data[10];
1376 res->sector_count = data[12];
1377 res->sector_count_exp = data[13];
1379 ch->hold[i]->ccb_h.status &= ~CAM_STATUS_MASK;
1380 ch->hold[i]->ccb_h.status |= CAM_REQUEUE_REQ;
1382 xpt_done(ch->hold[i]);
1386 if ((ccb->ccb_h.status & CAM_STATUS_MASK) != CAM_REQ_CMP)
1387 device_printf(dev, "Error while READ LOG EXT\n");
1388 else if ((data[0] & 0x80) == 0) {
1389 device_printf(dev, "Non-queued command error in READ LOG EXT\n");
1391 for (i = 0; i < ch->numslots; i++) {
1394 xpt_done(ch->hold[i]);
1398 free(ccb->ataio.data_ptr, M_AHCI);
1403 ahci_start(device_t dev)
1405 struct ahci_channel *ch = device_get_softc(dev);
1408 /* Clear SATA error register */
1409 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xFFFFFFFF);
1410 /* Clear any interrupts pending on this channel */
1411 ATA_OUTL(ch->r_mem, AHCI_P_IS, 0xFFFFFFFF);
1412 /* Start operations on this channel */
1413 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
1414 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_ST |
1415 (ch->pm_present ? AHCI_P_CMD_PMA : 0));
1419 ahci_stop(device_t dev)
1421 struct ahci_channel *ch = device_get_softc(dev);
1425 /* Kill all activity on this channel */
1426 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
1427 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_ST);
1428 /* Wait for activity stop. */
1432 if (timeout++ > 1000) {
1433 device_printf(dev, "stopping AHCI engine failed\n");
1436 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CR);
1440 ahci_clo(device_t dev)
1442 struct ahci_channel *ch = device_get_softc(dev);
1446 /* Issue Command List Override if supported */
1447 if (ch->caps & AHCI_CAP_SCLO) {
1448 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
1449 cmd |= AHCI_P_CMD_CLO;
1450 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd);
1454 if (timeout++ > 1000) {
1455 device_printf(dev, "executing CLO failed\n");
1458 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_CLO);
1463 ahci_stop_fr(device_t dev)
1465 struct ahci_channel *ch = device_get_softc(dev);
1469 /* Kill all FIS reception on this channel */
1470 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
1471 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd & ~AHCI_P_CMD_FRE);
1472 /* Wait for FIS reception stop. */
1476 if (timeout++ > 1000) {
1477 device_printf(dev, "stopping AHCI FR engine failed\n");
1480 } while (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_FR);
1484 ahci_start_fr(device_t dev)
1486 struct ahci_channel *ch = device_get_softc(dev);
1489 /* Start FIS reception on this channel */
1490 cmd = ATA_INL(ch->r_mem, AHCI_P_CMD);
1491 ATA_OUTL(ch->r_mem, AHCI_P_CMD, cmd | AHCI_P_CMD_FRE);
1495 ahci_wait_ready(device_t dev, int t)
1497 struct ahci_channel *ch = device_get_softc(dev);
1501 while ((val = ATA_INL(ch->r_mem, AHCI_P_TFD)) &
1502 (ATA_S_BUSY | ATA_S_DRQ)) {
1504 if (timeout++ > t) {
1505 device_printf(dev, "port is not ready (timeout %dms) "
1506 "tfd = %08x\n", t, val);
1511 device_printf(dev, "ready wait time=%dms\n", timeout);
1516 ahci_reset(device_t dev)
1518 struct ahci_channel *ch = device_get_softc(dev);
1522 device_printf(dev, "AHCI reset...\n");
1523 xpt_freeze_simq(ch->sim, ch->numrslots);
1524 /* Requeue freezed command. */
1526 union ccb *fccb = ch->frozen;
1528 fccb->ccb_h.status = CAM_REQUEUE_REQ | CAM_RELEASE_SIMQ;
1531 /* Kill the engine and requeue all running commands. */
1533 for (i = 0; i < ch->numslots; i++) {
1534 /* Do we have a running request on slot? */
1535 if (ch->slot[i].state < AHCI_SLOT_RUNNING)
1537 /* XXX; Commands in loading state. */
1538 ahci_end_transaction(&ch->slot[i], AHCI_ERR_INNOCENT);
1540 /* Disable port interrupts */
1541 ATA_OUTL(ch->r_mem, AHCI_P_IE, 0);
1542 /* Reset and reconnect PHY, */
1543 if (!ahci_sata_phy_reset(dev, 0)) {
1546 "AHCI reset done: phy reset found no device\n");
1548 /* Enable wanted port interrupts */
1549 ATA_OUTL(ch->r_mem, AHCI_P_IE,
1550 (AHCI_P_IX_CPD | AHCI_P_IX_PRC | AHCI_P_IX_PC));
1553 /* Wait for clearing busy status. */
1554 if (ahci_wait_ready(dev, 10000)) {
1555 device_printf(dev, "device ready timeout\n");
1560 /* Enable wanted port interrupts */
1561 ATA_OUTL(ch->r_mem, AHCI_P_IE,
1562 (AHCI_P_IX_CPD | AHCI_P_IX_TFE | AHCI_P_IX_HBF |
1563 AHCI_P_IX_HBD | AHCI_P_IX_IF | AHCI_P_IX_OF |
1564 ((ch->pm_level == 0) ? AHCI_P_IX_PRC | AHCI_P_IX_PC : 0) |
1565 AHCI_P_IX_DP | AHCI_P_IX_UF | AHCI_P_IX_SDB |
1566 AHCI_P_IX_DS | AHCI_P_IX_PS | AHCI_P_IX_DHR));
1568 device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices);
1569 /* Tell the XPT about the event */
1570 xpt_async(AC_BUS_RESET, ch->path, NULL);
1574 ahci_setup_fis(struct ahci_cmd_tab *ctp, union ccb *ccb, int tag)
1576 u_int8_t *fis = &ctp->cfis[0];
1578 bzero(ctp->cfis, 64);
1579 fis[0] = 0x27; /* host to device */
1580 fis[1] = (ccb->ccb_h.target_id & 0x0f);
1581 if (ccb->ccb_h.func_code == XPT_SCSI_IO) {
1583 fis[2] = ATA_PACKET_CMD;
1584 if ((ccb->ccb_h.flags & CAM_DIR_MASK) != CAM_DIR_NONE)
1587 fis[5] = ccb->csio.dxfer_len;
1588 fis[6] = ccb->csio.dxfer_len >> 8;
1591 fis[15] = ATA_A_4BIT;
1592 bzero(ctp->acmd, 32);
1593 bcopy((ccb->ccb_h.flags & CAM_CDB_POINTER) ?
1594 ccb->csio.cdb_io.cdb_ptr : ccb->csio.cdb_io.cdb_bytes,
1595 ctp->acmd, ccb->csio.cdb_len);
1596 } else if ((ccb->ataio.cmd.flags & CAM_ATAIO_CONTROL) == 0) {
1598 fis[2] = ccb->ataio.cmd.command;
1599 fis[3] = ccb->ataio.cmd.features;
1600 fis[4] = ccb->ataio.cmd.lba_low;
1601 fis[5] = ccb->ataio.cmd.lba_mid;
1602 fis[6] = ccb->ataio.cmd.lba_high;
1603 fis[7] = ccb->ataio.cmd.device;
1604 fis[8] = ccb->ataio.cmd.lba_low_exp;
1605 fis[9] = ccb->ataio.cmd.lba_mid_exp;
1606 fis[10] = ccb->ataio.cmd.lba_high_exp;
1607 fis[11] = ccb->ataio.cmd.features_exp;
1608 if (ccb->ataio.cmd.flags & CAM_ATAIO_FPDMA) {
1612 fis[12] = ccb->ataio.cmd.sector_count;
1613 fis[13] = ccb->ataio.cmd.sector_count_exp;
1615 fis[15] = ATA_A_4BIT;
1617 fis[15] = ccb->ataio.cmd.control;
1623 ahci_sata_connect(struct ahci_channel *ch)
1628 /* Wait up to 100ms for "connect well" */
1629 for (timeout = 0; timeout < 100 ; timeout++) {
1630 status = ATA_INL(ch->r_mem, AHCI_P_SSTS);
1631 if (((status & ATA_SS_DET_MASK) == ATA_SS_DET_PHY_ONLINE) &&
1632 ((status & ATA_SS_SPD_MASK) != ATA_SS_SPD_NO_SPEED) &&
1633 ((status & ATA_SS_IPM_MASK) == ATA_SS_IPM_ACTIVE))
1637 if (timeout >= 100) {
1639 device_printf(ch->dev, "SATA connect timeout status=%08x\n",
1645 device_printf(ch->dev, "SATA connect time=%dms status=%08x\n",
1648 /* Clear SATA error register */
1649 ATA_OUTL(ch->r_mem, AHCI_P_SERR, 0xffffffff);
1654 ahci_sata_phy_reset(device_t dev, int quick)
1656 struct ahci_channel *ch = device_get_softc(dev);
1660 val = ATA_INL(ch->r_mem, AHCI_P_SCTL);
1661 if ((val & ATA_SC_DET_MASK) == ATA_SC_DET_IDLE)
1662 return (ahci_sata_connect(ch));
1666 device_printf(dev, "hardware reset ...\n");
1667 ATA_OUTL(ch->r_mem, AHCI_P_SCTL, ATA_SC_IPM_DIS_PARTIAL |
1668 ATA_SC_IPM_DIS_SLUMBER | ATA_SC_DET_RESET);
1670 if (ch->sata_rev == 1)
1671 val = ATA_SC_SPD_SPEED_GEN1;
1672 else if (ch->sata_rev == 2)
1673 val = ATA_SC_SPD_SPEED_GEN2;
1674 else if (ch->sata_rev == 3)
1675 val = ATA_SC_SPD_SPEED_GEN3;
1678 ATA_OUTL(ch->r_mem, AHCI_P_SCTL,
1679 ATA_SC_DET_IDLE | val | ((ch->pm_level > 0) ? 0 :
1680 (ATA_SC_IPM_DIS_PARTIAL | ATA_SC_IPM_DIS_SLUMBER)));
1682 return (ahci_sata_connect(ch));
1686 ahciaction(struct cam_sim *sim, union ccb *ccb)
1689 struct ahci_channel *ch;
1691 CAM_DEBUG(ccb->ccb_h.path, CAM_DEBUG_TRACE, ("ahciaction func_code=%x\n",
1692 ccb->ccb_h.func_code));
1694 ch = (struct ahci_channel *)cam_sim_softc(sim);
1696 switch (ccb->ccb_h.func_code) {
1697 /* Common cases first */
1698 case XPT_ATA_IO: /* Execute the requested I/O operation */
1700 if (ch->devices == 0) {
1701 ccb->ccb_h.status = CAM_SEL_TIMEOUT;
1705 /* Check for command collision. */
1706 if (ahci_check_collision(dev, ccb)) {
1707 /* Freeze command. */
1709 /* We have only one frozen slot, so freeze simq also. */
1710 xpt_freeze_simq(ch->sim, 1);
1713 ahci_begin_transaction(dev, ccb);
1715 case XPT_EN_LUN: /* Enable LUN as a target */
1716 case XPT_TARGET_IO: /* Execute target I/O request */
1717 case XPT_ACCEPT_TARGET_IO: /* Accept Host Target Mode CDB */
1718 case XPT_CONT_TARGET_IO: /* Continue Host Target I/O Connection*/
1719 case XPT_ABORT: /* Abort the specified CCB */
1721 ccb->ccb_h.status = CAM_REQ_INVALID;
1724 case XPT_SET_TRAN_SETTINGS:
1726 struct ccb_trans_settings *cts = &ccb->cts;
1728 if (cts->xport_specific.sata.valid & CTS_SATA_VALID_PM) {
1729 ch->pm_present = cts->xport_specific.sata.pm_present;
1731 ccb->ccb_h.status = CAM_REQ_CMP;
1735 case XPT_GET_TRAN_SETTINGS:
1736 /* Get default/user set transfer settings for the target */
1738 struct ccb_trans_settings *cts = &ccb->cts;
1741 cts->protocol = PROTO_ATA;
1742 cts->protocol_version = SCSI_REV_2;
1743 cts->transport = XPORT_SATA;
1744 cts->transport_version = 2;
1745 cts->proto_specific.valid = 0;
1746 cts->xport_specific.sata.valid = 0;
1747 if (cts->type == CTS_TYPE_CURRENT_SETTINGS)
1748 status = ATA_INL(ch->r_mem, AHCI_P_SSTS) & ATA_SS_SPD_MASK;
1750 status = ATA_INL(ch->r_mem, AHCI_P_SCTL) & ATA_SC_SPD_MASK;
1751 if (status & ATA_SS_SPD_GEN3) {
1752 cts->xport_specific.sata.bitrate = 600000;
1753 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED;
1754 } else if (status & ATA_SS_SPD_GEN2) {
1755 cts->xport_specific.sata.bitrate = 300000;
1756 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED;
1757 } else if (status & ATA_SS_SPD_GEN1) {
1758 cts->xport_specific.sata.bitrate = 150000;
1759 cts->xport_specific.sata.valid |= CTS_SATA_VALID_SPEED;
1761 if (cts->type == CTS_TYPE_CURRENT_SETTINGS) {
1762 cts->xport_specific.sata.pm_present =
1763 (ATA_INL(ch->r_mem, AHCI_P_CMD) & AHCI_P_CMD_PMA) ?
1766 cts->xport_specific.sata.pm_present = ch->pm_present;
1768 cts->xport_specific.sata.valid |= CTS_SATA_VALID_PM;
1769 ccb->ccb_h.status = CAM_REQ_CMP;
1774 case XPT_CALC_GEOMETRY:
1776 struct ccb_calc_geometry *ccg;
1778 uint32_t secs_per_cylinder;
1781 size_mb = ccg->volume_size
1782 / ((1024L * 1024L) / ccg->block_size);
1783 if (size_mb >= 1024 && (aha->extended_trans != 0)) {
1784 if (size_mb >= 2048) {
1786 ccg->secs_per_track = 63;
1789 ccg->secs_per_track = 32;
1793 ccg->secs_per_track = 32;
1795 secs_per_cylinder = ccg->heads * ccg->secs_per_track;
1796 ccg->cylinders = ccg->volume_size / secs_per_cylinder;
1797 ccb->ccb_h.status = CAM_REQ_CMP;
1802 case XPT_RESET_BUS: /* Reset the specified SCSI bus */
1803 case XPT_RESET_DEV: /* Bus Device Reset the specified SCSI device */
1805 ccb->ccb_h.status = CAM_REQ_CMP;
1808 case XPT_TERM_IO: /* Terminate the I/O process */
1810 ccb->ccb_h.status = CAM_REQ_INVALID;
1813 case XPT_PATH_INQ: /* Path routing inquiry */
1815 struct ccb_pathinq *cpi = &ccb->cpi;
1817 cpi->version_num = 1; /* XXX??? */
1818 cpi->hba_inquiry = PI_SDTR_ABLE | PI_TAG_ABLE;
1819 if (ch->caps & AHCI_CAP_SPM)
1820 cpi->hba_inquiry |= PI_SATAPM;
1821 cpi->target_sprt = 0;
1822 cpi->hba_misc = PIM_SEQSCAN;
1823 cpi->hba_eng_cnt = 0;
1824 if (ch->caps & AHCI_CAP_SPM)
1825 cpi->max_target = 14;
1827 cpi->max_target = 0;
1829 cpi->initiator_id = 0;
1830 cpi->bus_id = cam_sim_bus(sim);
1831 cpi->base_transfer_speed = 150000;
1832 strncpy(cpi->sim_vid, "FreeBSD", SIM_IDLEN);
1833 strncpy(cpi->hba_vid, "AHCI", HBA_IDLEN);
1834 strncpy(cpi->dev_name, cam_sim_name(sim), DEV_IDLEN);
1835 cpi->unit_number = cam_sim_unit(sim);
1836 cpi->transport = XPORT_SATA;
1837 cpi->transport_version = 2;
1838 cpi->protocol = PROTO_ATA;
1839 cpi->protocol_version = SCSI_REV_2;
1840 cpi->maxio = MAXPHYS;
1841 cpi->ccb_h.status = CAM_REQ_CMP;
1846 ccb->ccb_h.status = CAM_REQ_INVALID;
1853 ahcipoll(struct cam_sim *sim)
1855 struct ahci_channel *ch = (struct ahci_channel *)cam_sim_softc(sim);
1857 ahci_ch_intr(ch->dev);