sys/dev/asmc/asmcvar.h

   1 /*-
   2  * Copyright (c) 2007, 2008 Rui Paulo <rpaulo@FreeBSD.org>
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions
   7  * are met:
   8  * 1. Redistributions of source code must retain the above copyright
   9  *    notice, this list of conditions and the following disclaimer.
  10  * 2. Redistributions in binary form must reproduce the above copyright
  11  *    notice, this list of conditions and the following disclaimer in the
  12  *    documentation and/or other materials provided with the distribution.
  13  *
  14  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
  15  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  16  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  17  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
  18  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  19  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  20  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
  21  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
  22  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
  23  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  24  * POSSIBILITY OF SUCH DAMAGE.
  25  *
  26  * $FreeBSD$
  27  *
  28  */
  29
  30 #define ASMC_MAXFANS    2
  31
  32 struct asmc_softc {
  33         device_t                sc_dev;
  34         struct mtx              sc_mtx;
  35         int                     sc_nfan;
  36         int16_t                 sms_rest_x;
  37         int16_t                 sms_rest_y;
  38         int16_t                 sms_rest_z;
  39         struct sysctl_oid       *sc_fan_tree[ASMC_MAXFANS+1];
  40         struct sysctl_oid       *sc_temp_tree;
  41         struct sysctl_oid       *sc_sms_tree;
  42         struct sysctl_oid       *sc_light_tree;
  43         struct asmc_model       *sc_model;
  44         int                     sc_rid_port;
  45         int                     sc_rid_irq;
  46         struct resource         *sc_ioport;
  47         struct resource         *sc_irq;
  48         void                    *sc_cookie;
  49         int                     sc_sms_intrtype;
  50         struct taskqueue        *sc_sms_tq;
  51         struct task             sc_sms_task;
  52 };
  53
  54 /*
  55  * Data port.
  56  */
  57 #define ASMC_DATAPORT_READ(sc)  bus_read_1(sc->sc_ioport, 0x00)
  58 #define ASMC_DATAPORT_WRITE(sc, val) \
  59         bus_write_1(sc->sc_ioport, 0x00, val)
  60 #define ASMC_STATUS_MASK        0x0f
  61
  62 /*
  63  * Command port.
  64  */
  65 #define ASMC_CMDPORT_READ(sc)   bus_read_1(sc->sc_ioport, 0x04)
  66 #define ASMC_CMDPORT_WRITE(sc, val) \
  67         bus_write_1(sc->sc_ioport, 0x04, val)
  68 #define ASMC_CMDREAD            0x10
  69 #define ASMC_CMDWRITE           0x11
  70
  71 /*
  72  * Interrupt port.
  73  */
  74 #define ASMC_INTPORT_READ(sc)   bus_read_1(sc->sc_ioport, 0x1f)
  75
  76
  77 /* Number of keys */
  78 #define ASMC_NKEYS              "#KEY"  /* RO; 4 bytes */
  79
  80 /*
  81  * Fan control via SMC.
  82  */
  83 #define ASMC_KEY_FANCOUNT       "FNum"  /* RO; 1 byte */
  84 #define ASMC_KEY_FANMANUAL      "FS! "  /* RW; 2 bytes */
  85 #define ASMC_KEY_FANSPEED       "F%dAc" /* RO; 2 bytes */
  86 #define ASMC_KEY_FANMINSPEED    "F%dMn" /* RO; 2 bytes */
  87 #define ASMC_KEY_FANMAXSPEED    "F%dMx" /* RO; 2 bytes */
  88 #define ASMC_KEY_FANSAFESPEED   "F%dSf" /* RO; 2 bytes */
  89 #define ASMC_KEY_FANTARGETSPEED "F%dTg" /* RW; 2 bytes */
  90
  91 /*
  92  * Sudden Motion Sensor (SMS).
  93  */
  94 #define ASMC_SMS_INIT1          0xe0
  95 #define ASMC_SMS_INIT2          0xf8
  96 #define ASMC_KEY_SMS            "MOCN"  /* RW; 2 bytes */
  97 #define ASMC_KEY_SMS_X          "MO_X"  /* RO; 2 bytes */
  98 #define ASMC_KEY_SMS_Y          "MO_Y"  /* RO; 2 bytes */
  99 #define ASMC_KEY_SMS_Z          "MO_Z"  /* RO; 2 bytes */
 100 #define ASMC_KEY_SMS_LOW        "MOLT"  /* RW; 2 bytes */
 101 #define ASMC_KEY_SMS_HIGH       "MOHT"  /* RW; 2 bytes */
 102 #define ASMC_KEY_SMS_LOW_INT    "MOLD"  /* RW; 1 byte */
 103 #define ASMC_KEY_SMS_HIGH_INT   "MOHD"  /* RW; 1 byte */
 104 #define ASMC_KEY_SMS_FLAG       "MSDW"  /* RW; 1 byte */
 105 #define ASMC_SMS_INTFF          0x60    /* Free fall Interrupt */
 106 #define ASMC_SMS_INTHA          0x6f    /* High Acceleration Interrupt */
 107 #define ASMC_SMS_INTSH          0x80    /* Shock Interrupt */
 108
 109 /*
 110  * Keyboard backlight.
 111  */
 112 #define ASMC_KEY_LIGHTLEFT      "ALV0"  /* RO; 6 bytes */
 113 #define ASMC_KEY_LIGHTRIGHT     "ALV1"  /* RO; 6 bytes */
 114 #define ASMC_KEY_LIGHTVALUE     "LKSB"  /* WO; 2 bytes */
 115
 116 /*
 117  * Clamshell.
 118  */
 119 #define ASMC_KEY_CLAMSHELL      "MSLD"  /* RO; 1 byte */
 120
 121 /*
 122  * Interrupt keys.
 123  */
 124 #define ASMC_KEY_INTOK          "NTOK"  /* WO; 1 byte */
 125
 126 /*
 127  * Temperatures.
 128  *
 129  * First for MacBook, second for MacBook Pro, third for Intel Mac Mini,
 130  * fourth the Mac Pro 8-core and finally the MacBook Air.
 131  *
 132  */
 133 /* maximum array size for temperatures including the last NULL */
 134 #define ASMC_TEMP_MAX           36
 135 #define ASMC_MB_TEMPS           { "TB0T", "TN0P", "TN1P", "Th0H", "Th1H", \
 136                                   "TM0P", NULL }
 137 #define ASMC_MB_TEMPNAMES       { "enclosure", "northbridge1", \
 138                                   "northbridge2", "heatsink1", \
 139                                   "heatsink2", "memory", }
 140 #define ASMC_MB_TEMPDESCS       { "Enclosure Bottomside", \
 141                                   "Northbridge Point 1", \
 142                                   "Northbridge Point 2", "Heatsink 1", \
 143                                   "Heatsink 2", "Memory Bank A", }
 144
 145 #define ASMC_MBP_TEMPS          { "TB0T", "Th0H", "Th1H", "Tm0P", \
 146                                   "TG0H", "TG0P", "TG0T", NULL }
 147
 148 #define ASMC_MBP_TEMPNAMES      { "enclosure", "heatsink1", \
 149                                   "heatsink2", "memory", "graphics", \
 150                                   "graphicssink", "unknown", }
 151
 152 #define ASMC_MBP_TEMPDESCS      { "Enclosure Bottomside", \
 153                                   "Heatsink 1", "Heatsink 2", \
 154                                   "Memory Controller", \
 155                                   "Graphics Chip", "Graphics Heatsink", \
 156                                   "Unknown", }
 157
 158 #define ASMC_MBP4_TEMPS         { "TB0T", "Th0H", "Th1H", "Th2H", "Tm0P", \
 159                                   "TG0H", "TG0D", "TC0D", "TC0P", "Ts0P", \
 160                                   "TTF0", "TW0P", NULL }
 161
 162 #define ASMC_MBP4_TEMPNAMES     { "enclosure", "heatsink1", "heatsink2", \
 163                                   "heatsink3", "memory", "graphicssink", \
 164                                   "graphics", "cpu", "cpu2", "unknown1", \
 165                                   "unknown2", "wireless", }
 166
 167 #define ASMC_MBP4_TEMPDESCS     { "Enclosure Bottomside", \
 168                                   "Main Heatsink 1", "Main Heatsink 2", \
 169                                   "Main Heatsink 3", \
 170                                   "Memory Controller", \
 171                                   "Graphics Chip Heatsink", \
 172                                   "Graphics Chip Diode", \
 173                                   "CPU Temperature Diode", "CPU Point 2", \
 174                                   "Unknown", "Unknown", \
 175                                   "Wireless Module", }
 176
 177 #define ASMC_MM_TEMPS           { "TN0P", "TN1P", NULL }
 178 #define ASMC_MM_TEMPNAMES       { "northbridge1", "northbridge2" }
 179 #define ASMC_MM_TEMPDESCS       { "Northbridge Point 1", \
 180                                   "Northbridge Point 2" }
 181
 182 #define ASMC_MP_TEMPS           { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 183                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 184                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 185                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 186                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 187                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 188                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
 189                                   NULL }
 190
 191 #define ASMC_MP_TEMPNAMES       { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 192                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 193                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 194                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 195                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 196                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 197                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
 198                                   NULL }
 199
 200 #define ASMC_MP_TEMPDESCS       { "TA0P", "TCAG", "TCAH", "TCBG", "TCBH", \
 201                                   "TC0C", "TC0D", "TC0P", "TC1C", "TC1D", \
 202                                   "TC2C", "TC2D", "TC3C", "TC3D", "THTG", \
 203                                   "TH0P", "TH1P", "TH2P", "TH3P", "TMAP", \
 204                                   "TMAS", "TMBS", "TM0P", "TM0S", "TM1P", \
 205                                   "TM1S", "TM2P", "TM2S", "TM3S", "TM8P", \
 206                                   "TM8S", "TM9P", "TM9S", "TN0H", "TS0C", \
 207                                   NULL }
 208
 209 #define ASMC_MBA_TEMPS          { "TB0T", NULL }
 210 #define ASMC_MBA_TEMPNAMES      { "enclosure" }
 211 #define ASMC_MBA_TEMPDESCS      { "Enclosure Bottom" }