2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org>
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
8 * 1. Redistributions of source code must retain the above copyright
9 * notice, this list of conditions and the following disclaimer,
10 * without modification, immediately at the beginning of the file.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 * notice, this list of conditions and the following disclaimer in the
13 * documentation and/or other materials provided with the distribution.
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 #include <sys/cdefs.h>
28 __FBSDID("$FreeBSD$");
31 #include <sys/param.h>
32 #include <sys/module.h>
33 #include <sys/systm.h>
34 #include <sys/kernel.h>
37 #include <sys/endian.h>
38 #include <sys/malloc.h>
40 #include <sys/mutex.h>
42 #include <sys/taskqueue.h>
44 #include <machine/stdarg.h>
45 #include <machine/resource.h>
46 #include <machine/bus.h>
48 #include <dev/pci/pcivar.h>
49 #include <dev/pci/pcireg.h>
50 #include <dev/ata/ata-all.h>
51 #include <dev/ata/ata-pci.h>
54 /* local prototypes */
55 static int ata_ahci_suspend(device_t dev);
56 static int ata_ahci_status(device_t dev);
57 static int ata_ahci_begin_transaction(struct ata_request *request);
58 static int ata_ahci_end_transaction(struct ata_request *request);
59 static int ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result);
60 static int ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t result);
61 static int ata_ahci_hardreset(device_t dev, int port, uint32_t *signature);
62 static u_int32_t ata_ahci_softreset(device_t dev, int port);
63 static void ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error);
64 static int ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *equest);
65 static void ata_ahci_dmainit(device_t dev);
66 static void ata_ahci_start(device_t dev);
67 static void ata_ahci_stop(device_t dev);
68 static void ata_ahci_clo(device_t dev);
69 static void ata_ahci_start_fr(device_t dev);
70 static void ata_ahci_stop_fr(device_t dev);
73 * AHCI v1.x compliant SATA chipset support functions
76 ata_ahci_probe(device_t dev)
78 struct ata_pci_controller *ctlr = device_get_softc(dev);
81 /* is this a possible AHCI candidate ? */
82 if (pci_get_class(dev) != PCIC_STORAGE ||
83 pci_get_subclass(dev) != PCIS_STORAGE_SATA)
86 /* is this PCI device flagged as an AHCI compliant chip ? */
87 if (pci_get_progif(dev) != PCIP_STORAGE_SATA_AHCI_1_0)
91 sprintf(buffer, "%s (ID=%08x) AHCI controller",
92 ata_pcivendor2str(dev), pci_get_devid(dev));
94 sprintf(buffer, "%s AHCI controller", ata_pcivendor2str(dev));
95 device_set_desc_copy(dev, buffer);
96 ctlr->chipinit = ata_ahci_chipinit;
97 return (BUS_PROBE_GENERIC);
101 ata_ahci_chipinit(device_t dev)
103 struct ata_pci_controller *ctlr = device_get_softc(dev);
105 u_int32_t caps, version;
107 /* if we have a memory BAR(5) we are likely on an AHCI part */
108 ctlr->r_type2 = SYS_RES_MEMORY;
109 ctlr->r_rid2 = PCIR_BAR(5);
110 if (!(ctlr->r_res2 = bus_alloc_resource_any(dev, ctlr->r_type2,
111 &ctlr->r_rid2, RF_ACTIVE)))
114 /* setup interrupt delivery if not done allready by a vendor driver */
116 if (ata_setup_interrupt(dev, ata_generic_intr)) {
117 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
122 device_printf(dev, "AHCI called from vendor specific driver\n");
124 /* reset controller */
125 if ((error = ata_ahci_ctlr_reset(dev)) != 0) {
126 bus_release_resource(dev, ctlr->r_type2, ctlr->r_rid2, ctlr->r_res2);
130 /* get the number of HW channels */
131 ctlr->ichannels = ATA_INL(ctlr->r_res2, ATA_AHCI_PI);
133 MAX(flsl(ctlr->ichannels),
134 (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_NPMASK) + 1);
136 ctlr->reset = ata_ahci_reset;
137 ctlr->ch_attach = ata_ahci_ch_attach;
138 ctlr->ch_detach = ata_ahci_ch_detach;
139 ctlr->ch_suspend = ata_ahci_ch_suspend;
140 ctlr->ch_resume = ata_ahci_ch_resume;
141 ctlr->setmode = ata_sata_setmode;
142 ctlr->suspend = ata_ahci_suspend;
143 ctlr->resume = ata_ahci_ctlr_reset;
145 /* announce we support the HW */
146 version = ATA_INL(ctlr->r_res2, ATA_AHCI_VS);
147 caps = ATA_INL(ctlr->r_res2, ATA_AHCI_CAP);
148 speed = (caps & ATA_AHCI_CAP_ISS) >> ATA_AHCI_CAP_ISS_SHIFT;
150 "AHCI v%x.%02x controller with %d %sGbps ports, PM %s\n",
151 ((version >> 20) & 0xf0) + ((version >> 16) & 0x0f),
152 ((version >> 4) & 0xf0) + (version & 0x0f),
153 (caps & ATA_AHCI_CAP_NPMASK) + 1,
154 ((speed == 1) ? "1.5":((speed == 2) ? "3":
155 ((speed == 3) ? "6":"?"))),
156 (caps & ATA_AHCI_CAP_SPM) ?
157 "supported" : "not supported");
159 device_printf(dev, "Caps:%s%s%s%s%s%s%s%s %sGbps",
160 (caps & ATA_AHCI_CAP_64BIT) ? " 64bit":"",
161 (caps & ATA_AHCI_CAP_SNCQ) ? " NCQ":"",
162 (caps & ATA_AHCI_CAP_SSNTF) ? " SNTF":"",
163 (caps & ATA_AHCI_CAP_SMPS) ? " MPS":"",
164 (caps & ATA_AHCI_CAP_SSS) ? " SS":"",
165 (caps & ATA_AHCI_CAP_SALP) ? " ALP":"",
166 (caps & ATA_AHCI_CAP_SAL) ? " AL":"",
167 (caps & ATA_AHCI_CAP_SCLO) ? " CLO":"",
168 ((speed == 1) ? "1.5":((speed == 2) ? "3":
169 ((speed == 3) ? "6":"?"))));
170 printf("%s%s%s%s%s%s %dcmd%s%s%s %dports\n",
171 (caps & ATA_AHCI_CAP_SAM) ? " AM":"",
172 (caps & ATA_AHCI_CAP_SPM) ? " PM":"",
173 (caps & ATA_AHCI_CAP_FBSS) ? " FBS":"",
174 (caps & ATA_AHCI_CAP_PMD) ? " PMD":"",
175 (caps & ATA_AHCI_CAP_SSC) ? " SSC":"",
176 (caps & ATA_AHCI_CAP_PSC) ? " PSC":"",
177 ((caps & ATA_AHCI_CAP_NCS) >> ATA_AHCI_CAP_NCS_SHIFT) + 1,
178 (caps & ATA_AHCI_CAP_CCCS) ? " CCC":"",
179 (caps & ATA_AHCI_CAP_EMS) ? " EM":"",
180 (caps & ATA_AHCI_CAP_SXS) ? " eSATA":"",
181 (caps & ATA_AHCI_CAP_NPMASK) + 1);
187 ata_ahci_ctlr_reset(device_t dev)
189 struct ata_pci_controller *ctlr = device_get_softc(dev);
192 /* enable AHCI mode */
193 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
195 /* reset AHCI controller */
196 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE|ATA_AHCI_GHC_HR);
197 for (timeout = 1000; timeout > 0; timeout--) {
199 if ((ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & ATA_AHCI_GHC_HR) == 0)
203 device_printf(dev, "AHCI controller reset failure\n");
207 /* reenable AHCI mode */
208 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC, ATA_AHCI_GHC_AE);
210 /* clear interrupts */
211 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, ATA_INL(ctlr->r_res2, ATA_AHCI_IS));
213 /* enable AHCI interrupts */
214 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
215 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) | ATA_AHCI_GHC_IE);
221 ata_ahci_suspend(device_t dev)
223 struct ata_pci_controller *ctlr = device_get_softc(dev);
225 /* disable interupts so the state change(s) doesn't trigger */
226 ATA_OUTL(ctlr->r_res2, ATA_AHCI_GHC,
227 ATA_INL(ctlr->r_res2, ATA_AHCI_GHC) & (~ATA_AHCI_GHC_IE));
232 ata_ahci_ch_attach(device_t dev)
234 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
235 struct ata_channel *ch = device_get_softc(dev);
236 int offset = ch->unit << 7;
238 ata_ahci_dmainit(dev);
240 /* set the SATA resources */
241 ch->r_io[ATA_SSTATUS].res = ctlr->r_res2;
242 ch->r_io[ATA_SSTATUS].offset = ATA_AHCI_P_SSTS + offset;
243 ch->r_io[ATA_SERROR].res = ctlr->r_res2;
244 ch->r_io[ATA_SERROR].offset = ATA_AHCI_P_SERR + offset;
245 ch->r_io[ATA_SCONTROL].res = ctlr->r_res2;
246 ch->r_io[ATA_SCONTROL].offset = ATA_AHCI_P_SCTL + offset;
247 ch->r_io[ATA_SACTIVE].res = ctlr->r_res2;
248 ch->r_io[ATA_SACTIVE].offset = ATA_AHCI_P_SACT + offset;
250 ch->hw.status = ata_ahci_status;
251 ch->hw.begin_transaction = ata_ahci_begin_transaction;
252 ch->hw.end_transaction = ata_ahci_end_transaction;
253 ch->hw.command = NULL; /* not used here */
254 ch->hw.softreset = ata_ahci_softreset;
255 ch->hw.pm_read = ata_ahci_pm_read;
256 ch->hw.pm_write = ata_ahci_pm_write;
258 ata_ahci_ch_resume(dev);
263 ata_ahci_ch_detach(device_t dev)
266 ata_ahci_ch_suspend(dev);
272 ata_ahci_ch_suspend(device_t dev)
274 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
275 struct ata_channel *ch = device_get_softc(dev);
276 int offset = ch->unit << 7;
278 /* Disable port interrupts. */
279 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
280 /* Reset command register. */
282 ata_ahci_stop_fr(dev);
283 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, 0);
285 /* Allow everything including partial and slumber modes. */
286 ATA_IDX_OUTL(ch, ATA_SCONTROL, 0);
287 /* Request slumber mode transition and give some time to get there. */
288 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, ATA_AHCI_P_CMD_SLUMBER);
291 ATA_IDX_OUTL(ch, ATA_SCONTROL, ATA_SC_DET_DISABLE);
297 ata_ahci_ch_resume(device_t dev)
299 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
300 struct ata_channel *ch = device_get_softc(dev);
302 int offset = ch->unit << 7;
304 /* Disable port interrupts */
305 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
307 /* setup work areas */
308 work = ch->dma.work_bus + ATA_AHCI_CL_OFFSET;
309 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLB + offset, work & 0xffffffff);
310 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CLBU + offset, work >> 32);
312 work = ch->dma.work_bus + ATA_AHCI_FB_OFFSET;
313 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FB + offset, work & 0xffffffff);
314 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_FBU + offset, work >> 32);
316 /* activate the channel and power/spin up device */
317 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
318 (ATA_AHCI_P_CMD_ACTIVE | ATA_AHCI_P_CMD_POD | ATA_AHCI_P_CMD_SUD |
319 ((ch->pm_level > 1) ? ATA_AHCI_P_CMD_ALPE : 0) |
320 ((ch->pm_level > 2) ? ATA_AHCI_P_CMD_ASP : 0 )));
321 ata_ahci_start_fr(dev);
328 ata_ahci_status(device_t dev)
330 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
331 struct ata_channel *ch = device_get_softc(dev);
332 u_int32_t action = ATA_INL(ctlr->r_res2, ATA_AHCI_IS);
333 int offset = ch->unit << 7;
335 #define ATA_AHCI_STATBITS \
336 (ATA_AHCI_P_IX_IF|ATA_AHCI_P_IX_HBD|ATA_AHCI_P_IX_HBF|ATA_AHCI_P_IX_TFE)
338 if (action & (1 << ch->unit)) {
339 u_int32_t istatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset);
340 u_int32_t cstatus = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset);
342 /* clear interrupt(s) */
343 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset, istatus);
344 ATA_OUTL(ctlr->r_res2, ATA_AHCI_IS, 1 << ch->unit);
346 /* do we have any PHY events ? */
347 if (istatus & (ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC))
348 ata_sata_phy_check_events(dev);
350 /* do we have a potentially hanging engine to take care of? */
351 /* XXX SOS what todo on NCQ */
352 if ((istatus & ATA_AHCI_STATBITS) && (cstatus & 1)) {
354 u_int32_t cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
357 /* kill off all activity on this channel */
358 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
359 cmd & ~(ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
361 /* XXX SOS this is not entirely wrong */
364 if (timeout++ > 1000) {
365 device_printf(dev, "stopping AHCI engine failed\n");
368 } while (ATA_INL(ctlr->r_res2,
369 ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
371 /* start operations on this channel */
372 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
373 cmd | (ATA_AHCI_P_CMD_FRE | ATA_AHCI_P_CMD_ST));
378 /* XXX SOS what todo on NCQ */
379 return (!(cstatus & 1));
384 /* must be called with ATA channel locked and state_mtx held */
386 ata_ahci_begin_transaction(struct ata_request *request)
388 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
389 struct ata_channel *ch = device_get_softc(request->parent);
390 struct ata_device *atadev = device_get_softc(request->dev);
391 struct ata_ahci_cmd_tab *ctp;
392 struct ata_ahci_cmd_list *clp;
393 int offset = ch->unit << 7;
394 int port = atadev->unit & 0x0f;
398 /* get a piece of the workspace for this request */
399 ctp = (struct ata_ahci_cmd_tab *)
400 (ch->dma.work + ATA_AHCI_CT_OFFSET + (ATA_AHCI_CT_SIZE*request->tag));
402 /* setup the FIS for this request */
403 if (!(fis_size = ata_ahci_setup_fis(ctp, request))) {
404 device_printf(request->dev, "setting up SATA FIS failed\n");
405 request->result = EIO;
406 return ATA_OP_FINISHED;
409 /* if request moves data setup and load SG list */
410 if (request->flags & (ATA_R_READ | ATA_R_WRITE)) {
411 if (ch->dma.load(request, ctp->prd_tab, &entries)) {
412 device_printf(request->dev, "setting up DMA failed\n");
413 request->result = EIO;
414 return ATA_OP_FINISHED;
418 /* setup the command list entry */
419 clp = (struct ata_ahci_cmd_list *)
420 (ch->dma.work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE*request->tag));
422 clp->prd_length = entries;
423 clp->cmd_flags = (request->flags & ATA_R_WRITE ? ATA_AHCI_CMD_WRITE : 0) |
424 (request->flags & ATA_R_ATAPI ?
425 (ATA_AHCI_CMD_ATAPI | ATA_AHCI_CMD_PREFETCH) : 0) |
426 (fis_size / sizeof(u_int32_t)) |
429 clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET +
430 (ATA_AHCI_CT_SIZE * request->tag));
432 /* clear eventual ACTIVE bit */
433 ATA_IDX_OUTL(ch, ATA_SACTIVE,
434 ATA_IDX_INL(ch, ATA_SACTIVE) & (1 << request->tag));
436 /* set command type bit */
437 if (request->flags & ATA_R_ATAPI)
438 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
439 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) |
440 ATA_AHCI_P_CMD_ATAPI);
442 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
443 ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) &
444 ~ATA_AHCI_P_CMD_ATAPI);
446 /* issue command to controller */
447 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, (1 << request->tag));
449 if (!(request->flags & ATA_R_ATAPI)) {
450 /* device reset doesn't interrupt */
451 if (request->u.ata.command == ATA_DEVICE_RESET) {
453 int timeout = 1000000;
457 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + (ch->unit<<7));
458 } while ((tf_data & ATA_S_BUSY) && timeout--);
460 device_printf(ch->dev, "device_reset timeout=%dus\n",
461 (1000000-timeout)*10);
462 request->status = tf_data;
463 if (request->status & ATA_S_ERROR)
464 request->error = tf_data >> 8;
465 return ATA_OP_FINISHED;
469 /* start the timeout */
470 callout_reset(&request->callout, request->timeout * hz,
471 (timeout_t*)ata_timeout, request);
472 return ATA_OP_CONTINUES;
475 /* must be called with ATA channel locked and state_mtx held */
477 ata_ahci_end_transaction(struct ata_request *request)
479 struct ata_pci_controller *ctlr=device_get_softc(GRANDPARENT(request->dev));
480 struct ata_channel *ch = device_get_softc(request->parent);
481 struct ata_ahci_cmd_list *clp;
483 int offset = ch->unit << 7;
485 /* kill the timeout */
486 callout_stop(&request->callout);
489 tf_data = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset);
490 request->status = tf_data;
492 /* if error status get details */
493 if (request->status & ATA_S_ERROR)
494 request->error = tf_data >> 8;
496 /* on control commands read back registers to the request struct */
497 if (request->flags & ATA_R_CONTROL) {
498 struct ata_device *atadev = device_get_softc(request->dev);
499 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
501 request->u.ata.count = fis[12] | ((u_int16_t)fis[13] << 8);
502 request->u.ata.lba = fis[4] | ((u_int64_t)fis[5] << 8) |
503 ((u_int64_t)fis[6] << 16);
504 if (atadev->flags & ATA_D_48BIT_ACTIVE)
505 request->u.ata.lba |= ((u_int64_t)fis[8] << 24) |
506 ((u_int64_t)fis[9] << 32) |
507 ((u_int64_t)fis[10] << 40);
509 request->u.ata.lba |= ((u_int64_t)(fis[7] & 0x0f) << 24);
512 /* record how much data we actually moved */
513 clp = (struct ata_ahci_cmd_list *)
514 (ch->dma.work + ATA_AHCI_CL_OFFSET + (ATA_AHCI_CL_SIZE*request->tag));
515 request->donecount = clp->bytecount;
517 /* release SG list etc */
518 ch->dma.unload(request);
520 return ATA_OP_FINISHED;
524 ata_ahci_issue_cmd(device_t dev, u_int16_t flags, int timeout)
526 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
527 struct ata_channel *ch = device_get_softc(dev);
528 struct ata_ahci_cmd_list *clp =
529 (struct ata_ahci_cmd_list *)(ch->dma.work + ATA_AHCI_CL_OFFSET);
530 struct ata_ahci_cmd_tab *ctp =
531 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
532 u_int32_t status = 0;
533 int offset = ch->unit << 7;
534 int port = (ctp->cfis[1] & 0x0f);
538 clp->cmd_flags = (20 / sizeof(u_int32_t)) | flags | (port << 12);
540 clp->cmd_table_phys = htole64(ch->dma.work_bus + ATA_AHCI_CT_OFFSET);
542 /* issue command to controller */
543 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CI + offset, 1);
545 /* poll for command finished */
546 for (count = 0; count < timeout; count++) {
548 if (!((status = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CI + offset)) & 1))
552 /* clear interrupts */
553 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
554 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
556 if (timeout && (count >= timeout)) {
558 device_printf(dev, "ahci_issue_cmd timeout: %d of %dms, status=%08x\n",
559 count, timeout, status);
568 ata_ahci_pm_read(device_t dev, int port, int reg, u_int32_t *result)
570 struct ata_channel *ch = device_get_softc(dev);
571 struct ata_ahci_cmd_tab *ctp =
572 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
573 u_int8_t *fis = ch->dma.work + ATA_AHCI_FB_OFFSET + 0x40;
575 bzero(ctp->cfis, 64);
576 ctp->cfis[0] = 0x27; /* host to device */
577 ctp->cfis[1] = 0x8f; /* command FIS to PM port */
578 ctp->cfis[2] = ATA_READ_PM;
580 ctp->cfis[7] = port | ATA_D_LBA;
581 ctp->cfis[15] = ATA_A_4BIT;
583 if (ata_ahci_issue_cmd(dev, 0, 10)) {
584 device_printf(dev, "error reading PM port\n");
588 *result = fis[12] | (fis[4] << 8) | (fis[5] << 16) | (fis[6] << 24);
593 ata_ahci_pm_write(device_t dev, int port, int reg, u_int32_t value)
595 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
596 struct ata_channel *ch = device_get_softc(dev);
597 struct ata_ahci_cmd_tab *ctp =
598 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
599 int offset = ch->unit << 7;
601 bzero(ctp->cfis, 64);
602 ctp->cfis[0] = 0x27; /* host to device */
603 ctp->cfis[1] = 0x8f; /* command FIS to PM port */
604 ctp->cfis[2] = ATA_WRITE_PM;
606 ctp->cfis[7] = port | ATA_D_LBA;
607 ctp->cfis[12] = value & 0xff;
608 ctp->cfis[4] = (value >> 8) & 0xff;;
609 ctp->cfis[5] = (value >> 16) & 0xff;;
610 ctp->cfis[6] = (value >> 24) & 0xff;;
611 ctp->cfis[15] = ATA_A_4BIT;
613 if (ata_ahci_issue_cmd(dev, 0, 100)) {
614 device_printf(dev, "error writing PM port\n");
618 return (ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset) >> 8) & 0xff;
622 ata_ahci_stop(device_t dev)
624 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
625 struct ata_channel *ch = device_get_softc(dev);
627 int offset = ch->unit << 7;
630 /* kill off all activity on this channel */
631 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
632 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
633 cmd & ~ATA_AHCI_P_CMD_ST);
635 /* XXX SOS this is not entirely wrong */
639 if (timeout++ > 1000) {
640 device_printf(dev, "stopping AHCI engine failed\n");
644 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_CR);
648 ata_ahci_clo(device_t dev)
650 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
651 struct ata_channel *ch = device_get_softc(dev);
653 int offset = ch->unit << 7;
656 /* issue Command List Override if supported */
657 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SCLO) {
658 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
659 cmd |= ATA_AHCI_P_CMD_CLO;
660 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd);
664 if (timeout++ > 1000) {
665 device_printf(dev, "executing CLO failed\n");
669 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD+offset)&ATA_AHCI_P_CMD_CLO);
674 ata_ahci_start(device_t dev)
676 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
677 struct ata_channel *ch = device_get_softc(dev);
679 int offset = ch->unit << 7;
681 /* clear SATA error register */
682 ATA_IDX_OUTL(ch, ATA_SERROR, ATA_IDX_INL(ch, ATA_SERROR));
684 /* clear any interrupts pending on this channel */
685 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IS + offset,
686 ATA_INL(ctlr->r_res2, ATA_AHCI_P_IS + offset));
688 /* start operations on this channel */
689 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
690 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset,
691 cmd | ATA_AHCI_P_CMD_ST |
692 (ch->devices & ATA_PORTMULTIPLIER ? ATA_AHCI_P_CMD_PMA : 0));
696 ata_ahci_stop_fr(device_t dev)
698 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
699 struct ata_channel *ch = device_get_softc(dev);
701 int offset = ch->unit << 7;
704 /* kill off all activity on this channel */
705 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
706 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd & ~ATA_AHCI_P_CMD_FRE);
711 if (timeout++ > 1000) {
712 device_printf(dev, "stopping AHCI FR engine failed\n");
716 while (ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset) & ATA_AHCI_P_CMD_FR);
720 ata_ahci_start_fr(device_t dev)
722 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
723 struct ata_channel *ch = device_get_softc(dev);
725 int offset = ch->unit << 7;
727 /* start FIS reception on this channel */
728 cmd = ATA_INL(ctlr->r_res2, ATA_AHCI_P_CMD + offset);
729 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_CMD + offset, cmd | ATA_AHCI_P_CMD_FRE);
733 ata_ahci_wait_ready(device_t dev, int t)
735 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
736 struct ata_channel *ch = device_get_softc(dev);
737 int offset = ch->unit << 7;
741 while ((val = ATA_INL(ctlr->r_res2, ATA_AHCI_P_TFD + offset)) &
742 (ATA_S_BUSY | ATA_S_DRQ)) {
745 device_printf(dev, "port is not ready (timeout %dms) tfd = %08x\n", t, val);
750 device_printf(dev, "ready wait time=%dms\n", timeout);
755 ata_ahci_hardreset(device_t dev, int port, uint32_t *signature)
757 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
758 struct ata_channel *ch = device_get_softc(dev);
759 int offset = ch->unit << 7;
761 *signature = 0xffffffff;
764 if (!ata_sata_phy_reset(dev, port, 0))
766 /* Wait for clearing busy status. */
767 if (ata_ahci_wait_ready(dev, 10000)) {
768 device_printf(dev, "hardware reset timeout\n");
771 *signature = ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
777 ata_ahci_softreset(device_t dev, int port)
779 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
780 struct ata_channel *ch = device_get_softc(dev);
781 int offset = ch->unit << 7;
782 struct ata_ahci_cmd_tab *ctp =
783 (struct ata_ahci_cmd_tab *)(ch->dma.work + ATA_AHCI_CT_OFFSET);
786 device_printf(dev, "software reset port %d...\n", port);
788 /* kick controller into sane state */
793 /* pull reset active */
794 bzero(ctp->cfis, 64);
796 ctp->cfis[1] = port & 0x0f;
797 //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
798 ctp->cfis[15] = (ATA_A_4BIT | ATA_A_RESET);
800 if (ata_ahci_issue_cmd(dev, ATA_AHCI_CMD_RESET | ATA_AHCI_CMD_CLR_BUSY,100)) {
801 device_printf(dev, "software reset set timeout\n");
807 /* pull reset inactive -> device softreset */
808 bzero(ctp->cfis, 64);
810 ctp->cfis[1] = port & 0x0f;
811 //ctp->cfis[7] = ATA_D_LBA | ATA_D_IBM;
812 ctp->cfis[15] = ATA_A_4BIT;
813 ata_ahci_issue_cmd(dev, 0, 3000);
815 if (ata_ahci_wait_ready(dev, 0)) {
816 device_printf(dev, "software reset clear timeout\n");
820 return ATA_INL(ctlr->r_res2, ATA_AHCI_P_SIG + offset);
824 ata_ahci_reset(device_t dev)
826 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
827 struct ata_channel *ch = device_get_softc(dev);
829 int offset = ch->unit << 7;
832 device_printf(dev, "AHCI reset...\n");
834 /* Disable port interrupts */
835 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset, 0);
837 if (ata_ahci_hardreset(dev, -1, &signature)) {
839 device_printf(dev, "AHCI reset done: phy reset found no device\n");
842 /* enable wanted port interrupts */
843 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
844 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC));
848 /* enable wanted port interrupts */
849 ATA_OUTL(ctlr->r_res2, ATA_AHCI_P_IE + offset,
850 (ATA_AHCI_P_IX_CPD | ATA_AHCI_P_IX_TFE | ATA_AHCI_P_IX_HBF |
851 ATA_AHCI_P_IX_HBD | ATA_AHCI_P_IX_IF | ATA_AHCI_P_IX_OF |
852 ((ch->pm_level == 0) ? ATA_AHCI_P_IX_PRC | ATA_AHCI_P_IX_PC : 0) |
853 ATA_AHCI_P_IX_DP | ATA_AHCI_P_IX_UF | ATA_AHCI_P_IX_SDB |
854 ATA_AHCI_P_IX_DS | ATA_AHCI_P_IX_PS | ATA_AHCI_P_IX_DHR));
856 /* only probe for PortMultiplier if HW has support */
857 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_SPM) {
858 signature = ata_ahci_softreset(dev, ATA_PM);
859 /* Workaround for some ATI chips, failing to soft-reset
860 * when port multiplicator supported, but absent.
861 * XXX: We can also check PxIS.IPMS==1 here to be sure. */
862 if (signature == 0xffffffff)
863 signature = ata_ahci_softreset(dev, 0);
865 signature = ata_ahci_softreset(dev, 0);
868 device_printf(dev, "SIGNATURE: %08x\n", signature);
870 switch (signature >> 16) {
872 ch->devices = ATA_ATA_MASTER;
875 ch->devices = ATA_PORTMULTIPLIER;
876 ata_pm_identify(dev);
879 ch->devices = ATA_ATAPI_MASTER;
881 default: /* SOS XXX */
883 device_printf(dev, "Unknown signature, assuming disk device\n");
884 ch->devices = ATA_ATA_MASTER;
887 device_printf(dev, "AHCI reset done: devices=%08x\n", ch->devices);
891 ata_ahci_dmasetprd(void *xsc, bus_dma_segment_t *segs, int nsegs, int error)
893 struct ata_dmasetprd_args *args = xsc;
894 struct ata_ahci_dma_prd *prd = args->dmatab;
897 if (!(args->error = error)) {
898 for (i = 0; i < nsegs; i++) {
899 prd[i].dba = htole64(segs[i].ds_addr);
900 prd[i].dbc = htole32((segs[i].ds_len - 1) & ATA_AHCI_PRD_MASK);
904 KASSERT(nsegs <= ATA_AHCI_DMA_ENTRIES, ("too many DMA segment entries\n"));
909 ata_ahci_dmainit(device_t dev)
911 struct ata_pci_controller *ctlr = device_get_softc(device_get_parent(dev));
912 struct ata_channel *ch = device_get_softc(dev);
915 /* note start and stop are not used here */
916 ch->dma.setprd = ata_ahci_dmasetprd;
917 ch->dma.max_iosize = (ATA_AHCI_DMA_ENTRIES - 1) * PAGE_SIZE;
918 if (ATA_INL(ctlr->r_res2, ATA_AHCI_CAP) & ATA_AHCI_CAP_64BIT)
919 ch->dma.max_address = BUS_SPACE_MAXADDR;
923 ata_ahci_setup_fis(struct ata_ahci_cmd_tab *ctp, struct ata_request *request)
925 bzero(ctp->cfis, 64);
926 if (request->flags & ATA_R_ATAPI) {
927 bzero(ctp->acmd, 32);
928 bcopy(request->u.atapi.ccb, ctp->acmd, 16);
930 return ata_request2fis_h2d(request, &ctp->cfis[0]);
933 ATA_DECLARE_DRIVER(ata_ahci);